[PATCH v2 1/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms

[PATCH v2 1/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms

[Ran Wang]

arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(), which
causing compile failure on some Layerscape Platforms (such as LS1021A and
LS2012A which also integrates FSL EHCI controller). So use
ioread32be()/iowrite32be() instead to make it workable on both
powerpc and arm.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Changes in v2:
  - Recover writel() calling in code of handling pdata->has_fsl_erratum_a007792
  - Remove unnecessary parens
  - Move this patch to be first one to avoid breaking the build on ARM.

 drivers/usb/host/ehci-fsl.c |   62 ++++++++++++++++++++++++++++--------------
 1 files changed, 41 insertions(+), 21 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 0a9fd20..0a867d9 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/fsl_devices.h>
 #include <linux/of_platform.h>
+#include <linux/io.h>
 
 #include "ehci.h"
 #include "ehci-fsl.h"
@@ -50,6 +51,7 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
 	struct resource *res;
 	int irq;
 	int retval;
+	u32 tmp;
 
 	pr_debug("initializing FSL-SOC USB Controller\n");
 
@@ -114,17 +116,22 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
 	}
 
 	/* Enable USB controller, 83xx or 8536 */
-	if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
-		clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
-				CONTROL_REGISTER_W1C_MASK, 0x4);
-
+	if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) {
+		tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
+		tmp &= ~CONTROL_REGISTER_W1C_MASK;
+		tmp |= 0x4;
+		iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
+	}
 	/*
 	 * Enable UTMI phy and program PTS field in UTMI mode before asserting
 	 * controller reset for USB Controller version 2.5
 	 */
 	if (pdata->has_fsl_erratum_a007792) {
-		clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
-				CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN);
+		tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
+		tmp &= ~CONTROL_REGISTER_W1C_MASK;
+		tmp |= CTRL_UTMI_PHY_EN;
+		iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
+
 		writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
 	}
 
@@ -174,7 +181,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
 			       enum fsl_usb2_phy_modes phy_mode,
 			       unsigned int port_offset)
 {
-	u32 portsc;
+	u32 portsc, tmp;
 	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 	void __iomem *non_ehci = hcd->regs;
 	struct device *dev = hcd->self.controller;
@@ -192,11 +199,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
 	case FSL_USB2_PHY_ULPI:
 		if (pdata->have_sysif_regs && pdata->controller_ver) {
 			/* controller version 1.6 or above */
-			clrbits32(non_ehci + FSL_SOC_USB_CTRL,
-				  CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
-			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
-					CONTROL_REGISTER_W1C_MASK,
-					ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
+			/* turn off UTMI PHY first */
+			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
+			tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
+			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
+
+			/* then turn on ULPI and enable USB controller */
+			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
+			tmp &= ~CONTROL_REGISTER_W1C_MASK;
+			tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN;
+			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
 		}
 		portsc |= PORT_PTS_ULPI;
 		break;
@@ -210,16 +222,21 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
 	case FSL_USB2_PHY_UTMI_DUAL:
 		if (pdata->have_sysif_regs && pdata->controller_ver) {
 			/* controller version 1.6 or above */
-			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
-					CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN);
+			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
+			tmp &= ~CONTROL_REGISTER_W1C_MASK;
+			tmp |= UTMI_PHY_EN;
+			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
+
 			mdelay(FSL_UTMI_PHY_DLY);  /* Delay for UTMI PHY CLK to
 						become stable - 10ms*/
 		}
 		/* enable UTMI PHY */
-		if (pdata->have_sysif_regs)
-			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
-					CONTROL_REGISTER_W1C_MASK,
-					CTRL_UTMI_PHY_EN);
+		if (pdata->have_sysif_regs) {
+			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
+			tmp &= ~CONTROL_REGISTER_W1C_MASK;
+			tmp |= CTRL_UTMI_PHY_EN;
+			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
+		}
 		portsc |= PORT_PTS_UTMI;
 		break;
 	case FSL_USB2_PHY_NONE:
@@ -241,9 +258,12 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
 
 	ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
 
-	if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
-		clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
-				CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN);
+	if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) {
+		tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
+		tmp &= ~CONTROL_REGISTER_W1C_MASK;
+		tmp |= USB_CTRL_USB_EN;
+		iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
+	}
 
 	return 0;
 }
-- 
1.7.1

[v2,1/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms

[Ran Wang]

arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(), which
causing compile failure on some Layerscape Platforms (such as LS1021A and
LS2012A which also integrates FSL EHCI controller). So use
ioread32be()/iowrite32be() instead to make it workable on both
powerpc and arm.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Changes in v2:
  - Recover writel() calling in code of handling pdata->has_fsl_erratum_a007792
  - Remove unnecessary parens
  - Move this patch to be first one to avoid breaking the build on ARM.

 drivers/usb/host/ehci-fsl.c |   62 ++++++++++++++++++++++++++++--------------
 1 files changed, 41 insertions(+), 21 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 0a9fd20..0a867d9 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/fsl_devices.h>
 #include <linux/of_platform.h>
+#include <linux/io.h>
 
 #include "ehci.h"
 #include "ehci-fsl.h"
@@ -50,6 +51,7 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
 	struct resource *res;
 	int irq;
 	int retval;
+	u32 tmp;
 
 	pr_debug("initializing FSL-SOC USB Controller\n");
 
@@ -114,17 +116,22 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
 	}
 
 	/* Enable USB controller, 83xx or 8536 */
-	if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
-		clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
-				CONTROL_REGISTER_W1C_MASK, 0x4);
-
+	if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) {
+		tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
+		tmp &= ~CONTROL_REGISTER_W1C_MASK;
+		tmp |= 0x4;
+		iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
+	}
 	/*
 	 * Enable UTMI phy and program PTS field in UTMI mode before asserting
 	 * controller reset for USB Controller version 2.5
 	 */
 	if (pdata->has_fsl_erratum_a007792) {
-		clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
-				CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN);
+		tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
+		tmp &= ~CONTROL_REGISTER_W1C_MASK;
+		tmp |= CTRL_UTMI_PHY_EN;
+		iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
+
 		writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
 	}
 
@@ -174,7 +181,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
 			       enum fsl_usb2_phy_modes phy_mode,
 			       unsigned int port_offset)
 {
-	u32 portsc;
+	u32 portsc, tmp;
 	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 	void __iomem *non_ehci = hcd->regs;
 	struct device *dev = hcd->self.controller;
@@ -192,11 +199,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
 	case FSL_USB2_PHY_ULPI:
 		if (pdata->have_sysif_regs && pdata->controller_ver) {
 			/* controller version 1.6 or above */
-			clrbits32(non_ehci + FSL_SOC_USB_CTRL,
-				  CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
-			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
-					CONTROL_REGISTER_W1C_MASK,
-					ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
+			/* turn off UTMI PHY first */
+			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
+			tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
+			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
+
+			/* then turn on ULPI and enable USB controller */
+			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
+			tmp &= ~CONTROL_REGISTER_W1C_MASK;
+			tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN;
+			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
 		}
 		portsc |= PORT_PTS_ULPI;
 		break;
@@ -210,16 +222,21 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
 	case FSL_USB2_PHY_UTMI_DUAL:
 		if (pdata->have_sysif_regs && pdata->controller_ver) {
 			/* controller version 1.6 or above */
-			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
-					CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN);
+			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
+			tmp &= ~CONTROL_REGISTER_W1C_MASK;
+			tmp |= UTMI_PHY_EN;
+			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
+
 			mdelay(FSL_UTMI_PHY_DLY);  /* Delay for UTMI PHY CLK to
 						become stable - 10ms*/
 		}
 		/* enable UTMI PHY */
-		if (pdata->have_sysif_regs)
-			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
-					CONTROL_REGISTER_W1C_MASK,
-					CTRL_UTMI_PHY_EN);
+		if (pdata->have_sysif_regs) {
+			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
+			tmp &= ~CONTROL_REGISTER_W1C_MASK;
+			tmp |= CTRL_UTMI_PHY_EN;
+			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
+		}
 		portsc |= PORT_PTS_UTMI;
 		break;
 	case FSL_USB2_PHY_NONE:
@@ -241,9 +258,12 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
 
 	ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
 
-	if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
-		clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
-				CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN);
+	if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) {
+		tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
+		tmp &= ~CONTROL_REGISTER_W1C_MASK;
+		tmp |= USB_CTRL_USB_EN;
+		iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
+	}
 
 	return 0;
 }

[PATCH v2 2/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver

[Ran Wang]

CONFIG_USB_EHCI_FSL is not dependent on FSL_SOC, it can be built on
non-PPC platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Changes in v2:
  - remove 'depends on USB_EHCI_HCD'
  - Move this patch to be second one to avoid breaking the build on ARM.

 drivers/usb/host/Kconfig |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 16758b1..11db5b2 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -179,8 +179,7 @@ config XPS_USB_HCD_XILINX
 		devices only.
 
 config USB_EHCI_FSL
-	tristate "Support for Freescale PPC on-chip EHCI USB controller"
-	depends on FSL_SOC
+	tristate "Support for Freescale on-chip EHCI USB controller"
 	select USB_EHCI_ROOT_HUB_TT
 	---help---
 	  Variation of ARC USB block used in some Freescale chips.
-- 
1.7.1

[v2,2/3] usb: kconfig: remove dependency FSL_SOC for ehci fsl driver

[Ran Wang]

CONFIG_USB_EHCI_FSL is not dependent on FSL_SOC, it can be built on
non-PPC platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Changes in v2:
  - remove 'depends on USB_EHCI_HCD'
  - Move this patch to be second one to avoid breaking the build on ARM.

 drivers/usb/host/Kconfig |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 16758b1..11db5b2 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -179,8 +179,7 @@ config XPS_USB_HCD_XILINX
 		devices only.
 
 config USB_EHCI_FSL
-	tristate "Support for Freescale PPC on-chip EHCI USB controller"
-	depends on FSL_SOC
+	tristate "Support for Freescale on-chip EHCI USB controller"
 	select USB_EHCI_ROOT_HUB_TT
 	---help---
 	  Variation of ARC USB block used in some Freescale chips.

[PATCH v2 3/3] drivers: usb :fsl: Remove USB Errata checking code

[Ran Wang]

Remove USB errata checking code from driver. Applicability of erratum
is retrieved by reading corresponding property in device tree.
This property is written during device tree fixup.

Besides, replace spaces with tabs to make code aligned.

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Changes in v2:
  - Correct signed-off name.
  - Use tabs rather than spaces to make code aligned.

 drivers/usb/host/ehci-fsl.c      |    7 +------
 drivers/usb/host/fsl-mph-dr-of.c |    6 ++++++
 include/linux/fsl_devices.h      |    7 ++++---
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 0a867d9..e3d0c1c 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -304,14 +304,9 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
 			return -EINVAL;
 
 	if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
-		unsigned int chip, rev, svr;
-
-		svr = mfspr(SPRN_SVR);
-		chip = svr >> 16;
-		rev = (svr >> 4) & 0xf;
 
 		/* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
-		if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
+		if (pdata->has_fsl_erratum_14 == 1)
 			ehci->has_fsl_port_bug = 1;
 
 		if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 677f9d5..4f8b8a0 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -225,6 +225,12 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device *ofdev)
 	pdata->has_fsl_erratum_a005697 =
 		of_property_read_bool(np, "fsl,usb_erratum-a005697");
 
+	if (of_get_property(np, "fsl,usb_erratum_14", NULL))
+		pdata->has_fsl_erratum_14 = 1;
+	else
+		pdata->has_fsl_erratum_14 = 0;
+
+
 	/*
 	 * Determine whether phy_clk_valid needs to be checked
 	 * by reading property in device tree
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 60cef82..5da56a6 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -98,10 +98,11 @@ struct fsl_usb2_platform_data {
 
 	unsigned	suspended:1;
 	unsigned	already_suspended:1;
-	unsigned        has_fsl_erratum_a007792:1;
-	unsigned        has_fsl_erratum_a005275:1;
+	unsigned	has_fsl_erratum_a007792:1;
+	unsigned	has_fsl_erratum_14:1;
+	unsigned	has_fsl_erratum_a005275:1;
 	unsigned	has_fsl_erratum_a005697:1;
-	unsigned        check_phy_clk_valid:1;
+	unsigned	check_phy_clk_valid:1;
 
 	/* register save area for suspend/resume */
 	u32		pm_command;
-- 
1.7.1

[v2,3/3] drivers: usb :fsl: Remove USB Errata checking code

[Ran Wang]

Remove USB errata checking code from driver. Applicability of erratum
is retrieved by reading corresponding property in device tree.
This property is written during device tree fixup.

Besides, replace spaces with tabs to make code aligned.

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Changes in v2:
  - Correct signed-off name.
  - Use tabs rather than spaces to make code aligned.

 drivers/usb/host/ehci-fsl.c      |    7 +------
 drivers/usb/host/fsl-mph-dr-of.c |    6 ++++++
 include/linux/fsl_devices.h      |    7 ++++---
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 0a867d9..e3d0c1c 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -304,14 +304,9 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
 			return -EINVAL;
 
 	if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
-		unsigned int chip, rev, svr;
-
-		svr = mfspr(SPRN_SVR);
-		chip = svr >> 16;
-		rev = (svr >> 4) & 0xf;
 
 		/* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
-		if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
+		if (pdata->has_fsl_erratum_14 == 1)
 			ehci->has_fsl_port_bug = 1;
 
 		if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 677f9d5..4f8b8a0 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -225,6 +225,12 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device *ofdev)
 	pdata->has_fsl_erratum_a005697 =
 		of_property_read_bool(np, "fsl,usb_erratum-a005697");
 
+	if (of_get_property(np, "fsl,usb_erratum_14", NULL))
+		pdata->has_fsl_erratum_14 = 1;
+	else
+		pdata->has_fsl_erratum_14 = 0;
+
+
 	/*
 	 * Determine whether phy_clk_valid needs to be checked
 	 * by reading property in device tree
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 60cef82..5da56a6 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -98,10 +98,11 @@ struct fsl_usb2_platform_data {
 
 	unsigned	suspended:1;
 	unsigned	already_suspended:1;
-	unsigned        has_fsl_erratum_a007792:1;
-	unsigned        has_fsl_erratum_a005275:1;
+	unsigned	has_fsl_erratum_a007792:1;
+	unsigned	has_fsl_erratum_14:1;
+	unsigned	has_fsl_erratum_a005275:1;
 	unsigned	has_fsl_erratum_a005697:1;
-	unsigned        check_phy_clk_valid:1;
+	unsigned	check_phy_clk_valid:1;
 
 	/* register save area for suspend/resume */
 	u32		pm_command;

Re: [PATCH v2 1/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms

[Alan Stern]

On Thu, 17 Jan 2019, Ran Wang wrote:

> arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(), which
> causing compile failure on some Layerscape Platforms (such as LS1021A and
> LS2012A which also integrates FSL EHCI controller). So use
> ioread32be()/iowrite32be() instead to make it workable on both
> powerpc and arm.

For patches 1/3 and 3/3:

Acked-by: Alan Stern <stern@rowland.harvard.edu>

Have you tested these on the Layerscape platforms to make sure they 
work correctly?

Alan Stern

[v2,1/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms

[Alan Stern]

On Thu, 17 Jan 2019, Ran Wang wrote:

> arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(), which
> causing compile failure on some Layerscape Platforms (such as LS1021A and
> LS2012A which also integrates FSL EHCI controller). So use
> ioread32be()/iowrite32be() instead to make it workable on both
> powerpc and arm.

For patches 1/3 and 3/3:

Acked-by: Alan Stern <stern@rowland.harvard.edu>

Have you tested these on the Layerscape platforms to make sure they 
work correctly?

Alan Stern

RE: [PATCH v2 1/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms

[Ran Wang]

Hi Alan,

On January 18, 2019 00:08, Alan Stern wrote:
> 
> On Thu, 17 Jan 2019, Ran Wang wrote:
> 
> > arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(),
> > which causing compile failure on some Layerscape Platforms (such as
> > LS1021A and LS2012A which also integrates FSL EHCI controller). So use
> > ioread32be()/iowrite32be() instead to make it workable on both powerpc
> > and arm.
> 
> For patches 1/3 and 3/3:
> 
> Acked-by: Alan Stern <stern@rowland.harvard.edu>
> 
> Have you tested these on the Layerscape platforms to make sure they work
> correctly?

To be honest, the first goal of this patch set is to fix compile issue. 
And I have verified it on LS1012AQDS, and encountered failure as below:

[    2.966755] ehci-fsl: Freescale EHCI Host controller driver
[    2.973113] fsl-ehci fsl-ehci.0: Freescale On-Chip EHCI Host Controller
[    2.979851] fsl-ehci fsl-ehci.0: new USB bus registered, assigned bus number 3
[    2.987549] fsl-ehci fsl-ehci.0: irq 22, io mem 0x08600000
[    3.005769] fsl-ehci fsl-ehci.0: USB 2.0 started, EHCI 0.00
[    3.012122] hub 3-0:1.0: USB hub found
[    3.016088] hub 3-0:1.0: config failed, hub doesn't have any ports! (err -19)

However, actually the only board which I can find so far has known HW issue on
EHCI part, so I plan to find other platform to do complete verification when
possible. And will submit other fix if needed. Is that OK?

BTW, for powerpc platform, I've tested on a T1042AD4RDB and USB worked fine with it.

Regards,
Ran

[v2,1/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms

[Ran Wang]

Hi Alan,

On January 18, 2019 00:08, Alan Stern wrote:
> 
> On Thu, 17 Jan 2019, Ran Wang wrote:
> 
> > arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(),
> > which causing compile failure on some Layerscape Platforms (such as
> > LS1021A and LS2012A which also integrates FSL EHCI controller). So use
> > ioread32be()/iowrite32be() instead to make it workable on both powerpc
> > and arm.
> 
> For patches 1/3 and 3/3:
> 
> Acked-by: Alan Stern <stern@rowland.harvard.edu>
> 
> Have you tested these on the Layerscape platforms to make sure they work
> correctly?

To be honest, the first goal of this patch set is to fix compile issue. 
And I have verified it on LS1012AQDS, and encountered failure as below:

[    2.966755] ehci-fsl: Freescale EHCI Host controller driver
[    2.973113] fsl-ehci fsl-ehci.0: Freescale On-Chip EHCI Host Controller
[    2.979851] fsl-ehci fsl-ehci.0: new USB bus registered, assigned bus number 3
[    2.987549] fsl-ehci fsl-ehci.0: irq 22, io mem 0x08600000
[    3.005769] fsl-ehci fsl-ehci.0: USB 2.0 started, EHCI 0.00
[    3.012122] hub 3-0:1.0: USB hub found
[    3.016088] hub 3-0:1.0: config failed, hub doesn't have any ports! (err -19)

However, actually the only board which I can find so far has known HW issue on
EHCI part, so I plan to find other platform to do complete verification when
possible. And will submit other fix if needed. Is that OK?

BTW, for powerpc platform, I've tested on a T1042AD4RDB and USB worked fine with it.

Regards,
Ran

RE: [PATCH v2 1/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms

[Alan Stern]

On Fri, 18 Jan 2019, Ran Wang wrote:

> Hi Alan,
> 
> On January 18, 2019 00:08, Alan Stern wrote:
> > 
> > On Thu, 17 Jan 2019, Ran Wang wrote:
> > 
> > > arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(),
> > > which causing compile failure on some Layerscape Platforms (such as
> > > LS1021A and LS2012A which also integrates FSL EHCI controller). So use
> > > ioread32be()/iowrite32be() instead to make it workable on both powerpc
> > > and arm.
> > 
> > For patches 1/3 and 3/3:
> > 
> > Acked-by: Alan Stern <stern@rowland.harvard.edu>
> > 
> > Have you tested these on the Layerscape platforms to make sure they work
> > correctly?
> 
> To be honest, the first goal of this patch set is to fix compile issue. 
> And I have verified it on LS1012AQDS, and encountered failure as below:
> 
> [    2.966755] ehci-fsl: Freescale EHCI Host controller driver
> [    2.973113] fsl-ehci fsl-ehci.0: Freescale On-Chip EHCI Host Controller
> [    2.979851] fsl-ehci fsl-ehci.0: new USB bus registered, assigned bus number 3
> [    2.987549] fsl-ehci fsl-ehci.0: irq 22, io mem 0x08600000
> [    3.005769] fsl-ehci fsl-ehci.0: USB 2.0 started, EHCI 0.00
> [    3.012122] hub 3-0:1.0: USB hub found
> [    3.016088] hub 3-0:1.0: config failed, hub doesn't have any ports! (err -19)
> 
> However, actually the only board which I can find so far has known HW issue on
> EHCI part, so I plan to find other platform to do complete verification when
> possible. And will submit other fix if needed. Is that OK?
> 
> BTW, for powerpc platform, I've tested on a T1042AD4RDB and USB worked fine with it.

Okay, that's good.

Alan Stern

[v2,1/3] usb: ehci: fsl: Update register accessing for arm/arm64 platforms

[Alan Stern]

On Fri, 18 Jan 2019, Ran Wang wrote:

> Hi Alan,
> 
> On January 18, 2019 00:08, Alan Stern wrote:
> > 
> > On Thu, 17 Jan 2019, Ran Wang wrote:
> > 
> > > arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(),
> > > which causing compile failure on some Layerscape Platforms (such as
> > > LS1021A and LS2012A which also integrates FSL EHCI controller). So use
> > > ioread32be()/iowrite32be() instead to make it workable on both powerpc
> > > and arm.
> > 
> > For patches 1/3 and 3/3:
> > 
> > Acked-by: Alan Stern <stern@rowland.harvard.edu>
> > 
> > Have you tested these on the Layerscape platforms to make sure they work
> > correctly?
> 
> To be honest, the first goal of this patch set is to fix compile issue. 
> And I have verified it on LS1012AQDS, and encountered failure as below:
> 
> [    2.966755] ehci-fsl: Freescale EHCI Host controller driver
> [    2.973113] fsl-ehci fsl-ehci.0: Freescale On-Chip EHCI Host Controller
> [    2.979851] fsl-ehci fsl-ehci.0: new USB bus registered, assigned bus number 3
> [    2.987549] fsl-ehci fsl-ehci.0: irq 22, io mem 0x08600000
> [    3.005769] fsl-ehci fsl-ehci.0: USB 2.0 started, EHCI 0.00
> [    3.012122] hub 3-0:1.0: USB hub found
> [    3.016088] hub 3-0:1.0: config failed, hub doesn't have any ports! (err -19)
> 
> However, actually the only board which I can find so far has known HW issue on
> EHCI part, so I plan to find other platform to do complete verification when
> possible. And will submit other fix if needed. Is that OK?
> 
> BTW, for powerpc platform, I've tested on a T1042AD4RDB and USB worked fine with it.

Okay, that's good.

Alan Stern