[PATCH][SVM] Update SVM V_TPR register on CR8 and MMIO accesses to APIC TPR

[PATCH][SVM] Update SVM V_TPR register on CR8 and MMIO accesses to APIC TPR

[Travis Betak]

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This patches ensures that the V_TPR stays in synch with the HVM VLAPIC
by reflecting writes to the TPR via MMIO and CR8 on to the VMCB's V_TPR
member.  Although we currently set IGN_TPR to 1, this code makes sure
that the V_TPR is correct if we ever do otherwise.

If possible, please apply to xen-3.0.4-testing.

Signed-off-by: Travis Betak <travis.betak@amd.com>

   --travis

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# HG changeset patch
# User Travis Betak <travis.betak@amd.com>
# Date 1168370530 21600
# Node ID e822926dd62492282e51c5847a8d85a3d22dda1d
# Parent  d401cb96d8a0da5febe737b86f453a88f1f45bb7
[HVM][SVM] Updated the SVM V_TPR register on MMIO writes to the VLAPIC TPR

The SVM architecture includes a virtual TPR register.  This patch
updates this register on MMIO writes to the HVM Virtual APIC.

VT does not have this register as far as I know so a stub is added in
the VT code.

Signed-off-by: Travis Betak <travis.betak@amd.com>

diff -r d401cb96d8a0 -r e822926dd624 xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c	Mon Jan 29 15:04:58 2007 +0000
+++ b/xen/arch/x86/hvm/svm/svm.c	Tue Jan 09 13:22:10 2007 -0600
@@ -502,6 +502,13 @@ void svm_update_guest_cr3(struct vcpu *v
     v->arch.hvm_svm.vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3; 
 }
 
+static void svm_update_vtpr(struct vcpu *v, unsigned long value)
+{
+    struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
+
+    vmcb->vintr.fields.tpr = value & 0x0f;
+}
+
 unsigned long svm_get_ctrl_reg(struct vcpu *v, unsigned int num)
 {
     switch ( num )
@@ -889,6 +896,8 @@ int start_svm(void)
     hvm_funcs.update_host_cr3 = svm_update_host_cr3;
     hvm_funcs.update_guest_cr3 = svm_update_guest_cr3;
     
+    hvm_funcs.update_vtpr = svm_update_vtpr;
+
     hvm_funcs.stts = svm_stts;
     hvm_funcs.set_tsc_offset = svm_set_tsc_offset;
 
@@ -1837,6 +1846,7 @@ static int mov_to_cr(int gpreg, int cr, 
 
     case 8:
         vlapic_set_reg(vlapic, APIC_TASKPRI, ((value & 0x0F) << 4));
+        vmcb->vintr.fields.tpr = value & 0x0F;
         break;
 
     default:
diff -r d401cb96d8a0 -r e822926dd624 xen/arch/x86/hvm/vlapic.c
--- a/xen/arch/x86/hvm/vlapic.c	Mon Jan 29 15:04:58 2007 +0000
+++ b/xen/arch/x86/hvm/vlapic.c	Tue Jan 09 13:22:10 2007 -0600
@@ -631,6 +631,7 @@ static void vlapic_write(struct vcpu *v,
     {
     case APIC_TASKPRI:
         vlapic_set_reg(vlapic, APIC_TASKPRI, val & 0xff);
+        hvm_update_vtpr(v, (val >> 4) & 0x0f);
         break;
 
     case APIC_EOI:
diff -r d401cb96d8a0 -r e822926dd624 xen/arch/x86/hvm/vmx/vmx.c
--- a/xen/arch/x86/hvm/vmx/vmx.c	Mon Jan 29 15:04:58 2007 +0000
+++ b/xen/arch/x86/hvm/vmx/vmx.c	Tue Jan 09 13:22:10 2007 -0600
@@ -738,6 +738,11 @@ static void vmx_inject_exception(
         v->arch.hvm_vmx.cpu_cr2 = cr2;
 }
 
+static void vmx_update_vtpr(struct vcpu *v, unsigned long value)
+{
+    /* VMX doesn't have a V_TPR field */
+}
+
 /* Setup HVM interfaces */
 static void vmx_setup_hvm_funcs(void)
 {
@@ -762,6 +767,8 @@ static void vmx_setup_hvm_funcs(void)
 
     hvm_funcs.update_host_cr3 = vmx_update_host_cr3;
     hvm_funcs.update_guest_cr3 = vmx_update_guest_cr3;
+
+    hvm_funcs.update_vtpr = vmx_update_vtpr;
 
     hvm_funcs.stts = vmx_stts;
     hvm_funcs.set_tsc_offset = vmx_set_tsc_offset;
diff -r d401cb96d8a0 -r e822926dd624 xen/include/asm-x86/hvm/hvm.h
--- a/xen/include/asm-x86/hvm/hvm.h	Mon Jan 29 15:04:58 2007 +0000
+++ b/xen/include/asm-x86/hvm/hvm.h	Tue Jan 09 13:22:10 2007 -0600
@@ -108,6 +108,11 @@ struct hvm_function_table {
     void (*update_guest_cr3)(struct vcpu *v);
 
     /*
+     * Reflect the virtual APIC's value in the guest's V_TPR register
+     */
+    void (*update_vtpr)(struct vcpu *v, unsigned long value);
+
+    /*
      * Update specifics of the guest state:
      * 1) TS bit in guest cr0 
      * 2) TSC offset in guest
@@ -191,6 +196,12 @@ hvm_update_host_cr3(struct vcpu *v)
 hvm_update_host_cr3(struct vcpu *v)
 {
     hvm_funcs.update_host_cr3(v);
+}
+
+static inline void
+hvm_update_vtpr(struct vcpu *v, unsigned long value)
+{
+    hvm_funcs.update_vtpr(v, value);
 }
 
 void hvm_update_guest_cr3(struct vcpu *v, unsigned long guest_cr3);

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