[U-Boot-Users] Please pull from 'mpc83xx' branch

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Kumar Gala]

Please pull from 'mpc83xx' branch of
git://git.kernel.org/pub/scm/boot/u-boot/galak/u-boot.git

to receive the following updates:

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Wolfgang Denk]

In message <Pine.LNX.4.64.0701301530370.10280@localhost.localdomain> you wrote:
> Please pull from 'mpc83xx' branch of
> git://git.kernel.org/pub/scm/boot/u-boot/galak/u-boot.git
> 
> to receive the following updates:
> 
> >From bec770f7708fde81e96eec3230851c04f8b822db Mon Sep 17 00:00:00 2001
> From: Kumar Gala <galak@kernel.crashing.org>
> Date: Tue, 30 Jan 2007 14:08:30 -0600
> Subject: [PATCH] Replace CONFIG_MPC8349 and use CONFIG_MPC834X instead
> 
> The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all
> MPC834X class processors.  Change the protections from CONFIG_MPC8349 to
> CONFIG_MPC834X so they are more generic.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
>   cpu/mpc83xx/cpu.c             |    2 +-
>   cpu/mpc83xx/speed.c           |    8 ++++----
>   include/asm-ppc/global_data.h |    4 ++--
>   include/asm-ppc/immap_83xx.h  |    2 +-
>   include/mpc83xx.h             |   14 +++++++-------
>   5 files changed, 15 insertions(+), 15 deletions(-)

What about all the other files that reference CONFIG_MPC8349, i. e.

	doc/README.mpc83xxads
	include/configs/MPC8349EMDS.h
	include/configs/TQM834x.h
	include/configs/MPC8349ITX.h

?

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Beauty is transitory." "Beauty survives."
	-- Spock and Kirk, "That Which Survives", stardate unknown

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Timur Tabi]

Wolfgang Denk wrote:

> What about all the other files that reference CONFIG_MPC8349, i. e.
> 
> 	doc/README.mpc83xxads

This file just says that MPC8349EMDS.h defines CONFIG_MPC8349, which is correct.

> 	include/configs/MPC8349EMDS.h
> 	include/configs/TQM834x.h
> 	include/configs/MPC8349ITX.h

These files define, but do not reference, CONFIG_MPC8349.  That is still 
correct, because these boards are all 8349 boards.  These files also already 
define CONFIG_MPC834X, so they should pick up Kumar's changes automatically.

-- 
Timur Tabi
Linux Kernel Developer @ Freescale

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Kumar Gala]

On Jan 30, 2007, at 4:49 PM, Timur Tabi wrote:

> Wolfgang Denk wrote:
>
>> What about all the other files that reference CONFIG_MPC8349, i. e.
>> 	doc/README.mpc83xxads
>
> This file just says that MPC8349EMDS.h defines CONFIG_MPC8349,  
> which is correct.
>
>> 	include/configs/MPC8349EMDS.h
>> 	include/configs/TQM834x.h
>> 	include/configs/MPC8349ITX.h
>
> These files define, but do not reference, CONFIG_MPC8349.  That is  
> still correct, because these boards are all 8349 boards.  These  
> files also already define CONFIG_MPC834X, so they should pick up  
> Kumar's changes automatically.

Yeah, we had this discussion last time I posted the patch and the  
feeling was the leave CONFIG_MPC8349 around since that's what's on  
these boards.

(I did this since I've got a board that is CONFIG_MPC8343 and thus  
didn't define CONFIG_MPC8349 and things broke).

- k

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Wolfgang Denk]

In message <BDB79FE5-1679-42EE-B282-087ED8D923D8@kernel.crashing.org> you wrote:
> 
> > These files define, but do not reference, CONFIG_MPC8349.  That is  
> > still correct, because these boards are all 8349 boards.  These  
> > files also already define CONFIG_MPC834X, so they should pick up  
> > Kumar's changes automatically.
> 
> Yeah, we had this discussion last time I posted the patch and the  
> feeling was the leave CONFIG_MPC8349 around since that's what's on  
> these boards.

OK, understood. Thanks for the explanation.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Uncontrolled power will turn even saints into savages. And we can all
be counted on to live down to our lowest impulses.
	-- Parmen, "Plato's Stepchildren", stardate 5784.3

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Timur Tabi]

Kumar Gala wrote:


> diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
> index eb256e5..d01311d 100644
> --- a/cpu/mpc83xx/cpu_init.c
> +++ b/cpu/mpc83xx/cpu_init.c
> @@ -69,31 +69,52 @@ void cpu_init_f (volatile immap_t * im)
> 
>   #ifdef CFG_ACR_PIPE_DEP
>   	/* Arbiter pipeline depth */
> -	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT);
> +	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
>   #endif
> 
>   #ifdef CFG_SPCR_TSEC1EP
>   	/* TSEC1 Emergency priority */
> -	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT);
> +	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
>   #endif
> 
>   #ifdef CFG_SPCR_TSEC2EP
>   	/* TSEC2 Emergency priority */
> -	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT);
> +	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
>   #endif
> 
> +#ifdef CONFIG_MPC834X
>   #ifdef CFG_SCCR_TSEC1CM
>   	/* TSEC1 clock mode */
> -	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT);
> +	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
>   #endif
>   #ifdef CFG_SCCR_TSEC2CM
>   	/* TSEC2 & I2C1 clock mode */
> -	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT);
> +	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
> +#endif
> +#ifdef CFG_SCCR_USBMPHCM
> +	/* USB MPH clock mode */
> +	im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
> +#endif
> +#endif /* CONFIG_MPC834X */
> +
> +#ifdef CFG_SCCR_PCICM
> +	/* PCI & DMA clock mode */
> +	im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
> +#endif
> +
> +#ifdef CFG_SCCR_USBDRCM
> +	/* USB DR clock mode */
> +	im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
> +#endif
> +
> +#ifdef CFG_SCCR_ENCCM
> +	/* Encryption clock mode */
> +	im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
>   #endif
> 
>   #ifdef CFG_ACR_RPTCNT
>   	/* Arbiter repeat count */
> -	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT));
> +	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
>   #endif

This patch is good.  Kim, please apply.  It fixes bug 292.

However, ....

> diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
> index 5bed2d0..d06b51d 100644
> --- a/include/configs/MPC8349EMDS.h
> +++ b/include/configs/MPC8349EMDS.h
> @@ -60,17 +60,6 @@
>   #endif
>   #endif
> 
> -#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
> -#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
> -#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
> -#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
> -#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
> -#define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
> -				| CFG_SCCR_TSEC1CM	\
> -				| CFG_SCCR_TSEC2CM	\
> -				| CFG_SCCR_ENCCM	\
> -				| CFG_SCCR_USBCM	)

I think your patch omits the new values of CFG_SCCR_TSEC1CM, CFG_SCCR_TSEC2CM, 
CFG_SCCR_ENCCM, and CFG_SCCR_USBCM.  Your changelog says these values are bogus, 
but without defining the macros, the code in cpu_init_f() won't be compiled.

+#define CFG_SCCR_TSEC1CM	1
+#define CFG_SCCR_TSEC2CM	1
+#define CFG_SCCR_ENCCM		3
+#define CFG_SCCR_USBCM		3

> diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
> index 728083b..ed03577 100644
> --- a/include/configs/TQM834x.h
> +++ b/include/configs/TQM834x.h
> @@ -57,17 +57,6 @@
>    */
>   #define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
> 
> -#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
> -#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
> -#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
> -#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
> -#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */

Same here

+#define CFG_SCCR_TSEC1CM	1
+#define CFG_SCCR_TSEC2CM	1
+#define CFG_SCCR_ENCCM		3
+#define CFG_SCCR_USBCM		3

> diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
> index 1876c61..321d3ce 100644
> --- a/include/configs/sbc8349.h
> +++ b/include/configs/sbc8349.h
> @@ -63,17 +63,6 @@
>   #endif
>   #endif
> 
> -#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
> -#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
> -#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
> -#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
> -#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */

And here

+#define CFG_SCCR_TSEC1CM	1
+#define CFG_SCCR_TSEC2CM	1
+#define CFG_SCCR_ENCCM		3
+#define CFG_SCCR_USBCM		3


You can also probably get rid of these macros in mpc83xx.h:

#define SCCR_ENCCM_0			0x00000000
#define SCCR_ENCCM_1			0x01000000
#define SCCR_ENCCM_2			0x02000000
#define SCCR_ENCCM_3			0x03000000
#define SCCR_TSEC1CM_0			0x00000000
#define SCCR_TSEC1CM_1			0x40000000
#define SCCR_TSEC1CM_2			0x80000000
#define SCCR_TSEC1CM_3			0xC0000000
#define SCCR_TSEC2CM_0			0x00000000
#define SCCR_TSEC2CM_1			0x10000000
#define SCCR_TSEC2CM_2			0x20000000
#define SCCR_TSEC2CM_3			0x30000000
#define SCCR_USBCM_0			0x00000000
#define SCCR_USBCM_1			0x00500000
#define SCCR_USBCM_2			0x00A00000
#define SCCR_USBCM_3			0x00F00000


-- 
Timur Tabi
Linux Kernel Developer @ Freescale

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Kumar Gala]

> This patch is good.  Kim, please apply.  It fixes bug 292.
>
> However, ....
>
>> diff --git a/include/configs/MPC8349EMDS.h b/include/configs/ 
>> MPC8349EMDS.h
>> index 5bed2d0..d06b51d 100644
>> --- a/include/configs/MPC8349EMDS.h
>> +++ b/include/configs/MPC8349EMDS.h
>> @@ -60,17 +60,6 @@
>>   #endif
>>   #endif
>> -#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
>> -#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
>> -#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
>> -#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
>> -#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
>> -#define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
>> -				| CFG_SCCR_TSEC1CM	\
>> -				| CFG_SCCR_TSEC2CM	\
>> -				| CFG_SCCR_ENCCM	\
>> -				| CFG_SCCR_USBCM	)
>
> I think your patch omits the new values of CFG_SCCR_TSEC1CM,  
> CFG_SCCR_TSEC2CM, CFG_SCCR_ENCCM, and CFG_SCCR_USBCM.  Your  
> changelog says these values are bogus, but without defining the  
> macros, the code in cpu_init_f() won't be compiled.

This is on purpose, the boards in question are using the default  
value of SCCR and have been.  Kim added the CFG_SCCR_* but it was  
never actually used by the boards.

If someone feels the default value should be changed for the boards,  
it should be a follow on patch to this one.

[snip]

> You can also probably get rid of these macros in mpc83xx.h:
>
> #define SCCR_ENCCM_0			0x00000000
> #define SCCR_ENCCM_1			0x01000000
> #define SCCR_ENCCM_2			0x02000000
> #define SCCR_ENCCM_3			0x03000000
> #define SCCR_TSEC1CM_0			0x00000000
> #define SCCR_TSEC1CM_1			0x40000000
> #define SCCR_TSEC1CM_2			0x80000000
> #define SCCR_TSEC1CM_3			0xC0000000
> #define SCCR_TSEC2CM_0			0x00000000
> #define SCCR_TSEC2CM_1			0x10000000
> #define SCCR_TSEC2CM_2			0x20000000
> #define SCCR_TSEC2CM_3			0x30000000
> #define SCCR_USBCM_0			0x00000000
> #define SCCR_USBCM_1			0x00500000
> #define SCCR_USBCM_2			0x00A00000
> #define SCCR_USBCM_3			0x00F00000

Don't see any harm in having them.

- k

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Timur Tabi]

Kumar Gala wrote:

> This is on purpose, the boards in question are using the default value 
> of SCCR and have been.  Kim added the CFG_SCCR_* but it was never 
> actually used by the boards.

I got an email a way back from someone complaining that because the USB clocks 
were not being initialized on an 8349EMDS, the USB Linux driver was hanging on 
initialization.  I have not seen this myself, and I don't remember who sent the 
email, but whoever did was convinced that programming the clocks fixed the problem.

>> You can also probably get rid of these macros in mpc83xx.h:
>>
>> #define SCCR_ENCCM_0            0x00000000
>> #define SCCR_ENCCM_1            0x01000000
>> #define SCCR_ENCCM_2            0x02000000
>> #define SCCR_ENCCM_3            0x03000000
>> #define SCCR_TSEC1CM_0            0x00000000
>> #define SCCR_TSEC1CM_1            0x40000000
>> #define SCCR_TSEC1CM_2            0x80000000
>> #define SCCR_TSEC1CM_3            0xC0000000
>> #define SCCR_TSEC2CM_0            0x00000000
>> #define SCCR_TSEC2CM_1            0x10000000
>> #define SCCR_TSEC2CM_2            0x20000000
>> #define SCCR_TSEC2CM_3            0x30000000
>> #define SCCR_USBCM_0            0x00000000
>> #define SCCR_USBCM_1            0x00500000
>> #define SCCR_USBCM_2            0x00A00000
>> #define SCCR_USBCM_3            0x00F00000
> 
> Don't see any harm in having them.

Someone might seem them and think they should be used to initialize the clocks. 
  With the changes to cpu_init_f(), these macros will never be used.

-- 
Timur Tabi
Linux Kernel Developer @ Freescale

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Kumar Gala]

On Feb 1, 2007, at 10:06 AM, Timur Tabi wrote:

> Kumar Gala wrote:
>
>> This is on purpose, the boards in question are using the default  
>> value of SCCR and have been.  Kim added the CFG_SCCR_* but it was  
>> never actually used by the boards.
>
> I got an email a way back from someone complaining that because the  
> USB clocks were not being initialized on an 8349EMDS, the USB Linux  
> driver was hanging on initialization.  I have not seen this myself,  
> and I don't remember who sent the email, but whoever did was  
> convinced that programming the clocks fixed the problem.

If that's an issue I'd suggest a follow up patch for it.  I was  
cleaning up the code and leaving the boards in the state I found them :)

>>> You can also probably get rid of these macros in mpc83xx.h:
>>>
>>> #define SCCR_ENCCM_0            0x00000000
>>> #define SCCR_ENCCM_1            0x01000000
>>> #define SCCR_ENCCM_2            0x02000000
>>> #define SCCR_ENCCM_3            0x03000000
>>> #define SCCR_TSEC1CM_0            0x00000000
>>> #define SCCR_TSEC1CM_1            0x40000000
>>> #define SCCR_TSEC1CM_2            0x80000000
>>> #define SCCR_TSEC1CM_3            0xC0000000
>>> #define SCCR_TSEC2CM_0            0x00000000
>>> #define SCCR_TSEC2CM_1            0x10000000
>>> #define SCCR_TSEC2CM_2            0x20000000
>>> #define SCCR_TSEC2CM_3            0x30000000
>>> #define SCCR_USBCM_0            0x00000000
>>> #define SCCR_USBCM_1            0x00500000
>>> #define SCCR_USBCM_2            0x00A00000
>>> #define SCCR_USBCM_3            0x00F00000
>> Don't see any harm in having them.
>
> Someone might seem them and think they should be used to initialize  
> the clocks.  With the changes to cpu_init_f(), these macros will  
> never be used.

I can for see using them if I wanted to set the SCCR in a single  
shot.  Feel free to post a patch to remove them.

Kim asked me to clean up the original patch because of the issues you  
pointed out, that's been done.  Anything beyond that I'll leave up to  
you guys.

- k

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Timur Tabi]

Kumar Gala wrote:

> Kim asked me to clean up the original patch because of the issues you 
> pointed out, that's been done.  Anything beyond that I'll leave up to 
> you guys.

Fair enough.  I just wish I could find that email about USB clocks.

I'll run some tests on the 8349ITX to see what it thinks about the default clocks.

-- 
Timur Tabi
Linux Kernel Developer @ Freescale

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Timur Tabi]

Kumar Gala wrote:

> Ok, I'll fix up the usage of CFG_SCCR_TSEC1M in my tree and leave the 
> other SCCR settings to you.

Ok.

-- 
Timur Tabi
Linux Kernel Developer @ Freescale

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Kumar Gala]

On Dec 14, 2006, at 4:18 PM, Timur Tabi wrote:

> Kumar Gala wrote:
>> Please pull from 'mpc83xx' branch of
>> git://git.kernel.org/pub/scm/boot/u-boot/galak/u-boot.git
>
> Unfortunately, I'm going to have to NACK one of these patches, "Fix  
> config of Arbiter, System Priority, and Clock Mode on MPC83xx".
>
> I just noticed the problem with this patch.  It will work for the  
> 8349ITX, but it will break the 8349EMDS and TQM834x.
>
>>   #ifdef CFG_SCCR_TSEC1CM
>>   	/* TSEC1 clock mode */
>> -	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 <<  
>> SCCR_TSEC1CM_SHIFT);
>> +	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |  
>> (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
>>   #endif
>
> This works as long as CFG_SCCR_TSEC1CM is between 0 and 4.  But  
> look what the MPC8349EMDS.h has:
>
> #define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
> #define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
> #define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
> #define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
> #define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
> #define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
> 				| CFG_SCCR_TSEC1CM	\
> 				| CFG_SCCR_TSEC2CM	\
> 				| CFG_SCCR_ENCCM	\
> 				| CFG_SCCR_USBCM	)
>
> SCCR_TSEC1CM_1 is defined in mpc83xx.h:
>
> #define SCCR_TSEC1CM_1			0x40000000

Ok so we need to fixup the defines of CFG_SCCR_TSEC1M/ 
CFG_SCCR_TSEC2CM to be set to 1 for the boards

> So the patch for mpc83xx/cpu_init.c needs to include changes to  
> MPC8349EMDS.h and TQM834x.h.
>
> But that's not the only problem.  cpu_init_f() does not have any  
> code that uses these two defines in MPC8349EMDS.h and TQM834x.h:
>
> #define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
> #define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
>
> Which means that currently, these bitfields aren't being set at  
> all!  If you try to load the Linux USB driver on an 8349EMDS, the  
> driver will hang at boot time.
>
> I'm working on follow-up patches to fix this.

Ok, I'll fix up the usage of CFG_SCCR_TSEC1M in my tree and leave the  
other SCCR settings to you.

- kumar

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Timur Tabi]

Kumar Gala wrote:
> Please pull from 'mpc83xx' branch of
> git://git.kernel.org/pub/scm/boot/u-boot/galak/u-boot.git

Unfortunately, I'm going to have to NACK one of these patches, "Fix config of 
Arbiter, System Priority, and Clock Mode on MPC83xx".

I just noticed the problem with this patch.  It will work for the 8349ITX, but 
it will break the 8349EMDS and TQM834x.

>   #ifdef CFG_SCCR_TSEC1CM
>   	/* TSEC1 clock mode */
> -	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT);
> +	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
>   #endif

This works as long as CFG_SCCR_TSEC1CM is between 0 and 4.  But look what the 
MPC8349EMDS.h has:

#define CFG_SCCR_INIT		(SCCR_DEFAULT & (~SCCR_CLK_MASK))
#define CFG_SCCR_TSEC1CM	SCCR_TSEC1CM_1	/* TSEC1 clock setting */
#define CFG_SCCR_TSEC2CM	SCCR_TSEC2CM_1	/* TSEC2 clock setting */
#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */
#define CFG_SCCR_VAL		( CFG_SCCR_INIT		\
				| CFG_SCCR_TSEC1CM	\
				| CFG_SCCR_TSEC2CM	\
				| CFG_SCCR_ENCCM	\
				| CFG_SCCR_USBCM	)

SCCR_TSEC1CM_1 is defined in mpc83xx.h:

#define SCCR_TSEC1CM_1			0x40000000

So the patch for mpc83xx/cpu_init.c needs to include changes to MPC8349EMDS.h 
and TQM834x.h.

But that's not the only problem.  cpu_init_f() does not have any code that uses 
these two defines in MPC8349EMDS.h and TQM834x.h:

#define CFG_SCCR_ENCCM		SCCR_ENCCM_3	/* ENC clock setting */
#define CFG_SCCR_USBCM		SCCR_USBCM_3	/* USB clock setting */

Which means that currently, these bitfields aren't being set at all!  If you try 
to load the Linux USB driver on an 8349EMDS, the driver will hang at boot time.

I'm working on follow-up patches to fix this.

-- 
Timur Tabi
Linux Kernel Developer @ Freescale

[U-Boot-Users] Please pull from 'mpc83xx' branch

[Kumar Gala]

Please pull from 'mpc83xx' branch of
git://git.kernel.org/pub/scm/boot/u-boot/galak/u-boot.git

to receive the following updates:

  cpu/mpc83xx/cpu.c             |    2 -
  cpu/mpc83xx/cpu_init.c        |   12 +++----
  cpu/mpc83xx/speed.c           |   12 +++----
  include/asm-ppc/global_data.h |    4 +-
  include/asm-ppc/immap_83xx.h  |   66 +++++++++++++++++++++---------------------
  include/mpc83xx.h             |   10 +++---
  6 files changed, 53 insertions(+), 53 deletions(-)

commit 05bdedd9ecd8819557b111b39309eb1ef9219d16
Author: Kumar Gala <galak@kernel.crashing.org>
Date:   Tue Dec 5 14:35:24 2006 -0600

     Fix config of Arbiter, System Priority, and Clock Mode on MPC83xx

     The config value for:
     * CFG_ACR_PIPE_DEP
     * CFG_ACR_RPTCNT
     * CFG_SPCR_TSEC1EP
     * CFG_SPCR_TSEC2EP
     * CFG_SCCR_TSEC1CM
     * CFG_SCCR_TSEC2CM

     Wasn't not being used when setting the appropriate register

     Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

commit 8a764deca0349437b6030e49fba208ec5d11ccff
Author: Kumar Gala <galak@kernel.crashing.org>
Date:   Tue Dec 5 14:34:51 2006 -0600

     Remove CONFIG_MPC8349 and use CONFIG_MPC834X instead

     CONFIG_MPC8349 is redudant with CONFIG_MPC834X.  Additionally
     CONFIG_MPC834X truly states the class of processors the code
     is applicable for.

     Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 1b51078..7efe7c5 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -97,7 +97,7 @@ int checkcpu(void)
  		return -1;	/* Not sure what this is */
  	}

-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  	printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock));
  #else
  	printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index e5725fb..442937c 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -69,31 +69,31 @@ void cpu_init_f (volatile immap_t * im)

  #ifdef CFG_ACR_PIPE_DEP
  	/* Arbiter pipeline depth */
-	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT);
+	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
  #endif

  #ifdef CFG_SPCR_TSEC1EP
  	/* TSEC1 Emergency priority */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT);
+	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
  #endif

  #ifdef CFG_SPCR_TSEC2EP
  	/* TSEC2 Emergency priority */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT);
+	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
  #endif

  #ifdef CFG_SCCR_TSEC1CM
  	/* TSEC1 clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT);
+	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
  #endif
  #ifdef CFG_SCCR_TSEC2CM
  	/* TSEC2 & I2C1 clock mode */
-	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT);
+	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
  #endif

  #ifdef CFG_ACR_RPTCNT
  	/* Arbiter repeat count */
-	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT));
+	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
  #endif

  	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 7e53b1e..d0fe34a 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -99,7 +99,7 @@ int get_clocks(void)
  	u32 lcrr;

  	u32 csb_clk;
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  	u32 tsec1_clk;
  	u32 tsec2_clk;
  	u32 usbmph_clk;
@@ -144,7 +144,7 @@ #endif

  	sccr = im->clk.sccr;

-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
  	case 0:
  		tsec1_clk = 0;
@@ -249,7 +249,7 @@ #endif
  		/* unkown SCCR_ENCCM value */
  		return -6;
  	}
-#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8360)
  	lbiu_clk = csb_clk *
  	           (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
  #else
@@ -266,7 +266,7 @@ #endif
  		/* unknown lcrr */
  		return -10;
  	}
-#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8360)
  	ddr_clk = csb_clk *
  		  (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
  	corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
@@ -314,7 +314,7 @@ #if defined (CONFIG_MPC8360)
  #endif

  	gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  	gd->tsec1_clk = tsec1_clk;
  	gd->tsec2_clk = tsec2_clk;
  	gd->usbmph_clk = usbmph_clk;
@@ -364,7 +364,7 @@ #endif
  	printf("  SEC:                 %4d MHz\n", gd->enc_clk / 1000000);
  	printf("  I2C1:                %4d MHz\n", gd->i2c1_clk / 1000000);
  	printf("  I2C2:                %4d MHz\n", gd->i2c2_clk / 1000000);
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
  	printf("  TSEC1:               %4d MHz\n", gd->tsec1_clk / 1000000);
  	printf("  TSEC2:               %4d MHz\n", gd->tsec2_clk / 1000000);
  	printf("  USB MPH:             %4d MHz\n", gd->usbmph_clk / 1000000);
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 8bc61b6..c113b7e 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -52,12 +52,12 @@ #endif
  #if defined(CONFIG_MPC83XX)
  	/* There are other clocks in the MPC83XX */
  	u32 csb_clk;
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  	u32 tsec1_clk;
  	u32 tsec2_clk;
  	u32 usbmph_clk;
  	u32 usbdr_clk;
-#endif /* CONFIG_MPC8349 */
+#endif /* CONFIG_MPC834X */
  	u32 core_clk;
  	u32 i2c1_clk;
  	u32 i2c2_clk;
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 43cde5e..b6f5bc4 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -90,7 +90,7 @@ #define SPCR_TBEN     0x00400000	/* E300
  #define SPCR_TBEN_SHIFT		(31-9)
  #define SPCR_COREPR   0x00300000	/* E300 PowerPC Core system bus request priority. */
  #define SPCR_COREPR_SHIFT	(31-11)
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SPCR_TSEC1DP  0x00003000	/* TSEC1 data priority. */
  #define SPCR_TSEC1DP_SHIFT	(31-19)
  #define SPCR_TSEC1BDP 0x00000C00	/* TSEC1 buffer descriptor priority. */
@@ -110,7 +110,7 @@ #elif defined (CONFIG_MPC8360)
  #define SPCR_RES      ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR)
  #endif
  	u32 sicrl;		/* System General Purpose Register Low */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SICRL_LDP_A   0x80000000
  #define SICRL_USB1    0x40000000
  #define SICRL_USB0    0x20000000
@@ -143,7 +143,7 @@ #define SICRL_RES     ~(SICRL_LDP_A | SI
  #endif
  	u32 sicrh;		/* System General Purpose Register High */
  #define SICRH_DDR     0x80000000
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SICRH_TSEC1_A 0x10000000
  #define SICRH_TSEC1_B 0x08000000
  #define SICRH_TSEC1_C 0x04000000
@@ -314,7 +314,7 @@ #define SICVR_IVECX 0xfc000000	/*  Inter
  #define SICVR_IVEC  0x0000007f	/*  Interrupt vector  */
  #define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
  	u32 sipnr_h;		/*  System Internal Interrupt Pending Register - High (SIPNR_H)	 */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SIIH_TSEC1TX 0x80000000 /*  TSEC1 Tx interrupt	*/
  #define SIIH_TSEC1RX 0x40000000 /*  TSEC1 Rx interrupt	*/
  #define SIIH_TSEC1ER 0x20000000 /*  TSEC1 Eror interrupt  */
@@ -333,7 +333,7 @@ #define SIIH_UART2   0x00000040 /*  UART
  #define SIIH_SEC     0x00000020 /*  SEC interrupt  */
  #define SIIH_I2C1    0x00000004 /*  I2C1 interrupt  */
  #define SIIH_I2C2    0x00000002 /*  I2C2 interrupt  */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SIIH_SPI     0x00000001 /*  SPI interrupt  */
  #define SIIH_RES	~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
  			| SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
@@ -349,7 +349,7 @@ #endif
  #define SIIL_RTCS  0x80000000	/*  RTC SECOND interrupt  */
  #define SIIL_PIT   0x40000000	/*  PIT interrupt  */
  #define SIIL_PCI1  0x20000000	/*  PCI1 interrupt  */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SIIL_PCI2  0x10000000	/*  PCI2 interrupt  */
  #endif
  #define SIIL_RTCA  0x08000000	/*  RTC ALARM interrupt	 */
@@ -358,7 +358,7 @@ #define SIIL_SBA   0x02000000	/*  System
  #define SIIL_DMA   0x01000000	/*  DMA interrupt  */
  #define SIIL_GTM4  0x00800000	/*  GTM4 interrupt  */
  #define SIIL_GTM8  0x00400000	/*  GTM8 interrupt  */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SIIL_GPIO1 0x00200000	/*  GPIO1 interrupt  */
  #define SIIL_GPIO2 0x00100000	/*  GPIO2 interrupt  */
  #endif
@@ -376,7 +376,7 @@ #define SIIL_GTM7  0x00000400	/*  GTM7 i
  #define SIIL_GTM1  0x00000020	/*  GTM1 interrupt  */
  #define SIIL_GTM5  0x00000010	/*  GTM5 interrupt  */
  #define SIIL_DPTC  0x00000001	/*  DPTC interrupt (!!! Invisible for user !!!)	 */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SIIL_RES	~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
  			| SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
  			| SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
@@ -444,7 +444,7 @@ #define SECNR_RES	~( SECNR_MIXB0T | SECN
  #define SERR_IRQ0 0x80000000	/*  IRQ0 MCP request  */
  #define SERR_WDT  0x40000000	/*  WDT MCP request  */
  #define SERR_SBA  0x20000000	/*  SBA MCP request  */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SERR_DDR  0x10000000	/*  DDR MCP request  */
  #define SERR_LBC  0x08000000	/*  LBC MCP request  */
  #define SERR_PCI1 0x04000000	/*  PCI1 MCP request  */
@@ -457,7 +457,7 @@ #define SERR_PCI  0x04000000	/*  PCI MCP
  #endif
  #define SERR_MU	  0x01000000	/*  MU MCP request  */
  #define SERR_RNC  0x00010000	/*  MU MCP request (!!! Non-visible for users !!!)  */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SERR_RES	~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
  			|SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
  			|SERR_RNC )
@@ -540,7 +540,7 @@ #define RCWL_LBIUCM  0x80000000 /* LBIUC
  #define RCWL_LBIUCM_SHIFT    31
  #define RCWL_DDRCM   0x40000000 /* DDRCM  */
  #define RCWL_DDRCM_SHIFT     30
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define RCWL_SVCOD   0x30000000 /* SVCOD  */
  #endif
  #define RCWL_SPMF    0x0f000000 /* SPMF	 */
@@ -552,7 +552,7 @@ #define RCWL_CEPDF   0x00000020 /* CEPDF
  #define RCWL_CEPDF_SHIFT      5
  #define RCWL_CEPMF   0x0000001F /* CEPMF  */
  #define RCWL_CEPMF_SHIFT      0
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
  #elif defined (CONFIG_MPC8360)
  #define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF)
@@ -560,7 +560,7 @@ #endif
  	u32 rcwh;		/* RCHL Register  */
  #define RCWH_PCIHOST 0x80000000 /* PCIHOST  */
  #define RCWH_PCIHOST_SHIFT   31
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define RCWH_PCI64   0x40000000 /* PCI64  */
  #define RCWH_PCI1ARB 0x20000000 /* PCI1ARB  */
  #define RCWH_PCI2ARB 0x10000000 /* PCI2ARB  */
@@ -573,7 +573,7 @@ #define RCWH_BMS     0x04000000 /* BMS	*
  #define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ  */
  #define RCWH_SWEN    0x00800000 /* SWEN	 */
  #define RCWH_ROMLOC  0x00700000 /* ROMLOC  */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define RCWH_TSEC1M  0x0000c000 /* TSEC1M  */
  #define RCWH_TSEC2M  0x00003000 /* TSEC2M  */
  #define RCWH_TPR     0x00000100 /* TPR	*/
@@ -582,7 +582,7 @@ #define RCWH_SDDRIOE  0x00000010	/* Seco
  #endif
  #define RCWH_TLE     0x00000008 /* TLE	*/
  #define RCWH_LALE    0x00000004 /* LALE	 */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define RCWH_RES	~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
  			| RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
  			| RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
@@ -637,7 +637,7 @@ typedef struct clk83xx {
  	u32 spmr;		/* system PLL mode Register  */
  #define SPMR_LBIUCM  0x80000000 /* LBIUCM  */
  #define SPMR_DDRCM   0x40000000 /* DDRCM  */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SPMR_SVCOD   0x30000000 /* SVCOD  */
  #endif
  #define SPMR_SPMF    0x0F000000 /* SPMF	 */
@@ -647,7 +647,7 @@ #define SPMR_COREPLL 0x007F0000 /* COREP
  #define SPMR_CEVCOD  0x000000C0 /* CEVCOD  */
  #define SPMR_CEPDF   0x00000020 /* CEPDF  */
  #define SPMR_CEPMF   0x0000001F /* CEPMF  */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SPMR_RES	~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
  			| SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
  			| SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
@@ -660,7 +660,7 @@ #endif
  #define OCCR_PCICOE0 0x80000000 /* PCICOE0  */
  #define OCCR_PCICOE1 0x40000000 /* PCICOE1  */
  #define OCCR_PCICOE2 0x20000000 /* PCICOE2  */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define OCCR_PCICOE3 0x10000000 /* PCICOE3  */
  #define OCCR_PCICOE4 0x08000000 /* PCICOE4  */
  #define OCCR_PCICOE5 0x04000000 /* PCICOE5  */
@@ -670,7 +670,7 @@ #endif
  #define OCCR_PCICD0  0x00800000 /* PCICD0  */
  #define OCCR_PCICD1  0x00400000 /* PCICD1  */
  #define OCCR_PCICD2  0x00200000 /* PCICD2  */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define OCCR_PCICD3  0x00100000 /* PCICD3  */
  #define OCCR_PCICD4  0x00080000 /* PCICD4  */
  #define OCCR_PCICD5  0x00040000 /* PCICD5  */
@@ -691,7 +691,7 @@ #define OCCR_RES	~(OCCR_PCICOE0|OCCR_PCI
  			|OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR )
  #endif
  	u32 sccr;		/* system clock control Register  */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SCCR_TSEC1CM  0xc0000000	/* TSEC1CM  */
  #define SCCR_TSEC1CM_SHIFT 30
  #define SCCR_TSEC2CM  0x30000000	/* TSEC2CM  */
@@ -699,14 +699,14 @@ #define SCCR_TSEC2CM_SHIFT 28
  #endif
  #define SCCR_ENCCM    0x03000000	/* ENCCM  */
  #define SCCR_ENCCM_SHIFT 24
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SCCR_USBMPHCM 0x00c00000	/* USBMPHCM  */
  #define SCCR_USBMPHCM_SHIFT 22
  #define SCCR_USBDRCM  0x00300000	/* USBDRCM  */
  #define SCCR_USBDRCM_SHIFT 20
  #endif
  #define SCCR_PCICM    0x00010000	/* PCICM  */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define SCCR_RES	~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
  			| SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
  #endif
@@ -726,7 +726,7 @@ #define PMCCR_DLPEN 0x00000002	/* DDR SD
  #if defined (CONFIG_MPC8360)
  #define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable	 */
  #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN)
-#elif defined (CONFIG_MPC8349)
+#elif defined (CONFIG_MPC834X)
  #define PMCCR_RES    ~(PMCCR_SLPEN | PMCCR_DLPEN)
  #endif
  	u32 pmcer;		/* PMC Event Register  */
@@ -738,7 +738,7 @@ #define PMCMR_RES ~(PMCMR_PMCIE)
  	u8 res0[0xF4];
  } pmc83xx_t;

-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  /*
   * general purpose I/O module
   */
@@ -1173,7 +1173,7 @@ #define LCRR_CLKDIV_SHIFT     0
  	u8 res8[0xF00];
  } lbus83xx_t;

-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  /*
   * Serial Peripheral Interface
   */
@@ -1403,18 +1403,18 @@ #define EATCR_ES_MASK		0x000f0000	/* err
  #define EATCR_ES_EM		0x00000000	/* external master */
  #define EATCR_ES_DMA		0x00050000
  #define EATCR_CMD_MASK		0x0000f000
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define EATCR_HBE_MASK		0x00000f00	/* PCI high byte enable */
  #endif
  #define EATCR_BE_MASK		0x000000f0	/* PCI byte enable */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define EATCR_HPB		0x00000004	/* high parity bit */
  #endif
  #define EATCR_PB		0x00000002	/* parity bit */
  #define EATCR_VI		0x00000001	/* error information valid */
  	u32 eacr;
  	u32 eeacr;
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  	u32 edlcr;
  	u32 edhcr;
  #elif defined (CONFIG_MPC8360)
@@ -1477,7 +1477,7 @@ #define PIWAR_IWS_1G	0x0000001D
  #define PIWAR_IWS_2G	0x0000001E
  } pcictrl83xx_t;

-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  /*
   * USB
   */
@@ -1988,7 +1988,7 @@ typedef struct immap {
  	reset83xx_t reset;	/* Reset Module */
  	clk83xx_t clk;		/* System Clock Module */
  	pmc83xx_t pmc;		/* Power Management Control Module */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  	gpio83xx_t pgio[2];	/* general purpose I/O module */
  #elif defined (CONFIG_MPC8360)
  	qepi83xx_t qepi;	/* QE Ports Interrupts Registers */
@@ -1999,7 +1999,7 @@ #if defined (CONFIG_MPC8360)
  #endif
  	u8 DDL_DDR[0x100];
  	u8 DDL_LBIU[0x100];
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  	u8 res1[0xE00];
  #elif defined (CONFIG_MPC8360)
  	u8 res1[0x200];
@@ -2010,7 +2010,7 @@ #endif
  	fsl_i2c_t i2c[2];	/* I2C Controllers */
  	u8 res2[0x1300];
  	duart83xx_t duart[2];	/* DUART */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  	u8 res3[0x900];
  	lbus83xx_t lbus;	/* Local Bus Controller Registers */
  	u8 res4[0x1000];
@@ -2022,7 +2022,7 @@ #elif defined (CONFIG_MPC8360)
  	u8 res4[0x2000];
  #endif
  	dma83xx_t dma;		/* DMA */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  	pciconf83xx_t pci_conf[2];	/* PCI Software Configuration Registers */
  	ios83xx_t ios;		/* Sequencer */
  	pcictrl83xx_t pci_ctrl[2];	/* PCI Controller Control and Status Registers */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 03dd0ca..005c043 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -140,7 +140,7 @@ #define BR_ATOM_SHIFT		2
  #endif
  #define BR_V		0x00000001
  #define BR_V_SHIFT		 0
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define BR_RES		~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
  #elif defined (CONFIG_MPC8360)
  #define BR_RES		~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V)
@@ -227,7 +227,7 @@ #define OR_SDRAM_EAD_SHIFT      0
  #define HRCWH_PCI_AGENT              0x00000000
  #define HRCWH_PCI_HOST               0x80000000

-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define HRCWH_32_BIT_PCI             0x00000000
  #define HRCWH_64_BIT_PCI             0x40000000
  #endif
@@ -235,7 +235,7 @@ #endif
  #define HRCWH_PCI1_ARBITER_DISABLE   0x00000000
  #define HRCWH_PCI1_ARBITER_ENABLE    0x20000000

-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define HRCWH_PCI2_ARBITER_DISABLE   0x00000000
  #define HRCWH_PCI2_ARBITER_ENABLE    0x10000000
  #elif defined (CONFIG_MPC8360)
@@ -258,14 +258,14 @@ #define HRCWH_SW_WATCHDOG_ENABLE     0x0

  #define HRCWH_ROM_LOC_DDR_SDRAM      0x00000000
  #define HRCWH_ROM_LOC_PCI1           0x00100000
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define HRCWH_ROM_LOC_PCI2           0x00200000
  #endif
  #define HRCWH_ROM_LOC_LOCAL_8BIT     0x00500000
  #define HRCWH_ROM_LOC_LOCAL_16BIT    0x00600000
  #define HRCWH_ROM_LOC_LOCAL_32BIT    0x00700000

-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
  #define HRCWH_TSEC1M_IN_RGMII        0x00000000
  #define HRCWH_TSEC1M_IN_RTBI         0x00004000
  #define HRCWH_TSEC1M_IN_GMII         0x00008000