* [PATCH 0/4] riscv: Add enhanced PMP support
@ 2020-08-08 8:56 ` Hou Weiying
0 siblings, 0 replies; 6+ messages in thread
From: Hou Weiying @ 2020-08-08 8:56 UTC (permalink / raw)
To: qemu-riscv, qemu-devel; +Cc: Alistair.Francis, palmer, sagark, kbastian
The ePMP can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2
Hou Weiying (4):
Define ePMP mseccfg
Implementation of enhanced PMP(ePMP) support
Add ePMP CSR accesses
Add a config option for ePMP.
target/riscv/cpu.c | 9 ++
target/riscv/cpu.h | 3 +
target/riscv/cpu_bits.h | 3 +
target/riscv/csr.c | 18 ++++
target/riscv/gdbstub.c | 2 +
target/riscv/pmp.c | 174 +++++++++++++++++++++++++++++++++++---
target/riscv/pmp.h | 12 +++
target/riscv/trace-events | 4 +
8 files changed, 213 insertions(+), 12 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 0/4] riscv: Add enhanced PMP support
@ 2020-08-08 8:56 ` Hou Weiying
0 siblings, 0 replies; 6+ messages in thread
From: Hou Weiying @ 2020-08-08 8:56 UTC (permalink / raw)
To: qemu-riscv, qemu-devel; +Cc: palmer, Alistair.Francis, sagark, kbastian
The ePMP can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2
Hou Weiying (4):
Define ePMP mseccfg
Implementation of enhanced PMP(ePMP) support
Add ePMP CSR accesses
Add a config option for ePMP.
target/riscv/cpu.c | 9 ++
target/riscv/cpu.h | 3 +
target/riscv/cpu_bits.h | 3 +
target/riscv/csr.c | 18 ++++
target/riscv/gdbstub.c | 2 +
target/riscv/pmp.c | 174 +++++++++++++++++++++++++++++++++++---
target/riscv/pmp.h | 12 +++
target/riscv/trace-events | 4 +
8 files changed, 213 insertions(+), 12 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 0/4] riscv: Add enhanced PMP support
@ 2020-08-08 9:09 ` Hongzheng-Li
0 siblings, 0 replies; 6+ messages in thread
From: Hongzheng-Li @ 2020-08-08 9:09 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Hou Weiying, Alistair.Francis, palmer, sagark, kbastian
From: Hou Weiying <weiying_hou@outlook.com>
The ePMP can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2
Hou Weiying (4):
Define ePMP mseccfg
Implementation of enhanced PMP(ePMP) support
Add ePMP CSR accesses
Add a config option for ePMP.
target/riscv/cpu.c | 9 ++
target/riscv/cpu.h | 3 +
target/riscv/cpu_bits.h | 3 +
target/riscv/csr.c | 18 ++++
target/riscv/gdbstub.c | 2 +
target/riscv/pmp.c | 174 +++++++++++++++++++++++++++++++++++---
target/riscv/pmp.h | 12 +++
target/riscv/trace-events | 4 +
8 files changed, 213 insertions(+), 12 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 0/4] riscv: Add enhanced PMP support
@ 2020-08-08 9:09 ` Hongzheng-Li
0 siblings, 0 replies; 6+ messages in thread
From: Hongzheng-Li @ 2020-08-08 9:09 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, Alistair.Francis, sagark, kbastian, Hou Weiying
From: Hou Weiying <weiying_hou@outlook.com>
The ePMP can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2
Hou Weiying (4):
Define ePMP mseccfg
Implementation of enhanced PMP(ePMP) support
Add ePMP CSR accesses
Add a config option for ePMP.
target/riscv/cpu.c | 9 ++
target/riscv/cpu.h | 3 +
target/riscv/cpu_bits.h | 3 +
target/riscv/csr.c | 18 ++++
target/riscv/gdbstub.c | 2 +
target/riscv/pmp.c | 174 +++++++++++++++++++++++++++++++++++---
target/riscv/pmp.h | 12 +++
target/riscv/trace-events | 4 +
8 files changed, 213 insertions(+), 12 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 0/4] riscv: Add enhanced PMP support
@ 2020-08-08 5:20 ` Hou Weiying
0 siblings, 0 replies; 6+ messages in thread
From: Hou Weiying @ 2020-08-08 5:20 UTC (permalink / raw)
To: qemu-riscv, qemu-devel; +Cc: Alistair.Francis, palmer, sagark, kbastian
The ePMP can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2
Hou Weiying (4):
Define ePMP mseccfg
Implementation of enhanced PMP(ePMP) support
Add ePMP CSR accesses
Add a config option for ePMP.
target/riscv/cpu.c | 9 ++
target/riscv/cpu.h | 3 +
target/riscv/cpu_bits.h | 3 +
target/riscv/csr.c | 18 ++++
target/riscv/gdbstub.c | 2 +
target/riscv/pmp.c | 174 +++++++++++++++++++++++++++++++++++---
target/riscv/pmp.h | 12 +++
target/riscv/trace-events | 4 +
8 files changed, 213 insertions(+), 12 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 0/4] riscv: Add enhanced PMP support
@ 2020-08-08 5:20 ` Hou Weiying
0 siblings, 0 replies; 6+ messages in thread
From: Hou Weiying @ 2020-08-08 5:20 UTC (permalink / raw)
To: qemu-riscv, qemu-devel; +Cc: palmer, Alistair.Francis, sagark, kbastian
The ePMP can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8/edit#heading=h.9wsr1lnxtwe2
Hou Weiying (4):
Define ePMP mseccfg
Implementation of enhanced PMP(ePMP) support
Add ePMP CSR accesses
Add a config option for ePMP.
target/riscv/cpu.c | 9 ++
target/riscv/cpu.h | 3 +
target/riscv/cpu_bits.h | 3 +
target/riscv/csr.c | 18 ++++
target/riscv/gdbstub.c | 2 +
target/riscv/pmp.c | 174 +++++++++++++++++++++++++++++++++++---
target/riscv/pmp.h | 12 +++
target/riscv/trace-events | 4 +
8 files changed, 213 insertions(+), 12 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-08-08 13:03 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2020-08-08 8:56 [PATCH 0/4] riscv: Add enhanced PMP support Hou Weiying
2020-08-08 8:56 ` Hou Weiying
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2020-08-08 9:09 Hongzheng-Li
2020-08-08 9:09 ` Hongzheng-Li
2020-08-08 5:20 Hou Weiying
2020-08-08 5:20 ` Hou Weiying
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