[PATCH 10/21] drm/amd/display: Add back code to allow for rounding error

[PATCH 10/21] drm/amd/display: Add back code to allow for rounding error

[Harry Wentland]

From: Anthony Koo <Anthony.Koo@amd.com>

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 4887c888bbe7..abd5c9374eb3 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -896,6 +896,17 @@ bool mod_freesync_is_valid_range(struct mod_freesync *mod_freesync,
 	unsigned long long nominal_field_rate_in_uhz =
 			mod_freesync_calc_nominal_field_rate(stream);
 
+	/* Allow for some rounding error of actual video timing by taking ceil.
+	 * For example, 144 Hz mode timing may actually be 143.xxx Hz when
+	 * calculated from pixel rate and vertical/horizontal totals, but
+	 * this should be allowed instead of blocking FreeSync.
+	 */
+	nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz, 1000000);
+	min_refresh_cap_in_uhz /= 1000000;
+	max_refresh_cap_in_uhz /= 1000000;
+	min_refresh_request_in_uhz /= 1000000;
+	max_refresh_request_in_uhz /= 1000000;
+
 	// Check nominal is within range
 	if (nominal_field_rate_in_uhz > max_refresh_cap_in_uhz ||
 		nominal_field_rate_in_uhz < min_refresh_cap_in_uhz)
@@ -921,7 +932,7 @@ bool mod_freesync_is_valid_range(struct mod_freesync *mod_freesync,
 
 	// For variable range, check for at least 10 Hz range
 	if ((max_refresh_request_in_uhz != min_refresh_request_in_uhz) &&
-		(max_refresh_request_in_uhz - min_refresh_request_in_uhz < 10000000))
+		(max_refresh_request_in_uhz - min_refresh_request_in_uhz < 10))
 		return false;
 
 	return true;
-- 
2.15.1

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[PATCH 15/21] drm/amd/display: HDMI has no sound after Panel power off/on

[Harry Wentland]

From: Charlene Liu <charlene.liu@amd.com>

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index 07c32421c226..84e26c894046 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -718,6 +718,8 @@ static void dce110_stream_encoder_update_hdmi_info_packets(
 		if (info_frame->avi.valid) {
 			const uint32_t *content =
 				(const uint32_t *) &info_frame->avi.sb[0];
+			/*we need turn on clock before programming AFMT block*/
+			REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
 
 			REG_WRITE(AFMT_AVI_INFO0, content[0]);
 
-- 
2.15.1

[PATCH 21/21] drm/amd/display: Use dig enable to determine fast boot optimization.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Linux doesn't know lid state, better to check dig enable
value from register.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_stream.h         |  1 -
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  |  6 ++-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  |  2 +
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 47 +++++++---------------
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   |  1 +
 5 files changed, 21 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 5f215ca38c07..046e87aa699a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -98,7 +98,6 @@ struct dc_stream_state {
 	int phy_pix_clk;
 	enum signal_type signal;
 	bool dpms_off;
-	bool lid_state_closed;
 
 	struct dc_stream_status status;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 8167cad7bcf7..dbe3b26b6d9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -113,6 +113,7 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = {
 	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
 	.enable_hpd = dce110_link_encoder_enable_hpd,
 	.disable_hpd = dce110_link_encoder_disable_hpd,
+	.is_dig_enabled = dce110_is_dig_enabled,
 	.destroy = dce110_link_encoder_destroy
 };
 
@@ -535,8 +536,9 @@ void dce110_psr_program_secondary_packet(struct link_encoder *enc,
 		DP_SEC_GSP0_PRIORITY, 1);
 }
 
-static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
+bool dce110_is_dig_enabled(struct link_encoder *enc)
 {
+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 	uint32_t value;
 
 	REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
@@ -1031,7 +1033,7 @@ void dce110_link_encoder_disable_output(
 	struct bp_transmitter_control cntl = { 0 };
 	enum bp_result result;
 
-	if (!is_dig_enabled(enc110)) {
+	if (!dce110_is_dig_enabled(enc)) {
 		/* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
 		return;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 0ec3433d34b6..347069461a22 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -263,4 +263,6 @@ void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
 void dce110_psr_program_secondary_packet(struct link_encoder *enc,
 			unsigned int sdp_transmit_line_num_deadline);
 
+bool dce110_is_dig_enabled(struct link_encoder *enc);
+
 #endif /* __DC_LINK_ENCODER__DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 9e1a8823d3d8..5dbd4335cd6e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1481,15 +1481,15 @@ static void disable_vga_and_power_gate_all_controllers(
 	}
 }
 
-static bool is_eDP_lid_closed(struct dc_state *context)
+static struct dc_link *get_link_for_edp(struct dc *dc)
 {
 	int i;
 
-	for (i = 0; i < context->stream_count; i++) {
-		if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
-			return context->streams[i]->lid_state_closed;
+	for (i = 0; i < dc->link_count; i++) {
+		if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
+			return dc->links[i];
 	}
-	return false;
+	return NULL;
 }
 
 static struct dc_link *get_link_for_edp_not_in_use(
@@ -1526,41 +1526,22 @@ static struct dc_link *get_link_for_edp_not_in_use(
  */
 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
 {
-	/* check eDP lid state and BIOS_SCRATCH_3 to determine fast boot optimization
-	 * UEFI boot
-	 *				edp_active_status_from_scratch		fast boot optimization
-	 * S4/S5 resume:
-	 * Lid Open		true								true
-	 * Lid Close	false								false
-	 *
-	 * S3/ resume:
-	 * Lid Open		false								false
-	 * Lid Close	false								false
-	 *
-	 * Legacy boot:
-	 *				edp_active_status_from_scratch		fast boot optimization
-	 * S4/S resume:
-	 * Lid Open		true								true
-	 * Lid Close	true								false
-	 *
-	 * S3/ resume:
-	 * Lid Open		false								false
-	 * Lid Close	false								false
-	 */
-	struct dc_bios *dcb = dc->ctx->dc_bios;
-	bool lid_state_closed = is_eDP_lid_closed(context);
 	struct dc_link *edp_link_to_turnoff = NULL;
-	bool edp_active_status_from_scratch =
-			(dcb->funcs->get_vga_enabled_displays(dc->ctx->dc_bios) == ATOM_DISPLAY_LCD1_ACTIVE);
+	struct dc_link *edp_link = get_link_for_edp(dc);
+	bool can_eDP_fast_boot_optimize = false;
+
+	if (edp_link) {
+		can_eDP_fast_boot_optimize =
+				edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc);
+	}
 
-	/*Lid open*/
-	if (!lid_state_closed) {
+	if (can_eDP_fast_boot_optimize) {
 		edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);
 
 		/* if OS doesn't light up eDP and eDP link is available, we want to disable
 		 * If resume from S4/S5, should optimization.
 		 */
-		if (!edp_link_to_turnoff && edp_active_status_from_scratch)
+		if (!edp_link_to_turnoff)
 			dc->apply_edp_fast_boot_optimization = true;
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 54d8a1386142..cf6df2e7beb2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -149,6 +149,7 @@ struct link_encoder_funcs {
 		bool connect);
 	void (*enable_hpd)(struct link_encoder *enc);
 	void (*disable_hpd)(struct link_encoder *enc);
+	bool (*is_dig_enabled)(struct link_encoder *enc);
 	void (*destroy)(struct link_encoder **enc);
 };
 
-- 
2.15.1

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Re: [PATCH 10/21] drm/amd/display: Add back code to allow for rounding error

[Nils Wallménius]

[-- Attachment #1.1: Type: text/plain, Size: 2717 bytes --]

Den tis 10 apr. 2018 23:11Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org> skrev:

> From: Anthony Koo <Anthony.Koo-5C7GfCeVMHo@public.gmane.org>
>
> Signed-off-by: Anthony Koo <Anthony.Koo-5C7GfCeVMHo@public.gmane.org>
> Reviewed-by: Aric Cyr <Aric.Cyr-5C7GfCeVMHo@public.gmane.org>
> Acked-by: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> index 4887c888bbe7..abd5c9374eb3 100644
> --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
> @@ -896,6 +896,17 @@ bool mod_freesync_is_valid_range(struct mod_freesync
> *mod_freesync,
>         unsigned long long nominal_field_rate_in_uhz =
>                         mod_freesync_calc_nominal_field_rate(stream);
>
> +       /* Allow for some rounding error of actual video timing by taking
> ceil.
> +        * For example, 144 Hz mode timing may actually be 143.xxx Hz when
> +        * calculated from pixel rate and vertical/horizontal totals, but
> +        * this should be allowed instead of blocking FreeSync.
> +        */
>

Hi, with this change the var names ending in *_in_uhz are a bit confusing,
also the integer division will not round up (take ceil) as seems to be the
intention from the above comment. Perhaps the comment needs to be improved?

BR
Nils


+       nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz,
> 1000000);
> +       min_refresh_cap_in_uhz /= 1000000;
> +       max_refresh_cap_in_uhz /= 1000000;
> +       min_refresh_request_in_uhz /= 1000000;
> +       max_refresh_request_in_uhz /= 1000000;
> +
>         // Check nominal is within range
>         if (nominal_field_rate_in_uhz > max_refresh_cap_in_uhz ||
>                 nominal_field_rate_in_uhz < min_refresh_cap_in_uhz)
> @@ -921,7 +932,7 @@ bool mod_freesync_is_valid_range(struct mod_freesync
> *mod_freesync,
>
>         // For variable range, check for at least 10 Hz range
>         if ((max_refresh_request_in_uhz != min_refresh_request_in_uhz) &&
> -               (max_refresh_request_in_uhz - min_refresh_request_in_uhz <
> 10000000))
> +               (max_refresh_request_in_uhz - min_refresh_request_in_uhz <
> 10))
>                 return false;
>
>         return true;
> --
> 2.15.1
>
> _______________________________________________
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> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 10/21] drm/amd/display: Add back code to allow for rounding error

[Koo, Anthony]

[-- Attachment #1.1: Type: text/plain, Size: 3378 bytes --]

Thanks for the comments.

The input parameters are intended as uHz, but units do get translated within the function. We did not want to create new unnecessary parameters on the stack, which led up to the slightly confusing units. Maybe a better comment here would also help.
And indeed, the comment about ceil needs to be fixed up.

Thanks,
Anthony

From: Nils Wallménius [mailto:nils.wallmenius@gmail.com]
Sent: Friday, April 13, 2018 1:05 AM
To: Wentland, Harry <Harry.Wentland@amd.com>
Cc: amd-gfx@lists.freedesktop.org; Koo, Anthony <Anthony.Koo@amd.com>
Subject: Re: [PATCH 10/21] drm/amd/display: Add back code to allow for rounding error


Den tis 10 apr. 2018 23:11Harry Wentland <harry.wentland@amd.com<mailto:harry.wentland@amd.com>> skrev:
From: Anthony Koo <Anthony.Koo@amd.com<mailto:Anthony.Koo@amd.com>>

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com<mailto:Anthony.Koo@amd.com>>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com<mailto:Aric.Cyr@amd.com>>
Acked-by: Harry Wentland <harry.wentland@amd.com<mailto:harry.wentland@amd.com>>
---
 drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 4887c888bbe7..abd5c9374eb3 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -896,6 +896,17 @@ bool mod_freesync_is_valid_range(struct mod_freesync *mod_freesync,
        unsigned long long nominal_field_rate_in_uhz =
                        mod_freesync_calc_nominal_field_rate(stream);

+       /* Allow for some rounding error of actual video timing by taking ceil.
+        * For example, 144 Hz mode timing may actually be 143.xxx Hz when
+        * calculated from pixel rate and vertical/horizontal totals, but
+        * this should be allowed instead of blocking FreeSync.
+        */

Hi, with this change the var names ending in *_in_uhz are a bit confusing, also the integer division will not round up (take ceil) as seems to be the intention from the above comment. Perhaps the comment needs to be improved?

BR
Nils


+       nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz, 1000000);
+       min_refresh_cap_in_uhz /= 1000000;
+       max_refresh_cap_in_uhz /= 1000000;
+       min_refresh_request_in_uhz /= 1000000;
+       max_refresh_request_in_uhz /= 1000000;
+
        // Check nominal is within range
        if (nominal_field_rate_in_uhz > max_refresh_cap_in_uhz ||
                nominal_field_rate_in_uhz < min_refresh_cap_in_uhz)
@@ -921,7 +932,7 @@ bool mod_freesync_is_valid_range(struct mod_freesync *mod_freesync,

        // For variable range, check for at least 10 Hz range
        if ((max_refresh_request_in_uhz != min_refresh_request_in_uhz) &&
-               (max_refresh_request_in_uhz - min_refresh_request_in_uhz < 10000000))
+               (max_refresh_request_in_uhz - min_refresh_request_in_uhz < 10))
                return false;

        return true;
--
2.15.1

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