* [U-Boot] [RFC PATCH 0/2] Add support for two modules from Laird
@ 2017-07-07 10:40 Ben Whitten
2017-07-07 10:40 ` [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module Ben Whitten
2017-07-07 10:40 ` [U-Boot] [RFC PATCH 2/2] board: laird: add WB50N " Ben Whitten
0 siblings, 2 replies; 9+ messages in thread
From: Ben Whitten @ 2017-07-07 10:40 UTC (permalink / raw)
To: u-boot
Hi
These patches add basic support for two cpu modules from Laird. These boards
are based on the at91sam9x5ek and the sama5d3xek and have been updated from
old versions. I believe I have captured the KConfig moves and adjustents
but if there are better solutions now I should look into please let me know.
Kind regards,
Ben Whitten (2):
board: laird: add WB45N CPU module
board: laird: add WB50N CPU module
arch/arm/mach-at91/Kconfig | 14 +++
arch/arm/mach-at91/include/mach/gpio.h | 2 +
board/laird/wb45n/Kconfig | 12 ++
board/laird/wb45n/MAINTAINERS | 6 +
board/laird/wb45n/Makefile | 6 +
board/laird/wb45n/wb45n.c | 199 +++++++++++++++++++++++++++++++
board/laird/wb50n/Kconfig | 12 ++
board/laird/wb50n/MAINTAINERS | 6 +
board/laird/wb50n/Makefile | 6 +
board/laird/wb50n/wb50n.c | 206 +++++++++++++++++++++++++++++++++
configs/wb45n_defconfig | 27 +++++
configs/wb50n_defconfig | 26 +++++
include/configs/wb45n.h | 163 ++++++++++++++++++++++++++
include/configs/wb50n.h | 143 +++++++++++++++++++++++
14 files changed, 828 insertions(+)
create mode 100644 board/laird/wb45n/Kconfig
create mode 100644 board/laird/wb45n/MAINTAINERS
create mode 100644 board/laird/wb45n/Makefile
create mode 100644 board/laird/wb45n/wb45n.c
create mode 100644 board/laird/wb50n/Kconfig
create mode 100644 board/laird/wb50n/MAINTAINERS
create mode 100644 board/laird/wb50n/Makefile
create mode 100644 board/laird/wb50n/wb50n.c
create mode 100644 configs/wb45n_defconfig
create mode 100644 configs/wb50n_defconfig
create mode 100644 include/configs/wb45n.h
create mode 100644 include/configs/wb50n.h
--
2.7.4
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module
2017-07-07 10:40 [U-Boot] [RFC PATCH 0/2] Add support for two modules from Laird Ben Whitten
@ 2017-07-07 10:40 ` Ben Whitten
2017-07-07 14:33 ` Tom Rini
2017-08-02 9:58 ` Stefano Babic
2017-07-07 10:40 ` [U-Boot] [RFC PATCH 2/2] board: laird: add WB50N " Ben Whitten
1 sibling, 2 replies; 9+ messages in thread
From: Ben Whitten @ 2017-07-07 10:40 UTC (permalink / raw)
To: u-boot
This board is based on the Atmel 9x5 eval board.
Supporting the following features:
- Boot from NAND Flash
- Ethernet
- FIT
- SPL
Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
---
arch/arm/mach-at91/Kconfig | 6 +
arch/arm/mach-at91/include/mach/gpio.h | 2 +
board/laird/wb45n/Kconfig | 12 ++
board/laird/wb45n/MAINTAINERS | 6 +
board/laird/wb45n/Makefile | 6 +
board/laird/wb45n/wb45n.c | 199 +++++++++++++++++++++++++++++++++
configs/wb45n_defconfig | 27 +++++
include/configs/wb45n.h | 163 +++++++++++++++++++++++++++
8 files changed, 421 insertions(+)
create mode 100644 board/laird/wb45n/Kconfig
create mode 100644 board/laird/wb45n/MAINTAINERS
create mode 100644 board/laird/wb45n/Makefile
create mode 100644 board/laird/wb45n/wb45n.c
create mode 100644 configs/wb45n_defconfig
create mode 100644 include/configs/wb45n.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 99b88d1..e4d9690 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -164,6 +164,11 @@ config TARGET_VINCO
select CPU_V7
select SUPPORT_SPL
+config TARGET_WB45N
+ bool "Support Laird WB45N"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
endchoice
config SYS_SOC
@@ -197,5 +202,6 @@ source "board/ronetix/pm9g45/Kconfig"
source "board/siemens/corvus/Kconfig"
source "board/siemens/taurus/Kconfig"
source "board/siemens/smartweb/Kconfig"
+source "board/laird/wb45n/Kconfig"
endif
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index df0f719..e206316 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -219,6 +219,8 @@ static inline unsigned pin_to_mask(unsigned pin)
at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_B_periph(x, y) \
at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
+#define at91_set_gpio_deglitch(x, y) \
+ at91_set_pio_deglitch((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_gpio_output(x, y) \
at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
#define at91_set_gpio_input(x, y) \
diff --git a/board/laird/wb45n/Kconfig b/board/laird/wb45n/Kconfig
new file mode 100644
index 0000000..2a67337
--- /dev/null
+++ b/board/laird/wb45n/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WB45N
+
+config SYS_BOARD
+ default "wb45n"
+
+config SYS_VENDOR
+ default "laird"
+
+config SYS_CONFIG_NAME
+ default "wb45n"
+
+endif
diff --git a/board/laird/wb45n/MAINTAINERS b/board/laird/wb45n/MAINTAINERS
new file mode 100644
index 0000000..60bb563
--- /dev/null
+++ b/board/laird/wb45n/MAINTAINERS
@@ -0,0 +1,6 @@
+WB45N CPU MODULE
+M: Ben Whitten <ben.whitten@lairdtech.com>
+S: Maintained
+F: board/laird/wb45n/
+F: include/configs/wb45n.h
+F: configs/wb45n_defconfig
diff --git a/board/laird/wb45n/Makefile b/board/laird/wb45n/Makefile
new file mode 100644
index 0000000..fc645dd
--- /dev/null
+++ b/board/laird/wb45n/Makefile
@@ -0,0 +1,6 @@
+#
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += wb45n.o
diff --git a/board/laird/wb45n/wb45n.c b/board/laird/wb45n/wb45n.c
new file mode 100644
index 0000000..5914071
--- /dev/null
+++ b/board/laird/wb45n/wb45n.c
@@ -0,0 +1,199 @@
+/*
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+static void wb45n_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ csa = readl(&matrix->ebicsa);
+ /* Enable CS3 */
+ csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+ /* NAND flash on D0 */
+ csa &= ~AT91_MATRIX_NFD0_ON_D16;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode);
+
+ at91_periph_clk_enable(ATMEL_ID_PIOCD);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ /* Disable Flash Write Protect Line */
+ at91_set_gpio_output(AT91_PIN_PD10, 1);
+
+ at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
+ at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
+}
+
+static void wb45n_gpio_hw_init(void)
+{
+
+ /* Configure wifi gpio CHIP_PWD_L */
+ at91_set_gpio_output(AT91_PIN_PA28, 0);
+
+ /* Setup USB pins */
+ at91_set_gpio_input(AT91_PIN_PB11, 0);
+ at91_set_gpio_output(AT91_PIN_PB12, 0);
+
+ /* IRQ pin, pullup, deglitch */
+ at91_set_gpio_input(AT91_PIN_PB18, 1);
+ at91_set_gpio_deglitch(AT91_PIN_PB18, 1);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+ if (has_emac0())
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
+
+ return rc;
+}
+
+int board_early_init_f(void)
+{
+ at91_seriald_hw_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ wb45n_gpio_hw_init();
+
+ wb45n_nand_hw_init();
+
+ at91_macb_hw_init();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+ /* Setup GPIO first */
+ wb45n_gpio_hw_init();
+
+ /* Bring up NAND */
+ wb45n_nand_hw_init();
+}
+
+void matrix_init(void)
+{
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ csa = readl(&matrix->ebicsa);
+ /* Pull ups on D0 - D16 */
+ csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
+ csa |= AT91_MATRIX_EBI_DBPD_OFF;
+ /* Normal drive strength */
+ csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+ /* Multi-port off */
+ csa &= ~AT91_MATRIX_MP_ON;
+ writel(csa, &matrix->ebicsa);
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_DQMS_SHARED);
+
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct atmel_mpddrc_config ddr2;
+ unsigned long csa;
+
+ ddr2_conf(&ddr2);
+
+ /* enable DDR2 clock */
+ at91_system_clk_enable(AT91_PMC_DDR);
+
+ /* Chip select 1 is for DDR2/SDRAM */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+ writel(csa, &matrix->ebicsa);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
+}
+#endif
diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig
new file mode 100644
index 0000000..4ba0088
--- /dev/null
+++ b/configs/wb45n_defconfig
@@ -0,0 +1,27 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_WB45N=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_LZMA=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/wb45n.h b/include/configs/wb45n.h
new file mode 100644
index 0000000..fd714dd
--- /dev/null
+++ b/include/configs/wb45n.h
@@ -0,0 +1,163 @@
+/*
+ * Configuation settings for the WB45N CPU Module.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE 0x23f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
+#define CONFIG_USART_ID ATMEL_ID_SYS
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC 1
+#define CONFIG_ATMEL_NAND_HW_PMECC 1
+#define CONFIG_PMECC_CAP 4
+#define CONFIG_PMECC_SECTOR_SIZE 512
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_ETHADDR C0:EE:40:00:00:00
+#define CONFIG_ENV_OVERWRITE 1
+
+/* System */
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END 0x23e00000
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0xa0000
+#define CONFIG_ENV_OFFSET_REDUND 0xc0000
+#define CONFIG_ENV_SIZE 0x20000 /* 1 block = 128 kB */
+
+#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \
+ "run _mtd; bootm"
+
+#define MTDIDS_DEFAULT "nand0=atmel_nand"
+#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \
+ "128K(at91bs)," \
+ "512K(u-boot)," \
+ "128K(u-boot-env)," \
+ "128K(redund-env)," \
+ "2560K(kernel-a)," \
+ "2560K(kernel-b)," \
+ "38912K(rootfs-a)," \
+ "38912K(rootfs-b)," \
+ "46208K(user)," \
+ "512K(logs)"
+
+#else
+#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH'
+#endif
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \
+ "rw noinitrd mem=64M " \
+ "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "_mtd=mtdparts default; set bootargs ${bootargs} ${mtdparts}\0" \
+ "autoload=no\0" \
+ "autostart=no\0" \
+ "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
+ "\0"
+
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x300000
+#define CONFIG_SPL_MAX_SIZE 0x6000
+#define CONFIG_SPL_STACK 0x308000
+
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CONFIG_SYS_AT91_PLLA 0x20c73f03
+#define CONFIG_SYS_MCKR 0x1301
+#define CONFIG_SYS_MCKR_CSS 0x1302
+
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+
+#endif /* __CONFIG_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [RFC PATCH 2/2] board: laird: add WB50N CPU module
2017-07-07 10:40 [U-Boot] [RFC PATCH 0/2] Add support for two modules from Laird Ben Whitten
2017-07-07 10:40 ` [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module Ben Whitten
@ 2017-07-07 10:40 ` Ben Whitten
2017-07-07 14:33 ` Tom Rini
1 sibling, 1 reply; 9+ messages in thread
From: Ben Whitten @ 2017-07-07 10:40 UTC (permalink / raw)
To: u-boot
This board is based on the Atmel sama5d3 eval boards.
Supporting the following features:
- Boot from NAND Flash
- Ethernet
- FIT
- SPL
Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
---
arch/arm/mach-at91/Kconfig | 8 ++
board/laird/wb50n/Kconfig | 12 +++
board/laird/wb50n/MAINTAINERS | 6 ++
board/laird/wb50n/Makefile | 6 ++
board/laird/wb50n/wb50n.c | 206 ++++++++++++++++++++++++++++++++++++++++++
configs/wb50n_defconfig | 26 ++++++
include/configs/wb50n.h | 143 +++++++++++++++++++++++++++++
7 files changed, 407 insertions(+)
create mode 100644 board/laird/wb50n/Kconfig
create mode 100644 board/laird/wb50n/MAINTAINERS
create mode 100644 board/laird/wb50n/Makefile
create mode 100644 board/laird/wb50n/wb50n.c
create mode 100644 configs/wb50n_defconfig
create mode 100644 include/configs/wb50n.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index e4d9690..d89c53b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -169,6 +169,13 @@ config TARGET_WB45N
select CPU_ARM926EJS
select SUPPORT_SPL
+config TARGET_WB50N
+ bool "Support Laird WB50N"
+ select BOARD_LATE_INIT
+ select CPU_V7
+ select SUPPORT_SPL
+ select BOARD_EARLY_INIT_F
+
endchoice
config SYS_SOC
@@ -203,5 +210,6 @@ source "board/siemens/corvus/Kconfig"
source "board/siemens/taurus/Kconfig"
source "board/siemens/smartweb/Kconfig"
source "board/laird/wb45n/Kconfig"
+source "board/laird/wb50n/Kconfig"
endif
diff --git a/board/laird/wb50n/Kconfig b/board/laird/wb50n/Kconfig
new file mode 100644
index 0000000..2e7090e
--- /dev/null
+++ b/board/laird/wb50n/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WB50N
+
+config SYS_BOARD
+ default "wb50n"
+
+config SYS_VENDOR
+ default "laird"
+
+config SYS_CONFIG_NAME
+ default "wb50n"
+
+endif
diff --git a/board/laird/wb50n/MAINTAINERS b/board/laird/wb50n/MAINTAINERS
new file mode 100644
index 0000000..3d38fc4
--- /dev/null
+++ b/board/laird/wb50n/MAINTAINERS
@@ -0,0 +1,6 @@
+WB50N CPU MODULE
+M: Ben Whitten <ben.whitten@lairdtech.com>
+S: Maintained
+F: board/laird/wb50n/
+F: include/configs/wb50n.h
+F: configs/wb50n_defconfig
diff --git a/board/laird/wb50n/Makefile b/board/laird/wb50n/Makefile
new file mode 100644
index 0000000..d1b6cfa
--- /dev/null
+++ b/board/laird/wb50n/Makefile
@@ -0,0 +1,6 @@
+#
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += wb50n.o
diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c
new file mode 100644
index 0000000..354cecf
--- /dev/null
+++ b/board/laird/wb50n/wb50n.c
@@ -0,0 +1,206 @@
+/*
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sama5_sfr.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <micrel.h>
+#include <net.h>
+#include <netdev.h>
+#include <spl.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/at91_wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+void wb50n_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ at91_periph_clk_enable(ATMEL_ID_SMC);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+ AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
+ AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) |
+ AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode);
+
+ /* Disable Flash Write Protect Line */
+ at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
+}
+
+int board_early_init_f(void)
+{
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+ at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ wb50n_nand_hw_init();
+
+ at91_macb_hw_init();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* rx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
+ /* tx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
+ /* rx/tx clock delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+
+ return rc;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+#include <linux/ctype.h>
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ const char *LAIRD_NAME = "lrd_name";
+ char name[32], *p;
+
+ strcpy(name, get_cpu_name());
+ for (p = name; *p != '\0'; *p = tolower(*p), p++)
+ ;
+ strcat(name, "-wb50n");
+ setenv(LAIRD_NAME, name);
+
+#endif
+
+ return 0;
+}
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+ wb50n_nand_hw_init();
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
+ ATMEL_MPDDRC_CR_NR_ROW_13 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_NDQS_DISABLED |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+ struct atmel_mpddrc_config ddr2;
+
+ ddr2_conf(&ddr2);
+
+ writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN,
+ &sfr->ddrcfg);
+
+ /* enable MPDDR clock */
+ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+ at91_system_clk_enable(AT91_PMC_DDR);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+ u32 tmp;
+
+ tmp = AT91_PMC_PLLAR_29 |
+ AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+ AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1);
+ at91_plla_init(tmp);
+
+ at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
+
+ tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA;
+ at91_mck_init(tmp);
+}
+#endif
diff --git a/configs/wb50n_defconfig b/configs/wb50n_defconfig
new file mode 100644
index 0000000..e03a5d3
--- /dev/null
+++ b/configs/wb50n_defconfig
@@ -0,0 +1,26 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_WB50N=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_LZMA=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h
new file mode 100644
index 0000000..ba66daa
--- /dev/null
+++ b/include/configs/wb50n.h
@@ -0,0 +1,143 @@
+/*
+ * Configuation settings for the WB50N CPU Module.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE 0x23f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_IMAGE_FORMAT_LEGACY
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
+#define CONFIG_USART_ID ATMEL_ID_DBGU
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE 0x04000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR 0x310000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_MEMTEST_START 0x21000000
+#define CONFIG_SYS_MEMTEST_END 0x22000000
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* NAND flash */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP 8
+#define CONFIG_PMECC_SECTOR_SIZE 512
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_RGMII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_ETHADDR C0:EE:40:00:00:00
+#define CONFIG_ENV_OVERWRITE 1
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=no\0" \
+ "autostart=no\0"
+
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0xA0000
+#define CONFIG_ENV_OFFSET_REDUND 0xC0000
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_BOOTCOMMAND \
+ "nand read 0x22000000 0x000e0000 0x500000; " \
+ "bootm"
+
+#define CONFIG_BOOTARGS \
+ "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x300000
+#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+
+#define CONFIG_SYS_MONITOR_LEN (512 << 10)
+
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module
2017-07-07 10:40 ` [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module Ben Whitten
@ 2017-07-07 14:33 ` Tom Rini
2017-08-02 9:58 ` Stefano Babic
1 sibling, 0 replies; 9+ messages in thread
From: Tom Rini @ 2017-07-07 14:33 UTC (permalink / raw)
To: u-boot
On Fri, Jul 07, 2017 at 11:40:29AM +0100, Ben Whitten wrote:
> This board is based on the Atmel 9x5 eval board.
> Supporting the following features:
> - Boot from NAND Flash
> - Ethernet
> - FIT
> - SPL
>
> Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
> Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [RFC PATCH 2/2] board: laird: add WB50N CPU module
2017-07-07 10:40 ` [U-Boot] [RFC PATCH 2/2] board: laird: add WB50N " Ben Whitten
@ 2017-07-07 14:33 ` Tom Rini
0 siblings, 0 replies; 9+ messages in thread
From: Tom Rini @ 2017-07-07 14:33 UTC (permalink / raw)
To: u-boot
On Fri, Jul 07, 2017 at 11:40:30AM +0100, Ben Whitten wrote:
> This board is based on the Atmel sama5d3 eval boards.
> Supporting the following features:
> - Boot from NAND Flash
> - Ethernet
> - FIT
> - SPL
>
> Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
> Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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* [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module
2017-07-07 10:40 ` [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module Ben Whitten
2017-07-07 14:33 ` Tom Rini
@ 2017-08-02 9:58 ` Stefano Babic
2017-08-02 14:49 ` Tom Rini
1 sibling, 1 reply; 9+ messages in thread
From: Stefano Babic @ 2017-08-02 9:58 UTC (permalink / raw)
To: u-boot
On 07/07/2017 12:40, Ben Whitten wrote:
> This board is based on the Atmel 9x5 eval board.
> Supporting the following features:
> - Boot from NAND Flash
> - Ethernet
> - FIT
> - SPL
>
Patch is assigned to me. However, this is Atmel, now orphaned. I haven't
work with AT-91 since a very long time, so I cannot say more about
patches, but it is a pity if the patches will be lost. Tom, should I
merge them even if they are not i.MX related ? Or do you pick them
yourself ?
Regards,
Stefano
> Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
> Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
> ---
> arch/arm/mach-at91/Kconfig | 6 +
> arch/arm/mach-at91/include/mach/gpio.h | 2 +
> board/laird/wb45n/Kconfig | 12 ++
> board/laird/wb45n/MAINTAINERS | 6 +
> board/laird/wb45n/Makefile | 6 +
> board/laird/wb45n/wb45n.c | 199 +++++++++++++++++++++++++++++++++
> configs/wb45n_defconfig | 27 +++++
> include/configs/wb45n.h | 163 +++++++++++++++++++++++++++
> 8 files changed, 421 insertions(+)
> create mode 100644 board/laird/wb45n/Kconfig
> create mode 100644 board/laird/wb45n/MAINTAINERS
> create mode 100644 board/laird/wb45n/Makefile
> create mode 100644 board/laird/wb45n/wb45n.c
> create mode 100644 configs/wb45n_defconfig
> create mode 100644 include/configs/wb45n.h
>
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index 99b88d1..e4d9690 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -164,6 +164,11 @@ config TARGET_VINCO
> select CPU_V7
> select SUPPORT_SPL
>
> +config TARGET_WB45N
> + bool "Support Laird WB45N"
> + select CPU_ARM926EJS
> + select SUPPORT_SPL
> +
> endchoice
>
> config SYS_SOC
> @@ -197,5 +202,6 @@ source "board/ronetix/pm9g45/Kconfig"
> source "board/siemens/corvus/Kconfig"
> source "board/siemens/taurus/Kconfig"
> source "board/siemens/smartweb/Kconfig"
> +source "board/laird/wb45n/Kconfig"
>
> endif
> diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
> index df0f719..e206316 100644
> --- a/arch/arm/mach-at91/include/mach/gpio.h
> +++ b/arch/arm/mach-at91/include/mach/gpio.h
> @@ -219,6 +219,8 @@ static inline unsigned pin_to_mask(unsigned pin)
> at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y)
> #define at91_set_B_periph(x, y) \
> at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y)
> +#define at91_set_gpio_deglitch(x, y) \
> + at91_set_pio_deglitch((x - PIN_BASE) / 32,(x % 32), y)
> #define at91_set_gpio_output(x, y) \
> at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y)
> #define at91_set_gpio_input(x, y) \
> diff --git a/board/laird/wb45n/Kconfig b/board/laird/wb45n/Kconfig
> new file mode 100644
> index 0000000..2a67337
> --- /dev/null
> +++ b/board/laird/wb45n/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_WB45N
> +
> +config SYS_BOARD
> + default "wb45n"
> +
> +config SYS_VENDOR
> + default "laird"
> +
> +config SYS_CONFIG_NAME
> + default "wb45n"
> +
> +endif
> diff --git a/board/laird/wb45n/MAINTAINERS b/board/laird/wb45n/MAINTAINERS
> new file mode 100644
> index 0000000..60bb563
> --- /dev/null
> +++ b/board/laird/wb45n/MAINTAINERS
> @@ -0,0 +1,6 @@
> +WB45N CPU MODULE
> +M: Ben Whitten <ben.whitten@lairdtech.com>
> +S: Maintained
> +F: board/laird/wb45n/
> +F: include/configs/wb45n.h
> +F: configs/wb45n_defconfig
> diff --git a/board/laird/wb45n/Makefile b/board/laird/wb45n/Makefile
> new file mode 100644
> index 0000000..fc645dd
> --- /dev/null
> +++ b/board/laird/wb45n/Makefile
> @@ -0,0 +1,6 @@
> +#
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += wb45n.o
> diff --git a/board/laird/wb45n/wb45n.c b/board/laird/wb45n/wb45n.c
> new file mode 100644
> index 0000000..5914071
> --- /dev/null
> +++ b/board/laird/wb45n/wb45n.c
> @@ -0,0 +1,199 @@
> +/*
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/at91sam9x5_matrix.h>
> +#include <asm/arch/at91sam9_smc.h>
> +#include <asm/arch/at91_common.h>
> +#include <asm/arch/at91_rstc.h>
> +#include <asm/arch/clk.h>
> +#include <asm/arch/gpio.h>
> +#include <net.h>
> +#include <netdev.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* ------------------------------------------------------------------------- */
> +/*
> + * Miscelaneous platform dependent initialisations
> + */
> +static void wb45n_nand_hw_init(void)
> +{
> + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
> + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
> + unsigned long csa;
> +
> + csa = readl(&matrix->ebicsa);
> + /* Enable CS3 */
> + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
> + /* NAND flash on D0 */
> + csa &= ~AT91_MATRIX_NFD0_ON_D16;
> + writel(csa, &matrix->ebicsa);
> +
> + /* Configure SMC CS3 for NAND/SmartMedia */
> + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
> + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
> + &smc->cs[3].setup);
> + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
> + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
> + &smc->cs[3].pulse);
> + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
> + &smc->cs[3].cycle);
> + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
> + AT91_SMC_MODE_EXNW_DISABLE |
> + AT91_SMC_MODE_DBW_8 |
> + AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode);
> +
> + at91_periph_clk_enable(ATMEL_ID_PIOCD);
> +
> + /* Configure RDY/BSY */
> + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
> + /* Enable NandFlash */
> + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
> + /* Disable Flash Write Protect Line */
> + at91_set_gpio_output(AT91_PIN_PD10, 1);
> +
> + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
> + at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
> + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
> + at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
> +}
> +
> +static void wb45n_gpio_hw_init(void)
> +{
> +
> + /* Configure wifi gpio CHIP_PWD_L */
> + at91_set_gpio_output(AT91_PIN_PA28, 0);
> +
> + /* Setup USB pins */
> + at91_set_gpio_input(AT91_PIN_PB11, 0);
> + at91_set_gpio_output(AT91_PIN_PB12, 0);
> +
> + /* IRQ pin, pullup, deglitch */
> + at91_set_gpio_input(AT91_PIN_PB18, 1);
> + at91_set_gpio_deglitch(AT91_PIN_PB18, 1);
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + int rc = 0;
> +
> + if (has_emac0())
> + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
> +
> + return rc;
> +}
> +
> +int board_early_init_f(void)
> +{
> + at91_seriald_hw_init();
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> +
> + wb45n_gpio_hw_init();
> +
> + wb45n_nand_hw_init();
> +
> + at91_macb_hw_init();
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
> + CONFIG_SYS_SDRAM_SIZE);
> + return 0;
> +}
> +
> +#if defined(CONFIG_SPL_BUILD)
> +#include <spl.h>
> +#include <nand.h>
> +
> +void at91_spl_board_init(void)
> +{
> + /* Setup GPIO first */
> + wb45n_gpio_hw_init();
> +
> + /* Bring up NAND */
> + wb45n_nand_hw_init();
> +}
> +
> +void matrix_init(void)
> +{
> + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
> + unsigned long csa;
> +
> + csa = readl(&matrix->ebicsa);
> + /* Pull ups on D0 - D16 */
> + csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
> + csa |= AT91_MATRIX_EBI_DBPD_OFF;
> + /* Normal drive strength */
> + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
> + /* Multi-port off */
> + csa &= ~AT91_MATRIX_MP_ON;
> + writel(csa, &matrix->ebicsa);
> +}
> +
> +#include <asm/arch/atmel_mpddrc.h>
> +static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
> +{
> + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
> +
> + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
> + ATMEL_MPDDRC_CR_NR_ROW_13 |
> + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
> + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
> + ATMEL_MPDDRC_CR_DQMS_SHARED);
> +
> + ddr2->rtr = 0x411;
> +
> + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
> + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
> +
> + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
> + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
> + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
> + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
> +
> + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
> + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
> + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
> + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
> +}
> +
> +void mem_init(void)
> +{
> + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
> + struct atmel_mpddrc_config ddr2;
> + unsigned long csa;
> +
> + ddr2_conf(&ddr2);
> +
> + /* enable DDR2 clock */
> + at91_system_clk_enable(AT91_PMC_DDR);
> +
> + /* Chip select 1 is for DDR2/SDRAM */
> + csa = readl(&matrix->ebicsa);
> + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
> + writel(csa, &matrix->ebicsa);
> +
> + /* DDRAM2 Controller initialize */
> + ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
> +}
> +#endif
> diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig
> new file mode 100644
> index 0000000..4ba0088
> --- /dev/null
> +++ b/configs/wb45n_defconfig
> @@ -0,0 +1,27 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_AT91=y
> +CONFIG_TARGET_WB45N=y
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_NAND_SUPPORT=y
> +CONFIG_FIT=y
> +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
> +CONFIG_BOOTDELAY=3
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_SPL=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_CMD_BOOTZ=y
> +# CONFIG_CMD_IMLS is not set
> +CONFIG_CMD_MEMTEST=y
> +# CONFIG_CMD_LOADS is not set
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_NAND=y
> +CONFIG_CMD_NAND_TRIMFFS=y
> +# CONFIG_CMD_FPGA is not set
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_LZMA=y
> +CONFIG_OF_LIBFDT=y
> diff --git a/include/configs/wb45n.h b/include/configs/wb45n.h
> new file mode 100644
> index 0000000..fd714dd
> --- /dev/null
> +++ b/include/configs/wb45n.h
> @@ -0,0 +1,163 @@
> +/*
> + * Configuation settings for the WB45N CPU Module.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_H__
> +#define __CONFIG_H__
> +
> +#include <asm/hardware.h>
> +
> +#define CONFIG_SYS_TEXT_BASE 0x23f00000
> +
> +/* ARM asynchronous clock */
> +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
> +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
> +
> +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +
> +/* general purpose I/O */
> +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
> +#define CONFIG_AT91_GPIO
> +
> +/* serial console */
> +#define CONFIG_ATMEL_USART
> +#define CONFIG_USART_BASE ATMEL_BASE_DBGU
> +#define CONFIG_USART_ID ATMEL_ID_SYS
> +
> +/*
> + * BOOTP options
> + */
> +#define CONFIG_BOOTP_BOOTFILESIZE
> +#define CONFIG_BOOTP_BOOTPATH
> +#define CONFIG_BOOTP_GATEWAY
> +#define CONFIG_BOOTP_HOSTNAME
> +
> +/* SDRAM */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define CONFIG_SYS_SDRAM_BASE 0x20000000
> +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */
> +
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
> +
> +/* NAND flash */
> +#define CONFIG_CMD_NAND_TRIMFFS
> +#define CONFIG_NAND_ATMEL
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_BASE 0x40000000
> +/* our ALE is AD21 */
> +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
> +/* our CLE is AD22 */
> +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
> +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
> +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
> +
> +/* PMECC & PMERRLOC */
> +#define CONFIG_ATMEL_NAND_HWECC 1
> +#define CONFIG_ATMEL_NAND_HW_PMECC 1
> +#define CONFIG_PMECC_CAP 4
> +#define CONFIG_PMECC_SECTOR_SIZE 512
> +
> +#define CONFIG_MTD_DEVICE
> +#define CONFIG_CMD_MTDPARTS
> +#define CONFIG_MTD_PARTITIONS
> +#define CONFIG_RBTREE
> +#define CONFIG_LZO
> +
> +/* Ethernet */
> +#define CONFIG_MACB
> +#define CONFIG_RMII
> +#define CONFIG_NET_RETRY_COUNT 20
> +#define CONFIG_MACB_SEARCH_PHY
> +#define CONFIG_ETHADDR C0:EE:40:00:00:00
> +#define CONFIG_ENV_OVERWRITE 1
> +
> +/* System */
> +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
> +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END 0x23e00000
> +
> +#ifdef CONFIG_SYS_USE_NANDFLASH
> +/* bootstrap + u-boot + env + linux in nandflash */
> +#define CONFIG_ENV_IS_IN_NAND
> +#define CONFIG_ENV_OFFSET 0xa0000
> +#define CONFIG_ENV_OFFSET_REDUND 0xc0000
> +#define CONFIG_ENV_SIZE 0x20000 /* 1 block = 128 kB */
> +
> +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \
> + "run _mtd; bootm"
> +
> +#define MTDIDS_DEFAULT "nand0=atmel_nand"
> +#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \
> + "128K(at91bs)," \
> + "512K(u-boot)," \
> + "128K(u-boot-env)," \
> + "128K(redund-env)," \
> + "2560K(kernel-a)," \
> + "2560K(kernel-b)," \
> + "38912K(rootfs-a)," \
> + "38912K(rootfs-b)," \
> + "46208K(user)," \
> + "512K(logs)"
> +
> +#else
> +#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH'
> +#endif
> +
> +#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \
> + "rw noinitrd mem=64M " \
> + "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6"
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "_mtd=mtdparts default; set bootargs ${bootargs} ${mtdparts}\0" \
> + "autoload=no\0" \
> + "autostart=no\0" \
> + "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
> + "\0"
> +
> +#define CONFIG_SYS_CBSIZE 256
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_AUTO_COMPLETE
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
> +
> +/* SPL */
> +#define CONFIG_SPL_FRAMEWORK
> +#define CONFIG_SPL_TEXT_BASE 0x300000
> +#define CONFIG_SPL_MAX_SIZE 0x6000
> +#define CONFIG_SPL_STACK 0x308000
> +
> +#define CONFIG_SPL_BSS_START_ADDR 0x20000000
> +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
> +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
> +
> +#define CONFIG_SYS_MONITOR_LEN (512 << 10)
> +
> +#define CONFIG_SYS_MASTER_CLOCK 132096000
> +#define CONFIG_SYS_AT91_PLLA 0x20c73f03
> +#define CONFIG_SYS_MCKR 0x1301
> +#define CONFIG_SYS_MCKR_CSS 0x1302
> +
> +#define CONFIG_SPL_NAND_DRIVERS
> +#define CONFIG_SPL_NAND_BASE
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
> +#define CONFIG_SYS_NAND_PAGE_COUNT 64
> +#define CONFIG_SYS_NAND_OOBSIZE 64
> +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
> +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
> +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
> +
> +#endif /* __CONFIG_H__ */
>
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module
2017-08-02 9:58 ` Stefano Babic
@ 2017-08-02 14:49 ` Tom Rini
2017-11-09 10:24 ` Ben Whitten
0 siblings, 1 reply; 9+ messages in thread
From: Tom Rini @ 2017-08-02 14:49 UTC (permalink / raw)
To: u-boot
On Wed, Aug 02, 2017 at 11:58:42AM +0200, Stefano Babic wrote:
> On 07/07/2017 12:40, Ben Whitten wrote:
> > This board is based on the Atmel 9x5 eval board.
> > Supporting the following features:
> > - Boot from NAND Flash
> > - Ethernet
> > - FIT
> > - SPL
> >
>
> Patch is assigned to me. However, this is Atmel, now orphaned. I haven't
> work with AT-91 since a very long time, so I cannot say more about
> patches, but it is a pity if the patches will be lost. Tom, should I
> merge them even if they are not i.MX related ? Or do you pick them
> yourself ?
Ah, sorry, I saw laird, had the WiFi modules they do for i.MX series
platforms in mind and went "oh, must be an i.MX system". Please toss
them back to me, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module
2017-08-02 14:49 ` Tom Rini
@ 2017-11-09 10:24 ` Ben Whitten
2017-11-15 3:29 ` Tom Rini
0 siblings, 1 reply; 9+ messages in thread
From: Ben Whitten @ 2017-11-09 10:24 UTC (permalink / raw)
To: u-boot
On 02 August 2017 15:49, Tom Rini wrote:
> On Wed, Aug 02, 2017 at 11:58:42AM +0200, Stefano Babic wrote:
> > On 07/07/2017 12:40, Ben Whitten wrote:
> > > This board is based on the Atmel 9x5 eval board.
> > > Supporting the following features:
> > > - Boot from NAND Flash
> > > - Ethernet
> > > - FIT
> > > - SPL
> > >
> >
> > Patch is assigned to me. However, this is Atmel, now orphaned. I
> > haven't work with AT-91 since a very long time, so I cannot say more
> > about patches, but it is a pity if the patches will be lost. Tom,
> > should I merge them even if they are not i.MX related ? Or do you pick
> > them yourself ?
>
> Ah, sorry, I saw laird, had the WiFi modules they do for i.MX series platforms
> in mind and went "oh, must be an i.MX system". Please toss them back to
> me, thanks!
Hi Tom,
Any comments on these boards? Whilst I was at ELCE I bumped into Marek and
had a talk about adding new boards, he had mentioned new boards should be
using DM.
As this is the direction things are moving let me know and I can convert them.
Thanks,
Ben
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module
2017-11-09 10:24 ` Ben Whitten
@ 2017-11-15 3:29 ` Tom Rini
0 siblings, 0 replies; 9+ messages in thread
From: Tom Rini @ 2017-11-15 3:29 UTC (permalink / raw)
To: u-boot
On Thu, Nov 09, 2017 at 10:24:13AM +0000, Ben Whitten wrote:
> On 02 August 2017 15:49, Tom Rini wrote:
> > On Wed, Aug 02, 2017 at 11:58:42AM +0200, Stefano Babic wrote:
> > > On 07/07/2017 12:40, Ben Whitten wrote:
> > > > This board is based on the Atmel 9x5 eval board.
> > > > Supporting the following features:
> > > > - Boot from NAND Flash
> > > > - Ethernet
> > > > - FIT
> > > > - SPL
> > > >
> > >
> > > Patch is assigned to me. However, this is Atmel, now orphaned. I
> > > haven't work with AT-91 since a very long time, so I cannot say more
> > > about patches, but it is a pity if the patches will be lost. Tom,
> > > should I merge them even if they are not i.MX related ? Or do you pick
> > > them yourself ?
> >
> > Ah, sorry, I saw laird, had the WiFi modules they do for i.MX series platforms
> > in mind and went "oh, must be an i.MX system". Please toss them back to
> > me, thanks!
>
> Hi Tom,
> Any comments on these boards? Whilst I was at ELCE I bumped into Marek and
> had a talk about adding new boards, he had mentioned new boards should be
> using DM.
> As this is the direction things are moving let me know and I can convert them.
Sorry. Can you please re-test and re-post against top of tree and I'll
make sure it gets in, assuming no other problems show up. Thanks!
--
Tom
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-11-15 3:29 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-07-07 10:40 [U-Boot] [RFC PATCH 0/2] Add support for two modules from Laird Ben Whitten
2017-07-07 10:40 ` [U-Boot] [RFC PATCH 1/2] board: laird: add WB45N CPU module Ben Whitten
2017-07-07 14:33 ` Tom Rini
2017-08-02 9:58 ` Stefano Babic
2017-08-02 14:49 ` Tom Rini
2017-11-09 10:24 ` Ben Whitten
2017-11-15 3:29 ` Tom Rini
2017-07-07 10:40 ` [U-Boot] [RFC PATCH 2/2] board: laird: add WB50N " Ben Whitten
2017-07-07 14:33 ` Tom Rini
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