* [PATCH v5 01/17] configs: agilex: Remove CONFIG_OF_EMBED
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 02/17] arm: socfpga: add fit source file for pack itb with ATF chee.hong.ang at intel.com
` (16 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
CONFIG_OF_EMBED was primarily enabled to support the agilex
spl hex file requirements. Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
configs/socfpga_agilex_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index 4fd84ad..693a774 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -29,7 +29,6 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 02/17] arm: socfpga: add fit source file for pack itb with ATF
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 01/17] configs: agilex: Remove CONFIG_OF_EMBED chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 03/17] arm: socfpga: Add function for checking description from FIT image chee.hong.ang at intel.com
` (15 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Generate a FIT image for Intel SOCFPGA (64bits) which
include U-boot proper, ATF and DTB for U-boot proper.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
board/altera/soc64/its/fit_spl_atf.its | 52 ++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 board/altera/soc64/its/fit_spl_atf.its
diff --git a/board/altera/soc64/its/fit_spl_atf.its b/board/altera/soc64/its/fit_spl_atf.its
new file mode 100644
index 0000000..b868da5
--- /dev/null
+++ b/board/altera/soc64/its/fit_spl_atf.its
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with U-Boot proper, ATF bl31, DTB";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot SoC64";
+ data = /incbin/("../../../../u-boot-nodtb.bin");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <0x00200000>;
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ data = /incbin/("../../../../bl31.bin");
+ type = "firmware";
+ os = "arm-trusted-firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x00001000>;
+ entry = <0x00001000>;
+ };
+
+ fdt {
+ description = "U-Boot SoC64 flat device-tree";
+ data = /incbin/("../../../../u-boot.dtb");
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Intel SoC64 FPGA";
+ firmware = "atf";
+ loadables = "uboot";
+ fdt = "fdt";
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 03/17] arm: socfpga: Add function for checking description from FIT image
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 01/17] configs: agilex: Remove CONFIG_OF_EMBED chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 02/17] arm: socfpga: add fit source file for pack itb with ATF chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 04/17] arm: socfpga: Load FIT image with ATF support chee.hong.ang at intel.com
` (14 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/board.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 7c8c05c..5757041 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -86,3 +86,13 @@ int g_dnl_board_usb_cable_connected(void)
return 1;
}
#endif
+
+#ifdef CONFIG_SPL_BUILD
+__weak int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 04/17] arm: socfpga: Load FIT image with ATF support
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (2 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 03/17] arm: socfpga: Add function for checking description from FIT image chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 05/17] arm: socfpga: Override 'lowlevel_init' to support ATF chee.hong.ang at intel.com
` (13 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
include/configs/socfpga_soc64_common.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 87c7345..f035381 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -197,6 +197,10 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
/* SPL SDMMC boot support */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#ifdef CONFIG_SPL_LOAD_FIT
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb"
+#else
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
+#endif
#endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 05/17] arm: socfpga: Override 'lowlevel_init' to support ATF
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (3 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 04/17] arm: socfpga: Load FIT image with ATF support chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 06/17] arm: socfpga: Disable "spin-table" method for booting Linux chee.hong.ang at intel.com
` (12 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Override 'lowlevel_init' to make sure secondary CPUs
trapped in ATF instead of SPL. After ATF is initialized,
it will signal the secondary CPUs to jump from SPL to
ATF waiting to be 'activated' by Linux OS via PSCI call.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/lowlevel_init_64.S | 81 ++++++++++++++++++++++++++++++++
2 files changed, 83 insertions(+)
create mode 100644 arch/arm/mach-socfpga/lowlevel_init_64.S
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 418f543..3758c0a 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -29,6 +29,7 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += clock_manager_s10.o
+obj-y += lowlevel_init_64.o
obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
@@ -41,6 +42,7 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += clock_manager_agilex.o
+obj-y += lowlevel_init_64.o
obj-y += mailbox_s10.o
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
diff --git a/arch/arm/mach-socfpga/lowlevel_init_64.S b/arch/arm/mach-socfpga/lowlevel_init_64.S
new file mode 100644
index 0000000..21402c0
--- /dev/null
+++ b/arch/arm/mach-socfpga/lowlevel_init_64.S
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+ENTRY(lowlevel_init)
+ mov x29, lr /* Save LR */
+
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_SPL_ATF
+ branch_if_slave x0, 2f
+#else
+ branch_if_slave x0, 1f
+#endif
+
+ ldr x0, =GICD_BASE
+ bl gic_init_secure
+ b 2f
+
+1:
+#if defined(CONFIG_GICV3)
+ ldr x0, =GICR_BASE
+ bl gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+ ldr x0, =GICD_BASE
+ ldr x1, =GICC_BASE
+ bl gic_init_secure_percpu
+#endif
+#endif
+
+#ifdef CONFIG_ARMV8_MULTIENTRY
+ branch_if_master x0, x1, 3f
+
+ /*
+ * Slave should wait for master clearing spin table.
+ * This sync prevent slaves observing incorrect
+ * value of spin table and jumping to wrong place.
+ */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+ ldr x0, =GICC_BASE
+#endif
+ bl gic_wait_for_interrupt
+#endif
+
+ /*
+ * All slaves will enter EL2 and optionally EL1.
+ */
+ adr x4, lowlevel_in_el2
+ ldr x5, =ES_TO_AARCH64
+ bl armv8_switch_to_el2
+
+lowlevel_in_el2:
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ adr x4, lowlevel_in_el1
+ ldr x5, =ES_TO_AARCH64
+ bl armv8_switch_to_el1
+
+lowlevel_in_el1:
+#endif
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
+2:
+#ifdef CONFIG_SPL_BUILD
+ ldr x4, =CPU_RELEASE_ADDR
+ ldr x5, [x4]
+ cbz x5, checkslavecpu
+ br x5
+checkslavecpu:
+ branch_if_slave x0, 2b
+#endif
+
+3:
+ mov lr, x29 /* Restore LR */
+ ret
+ENDPROC(lowlevel_init)
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 06/17] arm: socfpga: Disable "spin-table" method for booting Linux
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (4 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 05/17] arm: socfpga: Override 'lowlevel_init' to support ATF chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 07/17] arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits) chee.hong.ang at intel.com
` (11 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable
SMP booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/Kconfig | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 38d6c1b..0b858af 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -33,7 +33,6 @@ config TARGET_SOCFPGA_AGILEX
bool
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
- select ARMV8_SPIN_TABLE
select CLK
select NCORE_CACHE
select SPL_CLK if SPL
@@ -77,7 +76,6 @@ config TARGET_SOCFPGA_STRATIX10
bool
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
- select ARMV8_SPIN_TABLE
select FPGA_STRATIX10
choice
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 07/17] arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits)
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (5 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 06/17] arm: socfpga: Disable "spin-table" method for booting Linux chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 08/17] arm: socfpga: Define SMC function identifiers for PSCI SiP services chee.hong.ang at intel.com
` (10 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Allow U-Boot proper running in non-secure mode (EL2) to invoke
SMC call to ATF's PSCI runtime services such as System Manager's
registers access, 2nd phase bitstream FPGA reconfiguration,
Remote System Update (RSU) and etc.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/include/mach/misc.h | 3 +++
arch/arm/mach-socfpga/misc_s10.c | 20 ++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index f6de1cc..b5625e1 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -43,4 +43,7 @@ void do_bridge_reset(int enable, unsigned int mask);
void socfpga_pl310_clear(void);
void socfpga_get_managers_addr(void);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len);
+#endif
#endif /* _SOCFPGA_MISC_H_ */
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index a3f5b43..adfff82 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -164,3 +164,23 @@ void do_bridge_reset(int enable, unsigned int mask)
socfpga_bridges_reset(enable);
}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+int invoke_smc(u32 func_id, u64 *args, int arg_len, u64 *ret_arg, int ret_len)
+{
+ struct pt_regs regs;
+
+ memset(®s, 0, sizeof(regs));
+ regs.regs[0] = func_id;
+
+ if (args)
+ memcpy(®s.regs[1], &args[0], arg_len * sizeof(u64));
+
+ smc_call(®s);
+
+ if (ret_arg)
+ memcpy(&ret_arg[0], ®s.regs[1], ret_len * sizeof(u64));
+
+ return regs.regs[0];
+}
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 08/17] arm: socfpga: Define SMC function identifiers for PSCI SiP services
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (6 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 07/17] arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits) chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 09/17] arm: socfpga: soc64: Remove PHY interface setup from misc arch init chee.hong.ang at intel.com
` (9 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
This header file defines the Secure Monitor Call (SMC) message
protocol for ATF (BL31) PSCI runtime services. It includes all
the PSCI SiP function identifiers for the secure runtime services
provided by ATF. The secure runtime services include System Manager's
registers access, 2nd phase bitstream FPGA reconfiguration, Remote
System Update (RSU) and etc.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
include/linux/intel-smc.h | 445 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 445 insertions(+)
create mode 100644 include/linux/intel-smc.h
diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h
new file mode 100644
index 0000000..81b97c0
--- /dev/null
+++ b/include/linux/intel-smc.h
@@ -0,0 +1,445 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017-2020, Intel Corporation
+ */
+
+#ifndef __INTEL_SMC_H
+#define __INTEL_SMC_H
+
+#include <linux/arm-smccc.h>
+#include <linux/bitops.h>
+
+/*
+ * This file defines the Secure Monitor Call (SMC) message protocol used for
+ * service layer driver in normal world (EL1) to communicate with secure
+ * monitor software in Secure Monitor Exception Level 3 (EL3).
+ *
+ * This file is shared with secure firmware (FW) which is out of kernel tree.
+ *
+ * An ARM SMC instruction takes a function identifier and up to 6 64-bit
+ * register values as arguments, and can return up to 4 64-bit register
+ * value. The operation of the secure monitor is determined by the parameter
+ * values passed in through registers.
+
+ * EL1 and EL3 communicates pointer as physical address rather than the
+ * virtual address.
+ */
+
+/*
+ * Functions specified by ARM SMC Calling convention:
+ *
+ * FAST call executes atomic operations, returns when the requested operation
+ * has completed.
+ * STD call starts a operation which can be preempted by a non-secure
+ * interrupt. The call can return before the requested operation has
+ * completed.
+ *
+ * a0..a7 is used as register names in the descriptions below, on arm32
+ * that translates to r0..r7 and on arm64 to w0..w7.
+ */
+
+#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
+ ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
+ ARM_SMCCC_OWNER_SIP, (func_num))
+
+#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
+ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
+ ARM_SMCCC_OWNER_SIP, (func_num))
+
+/*
+ * Return values in INTEL_SIP_SMC_* call
+ *
+ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION:
+ * Secure monitor software doesn't recognize the request.
+ *
+ * INTEL_SIP_SMC_STATUS_OK:
+ * FPGA configuration completed successfully,
+ * In case of FPGA configuration write operation, it means secure monitor
+ * software can accept the next chunk of FPGA configuration data.
+ *
+ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY:
+ * In case of FPGA configuration write operation, it means secure monitor
+ * software is still processing previous data & can't accept the next chunk
+ * of data. Service driver needs to issue
+ * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the
+ * completed block(s).
+ *
+ * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR:
+ * There is error during the FPGA configuration process.
+ *
+ * INTEL_SIP_SMC_REG_ERROR:
+ * There is error during a read or write operation of the protected
+ * registers.
+ */
+#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF
+#define INTEL_SIP_SMC_STATUS_OK 0x0
+#define INTEL_SIP_SMC_STATUS_BUSY 0x1
+#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
+#define INTEL_SIP_SMC_STATUS_ERROR 0x4
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_START
+ *
+ * Sync call used by service driver at EL1 to request the FPGA in EL3 to
+ * be prepare to receive a new configuration.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_START.
+ * a1: flag for full or partial configuration
+ * 0 full reconfiguration.
+ * 1 partial reconfiguration.
+ * a2-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1
+#define INTEL_SIP_SMC_FPGA_CONFIG_START \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE
+ *
+ * Async call used by service driver at EL1 to provide FPGA configuration data
+ * to secure world.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE.
+ * a1: 64bit physical address of the configuration data memory block
+ * a2: Size of configuration data block.
+ * a3-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY,
+ * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1: 64bit physical address of 1st completed memory block if any completed
+ * block, otherwise zero value.
+ * a2: 64bit physical address of 2nd completed memory block if any completed
+ * block, otherwise zero value.
+ * a3: 64bit physical address of 3rd completed memory block if any completed
+ * block, otherwise zero value.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2
+#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \
+ INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE
+ *
+ * Sync call used by service driver at EL1 to track the completed write
+ * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE
+ * call returns INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
+ * INTEL_SIP_SMC_STATUS_ERROR.
+ * a1: 64bit physical address of 1st completed memory block.
+ * a2: 64bit physical address of 2nd completed memory block if
+ * any completed block, otherwise zero value.
+ * a3: 64bit physical address of 3rd completed memory block if
+ * any completed block, otherwise zero value.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3
+#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \
+INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE
+ *
+ * Sync call used by service driver at EL1 to inform secure world that all
+ * data are sent, to check whether or not the secure world had completed
+ * the FPGA configuration process.
+ * Set 1 in 2nd argument (a1) to query the status of the first phase FPGA
+ * configuration by sending MBOX_CONFIG_STATUS to SDM. Otherwise this sync
+ * call always query the status of 2nd phase FPGA reconfiguration by sending
+ * MBOX_RECONFIG_STATUS to SDM.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE.
+ * a1: set 1 to send MBOX_CONFIG_STATUS otherwise send MBOX_RECONFIG_STATUS
+ * a2-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
+ * INTEL_SIP_SMC_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4
+#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE)
+
+/*
+ * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM
+ *
+ * Sync call used by service driver at EL1 to query the physical address of
+ * memory block reserved by secure monitor software.
+ *
+ * Call register usage:
+ * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM.
+ * a1-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1: start of physical address of reserved memory block.
+ * a2: size of reserved memory block.
+ * a3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5
+#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM)
+
+/*
+ * Request INTEL_SIP_SMC_REG_READ
+ *
+ * Read a protected register using SMCCC
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_READ.
+ * a1: register address.
+ * a2-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1: Value in the register
+ * a2-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_READ 7
+#define INTEL_SIP_SMC_REG_READ \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
+
+/*
+ * Request INTEL_SIP_SMC_REG_WRITE
+ *
+ * Write a protected register using SMCCC
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_WRITE.
+ * a1: register address
+ * a2: value to program into register.
+ * a3-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
+#define INTEL_SIP_SMC_REG_WRITE \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
+
+/*
+ * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE
+ *
+ * Update one or more bits in a protected register using a
+ * read-modify-write operation.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_UPDATE.
+ * a1: register address
+ * a2: Write Mask.
+ * a3: Value to write.
+ * a4-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1-3: Not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9
+#define INTEL_SIP_SMC_REG_UPDATE \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_STATUS
+ *
+ * Sync call used by service driver at EL1 to query the RSU status
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_STATUS
+ * a1-7 not used
+ *
+ * Return status
+ * a0: Current Image
+ * a1: Last Failing Image
+ * a2: Version [width 32 bit] | State [width 32 bit]
+ * a3: Error details [width 32 bit] | Error location [width 32 bit]
+ *
+ * Or
+ *
+ * a0: INTEL_SIP_SMC_STATUS_ERROR
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11
+#define INTEL_SIP_SMC_RSU_STATUS \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_UPDATE
+ *
+ * Sync call used by service driver at EL1 to tell you next reboot is RSU_UPDATE
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_UPDATE
+ * a1 64bit physical address of the configuration data memory in flash
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12
+#define INTEL_SIP_SMC_RSU_UPDATE \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)
+
+/*
+ * Request INTEL_SIP_SMC_ECC_DBE
+ *
+ * Sync call used by service driver at EL1 alert EL3 that a Double Bit
+ * ECC error has occurred.
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_ECC_DBE
+ * a1 SysManager Double Bit Error value
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13
+#define INTEL_SIP_SMC_ECC_DBE \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_NOTIFY
+ *
+ * Sync call used by service driver at EL1 to report HPS software execution
+ * stage
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_NOTIFY
+ * a1 32bit HPS software execution stage
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_NOTIFY 14
+#define INTEL_SIP_SMC_RSU_NOTIFY \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_NOTIFY)
+
+/*
+ * Request INTEL_SIP_SMC_RSU_RETRY_COUNTER
+ *
+ * Sync call used by service driver at EL1 to query the RSU retry counter
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER
+ * a1-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
+ * a1 retry counter
+ */
+#define INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER 15
+#define INTEL_SIP_SMC_RSU_RETRY_COUNTER \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER)
+
+/*
+ * Request INTEL_SIP_SMC_MBOX_SEND_CMD
+ *
+ * Send mailbox command to SDM
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_MBOX_SEND_CMD
+ * a1 Mailbox command
+ * a2 64bit physical address pointer to command's arguments
+ * a3 Length of the argument
+ * a4 Urgent command:
+ * 0 - Disable
+ * 1 - Enable
+ * a5 64bit physical address pointer to a buffer for receiving responses
+ * a6 Length of the buffer
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
+ * a1 Status of mailbox response
+ * a2 64bit physical address pointer to a buffer for receiving responses
+ * a3 Received length in the buffer
+ */
+#define INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD 30
+#define INTEL_SIP_SMC_MBOX_SEND_CMD \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD)
+
+/*
+ * Request INTEL_SIP_SMC_HPS_SET_BRIDGES
+ *
+ * Enable/disable the SoC FPGA bridges
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES
+ * a1 Set bridges status:
+ * 0 - Disable
+ * 1 - Enable
+ * a2-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES 60
+#define INTEL_SIP_SMC_HPS_SET_BRIDGES \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES)
+
+/*
+ * Request INTEL_SIP_SMC_HPS_SET_PHYINTF
+ *
+ * Select EMACx PHY interface
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_HPS_SET_PHYINTF
+ * a1 EMAC number:
+ * 0 - EMAC0
+ * 1 - EMAC1
+ * 2 - EMAC2
+ * a2 Type of PHY interface:
+ * 0 - GMII_MII
+ * 1 - RGMII
+ * 2 - RMII
+ * 3 - RESET
+ * a3-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
+ */
+#define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF 61
+#define INTEL_SIP_SMC_HPS_SET_PHYINTF \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF)
+
+/*
+ * Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
+ *
+ * Select which phase shift of the clocks (drvsel & smplsel) for SDMMC
+ *
+ * Call register usage:
+ * a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
+ * a1 Select which phase shift of the clock for cclk_in_drv (drvsel):
+ * 0 - 0 degree
+ * 1 - 45 degrees
+ * 2 - 90 degrees
+ * 3 - 135 degrees
+ * 4 - 180 degrees
+ * 5 - 225 degrees
+ * 6 - 270 degrees
+ * 7 - 315 degrees
+ * a2 Select which phase shift of the clock for cclk_in_sample (smplsel):
+ * (Same as above)
+ * a3-7 not used
+ *
+ * Return status
+ * a0 INTEL_SIP_SMC_STATUS_OK
+ */
+#define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK 62
+#define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK)
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 09/17] arm: socfpga: soc64: Remove PHY interface setup from misc arch init
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (7 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 08/17] arm: socfpga: Define SMC function identifiers for PSCI SiP services chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 10/17] mmc: dwmmc: socfpga: Add ATF support for MMC driver chee.hong.ang at intel.com
` (8 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
'dwmac_socfpga' driver will setup the PHY interface during probe.
PHY interface setup in arch_misc_init() is no longer needed.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/misc_s10.c | 85 +---------------------------------------
1 file changed, 1 insertion(+), 84 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index adfff82..ba11bfa 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -8,18 +8,10 @@
#include <common.h>
#include <env.h>
#include <errno.h>
-#include <fdtdec.h>
-#include <miiphy.h>
-#include <netdev.h>
#include <asm/io.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/arch/system_manager.h>
#include <asm/arch/misc.h>
-#include <asm/pl310.h>
-#include <linux/libfdt.h>
#include <asm/arch/mailbox_s10.h>
-
-#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+#include <asm/arch/reset_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -44,80 +36,6 @@ static Altera_desc altera_fpga[] = {
};
/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-
-static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
-{
- u32 modereg;
-
- if (!phymode)
- return -EINVAL;
-
- if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
- !strcmp(phymode, "sgmii"))
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
- else if (!strcmp(phymode, "rgmii"))
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
- else if (!strcmp(phymode, "rmii"))
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
- else
- return -EINVAL;
-
- clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
- gmac_index,
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
-
- return 0;
-}
-
-static int socfpga_set_phymode(void)
-{
- const void *fdt = gd->fdt_blob;
- struct fdtdec_phandle_args args;
- const char *phy_mode;
- u32 gmac_index;
- int nodes[3]; /* Max. 3 GMACs */
- int ret, count;
- int i, node;
-
- count = fdtdec_find_aliases_for_id(fdt, "ethernet",
- COMPAT_ALTERA_SOCFPGA_DWMAC,
- nodes, ARRAY_SIZE(nodes));
- for (i = 0; i < count; i++) {
- node = nodes[i];
- if (node <= 0)
- continue;
-
- ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
- "#reset-cells", 1, 0,
- &args);
- if (ret || args.args_count != 1) {
- debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
- continue;
- }
-
- gmac_index = args.args[0] - EMAC0_RESET;
-
- phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
- ret = socfpga_phymode_setup(gmac_index, phy_mode);
- if (ret) {
- debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
- continue;
- }
- }
-
- return 0;
-}
-#else
-static int socfpga_set_phymode(void)
-{
- return 0;
-};
-#endif
-
-/*
* Print CPU information
*/
#if defined(CONFIG_DISPLAY_CPUINFO)
@@ -137,7 +55,6 @@ int arch_misc_init(void)
sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
env_set("qspi_clock", qspi_string);
- socfpga_set_phymode();
return 0;
}
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 10/17] mmc: dwmmc: socfpga: Add ATF support for MMC driver
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (8 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 09/17] arm: socfpga: soc64: Remove PHY interface setup from misc arch init chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 11/17] net: designware: socfpga: Add ATF support for MAC driver chee.hong.ang at intel.com
` (7 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
drivers/mmc/socfpga_dw_mmc.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 786cdc7..d4d1132 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -5,13 +5,16 @@
#include <common.h>
#include <asm/arch/clock_manager.h>
+#include <asm/arch/misc.h>
#include <asm/arch/system_manager.h>
#include <clk.h>
#include <dm.h>
#include <dwmmc.h>
#include <errno.h>
#include <fdtdec.h>
+#include <hang.h>
#include <dm/device_compat.h>
+#include <linux/intel-smc.h>
#include <linux/libfdt.h>
#include <linux/err.h>
#include <malloc.h>
@@ -45,6 +48,20 @@ static void socfpga_dwmci_reset(struct udevice *dev)
reset_deassert_bulk(&reset_bulk);
}
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+static void socfpga_dwmci_fw_clksel(u32 sdmmc_mask)
+{
+ u64 args[2];
+
+ /* drvsel */
+ args[0] = (sdmmc_mask >> SYSMGR_SDMMC_DRVSEL_SHIFT) & 0x7;
+ /* smplsel */
+ args[1] = (sdmmc_mask >> SYSMGR_SDMMC_SMPLSEL_SHIFT) & 0x7;
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK, args, 2, NULL, 0))
+ hang();
+}
+#endif
+
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
@@ -57,10 +74,14 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ socfpga_dwmci_fw_clksel(sdmmc_mask);
+#else
writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
/* Enable SDMMC clock */
setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 11/17] net: designware: socfpga: Add ATF support for MAC driver
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (9 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 10/17] mmc: dwmmc: socfpga: Add ATF support for MMC driver chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 12/17] arm: socfpga: Add ATF support for Reset Manager driver chee.hong.ang at intel.com
` (6 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
drivers/net/dwmac_socfpga.c | 43 +++++++++++++++++++++++++++++++++++++++----
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561d..600b2e6 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -14,8 +14,10 @@
#include <reset.h>
#include <syscon.h>
#include "designware.h"
+#include <asm/arch/misc.h>
#include <dm/device_compat.h>
#include <linux/err.h>
+#include <linux/intel-smc.h>
#include <asm/arch/system_manager.h>
@@ -64,6 +66,35 @@ static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
return designware_eth_ofdata_to_platdata(dev);
}
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+static int dwmac_socfpga_fw_setphy(struct udevice *dev, u32 modereg)
+{
+ struct ofnode_phandle_args pargs;
+ u64 args[2];
+ int ret;
+
+ ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
+ 1, 0, &pargs);
+ if (ret) {
+ dev_err(dev, "Failed to get syscon: %d\n", ret);
+ return ret;
+ }
+
+ if (pargs.args_count < 1) {
+ dev_err(dev, "No syscon args found\n");
+ return -EINVAL;
+ }
+
+ args[0] = ((u64)pargs.args[0] - SYSMGR_SOC64_EMAC0) >> 2;
+ args[1] = modereg;
+
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_PHYINTF, args, 2, NULL, 0))
+ return -EIO;
+
+ return 0;
+}
+#endif
+
static int dwmac_socfpga_probe(struct udevice *dev)
{
struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
@@ -71,7 +102,6 @@ static int dwmac_socfpga_probe(struct udevice *dev)
struct reset_ctl_bulk reset_bulk;
int ret;
u32 modereg;
- u32 modemask;
switch (edata->phy_interface) {
case PHY_INTERFACE_MODE_MII:
@@ -97,9 +127,14 @@ static int dwmac_socfpga_probe(struct udevice *dev)
reset_assert_bulk(&reset_bulk);
- modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
- clrsetbits_le32(pdata->phy_intf, modemask,
- modereg << pdata->reg_shift);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ ret = dwmac_socfpga_fw_setphy(dev, modereg);
+ if (ret)
+ return ret;
+#else
+ clrsetbits_le32(pdata->phy_intf, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
+ pdata->reg_shift, modereg << pdata->reg_shift);
+#endif
reset_release_bulk(&reset_bulk);
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 12/17] arm: socfpga: Add ATF support for Reset Manager driver
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (10 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 11/17] net: designware: socfpga: Add ATF support for MAC driver chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 13/17] arm: socfpga: stratix10: Initialize timer in SPL chee.hong.ang at intel.com
` (5 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI services provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index c743077..c028e2d 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,10 +5,13 @@
*/
#include <common.h>
+#include <hang.h>
#include <asm/io.h>
+#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+#include <linux/intel-smc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -54,6 +57,12 @@ void socfpga_per_reset_all(void)
void socfpga_bridges_reset(int enable)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 arg = enable;
+
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0))
+ hang();
+#else
if (enable) {
/* clear idle request to all bridges */
setbits_le32(socfpga_get_sysmgr_addr() +
@@ -94,6 +103,7 @@ void socfpga_bridges_reset(int enable)
/* Disable NOC timeout */
writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
}
+#endif
}
/*
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 13/17] arm: socfpga: stratix10: Initialize timer in SPL
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (11 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 12/17] arm: socfpga: Add ATF support for Reset Manager driver chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 14/17] arm: socfpga: Add ATF support to query FPGA configuration status chee.hong.ang at intel.com
` (4 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
Initialize timer in SPL running in secure mode (EL3)
and skip timer initialization in U-Boot proper running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/timer_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c
index 5723789..0fa56c3 100644
--- a/arch/arm/mach-socfpga/timer_s10.c
+++ b/arch/arm/mach-socfpga/timer_s10.c
@@ -13,6 +13,7 @@
*/
int timer_init(void)
{
+#ifdef CONFIG_SPL_BUILD
int enable = 0x3; /* timer enable + output signal masked */
int loadval = ~0;
@@ -21,6 +22,6 @@ int timer_init(void)
/* enable processor pysical counter */
asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
-
+#endif
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 14/17] arm: socfpga: Add ATF support to query FPGA configuration status
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (12 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 13/17] arm: socfpga: stratix10: Initialize timer in SPL chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 15/17] arm: socfpga: stratix10: Add ATF support for FPGA reconfig driver chee.hong.ang at intel.com
` (3 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
In EL3, do_bridge_reset() directly send mailbox commands to SDM to
query the FPGA configuration status. If running in non-secure
mode (EL2), it invokes SMC service calls to ATF (EL3) to perform the
query.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/misc_s10.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index ba11bfa..6b5dd03 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -12,6 +12,7 @@
#include <asm/arch/misc.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/reset_manager.h>
+#include <linux/intel-smc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -70,11 +71,24 @@ void do_bridge_reset(int enable, unsigned int mask)
{
/* Check FPGA status before bridge enable */
if (enable) {
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ u64 config_status = 1;
+
+ /* Send MBOX_RECONFIG_STATUS to SDM */
+ int ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+ NULL, 0);
+
+ if (ret && ret != INTEL_SIP_SMC_STATUS_BUSY) {
+ /* Send MBOX_CONFIG_STATUS to SDM */
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE,
+ &config_status, 1, NULL, 0);
+ }
+#else
int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
-
+#endif
if (ret)
return;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 15/17] arm: socfpga: stratix10: Add ATF support for FPGA reconfig driver
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (13 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 14/17] arm: socfpga: Add ATF support to query FPGA configuration status chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 16/17] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() chee.hong.ang at intel.com
` (2 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
drivers/fpga/stratix10.c | 141 ++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 140 insertions(+), 1 deletion(-)
diff --git a/drivers/fpga/stratix10.c b/drivers/fpga/stratix10.c
index d8e3250..d726a1b 100644
--- a/drivers/fpga/stratix10.c
+++ b/drivers/fpga/stratix10.c
@@ -5,11 +5,148 @@
#include <common.h>
#include <altera.h>
-#include <asm/arch/mailbox_s10.h>
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000
#define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#include <asm/arch/misc.h>
+#include <linux/intel-smc.h>
+
+#define BITSTREAM_CHUNK_SIZE 0xFFFF0
+#define RECONFIG_STATUS_POLL_RETRY_MAX 100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+ int ret;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+ NULL, 0);
+
+ if (!ret)
+ return 0; /* configuration success */
+
+ if (ret != INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+
+ if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+ break; /* time out */
+
+ puts(".");
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int send_bistream(const void *rbf_data, size_t rbf_size)
+{
+ int i;
+ u64 res_buf[3];
+ u64 args[2];
+ u32 xfer_count = 0;
+ int ret, wr_ret = 0, retry = 0;
+ size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+ BITSTREAM_CHUNK_SIZE : rbf_size;
+
+ while (rbf_size || xfer_count) {
+ if (!wr_ret && rbf_size) {
+ args[0] = (u64)rbf_data;
+ args[1] = buf_size;
+ wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+ args, 2, NULL, 0);
+
+ debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+ wr_ret, rbf_data, buf_size);
+
+ if (wr_ret == INTEL_SIP_SMC_STATUS_REJECTED)
+ continue;
+
+ rbf_size -= buf_size;
+ rbf_data += buf_size;
+
+ if (buf_size >= rbf_size)
+ buf_size = rbf_size;
+
+ xfer_count++;
+ puts(".");
+ } else {
+ ret = invoke_smc(
+ INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+ NULL, 0, res_buf, 3);
+ if (!ret) {
+ for (i = 0; i < 3; i++) {
+ if (!res_buf[i])
+ break;
+ xfer_count--;
+ wr_ret = 0;
+ retry = 0;
+ }
+ } else if (ret !=
+ INTEL_SIP_SMC_STATUS_BUSY)
+ return ret;
+ else if (!xfer_count)
+ return INTEL_SIP_SMC_STATUS_ERROR;
+
+ if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+ return -ETIMEDOUT;
+
+ udelay(20000);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ int ret;
+
+ debug("Invoking FPGA_CONFIG_START...\n");
+
+ ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, NULL, 0, NULL, 0);
+
+ if (ret) {
+ puts("Failure in RECONFIG mailbox command!\n");
+ return ret;
+ }
+
+ ret = send_bistream(rbf_data, rbf_size);
+ if (ret) {
+ printf("Error sending bitstream!\n");
+ return ret;
+ }
+
+ /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+ udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+ debug("Polling with MBOX_RECONFIG_STATUS...\n");
+ ret = reconfig_status_polling_resp();
+ if (ret) {
+ printf("FPGA reconfiguration failed!");
+ return ret;
+ }
+
+ puts("FPGA reconfiguration OK!\n");
+
+ return ret;
+}
+
+#else
+
+#include <asm/arch/mailbox_s10.h>
+
static const struct mbox_cfgstat_state {
int err_no;
const char *error_name;
@@ -281,3 +418,5 @@ int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
return ret;
}
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 16/17] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (14 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 15/17] arm: socfpga: stratix10: Add ATF support for FPGA reconfig driver chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-12 13:23 ` [PATCH v5 17/17] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support chee.hong.ang at intel.com
2020-03-18 14:52 ` [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot Ang, Chee Hong
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: Chee Hong Ang <chee.hong.ang@intel.com>
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/mailbox_s10.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index f30e7f8..6b39576 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -330,6 +330,9 @@ error:
int mbox_reset_cold(void)
{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+ psci_system_reset();
+#else
int ret;
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
@@ -338,6 +341,7 @@ int mbox_reset_cold(void)
/* mailbox sent failure, wait for watchdog to kick in */
hang();
}
+#endif
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 17/17] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (15 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 16/17] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() chee.hong.ang at intel.com
@ 2020-03-12 13:23 ` chee.hong.ang at intel.com
2020-03-18 14:52 ` [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot Ang, Chee Hong
17 siblings, 0 replies; 20+ messages in thread
From: chee.hong.ang at intel.com @ 2020-03-12 13:23 UTC (permalink / raw)
To: u-boot
From: "Ang, Chee Hong" <chee.hong.ang@intel.com>
Booting Agilex and Stratix 10 with ATF support.
SPL now loads ATF (BL31), U-Boot proper and DTB from FIT
image. The new boot flow with ATF support is as follow:
SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)
U-Boot proper now starts at 0x200000 (CONFIG_SYS_TEXT_BASE).
ATF will occupy the address range starting from 0x1000.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
---
configs/socfpga_agilex_atf_defconfig | 63 ++++++++++++++++++++++++++++++
configs/socfpga_stratix10_atf_defconfig | 68 +++++++++++++++++++++++++++++++++
2 files changed, 131 insertions(+)
create mode 100644 configs/socfpga_agilex_atf_defconfig
create mode 100644 configs/socfpga_stratix10_atf_defconfig
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
new file mode 100644
index 0000000..2373f89
--- /dev/null
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -0,0 +1,63 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_DM_GPIO=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_agilex"
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="board/altera/soc64/its/fit_spl_atf.its"
+CONFIG_BOOTDELAY=5
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
new file mode 100644
index 0000000..dc34357
--- /dev/null
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_DM_GPIO=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_stratix10"
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="board/altera/soc64/its/fit_spl_atf.its"
+CONFIG_BOOTDELAY=5
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot
2020-03-12 13:23 [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
` (16 preceding siblings ...)
2020-03-12 13:23 ` [PATCH v5 17/17] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support chee.hong.ang at intel.com
@ 2020-03-18 14:52 ` Ang, Chee Hong
2020-04-01 9:48 ` Ang, Chee Hong
17 siblings, 1 reply; 20+ messages in thread
From: Ang, Chee Hong @ 2020-03-18 14:52 UTC (permalink / raw)
To: u-boot
Any comment on this v5 patchsets ?
> From: "Ang, Chee Hong" <chee.hong.ang@intel.com>
>
> v5 changes:
> This is another revision without the System Manager driver to handle the
> secure/non-secure access. DW MAC and MMC drivers will make direct calls to
> the high-level API to ATF if it's running in EL2 on Stratix10/Agilex otherwise these
> drivers work as it is.
>
> [PATCH v5 08/17] arm: socfpga: Define SMC function identifiers for PSCI SiP
> services
> - Add documentation for high-level API supported by ATF:
> - INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF (For setting PHY interface)
> - INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK (For setting SDMMC clock
> phase)
>
> [PATCH v5 10/17] mmc: dwmmc: socfpga: Add ATF support for MMC driver
> - Call 'INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK' if U-Boot running in
> EL2 (non-secure)
>
> [PATCH v5 11/17] net: designware: socfpga: Add ATF support for MAC driver
> - Call 'INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF' if U-Boot running in EL2
> (non-secure)
>
> [PATCH v5 17/17] configs: socfpga: Add defconfig for Agilex and Stratix 10 with
> ATF support
> - Keep the existing Stratix10/Agilex defconfigs and add new defconfigs with ATF
> support
>
> v4:
> https://lists.denx.de/pipermail/u-boot/2020-March/402289.html
>
> These patchsets have dependency on:
> https://lists.denx.de/pipermail/u-boot/2019-September/384906.html
>
> Ang, Chee Hong (1):
> configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
> support
>
> Chee Hong Ang (16):
> configs: agilex: Remove CONFIG_OF_EMBED
> arm: socfpga: add fit source file for pack itb with ATF
> arm: socfpga: Add function for checking description from FIT image
> arm: socfpga: Load FIT image with ATF support
> arm: socfpga: Override 'lowlevel_init' to support ATF
> arm: socfpga: Disable "spin-table" method for booting Linux
> arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits)
> arm: socfpga: Define SMC function identifiers for PSCI SiP services
> arm: socfpga: soc64: Remove PHY interface setup from misc arch init
> mmc: dwmmc: socfpga: Add ATF support for MMC driver
> net: designware: socfpga: Add ATF support for MAC driver
> arm: socfpga: Add ATF support for Reset Manager driver
> arm: socfpga: stratix10: Initialize timer in SPL
> arm: socfpga: Add ATF support to query FPGA configuration status
> arm: socfpga: stratix10: Add ATF support for FPGA reconfig driver
> arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
> mbox_reset_cold()
>
> arch/arm/mach-socfpga/Kconfig | 2 -
> arch/arm/mach-socfpga/Makefile | 2 +
> arch/arm/mach-socfpga/board.c | 10 +
> arch/arm/mach-socfpga/include/mach/misc.h | 3 +
> arch/arm/mach-socfpga/lowlevel_init_64.S | 81 ++++
> arch/arm/mach-socfpga/mailbox_s10.c | 4 +
> arch/arm/mach-socfpga/misc_s10.c | 121 ++----
> arch/arm/mach-socfpga/reset_manager_s10.c | 10 +
> arch/arm/mach-socfpga/timer_s10.c | 3 +-
> board/altera/soc64/its/fit_spl_atf.its | 52 +++
> ...ilex_defconfig => socfpga_agilex_atf_defconfig} | 8 +-
> configs/socfpga_agilex_defconfig | 1 -
> ...x_defconfig => socfpga_stratix10_atf_defconfig} | 23 +-
> drivers/fpga/stratix10.c | 141 ++++++-
> drivers/mmc/socfpga_dw_mmc.c | 21 +
> drivers/net/dwmac_socfpga.c | 43 +-
> include/configs/socfpga_soc64_common.h | 4 +
> include/linux/intel-smc.h | 445 +++++++++++++++++++++
> 18 files changed, 871 insertions(+), 103 deletions(-) create mode 100644
> arch/arm/mach-socfpga/lowlevel_init_64.S
> create mode 100644 board/altera/soc64/its/fit_spl_atf.its
> copy configs/{socfpga_agilex_defconfig => socfpga_agilex_atf_defconfig}
> (87%) copy configs/{socfpga_agilex_defconfig =>
> socfpga_stratix10_atf_defconfig} (68%) create mode 100644
> include/linux/intel-smc.h
>
> --
> 2.7.4
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot
2020-03-18 14:52 ` [PATCH v5 00/17] Enable ARM Trusted Firmware for U-Boot Ang, Chee Hong
@ 2020-04-01 9:48 ` Ang, Chee Hong
0 siblings, 0 replies; 20+ messages in thread
From: Ang, Chee Hong @ 2020-04-01 9:48 UTC (permalink / raw)
To: u-boot
Hi Marek/Simon,
Can you please help review and comment on this patchsets ?
> Any comment on this v5 patchsets ?
>
> > From: "Ang, Chee Hong" <chee.hong.ang@intel.com>
> >
> > v5 changes:
> > This is another revision without the System Manager driver to handle
> > the secure/non-secure access. DW MAC and MMC drivers will make direct
> > calls to the high-level API to ATF if it's running in EL2 on
> > Stratix10/Agilex otherwise these drivers work as it is.
> >
> > [PATCH v5 08/17] arm: socfpga: Define SMC function identifiers for
> > PSCI SiP services
> > - Add documentation for high-level API supported by ATF:
> > - INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF (For setting PHY interface)
> > - INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK (For setting SDMMC
> clock
> > phase)
> >
> > [PATCH v5 10/17] mmc: dwmmc: socfpga: Add ATF support for MMC driver
> > - Call 'INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK' if U-Boot running in
> > EL2 (non-secure)
> >
> > [PATCH v5 11/17] net: designware: socfpga: Add ATF support for MAC
> > driver
> > - Call 'INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF' if U-Boot running in EL2
> > (non-secure)
> >
> > [PATCH v5 17/17] configs: socfpga: Add defconfig for Agilex and
> > Stratix 10 with ATF support
> > - Keep the existing Stratix10/Agilex defconfigs and add new defconfigs
> > with ATF support
> >
> > v4:
> > https://lists.denx.de/pipermail/u-boot/2020-March/402289.html
> >
> > These patchsets have dependency on:
> > https://lists.denx.de/pipermail/u-boot/2019-September/384906.html
> >
> > Ang, Chee Hong (1):
> > configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
> > support
> >
> > Chee Hong Ang (16):
> > configs: agilex: Remove CONFIG_OF_EMBED
> > arm: socfpga: add fit source file for pack itb with ATF
> > arm: socfpga: Add function for checking description from FIT image
> > arm: socfpga: Load FIT image with ATF support
> > arm: socfpga: Override 'lowlevel_init' to support ATF
> > arm: socfpga: Disable "spin-table" method for booting Linux
> > arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits)
> > arm: socfpga: Define SMC function identifiers for PSCI SiP services
> > arm: socfpga: soc64: Remove PHY interface setup from misc arch init
> > mmc: dwmmc: socfpga: Add ATF support for MMC driver
> > net: designware: socfpga: Add ATF support for MAC driver
> > arm: socfpga: Add ATF support for Reset Manager driver
> > arm: socfpga: stratix10: Initialize timer in SPL
> > arm: socfpga: Add ATF support to query FPGA configuration status
> > arm: socfpga: stratix10: Add ATF support for FPGA reconfig driver
> > arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
> > mbox_reset_cold()
> >
> > arch/arm/mach-socfpga/Kconfig | 2 -
> > arch/arm/mach-socfpga/Makefile | 2 +
> > arch/arm/mach-socfpga/board.c | 10 +
> > arch/arm/mach-socfpga/include/mach/misc.h | 3 +
> > arch/arm/mach-socfpga/lowlevel_init_64.S | 81 ++++
> > arch/arm/mach-socfpga/mailbox_s10.c | 4 +
> > arch/arm/mach-socfpga/misc_s10.c | 121 ++----
> > arch/arm/mach-socfpga/reset_manager_s10.c | 10 +
> > arch/arm/mach-socfpga/timer_s10.c | 3 +-
> > board/altera/soc64/its/fit_spl_atf.its | 52 +++
> > ...ilex_defconfig => socfpga_agilex_atf_defconfig} | 8 +-
> > configs/socfpga_agilex_defconfig | 1 -
> > ...x_defconfig => socfpga_stratix10_atf_defconfig} | 23 +-
> > drivers/fpga/stratix10.c | 141 ++++++-
> > drivers/mmc/socfpga_dw_mmc.c | 21 +
> > drivers/net/dwmac_socfpga.c | 43 +-
> > include/configs/socfpga_soc64_common.h | 4 +
> > include/linux/intel-smc.h | 445 +++++++++++++++++++++
> > 18 files changed, 871 insertions(+), 103 deletions(-) create mode
> > 100644 arch/arm/mach-socfpga/lowlevel_init_64.S
> > create mode 100644 board/altera/soc64/its/fit_spl_atf.its
> > copy configs/{socfpga_agilex_defconfig =>
> > socfpga_agilex_atf_defconfig}
> > (87%) copy configs/{socfpga_agilex_defconfig =>
> > socfpga_stratix10_atf_defconfig} (68%) create mode 100644
> > include/linux/intel-smc.h
> >
> > --
> > 2.7.4
^ permalink raw reply [flat|nested] 20+ messages in thread