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* [Intel-wired-lan] [PATCH net-next v1] i40e: add description and modify interrupts configuration procedure
@ 2022-08-05 11:34 Andrii Staikov
  2022-08-05 17:47 ` Nguyen, Anthony L
  0 siblings, 1 reply; 2+ messages in thread
From: Andrii Staikov @ 2022-08-05 11:34 UTC (permalink / raw)
  To: intel-wired-lan; +Cc: Jaroslaw Gawin, Staikov Andrii

From: Staikov Andrii <andrii.staikov@intel.com>

Add description for values written into registers QINT_XXXX
and small cosmetic changes for MSI/LEGACY interrupts
configuration in the same way as for MSI-X.
Descriptions confirm the code is written correctly and
make the code clear. Small cosmetic changes for MSI/LEGACY
interrupts make code clear in the same manner as for MSI-X
interrupts.
Without this descriptions the code doesn't look right.

Signed-off-by: Jaroslaw Gawin <jaroslawx.gawin@intel.com>
Signed-off-by: Andrii Staikov <andrii.staikov@intel.com>
---
 drivers/net/ethernet/intel/i40e/i40e.h      | 14 ++++++++
 drivers/net/ethernet/intel/i40e/i40e_main.c | 36 ++++++++-------------
 2 files changed, 28 insertions(+), 22 deletions(-)

diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h
index d86b6d349ea9..9a60d6b207f7 100644
--- a/drivers/net/ethernet/intel/i40e/i40e.h
+++ b/drivers/net/ethernet/intel/i40e/i40e.h
@@ -399,6 +399,20 @@ struct i40e_ddp_old_profile_list {
 				 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
 				 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
 
+#define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \
+	(I40E_QINT_TQCTL_CAUSE_ENA_MASK | \
+	(I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \
+	((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \
+	((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \
+	(I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT))
+
+#define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \
+	(I40E_QINT_RQCTL_CAUSE_ENA_MASK | \
+	(I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
+	((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \
+	((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \
+	(I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))
+
 struct i40e_flex_pit {
 	struct list_head list;
 	u16 src_offset;
diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
index 9f1d5de7bf16..174511d64627 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
@@ -3878,7 +3878,7 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
 		wr32(hw, I40E_PFINT_RATEN(vector - 1),
 		     i40e_intrl_usec_to_reg(vsi->int_rate_limit));
 
-		/* Linked list for the queuepairs assigned to this vector */
+		/* begin of linked list for RX queue assigned to this vector */
 		wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
 		for (q = 0; q < q_vector->num_ringpairs; q++) {
 			u32 nextqp = has_xdp ? qp + vsi->alloc_queue_pairs : qp;
@@ -3894,6 +3894,7 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
 			wr32(hw, I40E_QINT_RQCTL(qp), val);
 
 			if (has_xdp) {
+				/* TX queue with next queue set to TX */
 				val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
 				      (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
 				      (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
@@ -3903,7 +3904,7 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
 
 				wr32(hw, I40E_QINT_TQCTL(nextqp), val);
 			}
-
+			/* TX queue with next RX or end of linked list */
 			val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
 			      (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
 			      (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
@@ -3972,7 +3973,6 @@ static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
 	struct i40e_q_vector *q_vector = vsi->q_vectors[0];
 	struct i40e_pf *pf = vsi->back;
 	struct i40e_hw *hw = &pf->hw;
-	u32 val;
 
 	/* set the ITR configuration */
 	q_vector->rx.next_update = jiffies + 1;
@@ -3989,28 +3989,20 @@ static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
 	/* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
 	wr32(hw, I40E_PFINT_LNKLST0, 0);
 
-	/* Associate the queue pair to the vector and enable the queue int */
-	val = I40E_QINT_RQCTL_CAUSE_ENA_MASK		       |
-	      (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT)  |
-	      (nextqp	   << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
-	      (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
-
-	wr32(hw, I40E_QINT_RQCTL(0), val);
-
-	if (i40e_enabled_xdp_vsi(vsi)) {
-		val = I40E_QINT_TQCTL_CAUSE_ENA_MASK		     |
-		      (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT)|
-		      (I40E_QUEUE_TYPE_TX
-		       << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
+	/* Associate the queue pair to the vector and enable the queue
+	 * interrupt RX queue in linked list with next queue set to TX
+	 */
+	wr32(hw, I40E_QINT_RQCTL(0), I40E_QINT_RQCTL_VAL(nextqp, 0, TX));
 
-		wr32(hw, I40E_QINT_TQCTL(nextqp), val);
+	if (nextqp) {
+		/* TX queue in linked list with next queue set to TX */
+		wr32(hw, I40E_QINT_TQCTL(nextqp),
+		     I40E_QINT_TQCTL_VAL(nextqp, 0, TX));
 	}
 
-	val = I40E_QINT_TQCTL_CAUSE_ENA_MASK		      |
-	      (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
-	      (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
-
-	wr32(hw, I40E_QINT_TQCTL(0), val);
+	/* last TX queue so the next RX queue doesn't matter */
+	wr32(hw, I40E_QINT_TQCTL(0),
+	     I40E_QINT_TQCTL_VAL(I40E_QUEUE_END_OF_LIST, 0, RX));
 	i40e_flush(hw);
 }
 
-- 
2.25.1

---------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.

_______________________________________________
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https://lists.osuosl.org/mailman/listinfo/intel-wired-lan

^ permalink raw reply related	[flat|nested] 2+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next v1] i40e: add description and modify interrupts configuration procedure
  2022-08-05 11:34 [Intel-wired-lan] [PATCH net-next v1] i40e: add description and modify interrupts configuration procedure Andrii Staikov
@ 2022-08-05 17:47 ` Nguyen, Anthony L
  0 siblings, 0 replies; 2+ messages in thread
From: Nguyen, Anthony L @ 2022-08-05 17:47 UTC (permalink / raw)
  To: Staikov, Andrii, intel-wired-lan; +Cc: Gawin, JaroslawX, Staikov, Andrii



> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
> Andrii Staikov
> Sent: Friday, August 05, 2022 4:34 AM
> To: intel-wired-lan@lists.osuosl.org
> Cc: Gawin, JaroslawX <jaroslawx.gawin@intel.com>; Staikov, Andrii
> <andrii.staikov@intel.com>
> Subject: [Intel-wired-lan] [PATCH net-next v1] i40e: add description and
> modify interrupts configuration procedure
> 
> From: Staikov Andrii <andrii.staikov@intel.com>

WARNING: From:/Signed-off-by: email name mismatch: 'From: Staikov Andrii <andrii.staikov@intel.com>' != 'Signed-off-by: Andrii Staikov <andrii.staikov@intel.com>'

> 
> Add description for values written into registers QINT_XXXX and small
> cosmetic changes for MSI/LEGACY interrupts configuration in the same way
> as for MSI-X.
> Descriptions confirm the code is written correctly and make the code clear.
> Small cosmetic changes for MSI/LEGACY interrupts make code clear in the
> same manner as for MSI-X interrupts.
> Without this descriptions the code doesn't look right.

I would say that's arguable 😊

> 
> Signed-off-by: Jaroslaw Gawin <jaroslawx.gawin@intel.com>
> Signed-off-by: Andrii Staikov <andrii.staikov@intel.com>

If you are the author, you should be the first Sign-off. That would make Jaroslaw a Co-developed-by? Which should be added if so.

> ---
>  drivers/net/ethernet/intel/i40e/i40e.h      | 14 ++++++++
>  drivers/net/ethernet/intel/i40e/i40e_main.c | 36 ++++++++-------------
>  2 files changed, 28 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/net/ethernet/intel/i40e/i40e.h
> b/drivers/net/ethernet/intel/i40e/i40e.h
> index d86b6d349ea9..9a60d6b207f7 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e.h
> +++ b/drivers/net/ethernet/intel/i40e/i40e.h
> @@ -399,6 +399,20 @@ struct i40e_ddp_old_profile_list {
>  				 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK
> | \
>  				 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
> 
> +#define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \
> +	(I40E_QINT_TQCTL_CAUSE_ENA_MASK | \
> +	(I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \
> +	((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \
> +	((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \
> +	(I40E_QUEUE_TYPE_##nextq_type <<
> I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT))
> +
> +#define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \
> +	(I40E_QINT_RQCTL_CAUSE_ENA_MASK | \
> +	(I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
> +	((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \
> +	((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \
> +	(I40E_QUEUE_TYPE_##nextq_type <<
> I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))
> +
>  struct i40e_flex_pit {
>  	struct list_head list;
>  	u16 src_offset;
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c
> b/drivers/net/ethernet/intel/i40e/i40e_main.c
> index 9f1d5de7bf16..174511d64627 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_main.c
> +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
> @@ -3878,7 +3878,7 @@ static void i40e_vsi_configure_msix(struct i40e_vsi
> *vsi)
>  		wr32(hw, I40E_PFINT_RATEN(vector - 1),
>  		     i40e_intrl_usec_to_reg(vsi->int_rate_limit));
> 
> -		/* Linked list for the queuepairs assigned to this vector */
> +		/* begin of linked list for RX queue assigned to this vector */
>  		wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
>  		for (q = 0; q < q_vector->num_ringpairs; q++) {
>  			u32 nextqp = has_xdp ? qp + vsi->alloc_queue_pairs :
> qp; @@ -3894,6 +3894,7 @@ static void i40e_vsi_configure_msix(struct
> i40e_vsi *vsi)
>  			wr32(hw, I40E_QINT_RQCTL(qp), val);
> 
>  			if (has_xdp) {
> +				/* TX queue with next queue set to TX */
>  				val = I40E_QINT_TQCTL_CAUSE_ENA_MASK
> |
>  				      (I40E_TX_ITR <<
> I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
>  				      (vector <<
> I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | @@ -3903,7 +3904,7 @@ static void
> i40e_vsi_configure_msix(struct i40e_vsi *vsi)
> 
>  				wr32(hw, I40E_QINT_TQCTL(nextqp), val);
>  			}
> -
> +			/* TX queue with next RX or end of linked list */
>  			val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
>  			      (I40E_TX_ITR <<
> I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
>  			      (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT)
> | @@ -3972,7 +3973,6 @@ static void i40e_configure_msi_and_legacy(struct
> i40e_vsi *vsi)
>  	struct i40e_q_vector *q_vector = vsi->q_vectors[0];
>  	struct i40e_pf *pf = vsi->back;
>  	struct i40e_hw *hw = &pf->hw;
> -	u32 val;
> 
>  	/* set the ITR configuration */
>  	q_vector->rx.next_update = jiffies + 1; @@ -3989,28 +3989,20 @@
> static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
>  	/* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
>  	wr32(hw, I40E_PFINT_LNKLST0, 0);
> 
> -	/* Associate the queue pair to the vector and enable the queue int
> */
> -	val = I40E_QINT_RQCTL_CAUSE_ENA_MASK		       |
> -	      (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT)  |
> -	      (nextqp	   << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
> -	      (I40E_QUEUE_TYPE_TX <<
> I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
> -
> -	wr32(hw, I40E_QINT_RQCTL(0), val);
> -
> -	if (i40e_enabled_xdp_vsi(vsi)) {
> -		val = I40E_QINT_TQCTL_CAUSE_ENA_MASK		     |
> -		      (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT)|
> -		      (I40E_QUEUE_TYPE_TX
> -		       << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
> +	/* Associate the queue pair to the vector and enable the queue
> +	 * interrupt RX queue in linked list with next queue set to TX
> +	 */
> +	wr32(hw, I40E_QINT_RQCTL(0), I40E_QINT_RQCTL_VAL(nextqp, 0,
> TX));
> 
> -		wr32(hw, I40E_QINT_TQCTL(nextqp), val);
> +	if (nextqp) {

I find this more readable using the existing i40e_enabled_xdp_vsi() check over nextqp.

> +		/* TX queue in linked list with next queue set to TX */
> +		wr32(hw, I40E_QINT_TQCTL(nextqp),
> +		     I40E_QINT_TQCTL_VAL(nextqp, 0, TX));
>  	}
> 
> -	val = I40E_QINT_TQCTL_CAUSE_ENA_MASK		      |
> -	      (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
> -	      (I40E_QUEUE_END_OF_LIST <<
> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
> -
> -	wr32(hw, I40E_QINT_TQCTL(0), val);
> +	/* last TX queue so the next RX queue doesn't matter */
> +	wr32(hw, I40E_QINT_TQCTL(0),
> +	     I40E_QINT_TQCTL_VAL(I40E_QUEUE_END_OF_LIST, 0, RX));
>  	i40e_flush(hw);
>  }
> 
> --
> 2.25.1
> 
> ---------------------------------------------------------------------
> Intel Technology Poland sp. z o.o.
> ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII
> Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-
> 07-52-316 | Kapital zakladowy 200.000 PLN.
> Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego
> adresata i moze zawierac informacje poufne. W razie przypadkowego
> otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale
> jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest
> zabronione.
> This e-mail and any attachments may contain confidential material for the
> sole use of the intended recipient(s). If you are not the intended recipient,
> please contact the sender and delete all copies; any review or distribution by
> others is strictly prohibited.

Please remove this footer.

_______________________________________________
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Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan

^ permalink raw reply	[flat|nested] 2+ messages in thread
end of thread, other threads:[~2022-08-05 17:48 UTC | newest]

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2022-08-05 17:47 ` Nguyen, Anthony L

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