[Intel-gfx] [PATCH 0/9] Add DSC fractional bpp support

[Intel-gfx] [PATCH 0/9] Add DSC fractional bpp support

[Ankit Nautiyal]

This patch series adds support for DSC fractional compressed bpp
for MTL+.

First fix patch is taken from :
https://patchwork.freedesktop.org/series/122613/
Adding here to to avoid issues while reading fractional bpp support.
The new few patches, add changes to accommodate compressed bpp with
fractional part, including changes to QP calculations.
To get the 'best' compressed bpp, we iterate over the valid compressed
bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
sink support.

The last 2 patches add support to depict DSC sink's fractional support,
and debugfs to enforce use of fractional bpp, while choosing an
appropriate compressed bpp.

Ankit Nautiyal (6):
  drm/display/dp: Fix the DP DSC Receiver cap size
  drm/i915/display: Store compressed bpp in U6.4 format
  drm/i915/display: Consider fractional vdsc bpp while computing m_n
    values
  drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
  drm/display/dp: Add helper function to get DSC bpp prescision
  drm/i915/dp: Iterate over output bpp with fractional step size

Swati Sharma (2):
  drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
  drm/i915/dsc: Allow DSC only with fractional bpp when forced from
    debugfs

Vandita Kulkarni (1):
  drm/i915/dsc/mtl: Add support for fractional bpp

 drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
 drivers/gpu/drm/i915/display/icl_dsi.c        | 10 +--
 drivers/gpu/drm/i915/display/intel_audio.c    | 14 ++--
 drivers/gpu/drm/i915/display/intel_bios.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  6 +-
 drivers/gpu/drm/i915/display/intel_display.h  |  2 +-
 .../drm/i915/display/intel_display_debugfs.c  | 82 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    | 17 +++-
 drivers/gpu/drm/i915/display/intel_dp.c       | 68 +++++++++------
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  6 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      |  2 +-
 .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 27 ++++--
 include/drm/display/drm_dp.h                  |  2 +-
 include/drm/display/drm_dp_helper.h           |  1 +
 15 files changed, 216 insertions(+), 53 deletions(-)

-- 
2.40.1

[Intel-gfx] [PATCH 1/9] drm/display/dp: Fix the DP DSC Receiver cap size

[Ankit Nautiyal]

DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.

Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: <stable@vger.kernel.org> # v5.0+

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 include/drm/display/drm_dp.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 02f2ac4dd2df..e69cece404b3 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1537,7 +1537,7 @@ enum drm_dp_phy {
 
 #define DP_BRANCH_OUI_HEADER_SIZE	0xc
 #define DP_RECEIVER_CAP_SIZE		0xf
-#define DP_DSC_RECEIVER_CAP_SIZE        0xf
+#define DP_DSC_RECEIVER_CAP_SIZE        0x10 /* DSC Capabilities 0x60 through 0x6F */
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
 #define EDP_DISPLAY_CTL_CAP_SIZE	3
 #define DP_LTTPR_COMMON_CAP_SIZE	8
-- 
2.40.1

[Intel-gfx] [PATCH 2/9] drm/i915/display: Store compressed bpp in U6.4 format

[Ankit Nautiyal]

DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractional part,
compressed_bpp is changed to store bpp in U6.4 formats. Intergral
part is retrieved by simply right shifting the member compressed_bpp by 4.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        | 10 ++++-----
 drivers/gpu/drm/i915/display/intel_audio.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_bios.c     |  2 +-
 .../drm/i915/display/intel_display_types.h    | 16 +++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.c       | 21 +++++++++++--------
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  4 ++--
 6 files changed, 36 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ad6488e9c2b2..81b8e97e9435 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder,
 	int bpp;
 
 	if (crtc_state->dsc.compression_enable)
-		bpp = crtc_state->dsc.compressed_bpp;
+		bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
 	else
 		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
@@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	 * compressed and non-compressed bpp.
 	 */
 	if (crtc_state->dsc.compression_enable) {
-		mul = crtc_state->dsc.compressed_bpp;
+		mul = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
 		div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 	}
 
@@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 		int bpp, line_time_us, byte_clk_period_ns;
 
 		if (crtc_state->dsc.compression_enable)
-			bpp = crtc_state->dsc.compressed_bpp;
+			bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
 		else
 			bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
@@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
 	struct drm_display_mode *adjusted_mode =
 					&pipe_config->hw.adjusted_mode;
 
-	if (pipe_config->dsc.compressed_bpp) {
-		int div = pipe_config->dsc.compressed_bpp;
+	if (dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)) {
+		int div = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
 		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
 		adjusted_mode->crtc_htotal =
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 3d9c9b4f27f8..93969b63cdd8 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
-	vdsc_bpp = crtc_state->dsc.compressed_bpp;
+	vdsc_bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
 	cdclk = i915->display.cdclk.hw.cdclk;
 	/* fec= 0.972261, using rounding multiplier of 1000000 */
 	fec_coeff = 972261;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 858c959f7bab..fe1e376c4ba7 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3385,7 +3385,7 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
 	crtc_state->pipe_bpp = bpc * 3;
 
 	crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
-					     VBT_DSC_MAX_BPP(dsc->max_bpp));
+					     VBT_DSC_MAX_BPP(dsc->max_bpp)) << 4;
 
 	/*
 	 * FIXME: This is ugly, and slice count should take DSC engine
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 731f2ec04d5c..f749dc4e70df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1353,7 +1353,7 @@ struct intel_crtc_state {
 	struct {
 		bool compression_enable;
 		bool dsc_split;
-		u16 compressed_bpp;
+		u16 compressed_bpp; /* U6.4 format (first 4 bits for fractional part) */
 		u8 slice_count;
 		struct drm_dsc_config config;
 	} dsc;
@@ -2108,4 +2108,18 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
 	return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
 }
 
+/* Returns integral part of the compressed bpp given in U6.4 format */
+static inline int
+dsc_integral_compressed_bpp(u16 compressed_bpp)
+{
+	return compressed_bpp >> 4;
+}
+
+/* Returns fractional part of the compressed bpp given in U6.4 format */
+static inline int
+dsc_fractional_compressed_bpp(u16 compressed_bpp)
+{
+	return ((compressed_bpp & 0xF) * 10000 / 16);
+}
+
 #endif /*  __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5b48bfe09d0e..32d0bee11f53 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1901,7 +1901,7 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 					      compressed_bpp,
 					      timeslots);
 		if (ret == 0) {
-			pipe_config->dsc.compressed_bpp = compressed_bpp;
+			pipe_config->dsc.compressed_bpp = compressed_bpp << 4;
 			return 0;
 		}
 	}
@@ -2171,17 +2171,19 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	if (ret < 0) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "Cannot compute valid DSC parameters for Input Bpp = %d "
-			    "Compressed BPP = %d\n",
+			    "Compressed BPP = %d.%d\n",
 			    pipe_config->pipe_bpp,
-			    pipe_config->dsc.compressed_bpp);
+			    dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp),
+			    dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp));
 		return ret;
 	}
 
 	pipe_config->dsc.compression_enable = true;
 	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
-		    "Compressed Bpp = %d Slice Count = %d\n",
+		    "Compressed Bpp = %d.%d Slice Count = %d\n",
 		    pipe_config->pipe_bpp,
-		    pipe_config->dsc.compressed_bpp,
+		    dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp),
+		    dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp),
 		    pipe_config->dsc.slice_count);
 
 	return 0;
@@ -2260,15 +2262,16 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 
 	if (pipe_config->dsc.compression_enable) {
 		drm_dbg_kms(&i915->drm,
-			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
+			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d.%d\n",
 			    pipe_config->lane_count, pipe_config->port_clock,
 			    pipe_config->pipe_bpp,
-			    pipe_config->dsc.compressed_bpp);
+			    dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp),
+			    dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp));
 
 		drm_dbg_kms(&i915->drm,
 			    "DP link rate required %i available %i\n",
 			    intel_dp_link_required(adjusted_mode->crtc_clock,
-						   pipe_config->dsc.compressed_bpp),
+						   dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)),
 			    intel_dp_max_data_rate(pipe_config->port_clock,
 						   pipe_config->lane_count));
 	} else {
@@ -2700,7 +2703,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		intel_dp_limited_color_range(pipe_config, conn_state);
 
 	if (pipe_config->dsc.compression_enable)
-		link_bpp = pipe_config->dsc.compressed_bpp;
+		link_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
 	else
 		link_bpp = intel_dp_output_bpp(pipe_config->output_format,
 					       pipe_config->pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index e4c395b4dc46..2dc6ea82c024 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
-	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
+	u16 compressed_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
 	int err;
 	int ret;
 
@@ -1040,7 +1040,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	if (pps0 & DSC_NATIVE_420_ENABLE)
 		vdsc_cfg->bits_per_pixel >>= 1;
 
-	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel;
 out:
 	intel_display_power_put(dev_priv, power_domain, wakeref);
 }
-- 
2.40.1

[Intel-gfx] [PATCH 3/9] drm/i915/display: Consider fractional vdsc bpp while computing m_n values

[Ankit Nautiyal]

MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
 drivers/gpu/drm/i915/display/intel_display.h | 2 +-
 drivers/gpu/drm/i915/display/intel_dp.c      | 7 ++++---
 drivers/gpu/drm/i915/display/intel_dp_mst.c  | 6 ++++--
 drivers/gpu/drm/i915/display/intel_fdi.c     | 2 +-
 5 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8c81206ce90d..9af36e600c87 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2380,10 +2380,14 @@ void
 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
 		       int pixel_clock, int link_clock,
 		       struct intel_link_m_n *m_n,
-		       bool fec_enable)
+		       bool fec_enable,
+		       bool is_dsc_fractional_bpp)
 {
 	u32 data_clock = bits_per_pixel * pixel_clock;
 
+	if (is_dsc_fractional_bpp)
+		data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16);
+
 	if (fec_enable)
 		data_clock = intel_dp_mode_to_fec_clock(data_clock);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 49ac8473b988..a4c4ca3cad65 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
 void intel_link_compute_m_n(u16 bpp, int nlanes,
 			    int pixel_clock, int link_clock,
 			    struct intel_link_m_n *m_n,
-			    bool fec_enable);
+			    bool fec_enable, bool is_dsc_fractional_bpp);
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 			      u32 pixel_format, u64 modifier);
 enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 32d0bee11f53..436889c601b1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2557,7 +2557,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 
 	intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
 			       pipe_config->port_clock, &pipe_config->dp_m2_n2,
-			       pipe_config->fec_enable);
+			       pipe_config->fec_enable, false);
 
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
@@ -2703,7 +2703,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		intel_dp_limited_color_range(pipe_config, conn_state);
 
 	if (pipe_config->dsc.compression_enable)
-		link_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
+		link_bpp = pipe_config->dsc.compressed_bpp;
 	else
 		link_bpp = intel_dp_output_bpp(pipe_config->output_format,
 					       pipe_config->pipe_bpp);
@@ -2735,7 +2735,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 			       adjusted_mode->crtc_clock,
 			       pipe_config->port_clock,
 			       &pipe_config->dp_m_n,
-			       pipe_config->fec_enable);
+			       pipe_config->fec_enable,
+			       pipe_config->dsc.compression_enable);
 
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3eb085fbc7c8..e224eebe7c17 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -171,7 +171,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 			       adjusted_mode->crtc_clock,
 			       crtc_state->port_clock,
 			       &crtc_state->dp_m_n,
-			       crtc_state->fec_enable);
+			       crtc_state->fec_enable,
+			       false);
 	crtc_state->dp_m_n.tu = slots;
 
 	return 0;
@@ -265,7 +266,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 			       adjusted_mode->crtc_clock,
 			       crtc_state->port_clock,
 			       &crtc_state->dp_m_n,
-			       crtc_state->fec_enable);
+			       crtc_state->fec_enable,
+			       crtc_state->dsc.compression_enable);
 	crtc_state->dp_m_n.tu = slots;
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index e12b46a84fa1..15fddabf7c2e 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
 	pipe_config->fdi_lanes = lane;
 
 	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
-			       link_bw, &pipe_config->fdi_m_n, false);
+			       link_bw, &pipe_config->fdi_m_n, false, false);
 
 	ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
 	if (ret == -EDEADLK)
-- 
2.40.1

[Intel-gfx] [PATCH 4/9] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data

[Ankit Nautiyal]

MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.

v2:
-Fixed tu_data calculation while dealing with U6.4 format. (Stan)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_audio.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 93969b63cdd8..bbd99e2fb399 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -521,14 +521,14 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 	unsigned int link_clks_available, link_clks_required;
 	unsigned int tu_data, tu_line, link_clks_active;
 	unsigned int h_active, h_total, hblank_delta, pixel_clk;
-	unsigned int fec_coeff, cdclk, vdsc_bpp;
+	unsigned int fec_coeff, cdclk, vdsc_bppx16;
 	unsigned int link_clk, lanes;
 	unsigned int hblank_rise;
 
 	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
-	vdsc_bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
+	vdsc_bppx16 = crtc_state->dsc.compressed_bpp;
 	cdclk = i915->display.cdclk.hw.cdclk;
 	/* fec= 0.972261, using rounding multiplier of 1000000 */
 	fec_coeff = 972261;
@@ -536,10 +536,10 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 	lanes = crtc_state->lane_count;
 
 	drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
-		    "lanes = %u vdsc_bpp = %u cdclk = %u\n",
-		    h_active, link_clk, lanes, vdsc_bpp, cdclk);
+		    "lanes = %u vdsc_bppx16 = %u cdclk = %u\n",
+		    h_active, link_clk, lanes, vdsc_bppx16, cdclk);
 
-	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
+	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
 		return 0;
 
 	link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
@@ -551,8 +551,8 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 		hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
 						  mul_u32_u32(link_clk, cdclk));
 
-	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
-			    mul_u32_u32(link_clk * lanes, fec_coeff));
+	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
+			    mul_u32_u32(link_clk * lanes * 16, fec_coeff));
 	tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
 			    mul_u32_u32(64 * pixel_clk, 1000000));
 	link_clks_active  = (tu_line - 1) * 64 + tu_data;
-- 
2.40.1

[Intel-gfx] [PATCH 5/9] drm/display/dp: Add helper function to get DSC bpp prescision

[Ankit Nautiyal]

Add helper to get the DSC bits_per_pixel precision for the DP sink.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++
 include/drm/display/drm_dp_helper.h     |  1 +
 2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index e6a78fd32380..aa8ea36211de 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
 }
 EXPORT_SYMBOL(drm_dp_read_desc);
 
+/**
+ * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
+ * @dsc_dpcd: DSC capabilities from DPCD
+ *
+ * Returns the bpp precision supported by the DP sink.
+ */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
+
+	switch (bpp_increment_dpcd) {
+	case DP_DSC_BITS_PER_PIXEL_1_16:
+		return 16;
+	case DP_DSC_BITS_PER_PIXEL_1_8:
+		return 8;
+	case DP_DSC_BITS_PER_PIXEL_1_4:
+		return 4;
+	case DP_DSC_BITS_PER_PIXEL_1_2:
+		return 2;
+	case DP_DSC_BITS_PER_PIXEL_1_1:
+		return 1;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
+
 /**
  * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
  * supported by the DSC sink.
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 86f24a759268..ba0514f0b032 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 }
 
 /* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
 				   bool is_edp);
 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
-- 
2.40.1

[Intel-gfx] [PATCH 6/9] drm/i915/dsc/mtl: Add support for fractional bpp

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Consider the fractional bpp while reading the qp values.

v2: Use helpers for fractional, integral bits of bits_per_pixel.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../gpu/drm/i915/display/intel_qp_tables.c    |  3 ---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 23 +++++++++++++++----
 2 files changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 543cdc46aa1d..600c815e37e4 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -34,9 +34,6 @@
  * These qp tables are as per the C model
  * and it has the rows pointing to bpps which increment
  * in steps of 0.5
- * We do not support fractional bpps as of today,
- * hence we would skip the fractional bpps during
- * our references for qp calclulations.
  */
 static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 2dc6ea82c024..4bd570fb0ab2 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -77,8 +77,9 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
 static void
 calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 {
+	int fractional_bits = dsc_fractional_compressed_bpp(vdsc_cfg->bits_per_pixel);
+	int bpp = dsc_integral_compressed_bpp(vdsc_cfg->bits_per_pixel);
 	int bpc = vdsc_cfg->bits_per_component;
-	int bpp = vdsc_cfg->bits_per_pixel >> 4;
 	int qp_bpc_modifier = (bpc - 8) * 2;
 	int uncompressed_bpg_rate;
 	int first_line_bpg_offset;
@@ -148,7 +149,13 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 		static const s8 ofs_und8[] = {
 			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
 		};
-
+	/*
+	 * For 420 format since bits_per_pixel (bpp) is set to target bpp * 2,
+	 * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0) are
+	 * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).
+	 * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5)
+	 * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.
+	 */
 		bpp_i  = bpp - 8;
 		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
 			u8 range_bpg_offset;
@@ -191,7 +198,14 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
 		};
 
-		bpp_i  = (2 * (bpp - 6));
+		/*
+		 * QP table rows have values in increment of 0.5.
+		 * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1,
+		 * and so on.
+		 * 0.5 represented as 0x8 in U6.4 format.
+		 */
+		bpp_i  = ((bpp - 6) + (fractional_bits < 0x8 ? 0 : 1));
+
 		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
 			u8 range_bpg_offset;
 
@@ -279,8 +293,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	/* Gen 11 does not support VBR */
 	vdsc_cfg->vbr_enable = false;
 
-	/* Gen 11 only supports integral values of bpp */
-	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+	vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp;
 
 	/*
 	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set
-- 
2.40.1

[Intel-gfx] [PATCH 7/9] drm/i915/dp: Iterate over output bpp with fractional step size

[Ankit Nautiyal]

This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.

v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 36 ++++++++++++++++---------
 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 436889c601b1..011bcfe2ecc5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1715,15 +1715,15 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
 	return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
 }
 
-static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
+static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
 					    u32 lane_count, u32 mode_clock,
 					    enum intel_output_format output_format,
 					    int timeslots)
 {
 	u32 available_bw, required_bw;
 
-	available_bw = (link_clock * lane_count * timeslots)  / 8;
-	required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
+	available_bw = (link_clock * lane_count * timeslots * 16)  / 8;
+	required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
 
 	return available_bw > required_bw;
 }
@@ -1731,7 +1731,7 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
 static int dsc_compute_link_config(struct intel_dp *intel_dp,
 				   struct intel_crtc_state *pipe_config,
 				   struct link_config_limits *limits,
-				   u16 compressed_bpp,
+				   u16 compressed_bppx16,
 				   int timeslots)
 {
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
@@ -1746,7 +1746,8 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
 		for (lane_count = limits->min_lane_count;
 		     lane_count <= limits->max_lane_count;
 		     lane_count <<= 1) {
-			if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count,
+
+			if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate, lane_count,
 							     adjusted_mode->clock,
 							     pipe_config->output_format,
 							     timeslots))
@@ -1860,7 +1861,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
 		ret = dsc_compute_link_config(intel_dp,
 					      pipe_config,
 					      limits,
-					      valid_dsc_bpp[i],
+					      valid_dsc_bpp[i] << 4,
 					      timeslots);
 		if (ret == 0) {
 			pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
@@ -1886,22 +1887,31 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 			      int pipe_bpp,
 			      int timeslots)
 {
-	u16 compressed_bpp;
+	u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd);
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	u16 compressed_bppx16;
+	u8 bppx16_step;
 	int ret;
 
+	if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
+		bppx16_step = 16;
+	else
+		bppx16_step = 16 / bppx16_incr;
+
 	/* Compressed BPP should be less than the Input DSC bpp */
-	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+	dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
+	dsc_min_bpp = dsc_min_bpp << 4;
 
-	for (compressed_bpp = dsc_max_bpp;
-	     compressed_bpp >= dsc_min_bpp;
-	     compressed_bpp--) {
+	for (compressed_bppx16 = dsc_max_bpp;
+	     compressed_bppx16 >= dsc_min_bpp;
+	     compressed_bppx16 -= bppx16_step) {
 		ret = dsc_compute_link_config(intel_dp,
 					      pipe_config,
 					      limits,
-					      compressed_bpp,
+					      compressed_bppx16,
 					      timeslots);
 		if (ret == 0) {
-			pipe_config->dsc.compressed_bpp = compressed_bpp << 4;
+			pipe_config->dsc.compressed_bpp = compressed_bppx16;
 			return 0;
 		}
 	}
-- 
2.40.1

[Intel-gfx] [PATCH 8/9] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Ankit Nautiyal]

From: Swati Sharma <swati2.sharma@intel.com>

DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  | 82 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 83 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 63c1fb9e479f..19975f613316 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1240,6 +1240,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 								      DP_DSC_YCbCr420_Native)),
 			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
 								      DP_DSC_YCbCr444)));
+		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+			   drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1432,6 +1434,83 @@ static const struct file_operations i915_dsc_output_format_fops = {
 	.write = i915_dsc_output_format_write
 };
 
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_dp *intel_dp;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	intel_dp = intel_attached_dp(to_intel_connector(connector));
+	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+					     const char __user *ubuf,
+					     size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	bool dsc_fractional_bpp_enable = false;
+	int ret;
+
+	if (len == 0)
+		return 0;
+
+	drm_dbg(&i915->drm,
+		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
+
+	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
+	if (ret < 0)
+		return ret;
+
+	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+		(dsc_fractional_bpp_enable) ? "true" : "false");
+	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+					struct file *file)
+{
+	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_fractional_bpp_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_fractional_bpp_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1509,6 +1588,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_output_format", 0644, root,
 				    connector, &i915_dsc_output_format_fops);
+
+		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+				    connector, &i915_dsc_fractional_bpp_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f749dc4e70df..5f21ee5bda21 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1796,6 +1796,7 @@ struct intel_dp {
 	/* Display stream compression testing */
 	bool force_dsc_en;
 	int force_dsc_output_format;
+	bool force_dsc_fractional_bpp_en;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
-- 
2.40.1

[Intel-gfx] [PATCH 9/9] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs

[Ankit Nautiyal]

From: Swati Sharma <swati2.sharma@intel.com>

If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if we computed compressed bpp is
computed as integer.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 011bcfe2ecc5..9098febf0c07 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1905,6 +1905,9 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 	for (compressed_bppx16 = dsc_max_bpp;
 	     compressed_bppx16 >= dsc_min_bpp;
 	     compressed_bppx16 -= bppx16_step) {
+		if (intel_dp->force_dsc_fractional_bpp_en &&
+		    !dsc_fractional_compressed_bpp(compressed_bppx16))
+			continue;
 		ret = dsc_compute_link_config(intel_dp,
 					      pipe_config,
 					      limits,
@@ -1912,6 +1915,11 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 					      timeslots);
 		if (ret == 0) {
 			pipe_config->dsc.compressed_bpp = compressed_bppx16;
+
+			if (intel_dp->force_dsc_fractional_bpp_en &&
+			    dsc_fractional_compressed_bpp(compressed_bppx16))
+				drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
+
 			return 0;
 		}
 	}
-- 
2.40.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev4)

[Patchwork]

== Series Details ==

Series: Add DSC fractional bpp support (rev4)
URL   : https://patchwork.freedesktop.org/series/111391/
State : warning

== Summary ==

Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DSC fractional bpp support (rev4)

[Patchwork]

== Series Details ==

Series: Add DSC fractional bpp support (rev4)
URL   : https://patchwork.freedesktop.org/series/111391/
State : warning

== Summary ==

Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory

[Intel-gfx] ✓ Fi.CI.BAT: success for Add DSC fractional bpp support (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5075 bytes --]

== Series Details ==

Series: Add DSC fractional bpp support (rev4)
URL   : https://patchwork.freedesktop.org/series/111391/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13543 -> Patchwork_111391v4
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/index.html

Participating hosts (41 -> 39)
------------------------------

  Missing    (2): fi-kbl-soraka fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_111391v4 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_suspend@basic-s2idle-without-i915:
    - bat-rpls-1:         [PASS][1] -> [ABORT][2] ([i915#8668])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html
    - fi-rkl-11600:       [PASS][3] -> [FAIL][4] ([fdo#103375])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/fi-rkl-11600/igt@i915_suspend@basic-s2idle-without-i915.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/fi-rkl-11600/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - bat-rpls-2:         NOTRUN -> [SKIP][5] ([i915#1845])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_psr@primary_mmap_gtt:
    - bat-rplp-1:         NOTRUN -> [ABORT][6] ([i915#8442] / [i915#8469] / [i915#8668])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-rplp-1:         NOTRUN -> [SKIP][7] ([i915#1072]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - bat-rpls-2:         [ABORT][8] ([i915#7978] / [i915#8668]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/bat-rpls-2/igt@gem_exec_suspend@basic-s3@smem.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/bat-rpls-2/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_selftest@live@migrate:
    - bat-atsm-1:         [DMESG-FAIL][10] ([i915#7699] / [i915#7913]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/bat-atsm-1/igt@i915_selftest@live@migrate.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/bat-atsm-1/igt@i915_selftest@live@migrate.html

  
#### Warnings ####

  * igt@kms_psr@primary_page_flip:
    - bat-rplp-1:         [ABORT][12] ([i915#8442] / [i915#8668] / [i915#8860]) -> [SKIP][13] ([i915#1072])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/bat-rplp-1/igt@kms_psr@primary_page_flip.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/bat-rplp-1/igt@kms_psr@primary_page_flip.html

  
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
  [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
  [i915#8469]: https://gitlab.freedesktop.org/drm/intel/issues/8469
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8860]: https://gitlab.freedesktop.org/drm/intel/issues/8860


Build changes
-------------

  * Linux: CI_DRM_13543 -> Patchwork_111391v4

  CI-20190529: 20190529
  CI_DRM_13543: f450aa57b6725458339a934f474d5a0e5cb2dce0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7448: 84aa6d50648d9349fb4f1520f37e5374908c9f4d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111391v4: f450aa57b6725458339a934f474d5a0e5cb2dce0 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

4c46549b99ea drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
b597effe2466 drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
67e1fd9c9025 drm/i915/dp: Iterate over output bpp with fractional step size
e1c7bcdc084d drm/i915/dsc/mtl: Add support for fractional bpp
5d7daf9a6a0e drm/display/dp: Add helper function to get DSC bpp prescision
b5302edcdaef drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
0d0f6bad3419 drm/i915/display: Consider fractional vdsc bpp while computing m_n values
bd0500225b0c drm/i915/display: Store compressed bpp in U6.4 format
0ed2f4c703c8 drm/display/dp: Fix the DP DSC Receiver cap size

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/index.html

[-- Attachment #2: Type: text/html, Size: 6234 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add DSC fractional bpp support (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 74976 bytes --]

== Series Details ==

Series: Add DSC fractional bpp support (rev4)
URL   : https://patchwork.freedesktop.org/series/111391/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13543_full -> Patchwork_111391v4_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_111391v4_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111391v4_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_111391v4_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg2-8/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-12/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0.html

  * igt@kms_hdr@bpc-switch@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-11/igt@kms_hdr@bpc-switch@pipe-a-dp-4.html

  
Known issues
------------

  Here are the changes found in Patchwork_111391v4_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-mtlp:         NOTRUN -> [SKIP][4] ([i915#8411])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@api_intel_bb@object-reloc-purge-cache.html
    - shard-dg1:          NOTRUN -> [SKIP][5] ([i915#8411])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@device_reset@cold-reset-bound:
    - shard-dg1:          NOTRUN -> [SKIP][6] ([i915#7701])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@device_reset@cold-reset-bound.html

  * igt@device_reset@unbind-reset-rebind:
    - shard-dg1:          NOTRUN -> [ABORT][7] ([i915#4983] / [i915#7461])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@device_reset@unbind-reset-rebind.html

  * igt@drm_fdinfo@busy-hang@rcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][8] ([i915#8414]) +12 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@drm_fdinfo@busy-hang@rcs0.html

  * igt@drm_fdinfo@busy@vcs1:
    - shard-dg1:          NOTRUN -> [SKIP][9] ([i915#8414]) +5 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@drm_fdinfo@busy@vcs1.html

  * igt@feature_discovery@display-2x:
    - shard-dg1:          NOTRUN -> [SKIP][10] ([i915#1839])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@feature_discovery@display-2x.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-dg1:          NOTRUN -> [SKIP][11] ([i915#3555] / [i915#5325])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gem_ccs@ctrl-surf-copy.html
    - shard-mtlp:         NOTRUN -> [SKIP][12] ([i915#5325])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-dg1:          NOTRUN -> [SKIP][13] ([i915#7697])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_persistence@heartbeat-close:
    - shard-mtlp:         NOTRUN -> [SKIP][14] ([i915#8555])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@gem_ctx_persistence@heartbeat-close.html

  * igt@gem_ctx_persistence@legacy-engines-mixed:
    - shard-snb:          NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#1099]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-snb1/igt@gem_ctx_persistence@legacy-engines-mixed.html

  * igt@gem_ctx_persistence@saturated-hostile@vecs0:
    - shard-mtlp:         NOTRUN -> [FAIL][16] ([i915#7816]) +2 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@gem_ctx_persistence@saturated-hostile@vecs0.html

  * igt@gem_eio@kms:
    - shard-snb:          [PASS][17] -> [FAIL][18] ([i915#8764])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-snb7/igt@gem_eio@kms.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-snb2/igt@gem_eio@kms.html

  * igt@gem_eio@suspend:
    - shard-dg1:          [PASS][19] -> [DMESG-WARN][20] ([i915#4423])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg1-15/igt@gem_eio@suspend.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-18/igt@gem_eio@suspend.html

  * igt@gem_eio@unwedge-stress:
    - shard-dg1:          [PASS][21] -> [FAIL][22] ([i915#5784])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg1-15/igt@gem_eio@unwedge-stress.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-18/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@bonded-false-hang:
    - shard-dg1:          NOTRUN -> [SKIP][23] ([i915#4812]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gem_exec_balancer@bonded-false-hang.html
    - shard-mtlp:         NOTRUN -> [SKIP][24] ([i915#4812])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@gem_exec_balancer@bonded-false-hang.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-mtlp:         NOTRUN -> [SKIP][25] ([i915#4036])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_basic@basic@ccs0-smem:
    - shard-mtlp:         [PASS][26] -> [DMESG-WARN][27] ([i915#1982])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-mtlp-1/igt@gem_exec_basic@basic@ccs0-smem.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-5/igt@gem_exec_basic@basic@ccs0-smem.html

  * igt@gem_exec_fair@basic-none-solo:
    - shard-mtlp:         NOTRUN -> [SKIP][28] ([i915#4473]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@gem_exec_fair@basic-none-solo.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][29] ([i915#2842]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-glk4/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglu:         [PASS][30] -> [FAIL][31] ([i915#2842])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-tglu-7/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_flush@basic-uc-rw-default:
    - shard-dg1:          NOTRUN -> [SKIP][32] ([i915#3539] / [i915#4852])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gem_exec_flush@basic-uc-rw-default.html

  * igt@gem_exec_params@secure-non-master:
    - shard-dg1:          NOTRUN -> [SKIP][33] ([fdo#112283])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gem_exec_params@secure-non-master.html
    - shard-mtlp:         NOTRUN -> [SKIP][34] ([fdo#112283])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@gem_exec_params@secure-non-master.html

  * igt@gem_exec_reloc@basic-gtt-cpu:
    - shard-dg1:          NOTRUN -> [SKIP][35] ([i915#3281]) +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gem_exec_reloc@basic-gtt-cpu.html

  * igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
    - shard-mtlp:         NOTRUN -> [SKIP][36] ([i915#3281]) +11 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html

  * igt@gem_exec_reloc@basic-wc-read-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][37] ([i915#3281])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@gem_exec_reloc@basic-wc-read-noreloc.html

  * igt@gem_fenced_exec_thrash@no-spare-fences:
    - shard-dg1:          NOTRUN -> [SKIP][38] ([i915#4860])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gem_fenced_exec_thrash@no-spare-fences.html
    - shard-mtlp:         NOTRUN -> [SKIP][39] ([i915#4860]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@gem_fenced_exec_thrash@no-spare-fences.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-glk:          NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#4613]) +5 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-glk6/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-mtlp:         NOTRUN -> [SKIP][41] ([i915#4613]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@massive:
    - shard-apl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#4613]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-apl7/igt@gem_lmem_swapping@massive.html

  * igt@gem_lmem_swapping@parallel-multi:
    - shard-rkl:          NOTRUN -> [SKIP][43] ([i915#4613])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@gem_lmem_swapping@parallel-multi.html

  * igt@gem_media_vme:
    - shard-rkl:          NOTRUN -> [SKIP][44] ([i915#284])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@gem_media_vme.html

  * igt@gem_mmap@bad-size:
    - shard-mtlp:         NOTRUN -> [SKIP][45] ([i915#4083]) +2 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@gem_mmap@bad-size.html

  * igt@gem_mmap@big-bo:
    - shard-dg1:          NOTRUN -> [SKIP][46] ([i915#4083]) +2 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gem_mmap@big-bo.html

  * igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][47] ([i915#4077]) +6 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html

  * igt@gem_mmap_gtt@close-race:
    - shard-dg1:          NOTRUN -> [SKIP][48] ([i915#4077]) +2 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gem_mmap_gtt@close-race.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-display:
    - shard-mtlp:         NOTRUN -> [SKIP][49] ([i915#3282]) +4 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

  * igt@gem_ppgtt@blt-vs-render-ctxn:
    - shard-snb:          [PASS][50] -> [DMESG-FAIL][51] ([i915#8295])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-snb2/igt@gem_ppgtt@blt-vs-render-ctxn.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-snb6/igt@gem_ppgtt@blt-vs-render-ctxn.html

  * igt@gem_pread@snoop:
    - shard-dg1:          NOTRUN -> [SKIP][52] ([i915#3282]) +3 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gem_pread@snoop.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-glk:          NOTRUN -> [WARN][53] ([i915#2658])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-glk7/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@create-protected-buffer:
    - shard-mtlp:         NOTRUN -> [SKIP][54] ([i915#4270])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@gem_pxp@create-protected-buffer.html

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - shard-dg1:          NOTRUN -> [SKIP][55] ([i915#4270])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gem_pxp@reject-modify-context-protection-off-1.html

  * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
    - shard-rkl:          NOTRUN -> [SKIP][56] ([i915#4270])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][57] ([i915#8428]) +4 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][58] ([i915#4079])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_tiled_pread_pwrite:
    - shard-rkl:          NOTRUN -> [SKIP][59] ([i915#3282])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@gem_tiled_pread_pwrite.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-mtlp:         NOTRUN -> [SKIP][60] ([i915#3297]) +1 similar issue
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-dg1:          NOTRUN -> [SKIP][61] ([i915#3297])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gen7_exec_parse@basic-offset:
    - shard-dg1:          NOTRUN -> [SKIP][62] ([fdo#109289])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gen7_exec_parse@basic-offset.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-rkl:          NOTRUN -> [SKIP][63] ([i915#2527])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@gen9_exec_parse@bb-chained.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-dg1:          NOTRUN -> [SKIP][64] ([i915#2527]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@gen9_exec_parse@bb-start-far.html

  * igt@gen9_exec_parse@unaligned-jump:
    - shard-mtlp:         NOTRUN -> [SKIP][65] ([i915#2856]) +2 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@gen9_exec_parse@unaligned-jump.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg2:          [PASS][66] -> [DMESG-WARN][67] ([i915#7061] / [i915#8617])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-10/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pipe_stress@stress-xrgb8888-untiled:
    - shard-apl:          NOTRUN -> [FAIL][68] ([i915#7036])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-apl4/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
    - shard-mtlp:         NOTRUN -> [FAIL][69] ([i915#8691])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@i915_pipe_stress@stress-xrgb8888-untiled.html

  * igt@i915_pm_rpm@dpms-mode-unset-lpsp:
    - shard-dg2:          [PASS][70] -> [SKIP][71] ([i915#1397])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg2-12/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-11/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@i915_pm_rpm@gem-mmap-type@gtt-smem0:
    - shard-mtlp:         NOTRUN -> [SKIP][72] ([i915#8431])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@i915_pm_rpm@gem-mmap-type@gtt-smem0.html

  * igt@i915_pm_rpm@modeset-lpsp:
    - shard-rkl:          [PASS][73] -> [SKIP][74] ([i915#1397])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@i915_pm_rpm@modeset-lpsp.html
    - shard-dg1:          NOTRUN -> [SKIP][75] ([i915#1397])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@i915_pm_rpm@modeset-lpsp.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-dg1:          [PASS][76] -> [SKIP][77] ([i915#1397]) +1 similar issue
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg1-17/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@i915_pm_rps@basic-api:
    - shard-mtlp:         NOTRUN -> [SKIP][78] ([i915#6621])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@i915_pm_rps@basic-api.html

  * igt@kms_async_flips@crc@pipe-d-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][79] ([i915#8247]) +3 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-11/igt@kms_async_flips@crc@pipe-d-dp-4.html

  * igt@kms_async_flips@crc@pipe-d-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [FAIL][80] ([i915#8247]) +3 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-14/igt@kms_async_flips@crc@pipe-d-hdmi-a-4.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-mtlp:         NOTRUN -> [SKIP][81] ([i915#404])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-apl:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#1769])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-apl6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-dg1:          NOTRUN -> [SKIP][83] ([i915#5286])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-dg1:          NOTRUN -> [SKIP][84] ([i915#4538] / [i915#5286])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [PASS][85] -> [FAIL][86] ([i915#5138])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][87] ([i915#3638])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_big_fb@linear-16bpp-rotate-90.html
    - shard-mtlp:         NOTRUN -> [SKIP][88] ([fdo#111614]) +3 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-mtlp:         NOTRUN -> [FAIL][89] ([i915#3743])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-mtlp:         NOTRUN -> [SKIP][90] ([i915#6187])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][91] ([fdo#110723])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-rkl:          NOTRUN -> [SKIP][92] ([fdo#111615])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-dg1:          NOTRUN -> [SKIP][93] ([i915#4538])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-mtlp:         NOTRUN -> [SKIP][94] ([fdo#111615]) +5 similar issues
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-mtlp:         NOTRUN -> [SKIP][95] ([i915#2705])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][96] ([i915#3734] / [i915#5354] / [i915#6095])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][97] ([fdo#109271]) +116 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-apl4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html
    - shard-mtlp:         NOTRUN -> [SKIP][98] ([i915#5354] / [i915#6095])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][99] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095]) +1 similar issue
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-mtlp:         NOTRUN -> [SKIP][100] ([i915#3886] / [i915#5354] / [i915#6095])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#3886]) +9 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-glk1/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][102] ([i915#3886] / [i915#6095]) +3 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][103] ([i915#6095]) +21 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][104] ([i915#3886] / [i915#5354] / [i915#6095])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_mtl_rc_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][105] ([i915#5354] / [i915#6095]) +1 similar issue
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_mtl_rc_ccs.html

  * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#3886]) +3 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-apl4/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
    - shard-rkl:          NOTRUN -> [SKIP][107] ([i915#5354]) +3 similar issues
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-d-bad-aux-stride-4_tiled_mtl_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][108] ([fdo#109271]) +248 similar issues
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-glk7/igt@kms_ccs@pipe-d-bad-aux-stride-4_tiled_mtl_mc_ccs.html

  * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_mc_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][109] ([i915#3689] / [i915#5354] / [i915#6095]) +10 similar issues
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_mc_ccs.html

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_mtl_mc_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][110] ([i915#5354] / [i915#6095]) +9 similar issues
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_mtl_mc_ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-dg1:          NOTRUN -> [SKIP][111] ([i915#3742])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_cdclk@mode-transition.html

  * igt@kms_cdclk@mode-transition@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][112] ([i915#7213] / [i915#9010]) +4 similar issues
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@kms_cdclk@mode-transition@pipe-b-edp-1.html

  * igt@kms_cdclk@plane-scaling@pipe-c-dp-2:
    - shard-dg2:          NOTRUN -> [SKIP][113] ([i915#4087]) +3 similar issues
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-12/igt@kms_cdclk@plane-scaling@pipe-c-dp-2.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-mtlp:         NOTRUN -> [SKIP][114] ([fdo#111827]) +1 similar issue
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-dg1:          NOTRUN -> [SKIP][115] ([fdo#111827])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_edid@vga-edid-read:
    - shard-rkl:          NOTRUN -> [SKIP][116] ([i915#7828]) +2 similar issues
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_chamelium_edid@vga-edid-read.html

  * igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][117] ([i915#7828]) +3 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
    - shard-dg1:          NOTRUN -> [SKIP][118] ([i915#7828]) +2 similar issues
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg1:          NOTRUN -> [SKIP][119] ([i915#7116]) +1 similar issue
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@legacy:
    - shard-dg2:          NOTRUN -> [SKIP][120] ([i915#7118])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-2/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][121] ([i915#7173])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-11/igt@kms_content_protection@lic@pipe-a-dp-4.html

  * igt@kms_content_protection@uevent:
    - shard-mtlp:         NOTRUN -> [SKIP][122] ([i915#6944]) +1 similar issue
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@kms_content_protection@uevent.html

  * igt@kms_content_protection@uevent@pipe-a-dp-1:
    - shard-apl:          NOTRUN -> [FAIL][123] ([i915#1339])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-apl4/igt@kms_content_protection@uevent@pipe-a-dp-1.html

  * igt@kms_content_protection@uevent@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][124] ([i915#1339])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-11/igt@kms_content_protection@uevent@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-mtlp:         NOTRUN -> [SKIP][125] ([i915#3359]) +1 similar issue
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-rkl:          NOTRUN -> [SKIP][126] ([i915#3555])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-mtlp:         NOTRUN -> [SKIP][127] ([i915#8814])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][128] ([i915#3359]) +1 similar issue
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][129] ([i915#3546]) +1 similar issue
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-dg1:          NOTRUN -> [SKIP][130] ([i915#4103] / [i915#4213]) +1 similar issue
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - shard-mtlp:         NOTRUN -> [SKIP][131] ([i915#4213])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
    - shard-snb:          [PASS][132] -> [ABORT][133] ([i915#8865])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-snb6/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-snb7/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-mtlp:         NOTRUN -> [SKIP][134] ([fdo#111767] / [i915#3546]) +1 similar issue
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [PASS][135] -> [FAIL][136] ([i915#2346]) +1 similar issue
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][137] ([i915#3804])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-dg1:          NOTRUN -> [SKIP][138] ([i915#3469])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-rkl:          NOTRUN -> [SKIP][139] ([fdo#111825]) +1 similar issue
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-plain-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][140] ([i915#3637]) +2 similar issues
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][141] ([fdo#111825]) +16 similar issues
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@flip-vs-fences-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][142] ([i915#8381])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_flip@flip-vs-fences-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3:
    - shard-dg2:          [PASS][143] -> [FAIL][144] ([fdo#103375]) +6 similar issues
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg2-3/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-5/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][145] ([i915#8810])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][146] ([i915#2672])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][147] ([i915#2672]) +1 similar issue
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][148] ([i915#2587] / [i915#2672]) +2 similar issues
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-4-rc_ccs-cc-to-x:
    - shard-mtlp:         [PASS][149] -> [FAIL][150] ([i915#9056]) +2 similar issues
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-mtlp-1/igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-4-rc_ccs-cc-to-x.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-6/igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-4-rc_ccs-cc-to-x.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
    - shard-dg2:          [PASS][151] -> [FAIL][152] ([i915#6880]) +2 similar issues
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][153] ([i915#1825]) +19 similar issues
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][154] ([i915#8708]) +5 similar issues
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-mtlp:         NOTRUN -> [SKIP][155] ([i915#5460])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][156] ([i915#8708])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][157] ([i915#3458]) +9 similar issues
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#3023]) +1 similar issue
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
    - shard-rkl:          NOTRUN -> [SKIP][159] ([fdo#111825] / [i915#1825]) +6 similar issues
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear:
    - shard-dg2:          NOTRUN -> [SKIP][160] ([i915#3458])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][161] ([i915#8708]) +10 similar issues
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-dg2:          [PASS][162] -> [SKIP][163] ([i915#433])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg2-6/igt@kms_hdmi_inject@inject-audio.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-1/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][164] ([i915#3555] / [i915#8228])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-1/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][165] ([i915#3555] / [i915#8228])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-10/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
    - shard-mtlp:         NOTRUN -> [SKIP][166] ([fdo#109289]) +2 similar issues
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html

  * igt@kms_plane@pixel-format@pipe-b-planes:
    - shard-mtlp:         NOTRUN -> [FAIL][167] ([i915#1623])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@kms_plane@pixel-format@pipe-b-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-snb:          NOTRUN -> [DMESG-WARN][168] ([i915#8841]) +2 similar issues
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-snb2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_lowres@tiling-x@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][169] ([i915#3582]) +3 similar issues
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@kms_plane_lowres@tiling-x@pipe-c-edp-1.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][170] ([i915#8292])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-11/igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [FAIL][171] ([i915#8292])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-14/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html

  * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][172] ([i915#5176]) +7 similar issues
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][173] ([i915#5176]) +3 similar issues
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-1/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][174] ([i915#5176]) +3 similar issues
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-edp-1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-d-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [SKIP][175] ([i915#5176]) +7 similar issues
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-19/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-d-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][176] ([i915#5235]) +5 similar issues
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][177] ([i915#5235]) +11 similar issues
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-14/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][178] ([i915#5235]) +11 similar issues
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][179] ([i915#5235]) +15 similar issues
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-mtlp:         NOTRUN -> [SKIP][180] ([i915#6524])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
    - shard-apl:          NOTRUN -> [SKIP][181] ([fdo#109271] / [i915#658]) +2 similar issues
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-apl4/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][182] ([fdo#109271] / [i915#658]) +4 similar issues
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-glk9/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
    - shard-dg1:          NOTRUN -> [SKIP][183] ([i915#658])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-dg1:          NOTRUN -> [SKIP][184] ([fdo#111068] / [i915#658])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_psr2_su@frontbuffer-xrgb8888.html
    - shard-mtlp:         NOTRUN -> [SKIP][185] ([i915#4348])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@dpms:
    - shard-dg1:          NOTRUN -> [SKIP][186] ([i915#1072]) +2 similar issues
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_psr@dpms.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-rkl:          NOTRUN -> [SKIP][187] ([i915#1072])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-snb:          NOTRUN -> [SKIP][188] ([fdo#109271]) +218 similar issues
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-snb2/igt@kms_rotation_crc@bad-pixel-format.html
    - shard-mtlp:         NOTRUN -> [SKIP][189] ([i915#4235]) +2 similar issues
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-mtlp:         NOTRUN -> [SKIP][190] ([i915#5289])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-dg1:          NOTRUN -> [SKIP][191] ([fdo#111615] / [i915#5289])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_selftest@drm_damage:
    - shard-dg1:          NOTRUN -> [SKIP][192] ([i915#8661])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_selftest@drm_damage.html

  * igt@kms_selftest@drm_dp_mst:
    - shard-mtlp:         NOTRUN -> [SKIP][193] ([i915#8661]) +1 similar issue
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@kms_selftest@drm_dp_mst.html
    - shard-apl:          NOTRUN -> [SKIP][194] ([fdo#109271] / [i915#8661]) +1 similar issue
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-apl4/igt@kms_selftest@drm_dp_mst.html
    - shard-glk:          NOTRUN -> [SKIP][195] ([fdo#109271] / [i915#8661])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-glk4/igt@kms_selftest@drm_dp_mst.html
    - shard-snb:          NOTRUN -> [SKIP][196] ([fdo#109271] / [i915#8661])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-snb2/igt@kms_selftest@drm_dp_mst.html

  * igt@kms_selftest@framebuffer:
    - shard-rkl:          NOTRUN -> [SKIP][197] ([i915#8661])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_selftest@framebuffer.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-dg1:          NOTRUN -> [SKIP][198] ([i915#3555])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg1:          NOTRUN -> [SKIP][199] ([i915#8623])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-rkl:          NOTRUN -> [SKIP][200] ([i915#4070] / [i915#533] / [i915#6768])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-glk:          NOTRUN -> [SKIP][201] ([fdo#109271] / [i915#2437]) +1 similar issue
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-glk7/igt@kms_writeback@writeback-pixel-formats.html
    - shard-mtlp:         NOTRUN -> [SKIP][202] ([i915#2437])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf@mi-rpc:
    - shard-dg1:          NOTRUN -> [SKIP][203] ([i915#2434])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@perf@mi-rpc.html

  * igt@perf_pmu@busy-double-start@rcs0:
    - shard-dg1:          NOTRUN -> [FAIL][204] ([i915#4349])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@perf_pmu@busy-double-start@rcs0.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          [PASS][205] -> [FAIL][206] ([i915#4349]) +3 similar issues
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg2-12/igt@perf_pmu@busy-double-start@vecs1.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-2/igt@perf_pmu@busy-double-start@vecs1.html

  * igt@perf_pmu@event-wait@rcs0:
    - shard-rkl:          NOTRUN -> [SKIP][207] ([fdo#112283])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@perf_pmu@event-wait@rcs0.html

  * igt@perf_pmu@faulting-read@gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][208] ([i915#8440])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@perf_pmu@faulting-read@gtt.html

  * igt@prime_vgem@basic-blt:
    - shard-mtlp:         NOTRUN -> [FAIL][209] ([i915#8445])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@prime_vgem@basic-blt.html

  * igt@runner@aborted:
    - shard-snb:          NOTRUN -> [FAIL][210] ([i915#7812] / [i915#8848])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-snb7/igt@runner@aborted.html

  * igt@v3d/v3d_perfmon@get-values-invalid-pointer:
    - shard-dg1:          NOTRUN -> [SKIP][211] ([i915#2575]) +4 similar issues
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@v3d/v3d_perfmon@get-values-invalid-pointer.html
    - shard-mtlp:         NOTRUN -> [SKIP][212] ([i915#2575]) +9 similar issues
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@v3d/v3d_perfmon@get-values-invalid-pointer.html

  * igt@v3d/v3d_submit_cl@bad-multisync-in-sync:
    - shard-rkl:          NOTRUN -> [SKIP][213] ([fdo#109315]) +1 similar issue
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@v3d/v3d_submit_cl@bad-multisync-in-sync.html

  * igt@vc4/vc4_label_bo@set-bad-handle:
    - shard-mtlp:         NOTRUN -> [SKIP][214] ([i915#7711]) +5 similar issues
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-8/igt@vc4/vc4_label_bo@set-bad-handle.html

  * igt@vc4/vc4_label_bo@set-kernel-name:
    - shard-dg1:          NOTRUN -> [SKIP][215] ([i915#7711]) +2 similar issues
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-15/igt@vc4/vc4_label_bo@set-kernel-name.html

  * igt@vc4/vc4_purgeable_bo@mark-purgeable-twice:
    - shard-rkl:          NOTRUN -> [SKIP][216] ([i915#7711])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@vc4/vc4_purgeable_bo@mark-purgeable-twice.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@smoketest:
    - shard-tglu:         [FAIL][217] ([i915#5099]) -> [PASS][218]
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-tglu-8/igt@gem_ctx_persistence@smoketest.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-tglu-6/igt@gem_ctx_persistence@smoketest.html

  * igt@gem_exec_capture@pi@vecs0:
    - shard-mtlp:         [FAIL][219] ([i915#4475] / [i915#7765]) -> [PASS][220]
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-mtlp-5/igt@gem_exec_capture@pi@vecs0.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-2/igt@gem_exec_capture@pi@vecs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-rkl:          [FAIL][221] ([i915#2842]) -> [PASS][222] +1 similar issue
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-rkl-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-7/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-wb:
    - shard-mtlp:         [DMESG-FAIL][223] ([i915#9121]) -> [PASS][224]
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-mtlp-4/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-1/igt@gem_exec_flush@basic-batch-kernel-default-wb.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [ABORT][225] ([i915#5566]) -> [PASS][226]
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-apl7/igt@gen9_exec_parse@allowed-all.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-apl7/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
    - shard-dg1:          [SKIP][227] ([i915#1937]) -> [PASS][228]
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg1-18/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-19/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
    - shard-dg1:          [FAIL][229] ([i915#3591]) -> [PASS][230]
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html

  * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-dg2:          [SKIP][231] ([i915#1397]) -> [PASS][232]
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg2-1/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-12/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          [SKIP][233] ([i915#1397]) -> [PASS][234] +1 similar issue
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-1/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
    - shard-dg1:          [SKIP][235] ([i915#1397]) -> [PASS][236]
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-14/igt@i915_pm_rpm@modeset-non-lpsp-stress.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [INCOMPLETE][237] ([i915#7790]) -> [PASS][238]
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-snb4/igt@i915_pm_rps@reset.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-snb6/igt@i915_pm_rps@reset.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-mtlp:         [FAIL][239] ([i915#3743]) -> [PASS][240]
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
    - shard-snb:          [ABORT][241] ([i915#8865]) -> [PASS][242] +1 similar issue
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-snb7/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-snb1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-apl:          [FAIL][243] ([i915#2346]) -> [PASS][244]
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-4-rc_ccs-to-4-rc_ccs-cc:
    - shard-mtlp:         [FAIL][245] ([i915#9056]) -> [PASS][246] +5 similar issues
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-mtlp-1/igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-4-rc_ccs-to-4-rc_ccs-cc.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-6/igt@kms_flip_tiling@flip-change-tiling@edp-1-pipe-b-4-rc_ccs-to-4-rc_ccs-cc.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
    - shard-dg2:          [FAIL][247] ([i915#6880]) -> [PASS][248]
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-3:
    - shard-dg2:          [FAIL][249] ([fdo#103375]) -> [PASS][250]
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg2-5/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-3.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-3/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-3.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-rkl:          [ABORT][251] ([i915#7461]) -> [PASS][252]
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-rkl-1/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-4/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html

  * igt@kms_sysfs_edid_timing:
    - shard-dg2:          [FAIL][253] ([IGT#2]) -> [PASS][254]
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg2-8/igt@kms_sysfs_edid_timing.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-11/igt@kms_sysfs_edid_timing.html

  * igt@perf_pmu@most-busy-idle-check-all@rcs0:
    - shard-dg1:          [FAIL][255] ([i915#5234]) -> [PASS][256]
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg1-14/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-19/igt@perf_pmu@most-busy-idle-check-all@rcs0.html

  * igt@sysfs_heartbeat_interval@nopreempt@rcs0:
    - shard-mtlp:         [FAIL][257] ([i915#6015]) -> [PASS][258]
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-mtlp-6/igt@sysfs_heartbeat_interval@nopreempt@rcs0.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-2/igt@sysfs_heartbeat_interval@nopreempt@rcs0.html

  
#### Warnings ####

  * igt@gem_spin_batch@spin-each:
    - shard-mtlp:         [DMESG-FAIL][259] ([i915#9121]) -> [DMESG-FAIL][260] ([i915#8962] / [i915#9121])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-mtlp-4/igt@gem_spin_batch@spin-each.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-4/igt@gem_spin_batch@spin-each.html

  * igt@kms_content_protection@type1:
    - shard-dg2:          [SKIP][261] ([i915#7118]) -> [SKIP][262] ([i915#7118] / [i915#7162])
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg2-2/igt@kms_content_protection@type1.html
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg2-12/igt@kms_content_protection@type1.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-mtlp:         [DMESG-FAIL][263] ([i915#2017] / [i915#5954]) -> [FAIL][264] ([i915#2346])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-mtlp-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-mtlp-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_fbcon_fbt@psr:
    - shard-rkl:          [SKIP][265] ([i915#3955]) -> [SKIP][266] ([fdo#110189] / [i915#3955])
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-rkl-4/igt@kms_fbcon_fbt@psr.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-2/igt@kms_fbcon_fbt@psr.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-rkl:          [SKIP][267] ([fdo#109285] / [i915#4098]) -> [SKIP][268] ([fdo#109285])
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-rkl-1/igt@kms_force_connector_basic@force-load-detect.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_psr@cursor_plane_move:
    - shard-dg1:          [SKIP][269] ([i915#1072]) -> [SKIP][270] ([i915#1072] / [i915#4078])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg1-19/igt@kms_psr@cursor_plane_move.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-12/igt@kms_psr@cursor_plane_move.html

  * igt@kms_psr@sprite_plane_onoff:
    - shard-dg1:          [SKIP][271] ([i915#1072] / [i915#4078]) -> [SKIP][272] ([i915#1072])
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13543/shard-dg1-16/igt@kms_psr@sprite_plane_onoff.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/shard-dg1-17/igt@kms_psr@sprite_plane_onoff.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1339]: https://gitlab.freedesktop.org/drm/intel/issues/1339
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1623]: https://gitlab.freedesktop.org/drm/intel/issues/1623
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3582]: https://gitlab.freedesktop.org/drm/intel/issues/3582
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
  [i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
  [i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5954]: https://gitlab.freedesktop.org/drm/intel/issues/5954
  [i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#7036]: https://gitlab.freedesktop.org/drm/intel/issues/7036
  [i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7765]: https://gitlab.freedesktop.org/drm/intel/issues/7765
  [i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
  [i915#7812]: https://gitlab.freedesktop.org/drm/intel/issues/7812
  [i915#7816]: https://gitlab.freedesktop.org/drm/intel/issues/7816
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
  [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
  [i915#8295]: https://gitlab.freedesktop.org/drm/intel/issues/8295
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
  [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
  [i915#8431]: https://gitlab.freedesktop.org/drm/intel/issues/8431
  [i915#8440]: https://gitlab.freedesktop.org/drm/intel/issues/8440
  [i915#8445]: https://gitlab.freedesktop.org/drm/intel/issues/8445
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8617]: https://gitlab.freedesktop.org/drm/intel/issues/8617
  [i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
  [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
  [i915#8691]: https://gitlab.freedesktop.org/drm/intel/issues/8691
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8764]: https://gitlab.freedesktop.org/drm/intel/issues/8764
  [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
  [i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
  [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
  [i915#8848]: https://gitlab.freedesktop.org/drm/intel/issues/8848
  [i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865
  [i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
  [i915#9010]: https://gitlab.freedesktop.org/drm/intel/issues/9010
  [i915#9056]: https://gitlab.freedesktop.org/drm/intel/issues/9056
  [i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121


Build changes
-------------

  * Linux: CI_DRM_13543 -> Patchwork_111391v4

  CI-20190529: 20190529
  CI_DRM_13543: f450aa57b6725458339a934f474d5a0e5cb2dce0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7448: 84aa6d50648d9349fb4f1520f37e5374908c9f4d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111391v4: f450aa57b6725458339a934f474d5a0e5cb2dce0 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v4/index.html

[-- Attachment #2: Type: text/html, Size: 89702 bytes --]

Re: [Intel-gfx] [PATCH 2/9] drm/i915/display: Store compressed bpp in U6.4 format

[Kandpal, Suraj]

> Subject: [Intel-gfx] [PATCH 2/9] drm/i915/display: Store compressed bpp in
> U6.4 format
> 
> DSC parameter bits_per_pixel is stored in U6.4 format.
> The 4 bits represent the fractional part of the bpp.
> Currently we use compressed_bpp member of dsc structure to store only the
> integral part of the bits_per_pixel.
> To store the full bits_per_pixel along with the fractional part, compressed_bpp
> is changed to store bpp in U6.4 formats. Intergral part is retrieved by simply
> right shifting the member compressed_bpp by 4.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c        | 10 ++++-----
>  drivers/gpu/drm/i915/display/intel_audio.c    |  2 +-
>  drivers/gpu/drm/i915/display/intel_bios.c     |  2 +-
>  .../drm/i915/display/intel_display_types.h    | 16 +++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dp.c       | 21 +++++++++++--------
>  drivers/gpu/drm/i915/display/intel_vdsc.c     |  4 ++--
>  6 files changed, 36 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ad6488e9c2b2..81b8e97e9435 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder,
>  	int bpp;
> 
>  	if (crtc_state->dsc.compression_enable)
> -		bpp = crtc_state->dsc.compressed_bpp;
> +		bpp = dsc_integral_compressed_bpp(crtc_state-
> >dsc.compressed_bpp);
>  	else
>  		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> 
> @@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct
> intel_encoder *encoder,
>  	 * compressed and non-compressed bpp.
>  	 */
>  	if (crtc_state->dsc.compression_enable) {
> -		mul = crtc_state->dsc.compressed_bpp;
> +		mul = dsc_integral_compressed_bpp(crtc_state-
> >dsc.compressed_bpp);
>  		div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>  	}
> 
> @@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct
> intel_encoder *encoder,
>  		int bpp, line_time_us, byte_clk_period_ns;
> 
>  		if (crtc_state->dsc.compression_enable)
> -			bpp = crtc_state->dsc.compressed_bpp;
> +			bpp = dsc_integral_compressed_bpp(crtc_state-
> >dsc.compressed_bpp);
>  		else
>  			bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
> 
> @@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct
> intel_encoder *encoder,
>  	struct drm_display_mode *adjusted_mode =
>  					&pipe_config->hw.adjusted_mode;
> 
> -	if (pipe_config->dsc.compressed_bpp) {
> -		int div = pipe_config->dsc.compressed_bpp;
> +	if (dsc_integral_compressed_bpp(pipe_config-
> >dsc.compressed_bpp)) {

Doesn't make sense to have this function to be called here this just
checks if we have compressed_bpp available or not extracting the
integral part should not be necessary

> +		int div =
> +dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
>  		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
> 
>  		adjusted_mode->crtc_htotal =
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index 3d9c9b4f27f8..93969b63cdd8 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct
> intel_encoder *encoder,
>  	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>  	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
>  	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
> -	vdsc_bpp = crtc_state->dsc.compressed_bpp;
> +	vdsc_bpp =
> +dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
>  	cdclk = i915->display.cdclk.hw.cdclk;
>  	/* fec= 0.972261, using rounding multiplier of 1000000 */
>  	fec_coeff = 972261;
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 858c959f7bab..fe1e376c4ba7 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -3385,7 +3385,7 @@ static void fill_dsc(struct intel_crtc_state
> *crtc_state,
>  	crtc_state->pipe_bpp = bpc * 3;
> 
>  	crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
> -					     VBT_DSC_MAX_BPP(dsc-
> >max_bpp));
> +					     VBT_DSC_MAX_BPP(dsc-
> >max_bpp)) << 4;
> 
>  	/*
>  	 * FIXME: This is ugly, and slice count should take DSC engine diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 731f2ec04d5c..f749dc4e70df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1353,7 +1353,7 @@ struct intel_crtc_state {
>  	struct {
>  		bool compression_enable;
>  		bool dsc_split;
> -		u16 compressed_bpp;
> +		u16 compressed_bpp; /* U6.4 format (first 4 bits for
> fractional part)
> +*/
>  		u8 slice_count;
>  		struct drm_dsc_config config;
>  	} dsc;
> @@ -2108,4 +2108,18 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
>  	return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;  }
> 
> +/* Returns integral part of the compressed bpp given in U6.4 format */
> +static inline int
> +dsc_integral_compressed_bpp(u16 compressed_bpp) {
> +	return compressed_bpp >> 4;
> +}

Maybe we can have two macro/functions that can be used to shift the fractional part for bpp
dsc_bpp_x_to_x16 and dsc_bpp_x16_to_x this can be used at a lot of places to avoid confusions everywhere
when and why we are shifting  by 4.
We can keep the dsc_fractional_compressed_bpp.

> +
> +/* Returns fractional part of the compressed bpp given in U6.4 format
> +*/ static inline int
> +dsc_fractional_compressed_bpp(u16 compressed_bpp) {
> +	return ((compressed_bpp & 0xF) * 10000 / 16); }
> +

Maybe dsc_get_fractional_bpp () ?

>  #endif /*  __INTEL_DISPLAY_TYPES_H__ */ diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5b48bfe09d0e..32d0bee11f53 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1901,7 +1901,7 @@ xelpd_dsc_compute_link_config(struct intel_dp
> *intel_dp,
>  					      compressed_bpp,
>  					      timeslots);
>  		if (ret == 0) {
> -			pipe_config->dsc.compressed_bpp =
> compressed_bpp;
> +			pipe_config->dsc.compressed_bpp =
> compressed_bpp << 4;
>  			return 0;
>  		}
>  	}
> @@ -2171,17 +2171,19 @@ int intel_dp_dsc_compute_config(struct
> intel_dp *intel_dp,
>  	if (ret < 0) {
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "Cannot compute valid DSC parameters for Input
> Bpp = %d "
> -			    "Compressed BPP = %d\n",
> +			    "Compressed BPP = %d.%d\n",
>  			    pipe_config->pipe_bpp,
> -			    pipe_config->dsc.compressed_bpp);
> +			    dsc_integral_compressed_bpp(pipe_config-
> >dsc.compressed_bpp),
> +			    dsc_fractional_compressed_bpp(pipe_config-
> >dsc.compressed_bpp));
>  		return ret;
>  	}
> 
>  	pipe_config->dsc.compression_enable = true;
>  	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp =
> %d "
> -		    "Compressed Bpp = %d Slice Count = %d\n",
> +		    "Compressed Bpp = %d.%d Slice Count = %d\n",
>  		    pipe_config->pipe_bpp,
> -		    pipe_config->dsc.compressed_bpp,
> +		    dsc_integral_compressed_bpp(pipe_config-
> >dsc.compressed_bpp),
> +		    dsc_fractional_compressed_bpp(pipe_config-
> >dsc.compressed_bpp),
>  		    pipe_config->dsc.slice_count);
> 
>  	return 0;
> @@ -2260,15 +2262,16 @@ intel_dp_compute_link_config(struct
> intel_encoder *encoder,
> 
>  	if (pipe_config->dsc.compression_enable) {
>  		drm_dbg_kms(&i915->drm,
> -			    "DP lane count %d clock %d Input bpp %d
> Compressed bpp %d\n",
> +			    "DP lane count %d clock %d Input bpp %d
> Compressed bpp %d.%d\n",
>  			    pipe_config->lane_count, pipe_config->port_clock,
>  			    pipe_config->pipe_bpp,
> -			    pipe_config->dsc.compressed_bpp);
> +			    dsc_integral_compressed_bpp(pipe_config-
> >dsc.compressed_bpp),
> +			    dsc_fractional_compressed_bpp(pipe_config-
> >dsc.compressed_bpp));
> 
>  		drm_dbg_kms(&i915->drm,
>  			    "DP link rate required %i available %i\n",
>  			    intel_dp_link_required(adjusted_mode->crtc_clock,
> -						   pipe_config-
> >dsc.compressed_bpp),
> +
> dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)),
>  			    intel_dp_max_data_rate(pipe_config->port_clock,
>  						   pipe_config->lane_count));
>  	} else {
> @@ -2700,7 +2703,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>  		intel_dp_limited_color_range(pipe_config, conn_state);
> 
>  	if (pipe_config->dsc.compression_enable)
> -		link_bpp = pipe_config->dsc.compressed_bpp;
> +		link_bpp =
> +dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
>  	else
>  		link_bpp = intel_dp_output_bpp(pipe_config-
> >output_format,
>  					       pipe_config->pipe_bpp);
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index e4c395b4dc46..2dc6ea82c024 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> -	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> +	u16 compressed_bpp =
> +dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
>  	int err;
>  	int ret;
> 
> @@ -1040,7 +1040,7 @@ void intel_dsc_get_config(struct intel_crtc_state
> *crtc_state)
>  	if (pps0 & DSC_NATIVE_420_ENABLE)
>  		vdsc_cfg->bits_per_pixel >>= 1;
> 
> -	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> +	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel;
>  out:
>  	intel_display_power_put(dev_priv, power_domain, wakeref);  }
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 3/9] drm/i915/display: Consider fractional vdsc bpp while computing m_n values

[Kandpal, Suraj]

> Subject: [Intel-gfx] [PATCH 3/9] drm/i915/display: Consider fractional vdsc
> bpp while computing m_n values
> 
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate this precision while computing m_n values.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c      | 7 ++++---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c  | 6 ++++--
>  drivers/gpu/drm/i915/display/intel_fdi.c     | 2 +-
>  5 files changed, 15 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8c81206ce90d..9af36e600c87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2380,10 +2380,14 @@ void
>  intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
>  		       int pixel_clock, int link_clock,
>  		       struct intel_link_m_n *m_n,
> -		       bool fec_enable)
> +		       bool fec_enable,
> +		       bool is_dsc_fractional_bpp)
>  {
>  	u32 data_clock = bits_per_pixel * pixel_clock;
> 
> +	if (is_dsc_fractional_bpp)
> +		data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock,
> 16);
> +

Is there any mention of this in bspec or dsc spec if so can you add that in commit message.

>  	if (fec_enable)
>  		data_clock = intel_dp_mode_to_fec_clock(data_clock);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 49ac8473b988..a4c4ca3cad65 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state
> *state,  void intel_link_compute_m_n(u16 bpp, int nlanes,
>  			    int pixel_clock, int link_clock,
>  			    struct intel_link_m_n *m_n,
> -			    bool fec_enable);
> +			    bool fec_enable, bool is_dsc_fractional_bpp);
>  u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>  			      u32 pixel_format, u64 modifier);  enum
> drm_mode_status diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 32d0bee11f53..436889c601b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2557,7 +2557,7 @@ intel_dp_drrs_compute_config(struct
> intel_connector *connector,
> 
>  	intel_link_compute_m_n(link_bpp, pipe_config->lane_count,
> pixel_clock,
>  			       pipe_config->port_clock, &pipe_config-
> >dp_m2_n2,
> -			       pipe_config->fec_enable);
> +			       pipe_config->fec_enable, false);
> 
>  	/* FIXME: abstract this better */
>  	if (pipe_config->splitter.enable)
> @@ -2703,7 +2703,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>  		intel_dp_limited_color_range(pipe_config, conn_state);
> 
>  	if (pipe_config->dsc.compression_enable)
> -		link_bpp = dsc_integral_compressed_bpp(pipe_config-
> >dsc.compressed_bpp);
> +		link_bpp = pipe_config->dsc.compressed_bpp;

In the second patch you added this but you end up deleting it here
which I believe is a mistake

Regards,
Suraj Kandpal

>  	else
>  		link_bpp = intel_dp_output_bpp(pipe_config-
> >output_format,
>  					       pipe_config->pipe_bpp);
> @@ -2735,7 +2735,8 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>  			       adjusted_mode->crtc_clock,
>  			       pipe_config->port_clock,
>  			       &pipe_config->dp_m_n,
> -			       pipe_config->fec_enable);
> +			       pipe_config->fec_enable,
> +			       pipe_config->dsc.compression_enable);
> 
>  	/* FIXME: abstract this better */
>  	if (pipe_config->splitter.enable)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 3eb085fbc7c8..e224eebe7c17 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -171,7 +171,8 @@ static int intel_dp_mst_compute_link_config(struct
> intel_encoder *encoder,
>  			       adjusted_mode->crtc_clock,
>  			       crtc_state->port_clock,
>  			       &crtc_state->dp_m_n,
> -			       crtc_state->fec_enable);
> +			       crtc_state->fec_enable,
> +			       false);
>  	crtc_state->dp_m_n.tu = slots;
> 
>  	return 0;
> @@ -265,7 +266,8 @@ static int
> intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
>  			       adjusted_mode->crtc_clock,
>  			       crtc_state->port_clock,
>  			       &crtc_state->dp_m_n,
> -			       crtc_state->fec_enable);
> +			       crtc_state->fec_enable,
> +			       crtc_state->dsc.compression_enable);
>  	crtc_state->dp_m_n.tu = slots;
> 
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
> b/drivers/gpu/drm/i915/display/intel_fdi.c
> index e12b46a84fa1..15fddabf7c2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
>  	pipe_config->fdi_lanes = lane;
> 
>  	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> -			       link_bw, &pipe_config->fdi_m_n, false);
> +			       link_bw, &pipe_config->fdi_m_n, false, false);
> 
>  	ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
>  	if (ret == -EDEADLK)
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 4/9] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data

[Kandpal, Suraj]

> Subject: [Intel-gfx] [PATCH 4/9] drm/i915/audio : Consider fractional vdsc bpp
> while computing tu_data
> 
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate the precision during calculation of transfer unit data for
> hblank_early calculation.
> 
> v2:
> -Fixed tu_data calculation while dealing with U6.4 format. (Stan)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_audio.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index 93969b63cdd8..bbd99e2fb399 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -521,14 +521,14 @@ static unsigned int calc_hblank_early_prog(struct
> intel_encoder *encoder,
>  	unsigned int link_clks_available, link_clks_required;
>  	unsigned int tu_data, tu_line, link_clks_active;
>  	unsigned int h_active, h_total, hblank_delta, pixel_clk;
> -	unsigned int fec_coeff, cdclk, vdsc_bpp;
> +	unsigned int fec_coeff, cdclk, vdsc_bppx16;
>  	unsigned int link_clk, lanes;
>  	unsigned int hblank_rise;
> 
>  	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>  	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
>  	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
> -	vdsc_bpp = dsc_integral_compressed_bpp(crtc_state-
> >dsc.compressed_bpp);
> +	vdsc_bppx16 = crtc_state->dsc.compressed_bpp;

This wouldn't be needed if dsc_integral_compressed_bpp wasn't called
Here in the second patch.
Maybe just a rename of the vdsc_bpp variable name as a part of this patch

Regards,
Suraj Kandpal

>  	cdclk = i915->display.cdclk.hw.cdclk;
>  	/* fec= 0.972261, using rounding multiplier of 1000000 */
>  	fec_coeff = 972261;
> @@ -536,10 +536,10 @@ static unsigned int calc_hblank_early_prog(struct
> intel_encoder *encoder,
>  	lanes = crtc_state->lane_count;
> 
>  	drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
> -		    "lanes = %u vdsc_bpp = %u cdclk = %u\n",
> -		    h_active, link_clk, lanes, vdsc_bpp, cdclk);
> +		    "lanes = %u vdsc_bppx16 = %u cdclk = %u\n",
> +		    h_active, link_clk, lanes, vdsc_bppx16, cdclk);
> 
> -	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
> +	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 ||
> +!cdclk))
>  		return 0;
> 
>  	link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; @@
> -551,8 +551,8 @@ static unsigned int calc_hblank_early_prog(struct
> intel_encoder *encoder,
>  		hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 *
> (link_clk + cdclk), pixel_clk),
>  						  mul_u32_u32(link_clk,
> cdclk));
> 
> -	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8,
> 1000000),
> -			    mul_u32_u32(link_clk * lanes, fec_coeff));
> +	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8,
> 1000000),
> +			    mul_u32_u32(link_clk * lanes * 16, fec_coeff));
>  	tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
>  			    mul_u32_u32(64 * pixel_clk, 1000000));
>  	link_clks_active  = (tu_line - 1) * 64 + tu_data;
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 5/9] drm/display/dp: Add helper function to get DSC bpp prescision

[Kandpal, Suraj]

> Add helper to get the DSC bits_per_pixel precision for the DP sink.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/display/drm_dp_helper.c | 27
> +++++++++++++++++++++++++
>  include/drm/display/drm_dp_helper.h     |  1 +
>  2 files changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
> b/drivers/gpu/drm/display/drm_dp_helper.c
> index e6a78fd32380..aa8ea36211de 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux,
> struct drm_dp_desc *desc,  }  EXPORT_SYMBOL(drm_dp_read_desc);
> 
> +/**
> + * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
> + * @dsc_dpcd: DSC capabilities from DPCD
> + *
> + * Returns the bpp precision supported by the DP sink.
> + */
> +u8 drm_dp_dsc_sink_bpp_incr(const u8
> +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> +{
> +	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC -
> +DP_DSC_SUPPORT];
> +
> +	switch (bpp_increment_dpcd) {
> +	case DP_DSC_BITS_PER_PIXEL_1_16:
> +		return 16;
> +	case DP_DSC_BITS_PER_PIXEL_1_8:
> +		return 8;
> +	case DP_DSC_BITS_PER_PIXEL_1_4:
> +		return 4;
> +	case DP_DSC_BITS_PER_PIXEL_1_2:
> +		return 2;
> +	case DP_DSC_BITS_PER_PIXEL_1_1:
> +		return 1;

Shouldn't there be a default MISSING_CASE to throw a warning if its none of the above case
Occurs in case a addition bit for step is added in dpcd going forward

Regards,
Suraj Kandpal

> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
> +
>  /**
>   * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
>   * supported by the DSC sink.
> diff --git a/include/drm/display/drm_dp_helper.h
> b/include/drm/display/drm_dp_helper.h
> index 86f24a759268..ba0514f0b032 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -164,6 +164,7 @@ drm_dp_is_branch(const u8
> dpcd[DP_RECEIVER_CAP_SIZE])  }
> 
>  /* DP/eDP DSC support */
> +u8 drm_dp_dsc_sink_bpp_incr(const u8
> +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
>  u8 drm_dp_dsc_sink_max_slice_count(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
>  				   bool is_edp);
>  u8 drm_dp_dsc_sink_line_buf_depth(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 5/9] drm/display/dp: Add helper function to get DSC bpp prescision

[Kandpal, Suraj]

> 
> > Add helper to get the DSC bits_per_pixel precision for the DP sink.
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Wouldn't we also need to send this patch to dri-devel

Regards,
Suraj Kandpal
> > ---
> >  drivers/gpu/drm/display/drm_dp_helper.c | 27
> > +++++++++++++++++++++++++
> >  include/drm/display/drm_dp_helper.h     |  1 +
> >  2 files changed, 28 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
> > b/drivers/gpu/drm/display/drm_dp_helper.c
> > index e6a78fd32380..aa8ea36211de 100644
> > --- a/drivers/gpu/drm/display/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> > @@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux,
> > struct drm_dp_desc *desc,  }  EXPORT_SYMBOL(drm_dp_read_desc);
> >
> > +/**
> > + * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
> > + * @dsc_dpcd: DSC capabilities from DPCD
> > + *
> > + * Returns the bpp precision supported by the DP sink.
> > + */
> > +u8 drm_dp_dsc_sink_bpp_incr(const u8
> > +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> > +{
> > +	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC -
> > +DP_DSC_SUPPORT];
> > +
> > +	switch (bpp_increment_dpcd) {
> > +	case DP_DSC_BITS_PER_PIXEL_1_16:
> > +		return 16;
> > +	case DP_DSC_BITS_PER_PIXEL_1_8:
> > +		return 8;
> > +	case DP_DSC_BITS_PER_PIXEL_1_4:
> > +		return 4;
> > +	case DP_DSC_BITS_PER_PIXEL_1_2:
> > +		return 2;
> > +	case DP_DSC_BITS_PER_PIXEL_1_1:
> > +		return 1;
> 
> Shouldn't there be a default MISSING_CASE to throw a warning if its none of the
> above case Occurs in case a addition bit for step is added in dpcd going forward
> 
> Regards,
> Suraj Kandpal
> 
> > +	}
> > +
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
> > +
> >  /**
> >   * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
> >   * supported by the DSC sink.
> > diff --git a/include/drm/display/drm_dp_helper.h
> > b/include/drm/display/drm_dp_helper.h
> > index 86f24a759268..ba0514f0b032 100644
> > --- a/include/drm/display/drm_dp_helper.h
> > +++ b/include/drm/display/drm_dp_helper.h
> > @@ -164,6 +164,7 @@ drm_dp_is_branch(const u8
> > dpcd[DP_RECEIVER_CAP_SIZE])  }
> >
> >  /* DP/eDP DSC support */
> > +u8 drm_dp_dsc_sink_bpp_incr(const u8
> > +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> >  u8 drm_dp_dsc_sink_max_slice_count(const u8
> > dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> >  				   bool is_edp);
> >  u8 drm_dp_dsc_sink_line_buf_depth(const u8
> > dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> > --
> > 2.40.1

Re: [Intel-gfx] [PATCH 2/9] drm/i915/display: Store compressed bpp in U6.4 format

[Kandpal, Suraj]

> Subject: RE: [Intel-gfx] [PATCH 2/9] drm/i915/display: Store compressed bpp in
> U6.4 format
> 
> > Subject: [Intel-gfx] [PATCH 2/9] drm/i915/display: Store compressed
> > bpp in
> > U6.4 format
> >
> > DSC parameter bits_per_pixel is stored in U6.4 format.
> > The 4 bits represent the fractional part of the bpp.
> > Currently we use compressed_bpp member of dsc structure to store only
> > the integral part of the bits_per_pixel.
> > To store the full bits_per_pixel along with the fractional part,
> > compressed_bpp is changed to store bpp in U6.4 formats. Intergral part
> > is retrieved by simply right shifting the member compressed_bpp by 4.
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/icl_dsi.c        | 10 ++++-----
> >  drivers/gpu/drm/i915/display/intel_audio.c    |  2 +-
> >  drivers/gpu/drm/i915/display/intel_bios.c     |  2 +-
> >  .../drm/i915/display/intel_display_types.h    | 16 +++++++++++++-
> >  drivers/gpu/drm/i915/display/intel_dp.c       | 21 +++++++++++--------
> >  drivers/gpu/drm/i915/display/intel_vdsc.c     |  4 ++--
> >  6 files changed, 36 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index ad6488e9c2b2..81b8e97e9435 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder,
> >  	int bpp;
> >
> >  	if (crtc_state->dsc.compression_enable)
> > -		bpp = crtc_state->dsc.compressed_bpp;
> > +		bpp = dsc_integral_compressed_bpp(crtc_state-
> > >dsc.compressed_bpp);
> >  	else
> >  		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> >
> > @@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct
> > intel_encoder *encoder,
> >  	 * compressed and non-compressed bpp.
> >  	 */
> >  	if (crtc_state->dsc.compression_enable) {
> > -		mul = crtc_state->dsc.compressed_bpp;
> > +		mul = dsc_integral_compressed_bpp(crtc_state-
> > >dsc.compressed_bpp);
> >  		div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> >  	}
> >
> > @@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct
> > intel_encoder *encoder,
> >  		int bpp, line_time_us, byte_clk_period_ns;
> >
> >  		if (crtc_state->dsc.compression_enable)
> > -			bpp = crtc_state->dsc.compressed_bpp;
> > +			bpp = dsc_integral_compressed_bpp(crtc_state-
> > >dsc.compressed_bpp);
> >  		else
> >  			bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> > >pixel_format);
> >
> > @@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct
> > intel_encoder *encoder,
> >  	struct drm_display_mode *adjusted_mode =
> >  					&pipe_config->hw.adjusted_mode;
> >
> > -	if (pipe_config->dsc.compressed_bpp) {
> > -		int div = pipe_config->dsc.compressed_bpp;
> > +	if (dsc_integral_compressed_bpp(pipe_config-
> > >dsc.compressed_bpp)) {
> 
> Doesn't make sense to have this function to be called here this just checks if we
> have compressed_bpp available or not extracting the integral part should not be
> necessary
> 
> > +		int div =
> > +dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
> >  		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> > >pixel_format);
> >
> >  		adjusted_mode->crtc_htotal =
> > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> > b/drivers/gpu/drm/i915/display/intel_audio.c
> > index 3d9c9b4f27f8..93969b63cdd8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> > @@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct
> > intel_encoder *encoder,
> >  	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> >  	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
> >  	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
> > -	vdsc_bpp = crtc_state->dsc.compressed_bpp;
> > +	vdsc_bpp =
> > +dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp);
> >  	cdclk = i915->display.cdclk.hw.cdclk;
> >  	/* fec= 0.972261, using rounding multiplier of 1000000 */
> >  	fec_coeff = 972261;
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 858c959f7bab..fe1e376c4ba7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -3385,7 +3385,7 @@ static void fill_dsc(struct intel_crtc_state
> > *crtc_state,
> >  	crtc_state->pipe_bpp = bpc * 3;
> >
> >  	crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
> > -					     VBT_DSC_MAX_BPP(dsc-
> > >max_bpp));
> > +					     VBT_DSC_MAX_BPP(dsc-
> > >max_bpp)) << 4;
> >
> >  	/*
> >  	 * FIXME: This is ugly, and slice count should take DSC engine diff
> > --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 731f2ec04d5c..f749dc4e70df 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1353,7 +1353,7 @@ struct intel_crtc_state {
> >  	struct {
> >  		bool compression_enable;
> >  		bool dsc_split;
> > -		u16 compressed_bpp;
> > +		u16 compressed_bpp; /* U6.4 format (first 4 bits for
> > fractional part)
> > +*/

Normally I have seen the comment come on top of variable declaration in
struct rather than right in front of it maybe follow that convention
I don't personally have such preference

Regards,
Suraj Kandpal
> >  		u8 slice_count;
> >  		struct drm_dsc_config config;
> >  	} dsc;
> > @@ -2108,4 +2108,18 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
> >  	return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;  }
> >
> > +/* Returns integral part of the compressed bpp given in U6.4 format
> > +*/ static inline int
> > +dsc_integral_compressed_bpp(u16 compressed_bpp) {
> > +	return compressed_bpp >> 4;
> > +}
> 
> Maybe we can have two macro/functions that can be used to shift the fractional
> part for bpp
> dsc_bpp_x_to_x16 and dsc_bpp_x16_to_x this can be used at a lot of places to
> avoid confusions everywhere when and why we are shifting  by 4.
> We can keep the dsc_fractional_compressed_bpp.
> 
> > +
> > +/* Returns fractional part of the compressed bpp given in U6.4 format
> > +*/ static inline int
> > +dsc_fractional_compressed_bpp(u16 compressed_bpp) {
> > +	return ((compressed_bpp & 0xF) * 10000 / 16); }
> > +
> 
> Maybe dsc_get_fractional_bpp () ?
> 
> >  #endif /*  __INTEL_DISPLAY_TYPES_H__ */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 5b48bfe09d0e..32d0bee11f53 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1901,7 +1901,7 @@ xelpd_dsc_compute_link_config(struct intel_dp
> > *intel_dp,
> >  					      compressed_bpp,
> >  					      timeslots);
> >  		if (ret == 0) {
> > -			pipe_config->dsc.compressed_bpp =
> > compressed_bpp;
> > +			pipe_config->dsc.compressed_bpp =
> > compressed_bpp << 4;
> >  			return 0;
> >  		}
> >  	}
> > @@ -2171,17 +2171,19 @@ int intel_dp_dsc_compute_config(struct
> > intel_dp *intel_dp,
> >  	if (ret < 0) {
> >  		drm_dbg_kms(&dev_priv->drm,
> >  			    "Cannot compute valid DSC parameters for Input
> Bpp = %d "
> > -			    "Compressed BPP = %d\n",
> > +			    "Compressed BPP = %d.%d\n",
> >  			    pipe_config->pipe_bpp,
> > -			    pipe_config->dsc.compressed_bpp);
> > +			    dsc_integral_compressed_bpp(pipe_config-
> > >dsc.compressed_bpp),
> > +			    dsc_fractional_compressed_bpp(pipe_config-
> > >dsc.compressed_bpp));
> >  		return ret;
> >  	}
> >
> >  	pipe_config->dsc.compression_enable = true;
> >  	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp =
> %d "
> > -		    "Compressed Bpp = %d Slice Count = %d\n",
> > +		    "Compressed Bpp = %d.%d Slice Count = %d\n",
> >  		    pipe_config->pipe_bpp,
> > -		    pipe_config->dsc.compressed_bpp,
> > +		    dsc_integral_compressed_bpp(pipe_config-
> > >dsc.compressed_bpp),
> > +		    dsc_fractional_compressed_bpp(pipe_config-
> > >dsc.compressed_bpp),
> >  		    pipe_config->dsc.slice_count);
> >
> >  	return 0;
> > @@ -2260,15 +2262,16 @@ intel_dp_compute_link_config(struct
> > intel_encoder *encoder,
> >
> >  	if (pipe_config->dsc.compression_enable) {
> >  		drm_dbg_kms(&i915->drm,
> > -			    "DP lane count %d clock %d Input bpp %d
> > Compressed bpp %d\n",
> > +			    "DP lane count %d clock %d Input bpp %d
> > Compressed bpp %d.%d\n",
> >  			    pipe_config->lane_count, pipe_config->port_clock,
> >  			    pipe_config->pipe_bpp,
> > -			    pipe_config->dsc.compressed_bpp);
> > +			    dsc_integral_compressed_bpp(pipe_config-
> > >dsc.compressed_bpp),
> > +			    dsc_fractional_compressed_bpp(pipe_config-
> > >dsc.compressed_bpp));
> >
> >  		drm_dbg_kms(&i915->drm,
> >  			    "DP link rate required %i available %i\n",
> >  			    intel_dp_link_required(adjusted_mode->crtc_clock,
> > -						   pipe_config-
> > >dsc.compressed_bpp),
> > +
> > dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)),
> >  			    intel_dp_max_data_rate(pipe_config->port_clock,
> >  						   pipe_config->lane_count));
> >  	} else {
> > @@ -2700,7 +2703,7 @@ intel_dp_compute_config(struct intel_encoder
> > *encoder,
> >  		intel_dp_limited_color_range(pipe_config, conn_state);
> >
> >  	if (pipe_config->dsc.compression_enable)
> > -		link_bpp = pipe_config->dsc.compressed_bpp;
> > +		link_bpp =
> > +dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
> >  	else
> >  		link_bpp = intel_dp_output_bpp(pipe_config-
> > >output_format,
> >  					       pipe_config->pipe_bpp);
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index e4c395b4dc46..2dc6ea82c024 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct
> > intel_crtc_state
> > *pipe_config)
> >  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> > -	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> > +	u16 compressed_bpp =
> > +dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp);
> >  	int err;
> >  	int ret;
> >
> > @@ -1040,7 +1040,7 @@ void intel_dsc_get_config(struct
> > intel_crtc_state
> > *crtc_state)
> >  	if (pps0 & DSC_NATIVE_420_ENABLE)
> >  		vdsc_cfg->bits_per_pixel >>= 1;
> >
> > -	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> > +	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel;
> >  out:
> >  	intel_display_power_put(dev_priv, power_domain, wakeref);  }
> > --
> > 2.40.1

Re: [Intel-gfx] [PATCH 6/9] drm/i915/dsc/mtl: Add support for fractional bpp

[Kandpal, Suraj]

> Subject: [Intel-gfx] [PATCH 6/9] drm/i915/dsc/mtl: Add support for fractional
> bpp
> 
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> Consider the fractional bpp while reading the qp values.
> 
> v2: Use helpers for fractional, integral bits of bits_per_pixel.
> 
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_qp_tables.c    |  3 ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c     | 23 +++++++++++++++----
>  2 files changed, 18 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c
> b/drivers/gpu/drm/i915/display/intel_qp_tables.c
> index 543cdc46aa1d..600c815e37e4 100644
> --- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
> +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
> @@ -34,9 +34,6 @@
>   * These qp tables are as per the C model
>   * and it has the rows pointing to bpps which increment
>   * in steps of 0.5
> - * We do not support fractional bpps as of today,
> - * hence we would skip the fractional bpps during
> - * our references for qp calclulations.
>   */
>  static const u8
> rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC
> _MAX_NUM_BPP] = {
>  	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git
> a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 2dc6ea82c024..4bd570fb0ab2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -77,8 +77,9 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config
> *vdsc_cfg, int buf,  static void  calculate_rc_params(struct drm_dsc_config
> *vdsc_cfg)  {
> +	int fractional_bits = dsc_fractional_compressed_bpp(vdsc_cfg-
> >bits_per_pixel);
> +	int bpp = dsc_integral_compressed_bpp(vdsc_cfg->bits_per_pixel);
>  	int bpc = vdsc_cfg->bits_per_component;
> -	int bpp = vdsc_cfg->bits_per_pixel >> 4;
>  	int qp_bpc_modifier = (bpc - 8) * 2;
>  	int uncompressed_bpg_rate;
>  	int first_line_bpg_offset;
> @@ -148,7 +149,13 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
>  		static const s8 ofs_und8[] = {
>  			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
>  		};
> -
> +	/*
> +	 * For 420 format since bits_per_pixel (bpp) is set to target bpp * 2,
> +	 * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0) are
> +	 * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).
> +	 * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5)
> +	 * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.
> +	 */
>  		bpp_i  = bpp - 8;
>  		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
>  			u8 range_bpg_offset;
> @@ -191,7 +198,14 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
>  			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
>  		};
> 
> -		bpp_i  = (2 * (bpp - 6));
> +		/*
> +		 * QP table rows have values in increment of 0.5.
> +		 * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will
> have index 1,
> +		 * and so on.
> +		 * 0.5 represented as 0x8 in U6.4 format.
> +		 */
> +		bpp_i  = ((bpp - 6) + (fractional_bits < 0x8 ? 0 : 1));

Can we have a the 0x8 as a #define rather than a direct comparison to 0x8

Also isn't what was previously present doing the same thing
Sure fractional bits weren't taken into consideration but they would still fall in the same
Index. Anyways the bpp taken is the integer part so I thing no change is required to the formula.

> +
>  		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
>  			u8 range_bpg_offset;
> 
> @@ -279,8 +293,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
>  	/* Gen 11 does not support VBR */
>  	vdsc_cfg->vbr_enable = false;
> 
> -	/* Gen 11 only supports integral values of bpp */
> -	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> +	vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp;
> 
>  	/*
>  	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 6/9] drm/i915/dsc/mtl: Add support for fractional bpp

[Kandpal, Suraj]

> Subject: RE: [Intel-gfx] [PATCH 6/9] drm/i915/dsc/mtl: Add support for fractional
> bpp
> 
> > Subject: [Intel-gfx] [PATCH 6/9] drm/i915/dsc/mtl: Add support for
> > fractional bpp
> >
> > From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >
> > Consider the fractional bpp while reading the qp values.
> >
> > v2: Use helpers for fractional, integral bits of bits_per_pixel.
> >
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_qp_tables.c    |  3 ---
> >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 23 +++++++++++++++----
> >  2 files changed, 18 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c
> > b/drivers/gpu/drm/i915/display/intel_qp_tables.c
> > index 543cdc46aa1d..600c815e37e4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
> > +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
> > @@ -34,9 +34,6 @@
> >   * These qp tables are as per the C model
> >   * and it has the rows pointing to bpps which increment
> >   * in steps of 0.5
> > - * We do not support fractional bpps as of today,
> > - * hence we would skip the fractional bpps during
> > - * our references for qp calclulations.
> >   */
> >  static const u8
> >
> rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC
> > _MAX_NUM_BPP] = {
> >  	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> > 0, diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index 2dc6ea82c024..4bd570fb0ab2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -77,8 +77,9 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config
> > *vdsc_cfg, int buf,  static void  calculate_rc_params(struct
> > drm_dsc_config
> > *vdsc_cfg)  {
> > +	int fractional_bits = dsc_fractional_compressed_bpp(vdsc_cfg-
> > >bits_per_pixel);
> > +	int bpp = dsc_integral_compressed_bpp(vdsc_cfg->bits_per_pixel);
> >  	int bpc = vdsc_cfg->bits_per_component;
> > -	int bpp = vdsc_cfg->bits_per_pixel >> 4;
> >  	int qp_bpc_modifier = (bpc - 8) * 2;
> >  	int uncompressed_bpg_rate;
> >  	int first_line_bpg_offset;
> > @@ -148,7 +149,13 @@ calculate_rc_params(struct drm_dsc_config
> *vdsc_cfg)
> >  		static const s8 ofs_und8[] = {
> >  			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
> >  		};
> > -
> > +	/*
> > +	 * For 420 format since bits_per_pixel (bpp) is set to target bpp * 2,
> > +	 * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0) are
> > +	 * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).
> > +	 * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5)
> > +	 * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.
> > +	 */
> >  		bpp_i  = bpp - 8;
> >  		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
> >  			u8 range_bpg_offset;
> > @@ -191,7 +198,14 @@ calculate_rc_params(struct drm_dsc_config
> *vdsc_cfg)
> >  			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
> >  		};
> >
> > -		bpp_i  = (2 * (bpp - 6));
> > +		/*
> > +		 * QP table rows have values in increment of 0.5.
> > +		 * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will
> > have index 1,
> > +		 * and so on.
> > +		 * 0.5 represented as 0x8 in U6.4 format.
> > +		 */
> > +		bpp_i  = ((bpp - 6) + (fractional_bits < 0x8 ? 0 : 1));
> 
> Can we have a the 0x8 as a #define rather than a direct comparison to 0x8
> 

Also maybe we can have a function/macro which takes in the integral and fractional
part and spits out the closest integer
something like DIV_ROUND_CLOSEST but that won't directly work with this case
but I do think we can repurpose it for our use case.

> Also isn't what was previously present doing the same thing Sure fractional bits
> weren't taken into consideration but they would still fall in the same Index.
> Anyways the bpp taken is the integer part so I thing no change is required to
> the formula.

Also scratch this comment I had another looks and seems logical to me what we are doing.

Regards,
Suraj Kandpal

> 
> > +
> >  		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
> >  			u8 range_bpg_offset;
> >
> > @@ -279,8 +293,7 @@ int intel_dsc_compute_params(struct
> > intel_crtc_state
> > *pipe_config)
> >  	/* Gen 11 does not support VBR */
> >  	vdsc_cfg->vbr_enable = false;
> >
> > -	/* Gen 11 only supports integral values of bpp */
> > -	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> > +	vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp;
> >
> >  	/*
> >  	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set
> > --
> > 2.40.1