RE: [PATCH 2/2] serial: sh-sci: Document r7s9210 bindings

[Chris Brandt <Chris.Brandt@renesas.com>]

Hi Geert,

On Tuesday, July 17, 2018, Geert Uytterhoeven wrote:
> On Fri, Jul 13, 2018 at 5:50 PM Geert Uytterhoeven <geert@linux-m68k.org>
> wrote:
> > On Wed, Jul 11, 2018 at 4:42 PM Chris Brandt <chris.brandt@renesas.com>
> wrote:
> > > Add R7S9210 (RZ/A2) support
> > >
> > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Sorry, I spoke too soon.
> It seems the bindings were never updated for the use of multiple
> interrupts
> on RZ/A1.  As RZ/A2 adds one new interrupt, can you please document which
> interrupts are required?
> Thanks!

The issue that I ran into was the device driver assumed some signals 
were muxed together (TXI and DRI), and that other signals were individual.

The existing driver wanted interrupts to be specified in this order:
  1. Error
  2. RX
  3. TX (assumes DRI)
  4. Break

However, for the SCIF that is present in the RZ/A2M, Error and Break are
muxed together, and then DRI is not muxed with TX. This is different 
than any other SCIF supported by the driver.

My solution was to list the Error/Break twice, and then add a new 
interrupt for DRI.

As reference, here is what the DT node would look like:

	scif0: serial@e8007000 {
		compatible = "renesas,scif-r7s9210", "renesas,scif";
		reg = <0xe8007000 18>;
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, /* ERI0/BRI0 */
			     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,   /* RXI0 */
			     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,   /* TXI0 */
			     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,   /* ERI0/BRI0 */
			     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;   /* TEI/DRI0 */
		clocks = <&mstp4_clks R7S9210_CLK_SCIF0>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

Of course I have no problem documenting all this, but I first I just 
wanted to make sure I was not going to get push back when I submit a DT 
later that lists the same interrupt twice.

Thanks,
Chris