[PATCH v7 0/4] Add CPU identification support for RZ/G2 SoC's

[PATCH v7 0/4] Add CPU identification support for RZ/G2 SoC's

[Biju Das]

This patch series aims to add CPU identification support for RZ/G2 SoC's
and adding SDHI quirks using SoC identification driver.

This patch series depend on SoC identification driver[1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=214706

Biju Das (4):
  arm: rmobile: Add RZ/G2[HMNE] SoC support
  mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
  mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N
  mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H

 arch/arm/mach-rmobile/cpu_info-rcar.c        |  22 ++-
 arch/arm/mach-rmobile/cpu_info.c             |  10 +-
 arch/arm/mach-rmobile/include/mach/rmobile.h |  60 +++++--
 drivers/mmc/renesas-sdhi.c                   | 160 +++++++++++++++++++
 4 files changed, 233 insertions(+), 19 deletions(-)

-- 
2.17.1

[PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some
automotive peripherals.

RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951).
RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960).
RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965).
RZ/G2E (R8A774C0) = R-Car E3 (R8A77990).

As the devices are the same they also have the same SoC PRR
register values. SoC driver is used to distinguish the
cpu type based on the family.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v6->v7
 * Seperated driver patch series from board support patches.
v5->v6
 * Optimized the unique CPU identification method by using Renesas SoC identification driver.
v4->v5
 * Add support for unique identification of RZ/G2 CPU types
   (Ref: https://patchwork.ozlabs.org/project/uboot/patch/20201008085941.3600-1-biju.das.jz at bp.renesas.com/)
v3->v4
 * Dropped CPU info reporting logic for RZ/G2. Will address this later.
 * Added PRRID's for RZG2[HMNE]
   (Ref: https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-1-biju.das.jz at bp.renesas.com/)

v2->v3  
 * Reworked as per Marek's suggestion
 * Added rzg2_get_cpu_type function to get cpu_type by matching TFA compatible string
 * Removed SoC family type Enum
   (Ref: https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-2-biju.das.jz at bp.renesas.com/)

v1->v2:
 * Add comment's related to loop logic
   (ref: https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-1-biju.das.jz at bp.renesas.com/)

v1:
 * New patch
  (ref:https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-4-biju.das.jz at bp.renesas.com/
---
 arch/arm/mach-rmobile/cpu_info-rcar.c        | 22 ++++++-
 arch/arm/mach-rmobile/cpu_info.c             | 10 +++-
 arch/arm/mach-rmobile/include/mach/rmobile.h | 60 +++++++++++++++-----
 3 files changed, 73 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c
index 5bde24ae0e..08345503a2 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -6,6 +6,7 @@
  */
 #include <common.h>
 #include <asm/io.h>
+#include <soc.h>
 
 #define PRR_MASK		0x7fff
 #define R8A7796_REV_1_0		0x5200
@@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void)
 #endif
 }
 
+static bool is_rzg_family(void)
+{
+	bool rzg_family_type = false;
+	struct udevice *soc;
+	char name[16];
+
+	if (!(soc_get(&soc) || soc_get_family(soc, name, 16))) {
+		if (!strcmp(name, "RZ/G2"))
+			rzg_family_type = true;
+	}
+
+	return rzg_family_type;
+}
+
 u32 rmobile_get_cpu_type(void)
 {
-	return (rmobile_get_prr() & 0x00007F00) >> 8;
+	u32 soc_id = (rmobile_get_prr() & 0x7F00) >> 8;
+
+	if (is_rzg_family())
+		soc_id |= RZG_CPU_MASK;
+
+	return soc_id;
 }
 
 u32 rmobile_get_cpu_rev_integer(void)
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index fdbbd72e28..b19b7e3044 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -3,12 +3,12 @@
  * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  * (C) Copyright 2012 Renesas Solutions Corp.
  */
-#include <common.h>
-#include <cpu_func.h>
 #include <asm/cache.h>
-#include <init.h>
 #include <asm/io.h>
+#include <common.h>
+#include <cpu_func.h>
 #include <env.h>
+#include <init.h>
 #include <linux/ctype.h>
 
 #ifdef CONFIG_ARCH_CPU_INIT
@@ -59,6 +59,10 @@ static const struct {
 } rmobile_cpuinfo[] = {
 	{ RMOBILE_CPU_TYPE_SH73A0, "SH73A0" },
 	{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
+	{ RMOBILE_CPU_TYPE_R8A774A1, "R8A774A1" },
+	{ RMOBILE_CPU_TYPE_R8A774B1, "R8A774B1" },
+	{ RMOBILE_CPU_TYPE_R8A774C0, "R8A774C0" },
+	{ RMOBILE_CPU_TYPE_R8A774E1, "R8A774E1" },
 	{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
 	{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },
 	{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index a50249dc96..da099fa4c3 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -24,21 +24,51 @@
 #endif
 #endif /* CONFIG_ARCH_RMOBILE */
 
-/* PRR CPU IDs */
-#define RMOBILE_CPU_TYPE_SH73A0		0x37
-#define RMOBILE_CPU_TYPE_R8A7740	0x40
-#define RMOBILE_CPU_TYPE_R8A7790	0x45
-#define RMOBILE_CPU_TYPE_R8A7791	0x47
-#define RMOBILE_CPU_TYPE_R8A7792	0x4A
-#define RMOBILE_CPU_TYPE_R8A7793	0x4B
-#define RMOBILE_CPU_TYPE_R8A7794	0x4C
-#define RMOBILE_CPU_TYPE_R8A7795	0x4F
-#define RMOBILE_CPU_TYPE_R8A7796	0x52
-#define RMOBILE_CPU_TYPE_R8A77965	0x55
-#define RMOBILE_CPU_TYPE_R8A77970	0x54
-#define RMOBILE_CPU_TYPE_R8A77980	0x56
-#define RMOBILE_CPU_TYPE_R8A77990	0x57
-#define RMOBILE_CPU_TYPE_R8A77995	0x58
+/* PRR IDs */
+#define SOC_ID_SH73A0		0x37
+#define SOC_ID_R8A7740		0x40
+#define SOC_ID_R8A774A1		0x52
+#define SOC_ID_R8A774B1		0x55
+#define SOC_ID_R8A774C0		0x57
+#define SOC_ID_R8A774E1		0x4F
+#define SOC_ID_R8A7790		0x45
+#define SOC_ID_R8A7791		0x47
+#define SOC_ID_R8A7792		0x4A
+#define SOC_ID_R8A7793		0x4B
+#define SOC_ID_R8A7794		0x4C
+#define SOC_ID_R8A7795		0x4F
+#define SOC_ID_R8A7796		0x52
+#define SOC_ID_R8A77965		0x55
+#define SOC_ID_R8A77970		0x54
+#define SOC_ID_R8A77980		0x56
+#define SOC_ID_R8A77990		0x57
+#define SOC_ID_R8A77995		0x58
+
+/* CPU IDs */
+#define RMOBILE_CPU_TYPE_SH73A0		SOC_ID_SH73A0
+#define RMOBILE_CPU_TYPE_R8A7740	SOC_ID_R8A7740
+#define RMOBILE_CPU_TYPE_R8A774A1	(SOC_ID_R8A774A1 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A774B1	(SOC_ID_R8A774B1 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A774C0	(SOC_ID_R8A774C0 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A774E1	(SOC_ID_R8A774E1 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A7790	SOC_ID_R8A7790
+#define RMOBILE_CPU_TYPE_R8A7791	SOC_ID_R8A7791
+#define RMOBILE_CPU_TYPE_R8A7792	SOC_ID_R8A7792
+#define RMOBILE_CPU_TYPE_R8A7793	SOC_ID_R8A7793
+#define RMOBILE_CPU_TYPE_R8A7794	SOC_ID_R8A7794
+#define RMOBILE_CPU_TYPE_R8A7795	SOC_ID_R8A7795
+#define RMOBILE_CPU_TYPE_R8A7796	SOC_ID_R8A7796
+#define RMOBILE_CPU_TYPE_R8A77965	SOC_ID_R8A77965
+#define RMOBILE_CPU_TYPE_R8A77970	SOC_ID_R8A77970
+#define RMOBILE_CPU_TYPE_R8A77980	SOC_ID_R8A77980
+#define RMOBILE_CPU_TYPE_R8A77990	SOC_ID_R8A77990
+#define RMOBILE_CPU_TYPE_R8A77995	SOC_ID_R8A77995
+
+/*
+ * R-Car and RZ/G SoC's share same PRR ID's for the same SoC type. The
+ * RZG_CPU_MASK is used to provide a unique CPU identification for RZ/G SoC's.
+ */
+#define RZG_CPU_MASK 0x1000
 
 #ifndef __ASSEMBLY__
 u32 rmobile_get_cpu_type(void);
-- 
2.17.1

[PATCH v7 2/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M

[Biju Das]

Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v7:
 * Incorporated Jaehoon Chung's review comments.
 * Fixed the build error on Renesas ARM32 platforms.
v6:
 * New patch. quirks using soc_device_match.
---
 drivers/mmc/renesas-sdhi.c | 117 +++++++++++++++++++++++++++++++++++++
 1 file changed, 117 insertions(+)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index d80b3fc28f..7e3ea92cbf 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/sizes.h>
 #include <power/regulator.h>
+#include <soc.h>
 #include <asm/unaligned.h>
 #include "tmio-common.h"
 
@@ -855,6 +856,115 @@ static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
 	return clk_get_rate(&priv->clk);
 }
 
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+    CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+    CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+
+#define SDHI_CALIB_TABLE_MAX 32
+
+struct renesas_sdhi_quirks {
+	bool hs400_disabled;
+	bool hs400_4taps;
+	u32 hs400_bad_taps;
+	const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_b17_dtrend = {
+	.hs400_disabled = true,
+	.hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
+	.hs400_disabled = true,
+	.hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
+	.hs400_4taps = true,
+	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+	.hs400_calib_table = r8a7796_rev1_calib_table,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
+	.hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
+	.hs400_calib_table = r8a7796_rev3_calib_table,
+};
+
+/*
+ * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
+ * So, we want to treat them equally and only have a match for ES1.2 to enforce
+ * this if there ever will be a way to distinguish ES1.2.
+ */
+static const struct soc_attr sdhi_quirks_match[]  = {
+	{ .soc_id = "r8a774a1",
+	  .revision = "ES1.0",
+	  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
+	},
+	{ .soc_id = "r8a774a1",
+	  .revision = "ES1.1",
+	  .data = &sdhi_quirks_4tap_nohs400
+	},
+	{ .soc_id = "r8a774a1",
+	  .revision = "ES1.2",
+	  .data = &sdhi_quirks_r8a7796_es12
+	},
+	{ .soc_id = "r8a774a1",
+	  .revision = "ES1.3",
+	  .data = &sdhi_quirks_r8a7796_es13
+	},
+	{ .soc_id = "r8a7796",
+	  .revision = "ES1.0",
+	  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
+	},
+	{ .soc_id = "r8a7796",
+	  .revision = "ES1.1",
+	  .data = &sdhi_quirks_4tap_nohs400
+	},
+	{ .soc_id = "r8a7796",
+	  .revision = "ES1.2",
+	  .data = &sdhi_quirks_r8a7796_es12
+	},
+	{ .soc_id = "r8a7796",
+	  .revision = "ES1.3",
+	  .data = &sdhi_quirks_r8a7796_es13
+	},
+	{ /* Sentinel. */ },
+};
+
+static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
+				    struct tmio_sd_priv *priv,
+				    const struct renesas_sdhi_quirks *quirks)
+{
+	priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
+	priv->nrtaps = 8;
+
+	if (!quirks)
+		return;
+
+	if (quirks->hs400_disabled) {
+		plat->cfg.host_caps &= ~MMC_MODE_HS400;
+		if (quirks == &sdhi_quirks_4tap_nohs400_b17_dtrend)
+			priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
+	}
+
+	if (quirks->hs400_4taps)
+		priv->nrtaps = 4;
+
+	if (quirks->hs400_bad_taps)
+		priv->hs400_bad_tap = quirks->hs400_bad_taps;
+
+	if (quirks->hs400_calib_table) {
+		priv->adjust_hs400_enable = true;
+		priv->adjust_hs400_calib_table =
+			quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
+		if (quirks == &sdhi_quirks_r8a7796_es12)
+			priv->adjust_hs400_offset = 3;
+		else if (quirks == &sdhi_quirks_r8a7796_es13)
+			priv->adjust_hs400_offset = 0;
+	}
+}
+#endif
+
 static void renesas_sdhi_filter_caps(struct udevice *dev)
 {
 	struct tmio_sd_priv *priv = dev_get_priv(dev);
@@ -866,6 +976,13 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 	struct tmio_sd_plat *plat = dev_get_platdata(dev);
+	const struct soc_attr *attr;
+
+	attr = soc_device_match(sdhi_quirks_match);
+	if (attr) {
+		renesas_sdhi_add_quirks(plat, priv, attr->data);
+		return;
+	}
 
 	/* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
 	if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
-- 
2.17.1

[PATCH v7 3/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N

[Biju Das]

Add SDHI quirks for R-Car M3-N and RZ/G2N SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v7:
 * No Change.
v6: 
 * New patch. quirks using soc_device_match.
---
 drivers/mmc/renesas-sdhi.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 7e3ea92cbf..b84cfaa9a3 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -890,6 +890,11 @@ static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
 	.hs400_calib_table = r8a7796_rev3_calib_table,
 };
 
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
+	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+	.hs400_calib_table = r8a77965_calib_table,
+};
+
 /*
  * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
  * So, we want to treat them equally and only have a match for ES1.2 to enforce
@@ -912,6 +917,9 @@ static const struct soc_attr sdhi_quirks_match[]  = {
 	  .revision = "ES1.3",
 	  .data = &sdhi_quirks_r8a7796_es13
 	},
+	{ .soc_id = "r8a774b1",
+	  .data = &sdhi_quirks_r8a77965
+	},
 	{ .soc_id = "r8a7796",
 	  .revision = "ES1.0",
 	  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
@@ -928,6 +936,9 @@ static const struct soc_attr sdhi_quirks_match[]  = {
 	  .revision = "ES1.3",
 	  .data = &sdhi_quirks_r8a7796_es13
 	},
+	{ .soc_id = "r8a77965",
+	  .data = &sdhi_quirks_r8a77965
+	},
 	{ /* Sentinel. */ },
 };
 
@@ -957,7 +968,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
 		priv->adjust_hs400_enable = true;
 		priv->adjust_hs400_calib_table =
 			quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
-		if (quirks == &sdhi_quirks_r8a7796_es12)
+		if (quirks == &sdhi_quirks_r8a7796_es12 ||
+		    quirks == &sdhi_quirks_r8a77965)
 			priv->adjust_hs400_offset = 3;
 		else if (quirks == &sdhi_quirks_r8a7796_es13)
 			priv->adjust_hs400_offset = 0;
-- 
2.17.1

[PATCH v7 4/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H

[Biju Das]

Add SDHI quirks for R-Car H3 and RZ/G2H SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v7:
  * No Change.
v6:
  * New patch. quirks using soc_device_match.
---
 drivers/mmc/renesas-sdhi.c | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index b84cfaa9a3..09d8a2aa0a 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -879,6 +879,16 @@ static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
 	.hs400_4taps = true,
 };
 
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
+	.hs400_4taps = true,
+	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {
+	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+	.hs400_calib_table = r8a7795_calib_table,
+};
+
 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
 	.hs400_4taps = true,
 	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
@@ -920,6 +930,26 @@ static const struct soc_attr sdhi_quirks_match[]  = {
 	{ .soc_id = "r8a774b1",
 	  .data = &sdhi_quirks_r8a77965
 	},
+	{ .soc_id = "r8a774e1",
+	  .revision = "ES3.0",
+	  .data = &sdhi_quirks_r8a7795_es30
+	},
+	{ .soc_id = "r8a7795",
+	  .revision = "ES1.0",
+	  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
+	},
+	{ .soc_id = "r8a7795",
+	  .revision = "ES1.1",
+	  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
+	},
+	{ .soc_id = "r8a7795",
+	  .revision = "ES2.0",
+	  .data = &sdhi_quirks_4tap
+	},
+	{ .soc_id = "r8a7795",
+	  .revision = "ES3.0",
+	  .data = &sdhi_quirks_r8a7795_es30
+	},
 	{ .soc_id = "r8a7796",
 	  .revision = "ES1.0",
 	  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
@@ -971,7 +1001,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
 		if (quirks == &sdhi_quirks_r8a7796_es12 ||
 		    quirks == &sdhi_quirks_r8a77965)
 			priv->adjust_hs400_offset = 3;
-		else if (quirks == &sdhi_quirks_r8a7796_es13)
+		else if (quirks == &sdhi_quirks_r8a7796_es13 ||
+			 quirks == &sdhi_quirks_r8a7795_es30)
 			priv->adjust_hs400_offset = 0;
 	}
 }
-- 
2.17.1

[PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Marek Vasut]

On 11/27/20 3:52 PM, Biju Das wrote:

Sorry for the late reply.

[...]

> diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c
> index 5bde24ae0e..08345503a2 100644
> --- a/arch/arm/mach-rmobile/cpu_info-rcar.c
> +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
> @@ -6,6 +6,7 @@
>    */
>   #include <common.h>
>   #include <asm/io.h>
> +#include <soc.h>
>   
>   #define PRR_MASK		0x7fff
>   #define R8A7796_REV_1_0		0x5200
> @@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void)
>   #endif
>   }
>   
> +static bool is_rzg_family(void)
> +{
> +	bool rzg_family_type = false;
> +	struct udevice *soc;
> +	char name[16];
> +
> +	if (!(soc_get(&soc) || soc_get_family(soc, name, 16))) {

This depends on some other patchset, right ?
I will wait for that to land and then apply this one.

Did you check that this is still OK on RCar Gen2 with its size-limited SPL?

Also, do you have a git tree with all the remaining patches applied on 
top? It would be useful to get an overview what's still pending for 
mainline.

Thanks

> +		if (!strcmp(name, "RZ/G2"))
> +			rzg_family_type = true;
> +	}

[...]

[PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

Hi Marek,

Thanks for the reply.

> Subject: Re: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
> 
> On 11/27/20 3:52 PM, Biju Das wrote:
> 
> Sorry for the late reply.
> 
> [...]
> 
> > diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c
> > b/arch/arm/mach-rmobile/cpu_info-rcar.c
> > index 5bde24ae0e..08345503a2 100644
> > --- a/arch/arm/mach-rmobile/cpu_info-rcar.c
> > +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
> > @@ -6,6 +6,7 @@
> >    */
> >   #include <common.h>
> >   #include <asm/io.h>
> > +#include <soc.h>
> >
> >   #define PRR_MASK		0x7fff
> >   #define R8A7796_REV_1_0		0x5200
> > @@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void)
> >   #endif
> >   }
> >
> > +static bool is_rzg_family(void)
> > +{
> > +	bool rzg_family_type = false;
> > +	struct udevice *soc;
> > +	char name[16];
> > +
> > +	if (!(soc_get(&soc) || soc_get_family(soc, name, 16))) {
> 
> This depends on some other patchset, right ?
> I will wait for that to land and then apply this one.

Yes, Simon have reviewed this patches and not sure who needs to pick this up. So I have sent a gentle remainder for picking this patches [1]
[1] http://u-boot.10912.n7.nabble.com/PATCH-v4-0-4-Add-Renesas-SoC-identification-driver-support-tt432936.html

> 
> Did you check that this is still OK on RCar Gen2 with its size-limited
> SPL?

Unfortunately I do not have access currently to RCar Gen2 boards. 

Shall we enable "is_rzg_family" as a weekfunction and override it for RCar Gen3? or it will be grateful, please could you test this on RCar Gen2 boards, if you have any?

Please let us know.


> Also, do you have a git tree with all the remaining patches applied on
> top? It would be useful to get an overview what's still pending for
> mainline.

We have an internal private u-boot repository, where we run mainline u-boot CI job as part of patch submission.

Regarding status wise, all the patches required for boot RZ/G2[HMN] boards are submitted to mainline and is in review state.

For RZ/G2E, some patches are pending because of the dependency with RZ/G2[HMN]. We created a public repo[1] to get an overview what is still pending for  mainline.

[1] https://github.com/prabhakarlad/u-boot-rzg2

Regards,
Biju

> 
> Thanks
> 
> > +		if (!strcmp(name, "RZ/G2"))
> > +			rzg_family_type = true;
> > +	}
> 
> [...]

[PATCH v7 2/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M

[Jaehoon Chung]

On 11/27/20 11:52 PM, Biju Das wrote:
> Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Jaehoon chung <jh80.chung@samsung.com>

Best Regards,
Jaehoon Chung

> ---
> v7:
>  * Incorporated Jaehoon Chung's review comments.
>  * Fixed the build error on Renesas ARM32 platforms.
> v6:
>  * New patch. quirks using soc_device_match.
> ---
>  drivers/mmc/renesas-sdhi.c | 117 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 117 insertions(+)
> 
> diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> index d80b3fc28f..7e3ea92cbf 100644
> --- a/drivers/mmc/renesas-sdhi.c
> +++ b/drivers/mmc/renesas-sdhi.c
> @@ -19,6 +19,7 @@
>  #include <linux/io.h>
>  #include <linux/sizes.h>
>  #include <power/regulator.h>
> +#include <soc.h>
>  #include <asm/unaligned.h>
>  #include "tmio-common.h"
>  
> @@ -855,6 +856,115 @@ static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
>  	return clk_get_rate(&priv->clk);
>  }
>  
> +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
> +    CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
> +    CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
> +
> +#define SDHI_CALIB_TABLE_MAX 32
> +
> +struct renesas_sdhi_quirks {
> +	bool hs400_disabled;
> +	bool hs400_4taps;
> +	u32 hs400_bad_taps;
> +	const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_b17_dtrend = {
> +	.hs400_disabled = true,
> +	.hs400_4taps = true,
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
> +	.hs400_disabled = true,
> +	.hs400_4taps = true,
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
> +	.hs400_4taps = true,
> +	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> +	.hs400_calib_table = r8a7796_rev1_calib_table,
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
> +	.hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
> +	.hs400_calib_table = r8a7796_rev3_calib_table,
> +};
> +
> +/*
> + * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
> + * So, we want to treat them equally and only have a match for ES1.2 to enforce
> + * this if there ever will be a way to distinguish ES1.2.
> + */
> +static const struct soc_attr sdhi_quirks_match[]  = {
> +	{ .soc_id = "r8a774a1",
> +	  .revision = "ES1.0",
> +	  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> +	},
> +	{ .soc_id = "r8a774a1",
> +	  .revision = "ES1.1",
> +	  .data = &sdhi_quirks_4tap_nohs400
> +	},
> +	{ .soc_id = "r8a774a1",
> +	  .revision = "ES1.2",
> +	  .data = &sdhi_quirks_r8a7796_es12
> +	},
> +	{ .soc_id = "r8a774a1",
> +	  .revision = "ES1.3",
> +	  .data = &sdhi_quirks_r8a7796_es13
> +	},
> +	{ .soc_id = "r8a7796",
> +	  .revision = "ES1.0",
> +	  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> +	},
> +	{ .soc_id = "r8a7796",
> +	  .revision = "ES1.1",
> +	  .data = &sdhi_quirks_4tap_nohs400
> +	},
> +	{ .soc_id = "r8a7796",
> +	  .revision = "ES1.2",
> +	  .data = &sdhi_quirks_r8a7796_es12
> +	},
> +	{ .soc_id = "r8a7796",
> +	  .revision = "ES1.3",
> +	  .data = &sdhi_quirks_r8a7796_es13
> +	},
> +	{ /* Sentinel. */ },
> +};
> +
> +static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
> +				    struct tmio_sd_priv *priv,
> +				    const struct renesas_sdhi_quirks *quirks)
> +{
> +	priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
> +	priv->nrtaps = 8;
> +
> +	if (!quirks)
> +		return;
> +
> +	if (quirks->hs400_disabled) {
> +		plat->cfg.host_caps &= ~MMC_MODE_HS400;
> +		if (quirks == &sdhi_quirks_4tap_nohs400_b17_dtrend)
> +			priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
> +	}
> +
> +	if (quirks->hs400_4taps)
> +		priv->nrtaps = 4;
> +
> +	if (quirks->hs400_bad_taps)
> +		priv->hs400_bad_tap = quirks->hs400_bad_taps;
> +
> +	if (quirks->hs400_calib_table) {
> +		priv->adjust_hs400_enable = true;
> +		priv->adjust_hs400_calib_table =
> +			quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
> +		if (quirks == &sdhi_quirks_r8a7796_es12)
> +			priv->adjust_hs400_offset = 3;
> +		else if (quirks == &sdhi_quirks_r8a7796_es13)
> +			priv->adjust_hs400_offset = 0;
> +	}
> +}
> +#endif
> +
>  static void renesas_sdhi_filter_caps(struct udevice *dev)
>  {
>  	struct tmio_sd_priv *priv = dev_get_priv(dev);
> @@ -866,6 +976,13 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
>      CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
>      CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
>  	struct tmio_sd_plat *plat = dev_get_platdata(dev);
> +	const struct soc_attr *attr;
> +
> +	attr = soc_device_match(sdhi_quirks_match);
> +	if (attr) {
> +		renesas_sdhi_add_quirks(plat, priv, attr->data);
> +		return;
> +	}
>  
>  	/* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
>  	if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
> 

[PATCH v7 3/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N

[Jaehoon Chung]

On 11/27/20 11:52 PM, Biju Das wrote:
> Add SDHI quirks for R-Car M3-N and RZ/G2N SoC.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Jaehoon chung <jh80.chung@samsung.com>

Best Regards,
Jaehoon Chung

> ---
> v7:
>  * No Change.
> v6: 
>  * New patch. quirks using soc_device_match.
> ---
>  drivers/mmc/renesas-sdhi.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> index 7e3ea92cbf..b84cfaa9a3 100644
> --- a/drivers/mmc/renesas-sdhi.c
> +++ b/drivers/mmc/renesas-sdhi.c
> @@ -890,6 +890,11 @@ static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
>  	.hs400_calib_table = r8a7796_rev3_calib_table,
>  };
>  
> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
> +	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> +	.hs400_calib_table = r8a77965_calib_table,
> +};
> +
>  /*
>   * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
>   * So, we want to treat them equally and only have a match for ES1.2 to enforce
> @@ -912,6 +917,9 @@ static const struct soc_attr sdhi_quirks_match[]  = {
>  	  .revision = "ES1.3",
>  	  .data = &sdhi_quirks_r8a7796_es13
>  	},
> +	{ .soc_id = "r8a774b1",
> +	  .data = &sdhi_quirks_r8a77965
> +	},
>  	{ .soc_id = "r8a7796",
>  	  .revision = "ES1.0",
>  	  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> @@ -928,6 +936,9 @@ static const struct soc_attr sdhi_quirks_match[]  = {
>  	  .revision = "ES1.3",
>  	  .data = &sdhi_quirks_r8a7796_es13
>  	},
> +	{ .soc_id = "r8a77965",
> +	  .data = &sdhi_quirks_r8a77965
> +	},
>  	{ /* Sentinel. */ },
>  };
>  
> @@ -957,7 +968,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
>  		priv->adjust_hs400_enable = true;
>  		priv->adjust_hs400_calib_table =
>  			quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
> -		if (quirks == &sdhi_quirks_r8a7796_es12)
> +		if (quirks == &sdhi_quirks_r8a7796_es12 ||
> +		    quirks == &sdhi_quirks_r8a77965)
>  			priv->adjust_hs400_offset = 3;
>  		else if (quirks == &sdhi_quirks_r8a7796_es13)
>  			priv->adjust_hs400_offset = 0;
> 

[PATCH v7 4/4] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H

[Jaehoon Chung]

On 11/27/20 11:53 PM, Biju Das wrote:
> Add SDHI quirks for R-Car H3 and RZ/G2H SoC.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Jaehoon chung <jh80.chung@samsung.com>

Best Regards,
Jaehoon Chung

> ---
> v7:
>   * No Change.
> v6:
>   * New patch. quirks using soc_device_match.
> ---
>  drivers/mmc/renesas-sdhi.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> index b84cfaa9a3..09d8a2aa0a 100644
> --- a/drivers/mmc/renesas-sdhi.c
> +++ b/drivers/mmc/renesas-sdhi.c
> @@ -879,6 +879,16 @@ static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
>  	.hs400_4taps = true,
>  };
>  
> +static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
> +	.hs400_4taps = true,
> +	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {
> +	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> +	.hs400_calib_table = r8a7795_calib_table,
> +};
> +
>  static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
>  	.hs400_4taps = true,
>  	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> @@ -920,6 +930,26 @@ static const struct soc_attr sdhi_quirks_match[]  = {
>  	{ .soc_id = "r8a774b1",
>  	  .data = &sdhi_quirks_r8a77965
>  	},
> +	{ .soc_id = "r8a774e1",
> +	  .revision = "ES3.0",
> +	  .data = &sdhi_quirks_r8a7795_es30
> +	},
> +	{ .soc_id = "r8a7795",
> +	  .revision = "ES1.0",
> +	  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> +	},
> +	{ .soc_id = "r8a7795",
> +	  .revision = "ES1.1",
> +	  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> +	},
> +	{ .soc_id = "r8a7795",
> +	  .revision = "ES2.0",
> +	  .data = &sdhi_quirks_4tap
> +	},
> +	{ .soc_id = "r8a7795",
> +	  .revision = "ES3.0",
> +	  .data = &sdhi_quirks_r8a7795_es30
> +	},
>  	{ .soc_id = "r8a7796",
>  	  .revision = "ES1.0",
>  	  .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> @@ -971,7 +1001,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
>  		if (quirks == &sdhi_quirks_r8a7796_es12 ||
>  		    quirks == &sdhi_quirks_r8a77965)
>  			priv->adjust_hs400_offset = 3;
> -		else if (quirks == &sdhi_quirks_r8a7796_es13)
> +		else if (quirks == &sdhi_quirks_r8a7796_es13 ||
> +			 quirks == &sdhi_quirks_r8a7795_es30)
>  			priv->adjust_hs400_offset = 0;
>  	}
>  }
> 

[PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

Hi,

> Subject: RE: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
> 
> >
> > > diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > b/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > index 5bde24ae0e..08345503a2 100644
> > > --- a/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > @@ -6,6 +6,7 @@
> > >    */
> > >   #include <common.h>
> > >   #include <asm/io.h>
> > > +#include <soc.h>
> > >
> > >   #define PRR_MASK		0x7fff
> > >   #define R8A7796_REV_1_0		0x5200
> > > @@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void)
> > >   #endif
> > >   }
> > >
> > > +static bool is_rzg_family(void)
> > > +{
> > > +	bool rzg_family_type = false;
> > > +	struct udevice *soc;
> > > +	char name[16];
> > > +
> > > +	if (!(soc_get(&soc) || soc_get_family(soc, name, 16))) {
> >
> > This depends on some other patchset, right ?
> > I will wait for that to land and then apply this one.
> 
> Yes, Simon have reviewed this patches and not sure who needs to pick this
> up. So I have sent a gentle remainder for picking this patches [1] [1]
> http://u-boot.10912.n7.nabble.com/PATCH-v4-0-4-Add-Renesas-SoC-
> identification-driver-support-tt432936.html
> 
> >
> > Did you check that this is still OK on RCar Gen2 with its size-limited
> > SPL?
> 
> Unfortunately I do not have access currently to RCar Gen2 boards.
> 

Because of lock down, Still I don't have access to R-Car Gen2 boards.

As you said, R-Car Gen2 SPL has constraint on image size,
Can we make a decision, we won't enable SoC identification driver on R-Car Gen2 SPL?

Regards,
Biju

[PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support

[Biju Das]

Hi Marek,

> -----Original Message-----
> From: Biju Das
> Sent: 15 January 2021 10:02
> To: Marek Vasut <marek.vasut@gmail.com>; Nobuhiro Iwamatsu
> <iwamatsu@nigauri.org>
> Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; u-
> boot at lists.denx.de; Chris Paterson <Chris.Paterson2@renesas.com>; Simon
> Glass <sjg@chromium.org>; Tom Rini <trini@konsulko.com>
> Subject: RE: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
> 
> Hi,
> 
> > Subject: RE: [PATCH v7 1/4] arm: rmobile: Add RZ/G2[HMNE] SoC support
> >
> > >
> > > > diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > > b/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > > index 5bde24ae0e..08345503a2 100644
> > > > --- a/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > > +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
> > > > @@ -6,6 +6,7 @@
> > > >    */
> > > >   #include <common.h>
> > > >   #include <asm/io.h>
> > > > +#include <soc.h>
> > > >
> > > >   #define PRR_MASK		0x7fff
> > > >   #define R8A7796_REV_1_0		0x5200
> > > > @@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void)
> > > >   #endif
> > > >   }
> > > >
> > > > +static bool is_rzg_family(void)
> > > > +{
> > > > +	bool rzg_family_type = false;
> > > > +	struct udevice *soc;
> > > > +	char name[16];
> > > > +
> > > > +	if (!(soc_get(&soc) || soc_get_family(soc, name, 16))) {
> > >
> > > This depends on some other patchset, right ?
> > > I will wait for that to land and then apply this one.
> >
> > Yes, Simon have reviewed this patches and not sure who needs to pick
> > this up. So I have sent a gentle remainder for picking this patches
> > [1] [1]
> > http://u-boot.10912.n7.nabble.com/PATCH-v4-0-4-Add-Renesas-SoC-
> > identification-driver-support-tt432936.html
> >
> > >
> > > Did you check that this is still OK on RCar Gen2 with its
> > > size-limited SPL?

Good catch. I have built spl image for koelsch and I see there is a change in 
Size of SPL with and without soc identification driver + SoC uclass driver included

With SoC identification driver +  SoC uclass driver included
-----------------------------------------------------------

$ ls -al spl/u-boot-spl.bin 
    -rwxr-xr-x 1 biju biju 13996 Jan 16 14:16 spl/u-boot-spl.bin
$ size spl/u-boot-spl
       text	   data	    bss	    dec	    hex	filename
      13789	    204	   1100	  15093	   3af5	spl/u-boot-spl

Without SoC identification driver + SoC uclass driver
-----------------------------------------------------
$ ls -al spl/u-boot-spl.bin 
      -rwxr-xr-x 1 biju biju 13916 Jan 16 14:19 spl/u-boot-spl.bin
size spl/u-boot-spl
         text	   data	    bss	    dec	    hex	filename
        13785	    128	   1100	  15013	   3aa5	spl/u-boot-spl

I will post V5 with Renesas soc identification driver disabled for SPL builds along with SoC uclass driver.

Regards,
Biju