* [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support
@ 2020-11-02 16:16 Biju Das
2020-11-02 16:16 ` [PATCH v6 1/7] arm: rmobile: Add RZ/G2[HMNE] SoC support Biju Das
` (7 more replies)
0 siblings, 8 replies; 16+ messages in thread
From: Biju Das @ 2020-11-02 16:16 UTC (permalink / raw)
To: u-boot
This patch series adds the required SoC/Board support to boot HopeRun
HiHope RZ/G2[HMN] boards.
It uses SoC driver for unique cpu identification for RZ/G and R-Car SoC's,
since they share same PRR ID.
SDHI quirks added using soc_device_match api.
This patch series depend upon [1]
[1] https://lists.denx.de/pipermail/u-boot/2020-November/431539.html
Note:
1) This patch series tested on RZ/G2[HMN] boards.
2) SOC_DEVICE_RENESAS option enabled only RZ/G2[HMN] boards. After testing
this needs to be enabled for other boards.
Biju Das (7):
arm: rmobile: Add RZ/G2[HMNE] SoC support
mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
arm: rmobile: Add HopeRun HiHope RZ/G2M board support
mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N
arm: rmobile: Add HopeRun HiHope RZ/G2N board support
mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H
arm: rmobile: Add HopeRun HiHope RZ/G2H board support
arch/arm/dts/Makefile | 3 +
arch/arm/dts/hihope-common.dtsi | 377 ++++++++++++++++++
arch/arm/dts/hihope-rev4.dtsi | 124 ++++++
arch/arm/dts/hihope-rzg2-ex.dtsi | 92 +++++
arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts | 21 +
arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts | 27 ++
arch/arm/dts/r8a774a1-hihope-rzg2m.dts | 37 ++
arch/arm/dts/r8a774a1-u-boot.dtsi | 55 +++
arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts | 16 +
arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts | 27 ++
arch/arm/dts/r8a774b1-hihope-rzg2n.dts | 41 ++
arch/arm/dts/r8a774b1-u-boot.dtsi | 53 +++
arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts | 15 +
arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts | 27 ++
arch/arm/dts/r8a774e1-hihope-rzg2h.dts | 26 ++
arch/arm/dts/r8a774e1-u-boot.dtsi | 25 ++
arch/arm/mach-rmobile/Kconfig.64 | 16 +
arch/arm/mach-rmobile/cpu_info-rcar.c | 22 +-
arch/arm/mach-rmobile/cpu_info.c | 10 +-
arch/arm/mach-rmobile/include/mach/rmobile.h | 60 ++-
board/hoperun/hihope-rzg2/Kconfig | 15 +
board/hoperun/hihope-rzg2/MAINTAINERS | 6 +
board/hoperun/hihope-rzg2/Makefile | 9 +
board/hoperun/hihope-rzg2/hihope-rzg2.c | 99 +++++
configs/hihope_rzg2_defconfig | 77 ++++
drivers/mmc/renesas-sdhi.c | 157 ++++++++
include/configs/hihope-rzg2.h | 20 +
27 files changed, 1438 insertions(+), 19 deletions(-)
create mode 100644 arch/arm/dts/hihope-common.dtsi
create mode 100644 arch/arm/dts/hihope-rev4.dtsi
create mode 100644 arch/arm/dts/hihope-rzg2-ex.dtsi
create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts
create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m.dts
create mode 100644 arch/arm/dts/r8a774a1-u-boot.dtsi
create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n.dts
create mode 100644 arch/arm/dts/r8a774b1-u-boot.dtsi
create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h.dts
create mode 100644 arch/arm/dts/r8a774e1-u-boot.dtsi
create mode 100644 board/hoperun/hihope-rzg2/Kconfig
create mode 100644 board/hoperun/hihope-rzg2/MAINTAINERS
create mode 100644 board/hoperun/hihope-rzg2/Makefile
create mode 100644 board/hoperun/hihope-rzg2/hihope-rzg2.c
create mode 100644 configs/hihope_rzg2_defconfig
create mode 100644 include/configs/hihope-rzg2.h
--
2.17.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 1/7] arm: rmobile: Add RZ/G2[HMNE] SoC support
2020-11-02 16:16 [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support Biju Das
@ 2020-11-02 16:16 ` Biju Das
2020-11-02 16:16 ` [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M Biju Das
` (6 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Biju Das @ 2020-11-02 16:16 UTC (permalink / raw)
To: u-boot
RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some
automotive peripherals.
RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951).
RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960).
RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965).
RZ/G2E (R8A774C0) = R-Car E3 (R8A77990).
As the devices are the same they also have the same SoC PRR
register values. SoC driver is used to distinguish the
cpu type based on the family.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v5->v6
* Optimized the unique CPU identification method by using Renesas SoC identification driver.
v4->v5
* Add support for unique identification of RZ/G2 CPU types
(Ref: https://patchwork.ozlabs.org/project/uboot/patch/20201008085941.3600-1-biju.das.jz at bp.renesas.com/)
v3->v4
* Dropped CPU info reporting logic for RZ/G2. Will address this later.
* Added PRRID's for RZG2[HMNE]
(Ref: https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-1-biju.das.jz at bp.renesas.com/)
v2->v3
* Reworked as per Marek's suggestion
* Added rzg2_get_cpu_type function to get cpu_type by matching TFA compatible string
* Removed SoC family type Enum
(Ref: https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-2-biju.das.jz at bp.renesas.com/)
v1->v2:
* Add comment's related to loop logic
(ref: https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-1-biju.das.jz at bp.renesas.com/)
v1:
* New patch
(ref:https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-4-biju.das.jz at bp.renesas.com/
---
arch/arm/mach-rmobile/cpu_info-rcar.c | 22 ++++++-
arch/arm/mach-rmobile/cpu_info.c | 10 +++-
arch/arm/mach-rmobile/include/mach/rmobile.h | 60 +++++++++++++++-----
3 files changed, 73 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c
index 5bde24ae0e..08345503a2 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
#include <asm/io.h>
+#include <soc.h>
#define PRR_MASK 0x7fff
#define R8A7796_REV_1_0 0x5200
@@ -21,9 +22,28 @@ static u32 rmobile_get_prr(void)
#endif
}
+static bool is_rzg_family(void)
+{
+ bool rzg_family_type = false;
+ struct udevice *soc;
+ char name[16];
+
+ if (!(soc_get(&soc) || soc_get_family(soc, name, 16))) {
+ if (!strcmp(name, "RZ/G2"))
+ rzg_family_type = true;
+ }
+
+ return rzg_family_type;
+}
+
u32 rmobile_get_cpu_type(void)
{
- return (rmobile_get_prr() & 0x00007F00) >> 8;
+ u32 soc_id = (rmobile_get_prr() & 0x7F00) >> 8;
+
+ if (is_rzg_family())
+ soc_id |= RZG_CPU_MASK;
+
+ return soc_id;
}
u32 rmobile_get_cpu_rev_integer(void)
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index fdbbd72e28..b19b7e3044 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -3,12 +3,12 @@
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*/
-#include <common.h>
-#include <cpu_func.h>
#include <asm/cache.h>
-#include <init.h>
#include <asm/io.h>
+#include <common.h>
+#include <cpu_func.h>
#include <env.h>
+#include <init.h>
#include <linux/ctype.h>
#ifdef CONFIG_ARCH_CPU_INIT
@@ -59,6 +59,10 @@ static const struct {
} rmobile_cpuinfo[] = {
{ RMOBILE_CPU_TYPE_SH73A0, "SH73A0" },
{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
+ { RMOBILE_CPU_TYPE_R8A774A1, "R8A774A1" },
+ { RMOBILE_CPU_TYPE_R8A774B1, "R8A774B1" },
+ { RMOBILE_CPU_TYPE_R8A774C0, "R8A774C0" },
+ { RMOBILE_CPU_TYPE_R8A774E1, "R8A774E1" },
{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },
{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index a50249dc96..da099fa4c3 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -24,21 +24,51 @@
#endif
#endif /* CONFIG_ARCH_RMOBILE */
-/* PRR CPU IDs */
-#define RMOBILE_CPU_TYPE_SH73A0 0x37
-#define RMOBILE_CPU_TYPE_R8A7740 0x40
-#define RMOBILE_CPU_TYPE_R8A7790 0x45
-#define RMOBILE_CPU_TYPE_R8A7791 0x47
-#define RMOBILE_CPU_TYPE_R8A7792 0x4A
-#define RMOBILE_CPU_TYPE_R8A7793 0x4B
-#define RMOBILE_CPU_TYPE_R8A7794 0x4C
-#define RMOBILE_CPU_TYPE_R8A7795 0x4F
-#define RMOBILE_CPU_TYPE_R8A7796 0x52
-#define RMOBILE_CPU_TYPE_R8A77965 0x55
-#define RMOBILE_CPU_TYPE_R8A77970 0x54
-#define RMOBILE_CPU_TYPE_R8A77980 0x56
-#define RMOBILE_CPU_TYPE_R8A77990 0x57
-#define RMOBILE_CPU_TYPE_R8A77995 0x58
+/* PRR IDs */
+#define SOC_ID_SH73A0 0x37
+#define SOC_ID_R8A7740 0x40
+#define SOC_ID_R8A774A1 0x52
+#define SOC_ID_R8A774B1 0x55
+#define SOC_ID_R8A774C0 0x57
+#define SOC_ID_R8A774E1 0x4F
+#define SOC_ID_R8A7790 0x45
+#define SOC_ID_R8A7791 0x47
+#define SOC_ID_R8A7792 0x4A
+#define SOC_ID_R8A7793 0x4B
+#define SOC_ID_R8A7794 0x4C
+#define SOC_ID_R8A7795 0x4F
+#define SOC_ID_R8A7796 0x52
+#define SOC_ID_R8A77965 0x55
+#define SOC_ID_R8A77970 0x54
+#define SOC_ID_R8A77980 0x56
+#define SOC_ID_R8A77990 0x57
+#define SOC_ID_R8A77995 0x58
+
+/* CPU IDs */
+#define RMOBILE_CPU_TYPE_SH73A0 SOC_ID_SH73A0
+#define RMOBILE_CPU_TYPE_R8A7740 SOC_ID_R8A7740
+#define RMOBILE_CPU_TYPE_R8A774A1 (SOC_ID_R8A774A1 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A774B1 (SOC_ID_R8A774B1 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A774C0 (SOC_ID_R8A774C0 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A774E1 (SOC_ID_R8A774E1 | RZG_CPU_MASK)
+#define RMOBILE_CPU_TYPE_R8A7790 SOC_ID_R8A7790
+#define RMOBILE_CPU_TYPE_R8A7791 SOC_ID_R8A7791
+#define RMOBILE_CPU_TYPE_R8A7792 SOC_ID_R8A7792
+#define RMOBILE_CPU_TYPE_R8A7793 SOC_ID_R8A7793
+#define RMOBILE_CPU_TYPE_R8A7794 SOC_ID_R8A7794
+#define RMOBILE_CPU_TYPE_R8A7795 SOC_ID_R8A7795
+#define RMOBILE_CPU_TYPE_R8A7796 SOC_ID_R8A7796
+#define RMOBILE_CPU_TYPE_R8A77965 SOC_ID_R8A77965
+#define RMOBILE_CPU_TYPE_R8A77970 SOC_ID_R8A77970
+#define RMOBILE_CPU_TYPE_R8A77980 SOC_ID_R8A77980
+#define RMOBILE_CPU_TYPE_R8A77990 SOC_ID_R8A77990
+#define RMOBILE_CPU_TYPE_R8A77995 SOC_ID_R8A77995
+
+/*
+ * R-Car and RZ/G SoC's share same PRR ID's for the same SoC type. The
+ * RZG_CPU_MASK is used to provide a unique CPU identification for RZ/G SoC's.
+ */
+#define RZG_CPU_MASK 0x1000
#ifndef __ASSEMBLY__
u32 rmobile_get_cpu_type(void);
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
2020-11-02 16:16 [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support Biju Das
2020-11-02 16:16 ` [PATCH v6 1/7] arm: rmobile: Add RZ/G2[HMNE] SoC support Biju Das
@ 2020-11-02 16:16 ` Biju Das
2020-11-02 17:24 ` Biju Das
2020-11-02 21:41 ` Jaehoon Chung
2020-11-02 16:16 ` [PATCH v6 3/7] arm: rmobile: Add HopeRun HiHope RZ/G2M board support Biju Das
` (5 subsequent siblings)
7 siblings, 2 replies; 16+ messages in thread
From: Biju Das @ 2020-11-02 16:16 UTC (permalink / raw)
To: u-boot
Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v5->v6: Used soc_device_match api to add quirks.
v5 : New Patch
(Ref: https://patchwork.ozlabs.org/project/uboot/patch/20201008085941.3600-2-biju.das.jz at bp.renesas.com/)
---
drivers/mmc/renesas-sdhi.c | 110 +++++++++++++++++++++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index d80b3fc28f..39deeb94d8 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -19,6 +19,7 @@
#include <linux/io.h>
#include <linux/sizes.h>
#include <power/regulator.h>
+#include <soc.h>
#include <asm/unaligned.h>
#include "tmio-common.h"
@@ -105,6 +106,15 @@ static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
};
+#define SDHI_CALIB_TABLE_MAX 32
+
+struct renesas_sdhi_quirks {
+ bool hs400_disabled;
+ bool hs400_4taps;
+ u32 hs400_bad_taps;
+ const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
+};
+
static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
{
/* On R-Car Gen3, MMC0 is at 0xee140000 */
@@ -855,6 +865,99 @@ static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
return clk_get_rate(&priv->clk);
}
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_b17_dtrend = {
+ .hs400_disabled = true,
+ .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
+ .hs400_disabled = true,
+ .hs400_4taps = true,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
+ .hs400_4taps = true,
+ .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+ .hs400_calib_table = r8a7796_rev1_calib_table,
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
+ .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
+ .hs400_calib_table = r8a7796_rev3_calib_table,
+};
+
+/*
+ * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
+ * So, we want to treat them equally and only have a match for ES1.2 to enforce
+ * this if there ever will be a way to distinguish ES1.2.
+ */
+static const struct soc_attr sdhi_quirks_match[] = {
+ { .soc_id = "r8a774a1",
+ .revision = "ES1.0",
+ .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
+ },
+ { .soc_id = "r8a774a1",
+ .revision = "ES1.1",
+ .data = &sdhi_quirks_4tap_nohs400
+ },
+ { .soc_id = "r8a774a1",
+ .revision = "ES1.2",
+ .data = &sdhi_quirks_r8a7796_es12
+ },
+ { .soc_id = "r8a774a1",
+ .revision = "ES1.3",
+ .data = &sdhi_quirks_r8a7796_es13
+ },
+ { .soc_id = "r8a7796",
+ .revision = "ES1.0",
+ .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
+ },
+ { .soc_id = "r8a7796",
+ .revision = "ES1.1",
+ .data = &sdhi_quirks_4tap_nohs400
+ },
+ { .soc_id = "r8a7796",
+ .revision = "ES1.2",
+ .data = &sdhi_quirks_r8a7796_es12
+ },
+ { .soc_id = "r8a7796",
+ .revision = "ES1.3",
+ .data = &sdhi_quirks_r8a7796_es13
+ },
+ { /* Sentinel. */ },
+};
+
+static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
+ struct tmio_sd_priv *priv,
+ const struct renesas_sdhi_quirks *quirks)
+{
+ priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
+
+ if (quirks && quirks->hs400_disabled) {
+ plat->cfg.host_caps &= ~MMC_MODE_HS400;
+ if (quirks == &sdhi_quirks_4tap_nohs400_b17_dtrend)
+ priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
+ }
+
+ if (quirks && quirks->hs400_4taps)
+ priv->nrtaps = 4;
+ else
+ priv->nrtaps = 8;
+
+ if (quirks && quirks->hs400_bad_taps)
+ priv->hs400_bad_tap = quirks->hs400_bad_taps;
+
+ if (quirks && quirks->hs400_calib_table) {
+ priv->adjust_hs400_enable = true;
+ priv->adjust_hs400_calib_table =
+ quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
+ if (quirks == &sdhi_quirks_r8a7796_es12)
+ priv->adjust_hs400_offset = 3;
+ else if (quirks == &sdhi_quirks_r8a7796_es13)
+ priv->adjust_hs400_offset = 0;
+ }
+}
+
static void renesas_sdhi_filter_caps(struct udevice *dev)
{
struct tmio_sd_priv *priv = dev_get_priv(dev);
@@ -866,6 +969,13 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
struct tmio_sd_plat *plat = dev_get_platdata(dev);
+ const struct soc_attr *attr;
+
+ attr = soc_device_match(sdhi_quirks_match);
+ if (attr) {
+ renesas_sdhi_add_quirks(plat, priv, attr->data);
+ return;
+ }
/* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 3/7] arm: rmobile: Add HopeRun HiHope RZ/G2M board support
2020-11-02 16:16 [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support Biju Das
2020-11-02 16:16 ` [PATCH v6 1/7] arm: rmobile: Add RZ/G2[HMNE] SoC support Biju Das
2020-11-02 16:16 ` [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M Biju Das
@ 2020-11-02 16:16 ` Biju Das
2020-11-02 16:16 ` [PATCH v6 4/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N Biju Das
` (4 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Biju Das @ 2020-11-02 16:16 UTC (permalink / raw)
To: u-boot
The HiHope RZ/G2M board from HopeRun consists of main board
(HopeRun HiHope RZ/G2M main board) and sub board(HopeRun
HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits
below the HiHope RZ/G2M main board.
DTS files apart from r8a774a1-hihope-rzg2m-u-boot.dts and
r8a774a1-u-boot.dtsi have been imported from linux 5.9 commit
bbf5c979011a ("Linux 5.9").
This patch adds the required board support to boot HopeRun HiHope
RZ/G2M board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v5->v6
* Rebased to U-boot-sh/master
* Changed the logic for USB0 channel0 Host support.
* Enabled CONFIG_SOC_DEVICE_RENESAS option
V4->V5
* Rebased to U-boot-sh/next
(Ref: https://patchwork.ozlabs.org/project/uboot/patch/20201012151616.5384-4-biju.das.jz at bp.renesas.com/)
V3->V4
* Added USB0 channel0 Host support
(Ref: https://patchwork.ozlabs.org/project/uboot/patch/20201001103658.4835-2-biju.das.jz at bp.renesas.com/)
V2->V3
* Reworked as per Marek's suggestion
* Added rzg2_get_cpu_type function to get cpu_type by matching TFA compatible string
* Removed SoC family type Enum
Ref: https://patchwork.ozlabs.org/project/uboot/patch/20200922160317.16296-3-biju.das.jz at bp.renesas.com/
V1->V2
* Fixed indentation for R8A774A1 config
* Used GPIO hog for setting WLAN/BT REG ON
* Removed USB related initialization
Ref: https://patchwork.ozlabs.org/project/uboot/patch/20200918160307.14323-2-biju.das.jz at bp.renesas.com/
V1:-
* New Patch
Ref: https://patchwork.ozlabs.org/project/uboot/patch/20200915143630.7678-5-biju.das.jz at bp.renesas.com/
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/hihope-common.dtsi | 377 ++++++++++++++++++
arch/arm/dts/hihope-rev4.dtsi | 124 ++++++
arch/arm/dts/hihope-rzg2-ex.dtsi | 92 +++++
arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts | 21 +
arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts | 27 ++
arch/arm/dts/r8a774a1-hihope-rzg2m.dts | 37 ++
arch/arm/dts/r8a774a1-u-boot.dtsi | 55 +++
arch/arm/mach-rmobile/Kconfig.64 | 14 +
board/hoperun/hihope-rzg2/Kconfig | 15 +
board/hoperun/hihope-rzg2/MAINTAINERS | 6 +
board/hoperun/hihope-rzg2/Makefile | 9 +
board/hoperun/hihope-rzg2/hihope-rzg2.c | 91 +++++
configs/hihope_rzg2_defconfig | 77 ++++
include/configs/hihope-rzg2.h | 20 +
15 files changed, 966 insertions(+)
create mode 100644 arch/arm/dts/hihope-common.dtsi
create mode 100644 arch/arm/dts/hihope-rev4.dtsi
create mode 100644 arch/arm/dts/hihope-rzg2-ex.dtsi
create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts
create mode 100644 arch/arm/dts/r8a774a1-hihope-rzg2m.dts
create mode 100644 arch/arm/dts/r8a774a1-u-boot.dtsi
create mode 100644 board/hoperun/hihope-rzg2/Kconfig
create mode 100644 board/hoperun/hihope-rzg2/MAINTAINERS
create mode 100644 board/hoperun/hihope-rzg2/Makefile
create mode 100644 board/hoperun/hihope-rzg2/hihope-rzg2.c
create mode 100644 configs/hihope_rzg2_defconfig
create mode 100644 include/configs/hihope-rzg2.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5362b73441..ba46785078 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -792,6 +792,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \
dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
+ r8a774a1-hihope-rzg2m-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/dts/hihope-common.dtsi b/arch/arm/dts/hihope-common.dtsi
new file mode 100644
index 0000000000..51eb74fbe9
--- /dev/null
+++ b/arch/arm/dts/hihope-common.dtsi
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
+ * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ serial0 = &scif2;
+ serial1 = &hscif0;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi0-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi0_con: endpoint {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ led2 {
+ gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ led3 {
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ led4 {
+ gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_1p8v: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sound_card: sound {
+ compatible = "audio-graph-card";
+
+ label = "rcar-sound";
+
+ dais = <&rsnd_port>;
+ };
+
+ vbus0_usb2: regulator-vbus0-usb2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB20_VBUS0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>, <1800000 0>;
+ };
+
+ x302_clk: x302-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33000000>;
+ };
+
+ x304_clk: x304-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+&audio_clk_a {
+ clock-frequency = <22579200>;
+};
+
+&du {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&gpio6 {
+ usb1-reset {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "usb1-reset";
+ };
+};
+
+&hdmi0 {
+ status = "okay";
+
+ ports {
+ port at 1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ port at 2 {
+ reg = <2>;
+ dw_hdmi0_snd_in: endpoint {
+ remote-endpoint = <&rsnd_endpoint>;
+ };
+ };
+ };
+};
+
+&hscif0 {
+ pinctrl-0 = <&hscif0_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&hsusb {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ versaclock5: clock-generator at 6a {
+ compatible = "idt,5p49v5923";
+ reg = <0x6a>;
+ #clock-cells = <1>;
+ clocks = <&x304_clk>;
+ clock-names = "xin";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ hscif0_pins: hscif0 {
+ groups = "hscif0_data", "hscif0_ctrl";
+ function = "hscif0";
+ };
+
+ scif2_pins: scif2 {
+ groups = "scif2_data_a";
+ function = "scif2";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_a";
+ function = "scif_clk";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
+
+ sdhi2_pins: sd2 {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
+ };
+
+ sdhi3_pins: sd3 {
+ groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
+ function = "sdhi3";
+ power-source = <1800>;
+ };
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+
+ usb1_pins: usb1 {
+ mux {
+ groups = "usb1";
+ function = "usb1";
+ };
+
+ ovc {
+ pins = "GP_6_27";
+ bias-pull-up;
+ };
+ };
+
+ usb30_pins: usb30 {
+ groups = "usb30";
+ function = "usb30";
+ };
+};
+
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi2 {
+ status = "okay";
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <&wlan_en_reg>;
+ bus-width = <4>;
+ non-removable;
+ cap-power-off-card;
+ keep-power-in-suspend;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore at 2 {
+ compatible = "ti,wl1837";
+ reg = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&sdhi3 {
+ pinctrl-0 = <&sdhi3_pins>;
+ pinctrl-1 = <&sdhi3_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ fixed-emmc-driver-type = <1>;
+ status = "okay";
+};
+
+&usb_extal_clk {
+ clock-frequency = <50000000>;
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ vbus-supply = <&vbus0_usb2>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb3_peri0 {
+ phys = <&usb3_phy0>;
+ phy-names = "usb";
+
+ companion = <&xhci0>;
+
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3s0_clk {
+ clock-frequency = <100000000>;
+};
+
+&xhci0 {
+ pinctrl-0 = <&usb30_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
diff --git a/arch/arm/dts/hihope-rev4.dtsi b/arch/arm/dts/hihope-rev4.dtsi
new file mode 100644
index 0000000000..3046c07a28
--- /dev/null
+++ b/arch/arm/dts/hihope-rev4.dtsi
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
+ * HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "hihope-common.dtsi"
+
+/ {
+ audio_clkout: audio-clkout {
+ /*
+ * This is same as <&rcar_sound 0>
+ * but needed to avoid cs2000/rcar_sound probe dead-lock
+ */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+
+ wlan_en_reg: regulator-wlan_en {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ startup-delay-us = <70000>;
+
+ gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ x1801_clk: x1801-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+};
+
+&hscif0 {
+ bluetooth {
+ compatible = "ti,wl1837-st";
+ enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ cs2000: clk_multiplier at 4f {
+ #clock-cells = <0>;
+ compatible = "cirrus,cs2000-cp";
+ reg = <0x4f>;
+ clocks = <&audio_clkout>, <&x1801_clk>;
+ clock-names = "clk_in", "ref_clk";
+
+ assigned-clocks = <&cs2000>;
+ assigned-clock-rates = <24576000>; /* 1/1 divide */
+ };
+};
+
+&pfc {
+ i2c2_pins: i2c2 {
+ groups = "i2c2_a";
+ function = "i2c2";
+ };
+
+ sound_clk_pins: sound_clk {
+ groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a";
+ function = "audio_clk";
+ };
+
+ sound_pins: sound {
+ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
+ function = "ssi";
+ };
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ /* audio_clkout0/1/2/3 */
+ #clock-cells = <1>;
+ clock-frequency = <12288000 11289600>;
+
+ /* update <audio_clk_b> to <cs2000> */
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&cs2000>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
+
+ rsnd_port: port {
+ rsnd_endpoint: endpoint {
+ remote-endpoint = <&dw_hdmi0_snd_in>;
+
+ dai-format = "i2s";
+ bitclock-master = <&rsnd_endpoint>;
+ frame-master = <&rsnd_endpoint>;
+
+ playback = <&ssi2>;
+ };
+ };
+};
diff --git a/arch/arm/dts/hihope-rzg2-ex.dtsi b/arch/arm/dts/hihope-rzg2-ex.dtsi
new file mode 100644
index 0000000000..73dd14245f
--- /dev/null
+++ b/arch/arm/dts/hihope-rzg2-ex.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/ {
+ aliases {
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
+ };
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-txid";
+ status = "okay";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&can0 {
+ pinctrl-0 = <&can0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-0 = <&can1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pciec0 {
+ status = "okay";
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ avb_pins: avb {
+ mux {
+ groups = "avb_link", "avb_mdio", "avb_mii";
+ function = "avb";
+ };
+
+ pins_mdio {
+ groups = "avb_mdio";
+ drive-strength = <24>;
+ };
+
+ pins_mii_tx {
+ pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
+ "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
+ drive-strength = <12>;
+ };
+ };
+
+ can0_pins: can0 {
+ groups = "can0_data_a";
+ function = "can0";
+ };
+
+ can1_pins: can1 {
+ groups = "can1_data";
+ function = "can1";
+ };
+
+ pwm0_pins: pwm0 {
+ groups = "pwm0";
+ function = "pwm0";
+ };
+};
+
+&pwm0 {
+ pinctrl-0 = <&pwm0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
new file mode 100644
index 0000000000..a5ca86196a
--- /dev/null
+++ b/arch/arm/dts/r8a774a1-hihope-rzg2m-ex.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 connected to
+ * sub board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774a1-hihope-rzg2m.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2M with sub board";
+ compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
+ "renesas,r8a774a1";
+};
+
+/* SW43 should be OFF, if in ON state SATA port will be activated */
+&pciec1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts
new file mode 100644
index 0000000000..4881801eea
--- /dev/null
+++ b/arch/arm/dts/r8a774a1-hihope-rzg2m-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2M board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corporation
+ */
+
+#include "r8a774a1-hihope-rzg2m-ex.dts"
+#include "r8a774a1-u-boot.dtsi"
+
+&gpio3 {
+ bt_reg_on{
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "bt-reg-on";
+ };
+};
+
+&gpio4 {
+ wlan_reg_on{
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "wlan-reg-on";
+ };
+};
diff --git a/arch/arm/dts/r8a774a1-hihope-rzg2m.dts b/arch/arm/dts/r8a774a1-hihope-rzg2m.dts
new file mode 100644
index 0000000000..25ae255de0
--- /dev/null
+++ b/arch/arm/dts/r8a774a1-hihope-rzg2m.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 main board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774a1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2M main board based on r8a774a1";
+ compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1";
+
+ memory at 48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ memory at 600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&versaclock5 1>,
+ <&x302_clk>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.2",
+ "dclkin.0", "dclkin.1", "dclkin.2";
+};
diff --git a/arch/arm/dts/r8a774a1-u-boot.dtsi b/arch/arm/dts/r8a774a1-u-boot.dtsi
new file mode 100644
index 0000000000..86be1af351
--- /dev/null
+++ b/arch/arm/dts/r8a774a1-u-boot.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RZ/G2 R8A774A1 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corporation
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
+
+/delete-node/ &audma0;
+/delete-node/ &audma1;
+/delete-node/ &can0;
+/delete-node/ &can1;
+/delete-node/ &canfd;
+/delete-node/ &csi20;
+/delete-node/ &csi40;
+/delete-node/ &du;
+/delete-node/ &fcpf0;
+/delete-node/ &fcpvb0;
+/delete-node/ &fcpvd0;
+/delete-node/ &fcpvd1;
+/delete-node/ &fcpvd2;
+/delete-node/ &fcpvi0;
+/delete-node/ &hdmi0;
+/delete-node/ &lvds0;
+/delete-node/ &rcar_sound;
+/delete-node/ &sdhi2;
+/delete-node/ &sound_card;
+/delete-node/ &vin0;
+/delete-node/ &vin1;
+/delete-node/ &vin2;
+/delete-node/ &vin3;
+/delete-node/ &vin4;
+/delete-node/ &vin5;
+/delete-node/ &vin6;
+/delete-node/ &vin7;
+/delete-node/ &vspb;
+/delete-node/ &vspd0;
+/delete-node/ &vspd1;
+/delete-node/ &vspd2;
+/delete-node/ &vspi0;
+
+/ {
+ /delete-node/ hdmi0-out;
+};
+
+/ {
+ soc {
+ /delete-node/ fdp1 at fe940000;
+ };
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 0ef6cf619b..47ca4bfb2e 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -4,6 +4,8 @@ menu "Select Target SoC"
config R8A774A1
bool "Renesas SoC R8A774A1"
+ imply CLK_R8A774A1
+ imply PINCTRL_PFC_R8A774A1
config R8A774B1
bool "Renesas SoC R8A774B1"
@@ -89,6 +91,15 @@ config TARGET_EBISU
help
Support for Renesas R-Car Gen3 Ebisu platform
+config TARGET_HIHOPE_RZG2
+ bool "HiHope RZ/G2 board"
+ imply R8A774A1
+ imply SYS_MALLOC_F
+ imply MULTI_DTB_FIT
+ imply MULTI_DTB_FIT_USER_DEFINED_AREA
+ help
+ Support for RZG2 HiHope platform
+
config TARGET_SALVATOR_X
bool "Salvator-X board"
imply R8A7795
@@ -123,12 +134,15 @@ source "board/renesas/ebisu/Kconfig"
source "board/renesas/salvator-x/Kconfig"
source "board/renesas/ulcb/Kconfig"
source "board/beacon/beacon-rzg2m/Kconfig"
+source "board/hoperun/hihope-rzg2/Kconfig"
config MULTI_DTB_FIT_UNCOMPRESS_SZ
+ default 0x80000 if TARGET_HIHOPE_RZG2
default 0x80000 if TARGET_SALVATOR_X
default 0x80000 if TARGET_ULCB
config MULTI_DTB_FIT_USER_DEF_ADDR
+ default 0x49000000 if TARGET_HIHOPE_RZG2
default 0x49000000 if TARGET_SALVATOR_X
default 0x49000000 if TARGET_ULCB
diff --git a/board/hoperun/hihope-rzg2/Kconfig b/board/hoperun/hihope-rzg2/Kconfig
new file mode 100644
index 0000000000..ee422ba6c8
--- /dev/null
+++ b/board/hoperun/hihope-rzg2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HIHOPE_RZG2
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "hihope-rzg2"
+
+config SYS_VENDOR
+ default "hoperun"
+
+config SYS_CONFIG_NAME
+ default "hihope-rzg2"
+
+endif
diff --git a/board/hoperun/hihope-rzg2/MAINTAINERS b/board/hoperun/hihope-rzg2/MAINTAINERS
new file mode 100644
index 0000000000..e3702fd12e
--- /dev/null
+++ b/board/hoperun/hihope-rzg2/MAINTAINERS
@@ -0,0 +1,6 @@
+HIHOPE_RZG2 BOARD
+M: Biju Das <biju.das.jz@bp.renesas.com>
+S: Maintained
+F: board/hoperun/hihope-rzg2/
+F: include/configs/hihope-rzg2.h
+F: configs/hihope_rzg2_defconfig
diff --git a/board/hoperun/hihope-rzg2/Makefile b/board/hoperun/hihope-rzg2/Makefile
new file mode 100644
index 0000000000..44f5da227c
--- /dev/null
+++ b/board/hoperun/hihope-rzg2/Makefile
@@ -0,0 +1,9 @@
+#
+# board/hoperun/hihope-rzg2/Makefile
+#
+# Copyright (C) 2020 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := hihope-rzg2.o ../../renesas/rcar-common/common.o
diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c
new file mode 100644
index 0000000000..d49ad78871
--- /dev/null
+++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board/hoperun/hihope-rzg2/hihope-rzg2.c
+ * This file is HiHope RZ/G2M board support.
+ *
+ * Copyright (C) 2020 Renesas Electronics Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+
+#define RST_BASE 0xE6160000
+#define RST_CA57RESCNT (RST_BASE + 0x40)
+#define RST_CA53RESCNT (RST_BASE + 0x44)
+#define RST_CA57_CODE 0xA5A5000F
+#define RST_CA53_CODE 0x5A5A000F
+
+DECLARE_GLOBAL_DATA_PTR;
+#define HSUSB_MSTP704 BIT(4) /* HSUSB */
+
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS 0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
+#define HSUSB_REG_UGCTRL2 0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
+#define HSUSB_REG_UGCTRL2_RESERVED_3 0x1 /* bit[3:0] should be B'0001 */
+
+#define PRR_REGISTER (0xFFF00044)
+
+int board_init(void)
+{
+ u32 i;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+ /* Configure the HSUSB block */
+ mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
+ /*
+ * We need to add a barrier instruction after HSUSB module stop release.
+ * This barrier instruction can be either reading back the same MSTP
+ * register or any other register in the same IP block. So like linux
+ * adding check for MSTPSR register, which indicates the clock has been
+ * started.
+ */
+ for (i = 1000; i > 0; --i) {
+ if (!(readl(MSTPSR7) & HSUSB_MSTP704))
+ break;
+ cpu_relax();
+ }
+
+ /* Select EHCI/OHCI host module for USB2.0 ch0 */
+ writel(HSUSB_REG_UGCTRL2_USB0SEL_EHCI | HSUSB_REG_UGCTRL2_RESERVED_3,
+ HSUSB_REG_UGCTRL2);
+ /* low power status */
+ setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ unsigned long midr, cputype;
+
+ asm volatile("mrs %0, midr_el1" : "=r" (midr));
+ cputype = (midr >> 4) & 0xfff;
+
+ if (cputype == 0xd03)
+ writel(RST_CA53_CODE, RST_CA53RESCNT);
+ else
+ writel(RST_CA57_CODE, RST_CA57RESCNT);
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ const u32 soc_id = (readl(PRR_REGISTER) & 0x00007F00) >> 8;
+
+ if (soc_id == SOC_ID_R8A774A1 &&
+ !strcmp(name, "r8a774a1-hihope-rzg2m-u-boot"))
+ return 0;
+
+ return -1;
+}
+#endif
diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig
new file mode 100644
index 0000000000..ec57ff8e8c
--- /dev/null
+++ b/configs/hihope_rzg2_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xFFFE0000
+CONFIG_DM_GPIO=y
+CONFIG_GPIO_HOG=y
+CONFIG_RCAR_GEN3=y
+CONFIG_TARGET_HIHOPE_RZG2=y
+# CONFIG_BOARD_EARLY_INIT_F is not set
+# CONFIG_SPL is not set
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_RENESAS=y
+CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-hihope-rzg2m-u-boot"
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot"
+CONFIG_MULTI_DTB_FIT_LZO=y
+CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_RENESAS_SDHI=y
+CONFIG_BITBANGMII=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_SCIF_CONSOLE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/include/configs/hihope-rzg2.h b/include/configs/hihope-rzg2.h
new file mode 100644
index 0000000000..68a51176e3
--- /dev/null
+++ b/include/configs/hihope-rzg2.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/hihope-rzg2.h
+ * This file is HOPERUN HiHope RZ/G2 board configuration.
+ *
+ * Copyright (C) 2020 Renesas Electronics Corporation
+ */
+
+#ifndef __HIHOPE_RZG2_H
+#define __HIHOPE_RZG2_H
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_BITBANGMII_MULTI
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
+
+#endif /* __HIHOPE_RZG2_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 4/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N
2020-11-02 16:16 [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support Biju Das
` (2 preceding siblings ...)
2020-11-02 16:16 ` [PATCH v6 3/7] arm: rmobile: Add HopeRun HiHope RZ/G2M board support Biju Das
@ 2020-11-02 16:16 ` Biju Das
2020-11-02 16:16 ` [PATCH v6 5/7] arm: rmobile: Add HopeRun HiHope RZ/G2N board support Biju Das
` (3 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Biju Das @ 2020-11-02 16:16 UTC (permalink / raw)
To: u-boot
Add SDHI quirks for R-Car M3-N and RZ/G2N SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v6: New patch. quirks using soc_device_match.
---
drivers/mmc/renesas-sdhi.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 39deeb94d8..0e4a44d973 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -886,6 +886,11 @@ static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
.hs400_calib_table = r8a7796_rev3_calib_table,
};
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
+ .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+ .hs400_calib_table = r8a77965_calib_table,
+};
+
/*
* Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
* So, we want to treat them equally and only have a match for ES1.2 to enforce
@@ -908,6 +913,9 @@ static const struct soc_attr sdhi_quirks_match[] = {
.revision = "ES1.3",
.data = &sdhi_quirks_r8a7796_es13
},
+ { .soc_id = "r8a774b1",
+ .data = &sdhi_quirks_r8a77965
+ },
{ .soc_id = "r8a7796",
.revision = "ES1.0",
.data = &sdhi_quirks_4tap_nohs400_b17_dtrend
@@ -924,6 +932,9 @@ static const struct soc_attr sdhi_quirks_match[] = {
.revision = "ES1.3",
.data = &sdhi_quirks_r8a7796_es13
},
+ { .soc_id = "r8a77965",
+ .data = &sdhi_quirks_r8a77965
+ },
{ /* Sentinel. */ },
};
@@ -951,7 +962,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
priv->adjust_hs400_enable = true;
priv->adjust_hs400_calib_table =
quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
- if (quirks == &sdhi_quirks_r8a7796_es12)
+ if (quirks == &sdhi_quirks_r8a7796_es12 ||
+ quirks == &sdhi_quirks_r8a77965)
priv->adjust_hs400_offset = 3;
else if (quirks == &sdhi_quirks_r8a7796_es13)
priv->adjust_hs400_offset = 0;
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 5/7] arm: rmobile: Add HopeRun HiHope RZ/G2N board support
2020-11-02 16:16 [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support Biju Das
` (3 preceding siblings ...)
2020-11-02 16:16 ` [PATCH v6 4/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N Biju Das
@ 2020-11-02 16:16 ` Biju Das
2020-11-02 16:16 ` [PATCH v6 6/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H Biju Das
` (2 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Biju Das @ 2020-11-02 16:16 UTC (permalink / raw)
To: u-boot
The HiHope RZ/G2N board from HopeRun consists of main board
(HopeRun HiHope RZ/G2N main board) and sub board(HopeRun
HiHope RZ/G2N sub board). The HiHope RZ/G2N sub board sits
below the HiHope RZ/G2N main board.
DTS files apart from r8a774b1-hihope-rzg2n-u-boot.dts and
r8a774b1-u-boot.dtsi have been imported from linux 5.9 commit
bbf5c979011a ("Linux 5.9")
This patch adds the required board support to boot HopeRun HiHope
RZ/G2N board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v6: New patch
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts | 16 ++++++
arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts | 27 ++++++++++
arch/arm/dts/r8a774b1-hihope-rzg2n.dts | 41 ++++++++++++++
arch/arm/dts/r8a774b1-u-boot.dtsi | 53 +++++++++++++++++++
arch/arm/mach-rmobile/Kconfig.64 | 1 +
board/hoperun/hihope-rzg2/hihope-rzg2.c | 6 ++-
configs/hihope_rzg2_defconfig | 2 +-
8 files changed, 145 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
create mode 100644 arch/arm/dts/r8a774b1-hihope-rzg2n.dts
create mode 100644 arch/arm/dts/r8a774b1-u-boot.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ba46785078..9f14fb13ec 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -793,6 +793,7 @@ dtb-$(CONFIG_RCAR_GEN2) += \
dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
r8a774a1-hihope-rzg2m-u-boot.dtb \
+ r8a774b1-hihope-rzg2n-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
new file mode 100644
index 0000000000..a3edd55113
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-ex.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to
+ * sub board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2N with sub board";
+ compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
+ "renesas,r8a774b1";
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
new file mode 100644
index 0000000000..09378a70a2
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2N board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774b1-hihope-rzg2n-ex.dts"
+#include "r8a774b1-u-boot.dtsi"
+
+&gpio3 {
+ bt_reg_on{
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "bt-reg-on";
+ };
+};
+
+&gpio4 {
+ wlan_reg_on{
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "wlan-reg-on";
+ };
+};
diff --git a/arch/arm/dts/r8a774b1-hihope-rzg2n.dts b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
new file mode 100644
index 0000000000..f1883cbd1a
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-hihope-rzg2n.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774b1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
+ compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
+
+ memory at 48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ memory at 480000000 {
+ device_type = "memory";
+ reg = <0x4 0x80000000 0x0 0x80000000>;
+ };
+};
+
+&du {
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 721>,
+ <&versaclock5 1>,
+ <&x302_clk>,
+ <&versaclock5 2>;
+ clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
+
+&sdhi3 {
+ mmc-hs400-1_8v;
+};
diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi b/arch/arm/dts/r8a774b1-u-boot.dtsi
new file mode 100644
index 0000000000..2c0319fc39
--- /dev/null
+++ b/arch/arm/dts/r8a774b1-u-boot.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RZ/G2 R8A774B1 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
+
+/delete-node/ &audma0;
+/delete-node/ &audma1;
+/delete-node/ &can0;
+/delete-node/ &can1;
+/delete-node/ &canfd;
+/delete-node/ &csi20;
+/delete-node/ &csi40;
+/delete-node/ &du;
+/delete-node/ &fcpf0;
+/delete-node/ &fcpvb0;
+/delete-node/ &fcpvd0;
+/delete-node/ &fcpvd1;
+/delete-node/ &fcpvi0;
+/delete-node/ &hdmi0;
+/delete-node/ &lvds0;
+/delete-node/ &rcar_sound;
+/delete-node/ &sdhi2;
+/delete-node/ &sound_card;
+/delete-node/ &vin0;
+/delete-node/ &vin1;
+/delete-node/ &vin2;
+/delete-node/ &vin3;
+/delete-node/ &vin4;
+/delete-node/ &vin5;
+/delete-node/ &vin6;
+/delete-node/ &vin7;
+/delete-node/ &vspb;
+/delete-node/ &vspd0;
+/delete-node/ &vspd1;
+/delete-node/ &vspi0;
+
+/ {
+ /delete-node/ hdmi0-out;
+};
+
+/ {
+ soc {
+ /delete-node/ fdp1 at fe940000;
+ };
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 47ca4bfb2e..18153a809e 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -94,6 +94,7 @@ config TARGET_EBISU
config TARGET_HIHOPE_RZG2
bool "HiHope RZ/G2 board"
imply R8A774A1
+ imply R8A774B1
imply SYS_MALLOC_F
imply MULTI_DTB_FIT
imply MULTI_DTB_FIT_USER_DEFINED_AREA
diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c
index d49ad78871..66854bcadc 100644
--- a/board/hoperun/hihope-rzg2/hihope-rzg2.c
+++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board/hoperun/hihope-rzg2/hihope-rzg2.c
- * This file is HiHope RZ/G2M board support.
+ * This file is HiHope RZ/G2[MN] board support.
*
* Copyright (C) 2020 Renesas Electronics Corporation
*/
@@ -86,6 +86,10 @@ int board_fit_config_name_match(const char *name)
!strcmp(name, "r8a774a1-hihope-rzg2m-u-boot"))
return 0;
+ if (soc_id == SOC_ID_R8A774B1 &&
+ !strcmp(name, "r8a774b1-hihope-rzg2n-u-boot"))
+ return 0;
+
return -1;
}
#endif
diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig
index ec57ff8e8c..b89bff3584 100644
--- a/configs/hihope_rzg2_defconfig
+++ b/configs/hihope_rzg2_defconfig
@@ -36,7 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot"
+CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot r8a774b1-hihope-rzg2n-u-boot"
CONFIG_MULTI_DTB_FIT_LZO=y
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
CONFIG_ENV_OVERWRITE=y
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 6/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H
2020-11-02 16:16 [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support Biju Das
` (4 preceding siblings ...)
2020-11-02 16:16 ` [PATCH v6 5/7] arm: rmobile: Add HopeRun HiHope RZ/G2N board support Biju Das
@ 2020-11-02 16:16 ` Biju Das
2020-11-02 21:47 ` Jaehoon Chung
2020-11-02 16:16 ` [PATCH v6 7/7] arm: rmobile: Add HopeRun HiHope RZ/G2H board support Biju Das
2020-11-02 19:26 ` [PATCH v6 0/7] Add HiHope RZ/G2[HMN] " Marek Vasut
7 siblings, 1 reply; 16+ messages in thread
From: Biju Das @ 2020-11-02 16:16 UTC (permalink / raw)
To: u-boot
Add SDHI quirks for R-Car H3 and RZ/G2H SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v6: New patch. Quirks using soc_device_match.
---
drivers/mmc/renesas-sdhi.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 0e4a44d973..e19daf8bf8 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -875,6 +875,16 @@ static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
.hs400_4taps = true,
};
+static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
+ .hs400_4taps = true,
+ .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+};
+
+static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {
+ .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
+ .hs400_calib_table = r8a7795_calib_table,
+};
+
static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
.hs400_4taps = true,
.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
@@ -916,6 +926,30 @@ static const struct soc_attr sdhi_quirks_match[] = {
{ .soc_id = "r8a774b1",
.data = &sdhi_quirks_r8a77965
},
+ { .soc_id = "r8a774e1",
+ .revision = "ES2.0",
+ .data = &sdhi_quirks_4tap
+ },
+ { .soc_id = "r8a774e1",
+ .revision = "ES3.0",
+ .data = &sdhi_quirks_r8a7795_es30
+ },
+ { .soc_id = "r8a7795",
+ .revision = "ES1.0",
+ .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
+ },
+ { .soc_id = "r8a7795",
+ .revision = "ES1.1",
+ .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
+ },
+ { .soc_id = "r8a7795",
+ .revision = "ES2.0",
+ .data = &sdhi_quirks_4tap
+ },
+ { .soc_id = "r8a7795",
+ .revision = "ES3.0",
+ .data = &sdhi_quirks_r8a7795_es30
+ },
{ .soc_id = "r8a7796",
.revision = "ES1.0",
.data = &sdhi_quirks_4tap_nohs400_b17_dtrend
@@ -965,7 +999,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
if (quirks == &sdhi_quirks_r8a7796_es12 ||
quirks == &sdhi_quirks_r8a77965)
priv->adjust_hs400_offset = 3;
- else if (quirks == &sdhi_quirks_r8a7796_es13)
+ else if (quirks == &sdhi_quirks_r8a7796_es13 ||
+ quirks == &sdhi_quirks_r8a7795_es30)
priv->adjust_hs400_offset = 0;
}
}
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 7/7] arm: rmobile: Add HopeRun HiHope RZ/G2H board support
2020-11-02 16:16 [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support Biju Das
` (5 preceding siblings ...)
2020-11-02 16:16 ` [PATCH v6 6/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H Biju Das
@ 2020-11-02 16:16 ` Biju Das
2020-11-02 19:26 ` [PATCH v6 0/7] Add HiHope RZ/G2[HMN] " Marek Vasut
7 siblings, 0 replies; 16+ messages in thread
From: Biju Das @ 2020-11-02 16:16 UTC (permalink / raw)
To: u-boot
The HiHope RZ/G2H board from HopeRun consists of main board
(HopeRun HiHope RZ/G2H main board) and sub board(HopeRun
HiHope RZ/G2H sub board). The HiHope RZ/G2H sub board sits
below the HiHope RZ/G2H main board.
DTS files apart from r8a774e1-hihope-rzg2h-u-boot.dts and
r8a774e1-u-boot.dtsi have been imported from linux 5.9 commit
bbf5c979011a ("Linux 5.9").
This patch adds the required board support to boot HopeRun HiHope
RZ/G2H board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v6: New patch.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts | 15 +++++++++++
arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts | 27 +++++++++++++++++++
arch/arm/dts/r8a774e1-hihope-rzg2h.dts | 26 ++++++++++++++++++
arch/arm/dts/r8a774e1-u-boot.dtsi | 25 +++++++++++++++++
arch/arm/mach-rmobile/Kconfig.64 | 1 +
board/hoperun/hihope-rzg2/hihope-rzg2.c | 6 ++++-
configs/hihope_rzg2_defconfig | 2 +-
8 files changed, 101 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
create mode 100644 arch/arm/dts/r8a774e1-hihope-rzg2h.dts
create mode 100644 arch/arm/dts/r8a774e1-u-boot.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9f14fb13ec..3715640bbb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -794,6 +794,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a774a1-beacon-rzg2m-kit.dtb \
r8a774a1-hihope-rzg2m-u-boot.dtb \
r8a774b1-hihope-rzg2n-u-boot.dtb \
+ r8a774e1-hihope-rzg2h-u-boot.dtb \
r8a77950-ulcb-u-boot.dtb \
r8a77950-salvator-x-u-boot.dtb \
r8a77960-ulcb-u-boot.dtb \
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
new file mode 100644
index 0000000000..265355e0de
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H sub board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h.dts"
+#include "hihope-rzg2-ex.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2H with sub board";
+ compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h",
+ "renesas,r8a774e1";
+};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
new file mode 100644
index 0000000000..03a17bac7e
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h-u-boot.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Hihope RZ/G2H board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a774e1-hihope-rzg2h-ex.dts"
+#include "r8a774e1-u-boot.dtsi"
+
+&gpio3 {
+ bt_reg_on{
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "bt-reg-on";
+ };
+};
+
+&gpio4 {
+ wlan_reg_on{
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "wlan-reg-on";
+ };
+};
diff --git a/arch/arm/dts/r8a774e1-hihope-rzg2h.dts b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
new file mode 100644
index 0000000000..cdbe527e93
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-hihope-rzg2h.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H main board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774e1.dtsi"
+#include "hihope-rev4.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
+ compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
+
+ memory at 48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ memory at 500000000 {
+ device_type = "memory";
+ reg = <0x5 0x00000000 0x0 0x80000000>;
+ };
+};
diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi b/arch/arm/dts/r8a774e1-u-boot.dtsi
new file mode 100644
index 0000000000..30c38dcfba
--- /dev/null
+++ b/arch/arm/dts/r8a774e1-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RZ/G2 R8A774E1 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+ u-boot,dm-pre-reloc;
+};
+
+/delete-node/ &can0;
+/delete-node/ &can1;
+/delete-node/ &canfd;
+/delete-node/ &du;
+/delete-node/ &hdmi0;
+/delete-node/ &rcar_sound;
+/delete-node/ &sdhi2;
+/delete-node/ &sound_card;
+
+/ {
+ /delete-node/ hdmi0-out;
+};
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 18153a809e..56c522596a 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -95,6 +95,7 @@ config TARGET_HIHOPE_RZG2
bool "HiHope RZ/G2 board"
imply R8A774A1
imply R8A774B1
+ imply R8A774E1
imply SYS_MALLOC_F
imply MULTI_DTB_FIT
imply MULTI_DTB_FIT_USER_DEFINED_AREA
diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c
index 66854bcadc..cb3dcf8db2 100644
--- a/board/hoperun/hihope-rzg2/hihope-rzg2.c
+++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board/hoperun/hihope-rzg2/hihope-rzg2.c
- * This file is HiHope RZ/G2[MN] board support.
+ * This file is HiHope RZ/G2[HMN] board support.
*
* Copyright (C) 2020 Renesas Electronics Corporation
*/
@@ -90,6 +90,10 @@ int board_fit_config_name_match(const char *name)
!strcmp(name, "r8a774b1-hihope-rzg2n-u-boot"))
return 0;
+ if (soc_id == SOC_ID_R8A774E1 &&
+ !strcmp(name, "r8a774e1-hihope-rzg2h-u-boot"))
+ return 0;
+
return -1;
}
#endif
diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig
index b89bff3584..70a3d43fd9 100644
--- a/configs/hihope_rzg2_defconfig
+++ b/configs/hihope_rzg2_defconfig
@@ -36,7 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot r8a774b1-hihope-rzg2n-u-boot"
+CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot r8a774b1-hihope-rzg2n-u-boot r8a774e1-hihope-rzg2h-u-boot"
CONFIG_MULTI_DTB_FIT_LZO=y
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
CONFIG_ENV_OVERWRITE=y
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
2020-11-02 16:16 ` [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M Biju Das
@ 2020-11-02 17:24 ` Biju Das
2020-11-02 21:41 ` Jaehoon Chung
1 sibling, 0 replies; 16+ messages in thread
From: Biju Das @ 2020-11-02 17:24 UTC (permalink / raw)
To: u-boot
Hi All,
Please ignore this patch, it is giving compilation error for ARM 32 platforms. I will post v7 fixing this error.
arm: + blanche
+drivers/mmc/renesas-sdhi.c:868:21: error: variable 'sdhi_quirks_4tap_nohs400_b17_dtrend' has initializer but incomplete type
+ 868 | static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_b17_dtrend = {
+ |
Regards,
Biju
> Subject: [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W
> and RZ/G2M
>
> Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v5->v6: Used soc_device_match api to add quirks.
> v5 : New Patch
> (Ref:
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> work.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201008085941.3600-2-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp
> .renesas.com%7Ca8731933d03d4e7e826f08d87f4ab9bd%7C53d82571da1947e
> 49cb4625a166a4a2a%7C0%7C0%7C637399306207070943%7CUnknown%7CTW
> FpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX
> VCI6Mn0%3D%7C1000&sdata=YEZTOITdq0M0iLuBr%2BLd9QTo3oe6hfy
> wNTl9bODUS6c%3D&reserved=0)
> ---
> drivers/mmc/renesas-sdhi.c | 110
> +++++++++++++++++++++++++++++++++++++
> 1 file changed, 110 insertions(+)
>
> diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index
> d80b3fc28f..39deeb94d8 100644
> --- a/drivers/mmc/renesas-sdhi.c
> +++ b/drivers/mmc/renesas-sdhi.c
> @@ -19,6 +19,7 @@
> #include <linux/io.h>
> #include <linux/sizes.h>
> #include <power/regulator.h>
> +#include <soc.h>
> #include <asm/unaligned.h>
> #include "tmio-common.h"
>
> @@ -105,6 +106,15 @@ static const u8
> r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
> 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 } };
>
> +#define SDHI_CALIB_TABLE_MAX 32
> +
> +struct renesas_sdhi_quirks {
> + bool hs400_disabled;
> + bool hs400_4taps;
> + u32 hs400_bad_taps;
> + const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
> +};
> +
> static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv) {
> /* On R-Car Gen3, MMC0 is at 0xee140000 */ @@ -855,6 +865,99 @@
> static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
> return clk_get_rate(&priv->clk);
> }
>
> +static const struct renesas_sdhi_quirks
> sdhi_quirks_4tap_nohs400_b17_dtrend = {
> + .hs400_disabled = true,
> + .hs400_4taps = true,
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
> + .hs400_disabled = true,
> + .hs400_4taps = true,
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
> + .hs400_4taps = true,
> + .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> + .hs400_calib_table = r8a7796_rev1_calib_table, };
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
> + .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
> + .hs400_calib_table = r8a7796_rev3_calib_table, };
> +
> +/*
> + * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
> + * So, we want to treat them equally and only have a match for ES1.2 to
> +enforce
> + * this if there ever will be a way to distinguish ES1.2.
> + */
> +static const struct soc_attr sdhi_quirks_match[] = {
> + { .soc_id = "r8a774a1",
> + .revision = "ES1.0",
> + .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> + },
> + { .soc_id = "r8a774a1",
> + .revision = "ES1.1",
> + .data = &sdhi_quirks_4tap_nohs400
> + },
> + { .soc_id = "r8a774a1",
> + .revision = "ES1.2",
> + .data = &sdhi_quirks_r8a7796_es12
> + },
> + { .soc_id = "r8a774a1",
> + .revision = "ES1.3",
> + .data = &sdhi_quirks_r8a7796_es13
> + },
> + { .soc_id = "r8a7796",
> + .revision = "ES1.0",
> + .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> + },
> + { .soc_id = "r8a7796",
> + .revision = "ES1.1",
> + .data = &sdhi_quirks_4tap_nohs400
> + },
> + { .soc_id = "r8a7796",
> + .revision = "ES1.2",
> + .data = &sdhi_quirks_r8a7796_es12
> + },
> + { .soc_id = "r8a7796",
> + .revision = "ES1.3",
> + .data = &sdhi_quirks_r8a7796_es13
> + },
> + { /* Sentinel. */ },
> +};
> +
> +static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
> + struct tmio_sd_priv *priv,
> + const struct renesas_sdhi_quirks *quirks) {
> + priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
> +
> + if (quirks && quirks->hs400_disabled) {
> + plat->cfg.host_caps &= ~MMC_MODE_HS400;
> + if (quirks == &sdhi_quirks_4tap_nohs400_b17_dtrend)
> + priv->read_poll_flag =
> TMIO_SD_DMA_INFO1_END_RD;
> + }
> +
> + if (quirks && quirks->hs400_4taps)
> + priv->nrtaps = 4;
> + else
> + priv->nrtaps = 8;
> +
> + if (quirks && quirks->hs400_bad_taps)
> + priv->hs400_bad_tap = quirks->hs400_bad_taps;
> +
> + if (quirks && quirks->hs400_calib_table) {
> + priv->adjust_hs400_enable = true;
> + priv->adjust_hs400_calib_table =
> + quirks-
> >hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
> + if (quirks == &sdhi_quirks_r8a7796_es12)
> + priv->adjust_hs400_offset = 3;
> + else if (quirks == &sdhi_quirks_r8a7796_es13)
> + priv->adjust_hs400_offset = 0;
> + }
> +}
> +
> static void renesas_sdhi_filter_caps(struct udevice *dev) {
> struct tmio_sd_priv *priv = dev_get_priv(dev); @@ -866,6 +969,13
> @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
> CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
> CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
> struct tmio_sd_plat *plat = dev_get_platdata(dev);
> + const struct soc_attr *attr;
> +
> + attr = soc_device_match(sdhi_quirks_match);
> + if (attr) {
> + renesas_sdhi_add_quirks(plat, priv, attr->data);
> + return;
> + }
>
> /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
> if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
> --
> 2.17.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support
2020-11-02 16:16 [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support Biju Das
` (6 preceding siblings ...)
2020-11-02 16:16 ` [PATCH v6 7/7] arm: rmobile: Add HopeRun HiHope RZ/G2H board support Biju Das
@ 2020-11-02 19:26 ` Marek Vasut
2020-11-03 10:54 ` Biju Das
7 siblings, 1 reply; 16+ messages in thread
From: Marek Vasut @ 2020-11-02 19:26 UTC (permalink / raw)
To: u-boot
On 11/2/20 5:16 PM, Biju Das wrote:
> This patch series adds the required SoC/Board support to boot HopeRun
> HiHope RZ/G2[HMN] boards.
>
> It uses SoC driver for unique cpu identification for RZ/G and R-Car SoC's,
> since they share same PRR ID.
>
> SDHI quirks added using soc_device_match api.
Can you please split this into driver patch series and board patch
series ? And before you resend it, lets figure out the SoC
identification first.
Note that the driver patches look _much_ nicer, thanks.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
2020-11-02 16:16 ` [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M Biju Das
2020-11-02 17:24 ` Biju Das
@ 2020-11-02 21:41 ` Jaehoon Chung
2020-11-03 10:15 ` Biju Das
1 sibling, 1 reply; 16+ messages in thread
From: Jaehoon Chung @ 2020-11-02 21:41 UTC (permalink / raw)
To: u-boot
On 11/3/20 1:16 AM, Biju Das wrote:
> Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v5->v6: Used soc_device_match api to add quirks.
> v5 : New Patch
> (Ref: https://protect2.fireeye.com/v1/url?k=38bf0561-67243c69-38be8e2e-0cc47a31c8b4-1ef3629e787f84b8&q=1&e=36446b2d-ef7f-49cd-b2d1-5ec122c2b61e&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20201008085941.3600-2-biju.das.jz%40bp.renesas.com%2F)
> ---
> drivers/mmc/renesas-sdhi.c | 110 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 110 insertions(+)
>
> diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> index d80b3fc28f..39deeb94d8 100644
> --- a/drivers/mmc/renesas-sdhi.c
> +++ b/drivers/mmc/renesas-sdhi.c
> @@ -19,6 +19,7 @@
> #include <linux/io.h>
> #include <linux/sizes.h>
> #include <power/regulator.h>
> +#include <soc.h>
> #include <asm/unaligned.h>
> #include "tmio-common.h"
>
> @@ -105,6 +106,15 @@ static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
> 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
> };
>
> +#define SDHI_CALIB_TABLE_MAX 32
> +
> +struct renesas_sdhi_quirks {
> + bool hs400_disabled;
> + bool hs400_4taps;
> + u32 hs400_bad_taps;
> + const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
> +};
> +
> static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
> {
> /* On R-Car Gen3, MMC0 is at 0xee140000 */
> @@ -855,6 +865,99 @@ static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
> return clk_get_rate(&priv->clk);
> }
>
> +static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_b17_dtrend = {
> + .hs400_disabled = true,
> + .hs400_4taps = true,
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
> + .hs400_disabled = true,
> + .hs400_4taps = true,
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
> + .hs400_4taps = true,
> + .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
Use Macro, not magic code. We don't know what mean BIT(2), BIT(3), BIT(6)..
> + .hs400_calib_table = r8a7796_rev1_calib_table,
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
> + .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
Ditto.
> + .hs400_calib_table = r8a7796_rev3_calib_table,
> +};
> +
> +/*
> + * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
> + * So, we want to treat them equally and only have a match for ES1.2 to enforce
> + * this if there ever will be a way to distinguish ES1.2.
> + */
> +static const struct soc_attr sdhi_quirks_match[] = {
> + { .soc_id = "r8a774a1",
> + .revision = "ES1.0",
> + .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> + },
> + { .soc_id = "r8a774a1",
> + .revision = "ES1.1",
> + .data = &sdhi_quirks_4tap_nohs400
> + },
> + { .soc_id = "r8a774a1",
> + .revision = "ES1.2",
> + .data = &sdhi_quirks_r8a7796_es12
> + },
> + { .soc_id = "r8a774a1",
> + .revision = "ES1.3",
> + .data = &sdhi_quirks_r8a7796_es13
> + },
> + { .soc_id = "r8a7796",
> + .revision = "ES1.0",
> + .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> + },
> + { .soc_id = "r8a7796",
> + .revision = "ES1.1",
> + .data = &sdhi_quirks_4tap_nohs400
> + },
> + { .soc_id = "r8a7796",
> + .revision = "ES1.2",
> + .data = &sdhi_quirks_r8a7796_es12
> + },
> + { .soc_id = "r8a7796",
> + .revision = "ES1.3",
> + .data = &sdhi_quirks_r8a7796_es13
> + },
> + { /* Sentinel. */ },
> +};
> +
> +static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
> + struct tmio_sd_priv *priv,
> + const struct renesas_sdhi_quirks *quirks)
> +{
> + priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
> +
> + if (quirks && quirks->hs400_disabled) {
> + plat->cfg.host_caps &= ~MMC_MODE_HS400;
> + if (quirks == &sdhi_quirks_4tap_nohs400_b17_dtrend)
> + priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
> + }
> +
> + if (quirks && quirks->hs400_4taps)
> + priv->nrtaps = 4;
> + else
> + priv->nrtaps = 8;
priv->nrtraps = 8 should be default value.
And it needs to check one time about quirks's present at first time.
Then it can be changed to below..
priv->read_poll_flag = TMIO...;
priv->nrtaps = 8;
if (!quriks)
return;
if (quirks-.hs400_disabld) {
...
}
if (quirks->hs400_4taps)
priv->nrtaps = 4;
...
Then it's more readable..
Best Regards,
Jaehoon Chung
> +
> + if (quirks && quirks->hs400_bad_taps)
> + priv->hs400_bad_tap = quirks->hs400_bad_taps;> +
> + if (quirks && quirks->hs400_calib_table) {
> + priv->adjust_hs400_enable = true;
> + priv->adjust_hs400_calib_table =
> + quirks->hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
> + if (quirks == &sdhi_quirks_r8a7796_es12)
> + priv->adjust_hs400_offset = 3;
> + else if (quirks == &sdhi_quirks_r8a7796_es13)
> + priv->adjust_hs400_offset = 0;
> + }
> +}
> +
> static void renesas_sdhi_filter_caps(struct udevice *dev)
> {
> struct tmio_sd_priv *priv = dev_get_priv(dev);
> @@ -866,6 +969,13 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
> CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
> CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
> struct tmio_sd_plat *plat = dev_get_platdata(dev);
> + const struct soc_attr *attr;
> +
> + attr = soc_device_match(sdhi_quirks_match);
> + if (attr) {
> + renesas_sdhi_add_quirks(plat, priv, attr->data);
> + return;
> + }
>
> /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
> if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 6/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H
2020-11-02 16:16 ` [PATCH v6 6/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H Biju Das
@ 2020-11-02 21:47 ` Jaehoon Chung
2020-11-03 10:18 ` Biju Das
0 siblings, 1 reply; 16+ messages in thread
From: Jaehoon Chung @ 2020-11-02 21:47 UTC (permalink / raw)
To: u-boot
Hi,
On 11/3/20 1:16 AM, Biju Das wrote:
> Add SDHI quirks for R-Car H3 and RZ/G2H SoC.
Does it needs to use quirks? IMO, Using fixup for each SoC is better than quirks.
Best Regards,
Jaehoon Chung
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v6: New patch. Quirks using soc_device_match.
> ---
> drivers/mmc/renesas-sdhi.c | 37 ++++++++++++++++++++++++++++++++++++-
> 1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> index 0e4a44d973..e19daf8bf8 100644
> --- a/drivers/mmc/renesas-sdhi.c
> +++ b/drivers/mmc/renesas-sdhi.c
> @@ -875,6 +875,16 @@ static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
> .hs400_4taps = true,
> };
>
> +static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
> + .hs400_4taps = true,
> + .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> +};
> +
> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {
> + .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> + .hs400_calib_table = r8a7795_calib_table,
> +};
> +
> static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
> .hs400_4taps = true,
> .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> @@ -916,6 +926,30 @@ static const struct soc_attr sdhi_quirks_match[] = {
> { .soc_id = "r8a774b1",
> .data = &sdhi_quirks_r8a77965
> },
> + { .soc_id = "r8a774e1",
> + .revision = "ES2.0",
> + .data = &sdhi_quirks_4tap
> + },
> + { .soc_id = "r8a774e1",
> + .revision = "ES3.0",
> + .data = &sdhi_quirks_r8a7795_es30
> + },
> + { .soc_id = "r8a7795",
> + .revision = "ES1.0",
> + .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> + },
> + { .soc_id = "r8a7795",
> + .revision = "ES1.1",
> + .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> + },
> + { .soc_id = "r8a7795",
> + .revision = "ES2.0",
> + .data = &sdhi_quirks_4tap
> + },
> + { .soc_id = "r8a7795",
> + .revision = "ES3.0",
> + .data = &sdhi_quirks_r8a7795_es30
> + },
> { .soc_id = "r8a7796",
> .revision = "ES1.0",
> .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> @@ -965,7 +999,8 @@ static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
> if (quirks == &sdhi_quirks_r8a7796_es12 ||
> quirks == &sdhi_quirks_r8a77965)
> priv->adjust_hs400_offset = 3;
> - else if (quirks == &sdhi_quirks_r8a7796_es13)
> + else if (quirks == &sdhi_quirks_r8a7796_es13 ||
> + quirks == &sdhi_quirks_r8a7795_es30)
> priv->adjust_hs400_offset = 0;
> }
> }
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
2020-11-02 21:41 ` Jaehoon Chung
@ 2020-11-03 10:15 ` Biju Das
2020-11-03 10:28 ` Jaehoon Chung
0 siblings, 1 reply; 16+ messages in thread
From: Biju Das @ 2020-11-03 10:15 UTC (permalink / raw)
To: u-boot
Hi Jaehoon Chung,
Thanks for the feedback.
> Subject: Re: [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car
> M3-W and RZ/G2M
>
> On 11/3/20 1:16 AM, Biju Das wrote:
> > Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-
> lad.rj at bp.renesas.com>
> > ---
> > drivers/mmc/renesas-sdhi.c | 110
> > +++++++++++++++++++++++++++++++++++++
> > 1 file changed, 110 insertions(+)
> >
> > diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> > index d80b3fc28f..39deeb94d8 100644
> > --- a/drivers/mmc/renesas-sdhi.c
> > +++ b/drivers/mmc/renesas-sdhi.c
> > @@ -19,6 +19,7 @@
> > #include <linux/io.h>
> > #include <linux/sizes.h>
> > #include <power/regulator.h>
> > +#include <soc.h>
> > #include <asm/unaligned.h>
> > #include "tmio-common.h"
> >
> > @@ -105,6 +106,15 @@ static const u8
> r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
> > 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
> > };
> >
> > +#define SDHI_CALIB_TABLE_MAX 32
> > +
> > +struct renesas_sdhi_quirks {
> > + bool hs400_disabled;
> > + bool hs400_4taps;
> > + u32 hs400_bad_taps;
> > + const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
> > +};
> > +
> > static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv) {
> > /* On R-Car Gen3, MMC0 is at 0xee140000 */ @@ -855,6 +865,99 @@
> > static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
> > return clk_get_rate(&priv->clk);
> > }
> >
> > +static const struct renesas_sdhi_quirks
> sdhi_quirks_4tap_nohs400_b17_dtrend = {
> > + .hs400_disabled = true,
> > + .hs400_4taps = true,
> > +};
> > +
> > +static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
> > + .hs400_disabled = true,
> > + .hs400_4taps = true,
> > +};
> > +
> > +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
> > + .hs400_4taps = true,
> > + .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
>
> Use Macro, not magic code. We don't know what mean BIT(2), BIT(3), BIT(6)..
This work is based on linux[1]. For maintainability we want to make u-boot code similar to linux, so that in future if there
is any improvement in linux we can port here.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mmc/host/renesas_sdhi_core.c?h=v5.10-rc2#n886
>
> > + .hs400_calib_table = r8a7796_rev1_calib_table, };
> > +
> > +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
> > + .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
>
> Ditto.
>
> > + .hs400_calib_table = r8a7796_rev3_calib_table, };
> > +
> > +/*
> > + * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of
> now.
> > + * So, we want to treat them equally and only have a match for ES1.2
> > +to enforce
> > + * this if there ever will be a way to distinguish ES1.2.
> > + */
> > +static const struct soc_attr sdhi_quirks_match[] = {
> > + { .soc_id = "r8a774a1",
> > + .revision = "ES1.0",
> > + .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> > + },
> > + { .soc_id = "r8a774a1",
> > + .revision = "ES1.1",
> > + .data = &sdhi_quirks_4tap_nohs400
> > + },
> > + { .soc_id = "r8a774a1",
> > + .revision = "ES1.2",
> > + .data = &sdhi_quirks_r8a7796_es12
> > + },
> > + { .soc_id = "r8a774a1",
> > + .revision = "ES1.3",
> > + .data = &sdhi_quirks_r8a7796_es13
> > + },
> > + { .soc_id = "r8a7796",
> > + .revision = "ES1.0",
> > + .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> > + },
> > + { .soc_id = "r8a7796",
> > + .revision = "ES1.1",
> > + .data = &sdhi_quirks_4tap_nohs400
> > + },
> > + { .soc_id = "r8a7796",
> > + .revision = "ES1.2",
> > + .data = &sdhi_quirks_r8a7796_es12
> > + },
> > + { .soc_id = "r8a7796",
> > + .revision = "ES1.3",
> > + .data = &sdhi_quirks_r8a7796_es13
> > + },
> > + { /* Sentinel. */ },
> > +};
> > +
> > +static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
> > + struct tmio_sd_priv *priv,
> > + const struct renesas_sdhi_quirks *quirks) {
> > + priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
> > +
> > + if (quirks && quirks->hs400_disabled) {
> > + plat->cfg.host_caps &= ~MMC_MODE_HS400;
> > + if (quirks == &sdhi_quirks_4tap_nohs400_b17_dtrend)
> > + priv->read_poll_flag =
> TMIO_SD_DMA_INFO1_END_RD;
> > + }
> > +
> > + if (quirks && quirks->hs400_4taps)
> > + priv->nrtaps = 4;
> > + else
> > + priv->nrtaps = 8;
>
> priv->nrtraps = 8 should be default value.
> And it needs to check one time about quirks's present at first time.
> Then it can be changed to below..
Agreed. Will do this changes in next version.
Regards,
Biju
> priv->read_poll_flag = TMIO...;
> priv->nrtaps = 8;
>
> if (!quriks)
> return;
> if (quirks-.hs400_disabld) {
> ...
> }
>
> if (quirks->hs400_4taps)
> priv->nrtaps = 4;
>
> ...
>
> Then it's more readable..
>
> Best Regards,
> Jaehoon Chung
>
> > +
> > + if (quirks && quirks->hs400_bad_taps)
> > + priv->hs400_bad_tap = quirks->hs400_bad_taps;> +
> > + if (quirks && quirks->hs400_calib_table) {
> > + priv->adjust_hs400_enable = true;
> > + priv->adjust_hs400_calib_table =
> > + quirks-
> >hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
> > + if (quirks == &sdhi_quirks_r8a7796_es12)
> > + priv->adjust_hs400_offset = 3;
> > + else if (quirks == &sdhi_quirks_r8a7796_es13)
> > + priv->adjust_hs400_offset = 0;
> > + }
> > +}
> > +
> > static void renesas_sdhi_filter_caps(struct udevice *dev) {
> > struct tmio_sd_priv *priv = dev_get_priv(dev); @@ -866,6 +969,13
> @@
> > static void renesas_sdhi_filter_caps(struct udevice *dev)
> > CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
> > CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
> > struct tmio_sd_plat *plat = dev_get_platdata(dev);
> > + const struct soc_attr *attr;
> > +
> > + attr = soc_device_match(sdhi_quirks_match);
> > + if (attr) {
> > + renesas_sdhi_add_quirks(plat, priv, attr->data);
> > + return;
> > + }
> >
> > /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
> > if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
> >
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 6/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H
2020-11-02 21:47 ` Jaehoon Chung
@ 2020-11-03 10:18 ` Biju Das
0 siblings, 0 replies; 16+ messages in thread
From: Biju Das @ 2020-11-03 10:18 UTC (permalink / raw)
To: u-boot
Hi Jaehoon Chung,
Thanks for the feedback.
> Subject: Re: [PATCH v6 6/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3
> and RZ/G2H
>
> Hi,
>
> On 11/3/20 1:16 AM, Biju Das wrote:
> > Add SDHI quirks for R-Car H3 and RZ/G2H SoC.
>
> Does it needs to use quirks? IMO, Using fixup for each SoC is better than
> quirks.
This work is based on linux[1]. For maintainability we want to make u-boot code similar to linux, so that in future if there
is any improvement in linux we can port here easily.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mmc/host/renesas_sdhi_core.c?h=v5.10-rc2#n886
Regards,
Biju
>
> Best Regards,
> Jaehoon Chung
>
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-
> lad.rj at bp.renesas.com>
> > ---
> > v6: New patch. Quirks using soc_device_match.
> > ---
> > drivers/mmc/renesas-sdhi.c | 37
> ++++++++++++++++++++++++++++++++++++-
> > 1 file changed, 36 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> > index 0e4a44d973..e19daf8bf8 100644
> > --- a/drivers/mmc/renesas-sdhi.c
> > +++ b/drivers/mmc/renesas-sdhi.c
> > @@ -875,6 +875,16 @@ static const struct renesas_sdhi_quirks
> sdhi_quirks_4tap_nohs400 = {
> > .hs400_4taps = true,
> > };
> >
> > +static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
> > + .hs400_4taps = true,
> > + .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), };
> > +
> > +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7795_es30 = {
> > + .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
> > + .hs400_calib_table = r8a7795_calib_table, };
> > +
> > static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
> > .hs400_4taps = true,
> > .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), @@ -916,6
> > +926,30 @@ static const struct soc_attr sdhi_quirks_match[] = {
> > { .soc_id = "r8a774b1",
> > .data = &sdhi_quirks_r8a77965
> > },
> > + { .soc_id = "r8a774e1",
> > + .revision = "ES2.0",
> > + .data = &sdhi_quirks_4tap
> > + },
> > + { .soc_id = "r8a774e1",
> > + .revision = "ES3.0",
> > + .data = &sdhi_quirks_r8a7795_es30
> > + },
> > + { .soc_id = "r8a7795",
> > + .revision = "ES1.0",
> > + .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> > + },
> > + { .soc_id = "r8a7795",
> > + .revision = "ES1.1",
> > + .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> > + },
> > + { .soc_id = "r8a7795",
> > + .revision = "ES2.0",
> > + .data = &sdhi_quirks_4tap
> > + },
> > + { .soc_id = "r8a7795",
> > + .revision = "ES3.0",
> > + .data = &sdhi_quirks_r8a7795_es30
> > + },
> > { .soc_id = "r8a7796",
> > .revision = "ES1.0",
> > .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
> > @@ -965,7 +999,8 @@ static void renesas_sdhi_add_quirks(struct
> tmio_sd_plat *plat,
> > if (quirks == &sdhi_quirks_r8a7796_es12 ||
> > quirks == &sdhi_quirks_r8a77965)
> > priv->adjust_hs400_offset = 3;
> > - else if (quirks == &sdhi_quirks_r8a7796_es13)
> > + else if (quirks == &sdhi_quirks_r8a7796_es13 ||
> > + quirks == &sdhi_quirks_r8a7795_es30)
> > priv->adjust_hs400_offset = 0;
> > }
> > }
> >
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M
2020-11-03 10:15 ` Biju Das
@ 2020-11-03 10:28 ` Jaehoon Chung
0 siblings, 0 replies; 16+ messages in thread
From: Jaehoon Chung @ 2020-11-03 10:28 UTC (permalink / raw)
To: u-boot
On 11/3/20 7:15 PM, Biju Das wrote:
> Hi Jaehoon Chung,
>
> Thanks for the feedback.
>
>> Subject: Re: [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car
>> M3-W and RZ/G2M
>>
>> On 11/3/20 1:16 AM, Biju Das wrote:
>>> Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.
>>>
>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>>> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-
>> lad.rj at bp.renesas.com>
>>> ---
>>> drivers/mmc/renesas-sdhi.c | 110
>>> +++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 110 insertions(+)
>>>
>>> diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
>>> index d80b3fc28f..39deeb94d8 100644
>>> --- a/drivers/mmc/renesas-sdhi.c
>>> +++ b/drivers/mmc/renesas-sdhi.c
>>> @@ -19,6 +19,7 @@
>>> #include <linux/io.h>
>>> #include <linux/sizes.h>
>>> #include <power/regulator.h>
>>> +#include <soc.h>
>>> #include <asm/unaligned.h>
>>> #include "tmio-common.h"
>>>
>>> @@ -105,6 +106,15 @@ static const u8
>> r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
>>> 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
>>> };
>>>
>>> +#define SDHI_CALIB_TABLE_MAX 32
>>> +
>>> +struct renesas_sdhi_quirks {
>>> + bool hs400_disabled;
>>> + bool hs400_4taps;
>>> + u32 hs400_bad_taps;
>>> + const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
>>> +};
>>> +
>>> static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv) {
>>> /* On R-Car Gen3, MMC0 is at 0xee140000 */ @@ -855,6 +865,99 @@
>>> static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
>>> return clk_get_rate(&priv->clk);
>>> }
>>>
>>> +static const struct renesas_sdhi_quirks
>> sdhi_quirks_4tap_nohs400_b17_dtrend = {
>>> + .hs400_disabled = true,
>>> + .hs400_4taps = true,
>>> +};
>>> +
>>> +static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
>>> + .hs400_disabled = true,
>>> + .hs400_4taps = true,
>>> +};
>>> +
>>> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es12 = {
>>> + .hs400_4taps = true,
>>> + .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
>>
>> Use Macro, not magic code. We don't know what mean BIT(2), BIT(3), BIT(6)..
>
> This work is based on linux[1]. For maintainability we want to make u-boot code similar to linux, so that in future if there
> is any improvement in linux we can port here.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mmc/host/renesas_sdhi_core.c?h=v5.10-rc2#n886
I think that it needs to change to meaningful value in linux. :)
But I agreed that you want to maintain the similar code with linux.
Thanks for kindly explanation.
Best Regards,
Jaehoon Chung
>
>>
>>> + .hs400_calib_table = r8a7796_rev1_calib_table, };
>>> +
>>> +static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
>>> + .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
>>
>> Ditto.
>>
>>> + .hs400_calib_table = r8a7796_rev3_calib_table, };
>>> +
>>> +/*
>>> + * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of
>> now.
>>> + * So, we want to treat them equally and only have a match for ES1.2
>>> +to enforce
>>> + * this if there ever will be a way to distinguish ES1.2.
>>> + */
>>> +static const struct soc_attr sdhi_quirks_match[] = {
>>> + { .soc_id = "r8a774a1",
>>> + .revision = "ES1.0",
>>> + .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
>>> + },
>>> + { .soc_id = "r8a774a1",
>>> + .revision = "ES1.1",
>>> + .data = &sdhi_quirks_4tap_nohs400
>>> + },
>>> + { .soc_id = "r8a774a1",
>>> + .revision = "ES1.2",
>>> + .data = &sdhi_quirks_r8a7796_es12
>>> + },
>>> + { .soc_id = "r8a774a1",
>>> + .revision = "ES1.3",
>>> + .data = &sdhi_quirks_r8a7796_es13
>>> + },
>>> + { .soc_id = "r8a7796",
>>> + .revision = "ES1.0",
>>> + .data = &sdhi_quirks_4tap_nohs400_b17_dtrend
>>> + },
>>> + { .soc_id = "r8a7796",
>>> + .revision = "ES1.1",
>>> + .data = &sdhi_quirks_4tap_nohs400
>>> + },
>>> + { .soc_id = "r8a7796",
>>> + .revision = "ES1.2",
>>> + .data = &sdhi_quirks_r8a7796_es12
>>> + },
>>> + { .soc_id = "r8a7796",
>>> + .revision = "ES1.3",
>>> + .data = &sdhi_quirks_r8a7796_es13
>>> + },
>>> + { /* Sentinel. */ },
>>> +};
>>> +
>>> +static void renesas_sdhi_add_quirks(struct tmio_sd_plat *plat,
>>> + struct tmio_sd_priv *priv,
>>> + const struct renesas_sdhi_quirks *quirks) {
>>> + priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
>>> +
>>> + if (quirks && quirks->hs400_disabled) {
>>> + plat->cfg.host_caps &= ~MMC_MODE_HS400;
>>> + if (quirks == &sdhi_quirks_4tap_nohs400_b17_dtrend)
>>> + priv->read_poll_flag =
>> TMIO_SD_DMA_INFO1_END_RD;
>>> + }
>>> +
>>> + if (quirks && quirks->hs400_4taps)
>>> + priv->nrtaps = 4;
>>> + else
>>> + priv->nrtaps = 8;
>>
>> priv->nrtraps = 8 should be default value.
>> And it needs to check one time about quirks's present at first time.
>> Then it can be changed to below..
>
> Agreed. Will do this changes in next version.
>
> Regards,
> Biju
>
>> priv->read_poll_flag = TMIO...;
>> priv->nrtaps = 8;
>>
>> if (!quriks)
>> return;
>> if (quirks-.hs400_disabld) {
>> ...
>> }
>>
>> if (quirks->hs400_4taps)
>> priv->nrtaps = 4;
>>
>> ...
>>
>> Then it's more readable..
>>
>> Best Regards,
>> Jaehoon Chung
>>
>>> +
>>> + if (quirks && quirks->hs400_bad_taps)
>>> + priv->hs400_bad_tap = quirks->hs400_bad_taps;> +
>>> + if (quirks && quirks->hs400_calib_table) {
>>> + priv->adjust_hs400_enable = true;
>>> + priv->adjust_hs400_calib_table =
>>> + quirks-
>>> hs400_calib_table[!rmobile_is_gen3_mmc0(priv)];
>>> + if (quirks == &sdhi_quirks_r8a7796_es12)
>>> + priv->adjust_hs400_offset = 3;
>>> + else if (quirks == &sdhi_quirks_r8a7796_es13)
>>> + priv->adjust_hs400_offset = 0;
>>> + }
>>> +}
>>> +
>>> static void renesas_sdhi_filter_caps(struct udevice *dev) {
>>> struct tmio_sd_priv *priv = dev_get_priv(dev); @@ -866,6 +969,13
>> @@
>>> static void renesas_sdhi_filter_caps(struct udevice *dev)
>>> CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
>>> CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
>>> struct tmio_sd_plat *plat = dev_get_platdata(dev);
>>> + const struct soc_attr *attr;
>>> +
>>> + attr = soc_device_match(sdhi_quirks_match);
>>> + if (attr) {
>>> + renesas_sdhi_add_quirks(plat, priv, attr->data);
>>> + return;
>>> + }
>>>
>>> /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
>>> if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
>>>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support
2020-11-02 19:26 ` [PATCH v6 0/7] Add HiHope RZ/G2[HMN] " Marek Vasut
@ 2020-11-03 10:54 ` Biju Das
0 siblings, 0 replies; 16+ messages in thread
From: Biju Das @ 2020-11-03 10:54 UTC (permalink / raw)
To: u-boot
Hi Marek,
> Subject: Re: [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support
>
> On 11/2/20 5:16 PM, Biju Das wrote:
> > This patch series adds the required SoC/Board support to boot HopeRun
> > HiHope RZ/G2[HMN] boards.
> >
> > It uses SoC driver for unique cpu identification for RZ/G and R-Car
> > SoC's, since they share same PRR ID.
> >
> > SDHI quirks added using soc_device_match api.
>
> Can you please split this into driver patch series and board patch series ? And
> before you resend it, lets figure out the SoC identification first.
Ok, will split this series into driver patch series and board patch series. Will resend the patches after concluding SoC identification first.
Regards,
Biju
> Note that the driver patches look _much_ nicer, thanks.
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-11-03 10:54 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-02 16:16 [PATCH v6 0/7] Add HiHope RZ/G2[HMN] board support Biju Das
2020-11-02 16:16 ` [PATCH v6 1/7] arm: rmobile: Add RZ/G2[HMNE] SoC support Biju Das
2020-11-02 16:16 ` [PATCH v6 2/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-W and RZ/G2M Biju Das
2020-11-02 17:24 ` Biju Das
2020-11-02 21:41 ` Jaehoon Chung
2020-11-03 10:15 ` Biju Das
2020-11-03 10:28 ` Jaehoon Chung
2020-11-02 16:16 ` [PATCH v6 3/7] arm: rmobile: Add HopeRun HiHope RZ/G2M board support Biju Das
2020-11-02 16:16 ` [PATCH v6 4/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car M3-N and RZ/G2N Biju Das
2020-11-02 16:16 ` [PATCH v6 5/7] arm: rmobile: Add HopeRun HiHope RZ/G2N board support Biju Das
2020-11-02 16:16 ` [PATCH v6 6/7] mmc: renesas-sdhi: Add SDHI quirks for R-Car H3 and RZ/G2H Biju Das
2020-11-02 21:47 ` Jaehoon Chung
2020-11-03 10:18 ` Biju Das
2020-11-02 16:16 ` [PATCH v6 7/7] arm: rmobile: Add HopeRun HiHope RZ/G2H board support Biju Das
2020-11-02 19:26 ` [PATCH v6 0/7] Add HiHope RZ/G2[HMN] " Marek Vasut
2020-11-03 10:54 ` Biju Das
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