[PATCH 5.10.y-cip 0/5] Add SDHI support to the Renesas RZ/V2M

[PATCH 5.10.y-cip 0/5] Add SDHI support to the Renesas RZ/V2M

[Fabrizio Castro]

Dear All,

this series adds eMMC/SDHI support to the Renesas RZ/V2M SoC.

I would like to highlight that the driver patch looks fairly
different from upstream, and the reason for it is that the
SDHI IP found inside the RZ/V2M requires a couple of quirks.
The SDHI quirks have been reworked quite a bit over time, and
the implementation the upstream driver patch relies on depends
on changes spanning the renesas sdhi core, the renesas internal
DMAC implementation, and the CPG implemenation.
Considering the amount of patches that would need backporting
in order to get a similar solution to the one found upstream,
and considering that the changes would affect several platforms,
I thought that adapting the solution for the quirks found
upstream to the solution currently available in v5.10.y-cip is the
best way to go, as it adds the required support without introducing
unnecessary risks.

Cheers,
Fab

Fabrizio Castro (4):
  dt-bindings: mmc: renesas,sdhi: Document RZ/V2M support
  mmc: renesas_sdhi: Add RZ/V2M compatible string
  arm64: dts: renesas: r9a09g011: Add eMMC and SDHI support
  arm64: dts: renesas: rzv2mevk2: Add uSD card and eMMC support

Phil Edworthy (1):
  clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries

 .../devicetree/bindings/mmc/renesas,sdhi.yaml |   1 +
 .../boot/dts/renesas/r9a09g011-v2mevk2.dts    | 123 ++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi    |  48 +++++++
 drivers/clk/renesas/r9a09g011-cpg.c           |  20 +++
 drivers/mmc/host/renesas_sdhi_core.c          |   1 +
 drivers/mmc/host/renesas_sdhi_internal_dmac.c |   3 +
 6 files changed, 196 insertions(+)

-- 
2.25.1

[PATCH 5.10.y-cip 1/5] dt-bindings: mmc: renesas,sdhi: Document RZ/V2M support

[Fabrizio Castro]

Commit c9dc89944b66abf9aa0ad57aa45e4edf030e2441 upstream.

Document support for the SD Card/MMC interface on the Renesas
RZ/V2M (a.k.a. r9a09g011) SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221213230129.549968-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
 Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 19c9f1850528..91aa9b84d23f 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -59,6 +59,7 @@ properties:
               - renesas,sdhi-r9a07g043 # RZ/G2UL
               - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
               - renesas,sdhi-r9a07g054 # RZ/V2L
+              - renesas,sdhi-r9a09g011 # RZ/V2M
           - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
 
   reg:
-- 
2.25.1

[PATCH 5.10.y-cip 2/5] clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries

[Fabrizio Castro]

From: Phil Edworthy <phil.edworthy@renesas.com>

Commit d969103ac89de797fda351aa984f69602b149a72 upstream.

Add SDHI/eMMC clock/reset entries to CPG driver.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221213230129.549968-2-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
 drivers/clk/renesas/r9a09g011-cpg.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c
index 8ee4b5e27bdd..a3506abb990c 100644
--- a/drivers/clk/renesas/r9a09g011-cpg.c
+++ b/drivers/clk/renesas/r9a09g011-cpg.c
@@ -30,6 +30,7 @@
 #define SEL_B		SEL_PLL_PACK(0x214, 0, 1)
 #define SEL_D		SEL_PLL_PACK(0x214, 1, 1)
 #define SEL_E		SEL_PLL_PACK(0x214, 2, 1)
+#define SEL_SDI		SEL_PLL_PACK(0x300, 0, 1)
 #define SEL_W0		SEL_PLL_PACK(0x32C, 0, 1)
 
 enum clk_ids {
@@ -59,6 +60,7 @@ enum clk_ids {
 	CLK_SEL_B_D2,
 	CLK_SEL_D,
 	CLK_SEL_E,
+	CLK_SEL_SDI,
 	CLK_SEL_W0,
 
 	/* Module Clocks */
@@ -92,6 +94,7 @@ static const struct clk_div_table dtable_divd[] = {
 	{0, 0},
 };
 
+
 static const struct clk_div_table dtable_divw[] = {
 	{0, 6},
 	{1, 7},
@@ -108,6 +111,7 @@ static const char * const sel_b[] = { ".main", ".divb" };
 static const char * const sel_d[] = { ".main", ".divd" };
 static const char * const sel_e[] = { ".main", ".dive" };
 static const char * const sel_w[] = { ".main", ".divw" };
+static const char * const sel_sdi[] = { ".main", ".pll2_200" };
 
 static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
 	/* External Clock Inputs */
@@ -134,6 +138,7 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
 	DEF_MUX_RO(".selb",	CLK_SEL_B,	SEL_B,		sel_b),
 	DEF_MUX_RO(".seld",	CLK_SEL_D,	SEL_D,		sel_d),
 	DEF_MUX_RO(".sele",	CLK_SEL_E,	SEL_E,		sel_e),
+	DEF_MUX(".selsdi",	CLK_SEL_SDI,	SEL_SDI,	sel_sdi),
 	DEF_MUX(".selw0",	CLK_SEL_W0,	SEL_W0,		sel_w),
 
 	DEF_FIXED(".selb_d2",	CLK_SEL_B_D2,	CLK_SEL_B,	1,	2),
@@ -142,6 +147,18 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
 static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
 	DEF_MOD("pfc",		R9A09G011_PFC_PCLK,	 CLK_MAIN,     0x400, 2),
 	DEF_MOD("gic",		R9A09G011_GIC_CLK,	 CLK_SEL_B_D2, 0x400, 5),
+	DEF_MOD("sdi0_aclk",	R9A09G011_SDI0_ACLK,	 CLK_SEL_D,    0x408, 0),
+	DEF_MOD("sdi0_imclk",	R9A09G011_SDI0_IMCLK,	 CLK_SEL_SDI,  0x408, 1),
+	DEF_MOD("sdi0_imclk2",	R9A09G011_SDI0_IMCLK2,	 CLK_SEL_SDI,  0x408, 2),
+	DEF_MOD("sdi0_clk_hs",	R9A09G011_SDI0_CLK_HS,	 CLK_PLL2_800, 0x408, 3),
+	DEF_MOD("sdi1_aclk",	R9A09G011_SDI1_ACLK,	 CLK_SEL_D,    0x408, 4),
+	DEF_MOD("sdi1_imclk",	R9A09G011_SDI1_IMCLK,	 CLK_SEL_SDI,  0x408, 5),
+	DEF_MOD("sdi1_imclk2",	R9A09G011_SDI1_IMCLK2,	 CLK_SEL_SDI,  0x408, 6),
+	DEF_MOD("sdi1_clk_hs",	R9A09G011_SDI1_CLK_HS,	 CLK_PLL2_800, 0x408, 7),
+	DEF_MOD("emm_aclk",	R9A09G011_EMM_ACLK,	 CLK_SEL_D,    0x408, 8),
+	DEF_MOD("emm_imclk",	R9A09G011_EMM_IMCLK,	 CLK_SEL_SDI,  0x408, 9),
+	DEF_MOD("emm_imclk2",	R9A09G011_EMM_IMCLK2,	 CLK_SEL_SDI,  0x408, 10),
+	DEF_MOD("emm_clk_hs",	R9A09G011_EMM_CLK_HS,	 CLK_PLL2_800, 0x408, 11),
 	DEF_COUPLED("eth_axi",	R9A09G011_ETH0_CLK_AXI,	 CLK_PLL2_200, 0x40c, 8),
 	DEF_COUPLED("eth_chi",	R9A09G011_ETH0_CLK_CHI,	 CLK_PLL2_100, 0x40c, 8),
 	DEF_MOD("eth_clk_gptp",	R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
@@ -178,6 +195,9 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
 
 static const struct rzg2l_reset r9a09g011_resets[] = {
 	DEF_RST(R9A09G011_PFC_PRESETN,		0x600, 2),
+	DEF_RST_MON(R9A09G011_SDI0_IXRST,	0x608, 0,  6),
+	DEF_RST_MON(R9A09G011_SDI1_IXRST,	0x608, 1,  7),
+	DEF_RST_MON(R9A09G011_EMM_IXRST,	0x608, 2,  8),
 	DEF_RST(R9A09G011_USB_PRESET_N,		0x608, 7),
 	DEF_RST(R9A09G011_USB_DRD_RESET,	0x608, 8),
 	DEF_RST(R9A09G011_USB_ARESETN_P,	0x608, 9),
-- 
2.25.1

[PATCH 5.10.y-cip 3/5] mmc: renesas_sdhi: Add RZ/V2M compatible string

[Fabrizio Castro]

Commit 08e03039e0000a7ec7ba13dc18bddc6afd32cb27 upstream.

The SDHI/eMMC IPs found with the RZ/V2M (a.k.a. r9a09g011), are
very similar to the ones found in R-Car Gen3, but they are not
exactly the same, and as a result need an SoC specific compatible
string for fine tuning driver support.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221213230129.549968-4-fabrizio.castro.jz@renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
[Fabrizio: Adapted data structures to what's available in v5.10.y-cip ]
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
 drivers/mmc/host/renesas_sdhi_core.c          | 1 +
 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index b96f16ed6fd5..ab6c3d6fcc63 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -964,6 +964,7 @@ static const struct soc_device_attribute sdhi_quirks_match[]  = {
 	{ .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 },
 	{ .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
 	{ .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 },
+	{ .soc_id = "r9a09g011", .data = &sdhi_quirks_nohs400 },
 	{ /* Sentinel. */ },
 };
 
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index bc6040be657b..c6ddfe8215c7 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -127,6 +127,7 @@ static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
 	{ .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, },
 	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
 	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
+	{ .compatible = "renesas,sdhi-r9a09g011", .data = &of_rcar_gen3_compatible, },
 	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
 	{},
 };
@@ -400,6 +401,8 @@ static const struct soc_device_attribute soc_dma_quirks[] = {
 	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
 	{ .soc_id = "r8a7796", .revision = "ES1.0",
 	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
+	{ .soc_id = "r9a09g011",
+	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) },
 	{ /* sentinel */ }
 };
 
-- 
2.25.1

[PATCH 5.10.y-cip 4/5] arm64: dts: renesas: r9a09g011: Add eMMC and SDHI support

[Fabrizio Castro]

Commit 36aa3eee39b2bce5596d3a1178d3c381c1cf3b57 upstream.

The RZ/V2M comes with 2 SDHI interfaces and 1 eMMC interface.
Add the relevant nodes to the SoC specific device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221213230129.549968-5-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 48 ++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index d3af097f5fae..46d67b200a66 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -69,6 +69,54 @@ gic: interrupt-controller@82010000 {
 			clock-names = "clk";
 		};
 
+		sdhi0: mmc@85000000 {
+			compatible = "renesas,sdhi-r9a09g011",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0x0 0x85000000 0 0x2000>;
+			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
+				 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
+				 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
+				 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
+			clock-names = "core", "clkh", "cd", "aclk";
+			resets = <&cpg R9A09G011_SDI0_IXRST>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		sdhi1: mmc@85010000  {
+			compatible = "renesas,sdhi-r9a09g011",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0x0 0x85010000 0 0x2000>;
+			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
+				 <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>,
+				 <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>,
+				 <&cpg CPG_MOD R9A09G011_SDI1_ACLK>;
+			clock-names = "core", "clkh", "cd", "aclk";
+			resets = <&cpg R9A09G011_SDI1_IXRST>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		emmc: mmc@85020000  {
+			compatible = "renesas,sdhi-r9a09g011",
+				     "renesas,rcar-gen3-sdhi";
+			reg = <0x0 0x85020000 0 0x2000>;
+			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>,
+				 <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>,
+				 <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>,
+				 <&cpg CPG_MOD R9A09G011_EMM_ACLK>;
+			clock-names = "core", "clkh", "cd", "aclk";
+			resets = <&cpg R9A09G011_EMM_IXRST>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		usb3drd: usb3drd@85070400 {
 			compatible = "renesas,r9a09g011-usb3drd",
 				     "renesas,rzv2m-usb3drd";
-- 
2.25.1

[PATCH 5.10.y-cip 5/5] arm64: dts: renesas: rzv2mevk2: Add uSD card and eMMC support

[Fabrizio Castro]

Commit b6c0be722b0c0a7204b6289464a04cd7b4fdfca0 upstream.

The RZ/V2M EVK comes with a slot for a uSD card, and an eMMC.
Add support for the both of them.

Please note that the pinctrl driver for RZ/V2M doesn't support
interrupts yet, therefore the card detect pin has been connected
to the SDHI IP directly in this patch.
We'll connect the card detect pin to its corresponding GPIO when
we'll have driver support for interrupts in the RZ/V2M pinctrl
driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230130191152.182826-1-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[Fabrizio: Changed the eMMC/SDHI pinctrl subnode names to avoid
           conflicts during parsing]
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
 .../boot/dts/renesas/r9a09g011-v2mevk2.dts    | 123 ++++++++++++++++++
 1 file changed, 123 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
index 8b7f6da693a7..11c5cffea5a5 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 #include "r9a09g011.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
 
 / {
@@ -60,6 +61,36 @@ memory@180000000 {
 		device_type = "memory";
 		reg = <0x1 0x80000000 0x0 0x80000000>;
 	};
+
+	reg_1v8: regulator-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3v3: regulator-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vccq_sdhi0: regulator-vccq-sdhi0 {
+		compatible = "regulator-gpio";
+
+		regulator-name = "SDHI0 VccQ";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&pwc 0 GPIO_ACTIVE_HIGH>;
+		gpios-states = <1>;
+		states = <3300000 0>, <1800000 1>;
+	};
 };
 
 &avb {
@@ -75,6 +106,23 @@ phy0: ethernet-phy@0 {
 	};
 };
 
+&emmc {
+	pinctrl-0 = <&emmc_pins>;
+	pinctrl-1 = <&emmc_pins>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&reg_3v3>;
+	vqmmc-supply = <&reg_1v8>;
+	bus-width = <8>;
+	mmc-hs200-1_8v;
+	no-sd;
+	no-sdio;
+	non-removable;
+	fixed-emmc-driver-type = <1>;
+	max-frequency = <200000000>;
+	status = "okay";
+};
+
 &extal_clk {
 	clock-frequency = <48000000>;
 };
@@ -118,6 +166,26 @@ &i2c2 {
 };
 
 &pinctrl {
+	emmc_pins: emmc {
+		emmc_data {
+			pinmux = <RZV2M_PORT_PINMUX(0, 0, 2)>, /* MMDAT0 */
+				 <RZV2M_PORT_PINMUX(0, 1, 2)>, /* MMDAT1 */
+				 <RZV2M_PORT_PINMUX(0, 2, 2)>, /* MMDAT2 */
+				 <RZV2M_PORT_PINMUX(0, 3, 2)>, /* MMDAT3 */
+				 <RZV2M_PORT_PINMUX(0, 4, 2)>, /* MMDAT4 */
+				 <RZV2M_PORT_PINMUX(0, 5, 2)>, /* MMDAT5 */
+				 <RZV2M_PORT_PINMUX(0, 6, 2)>, /* MMDAT6 */
+				 <RZV2M_PORT_PINMUX(0, 7, 2)>; /* MMDAT7 */
+			power-source = <1800>;
+		};
+
+		emmc_ctrl {
+			pinmux = <RZV2M_PORT_PINMUX(0, 10, 2)>, /* MMCMD */
+				 <RZV2M_PORT_PINMUX(0, 11, 2)>; /* MMCLK */
+			power-source = <1800>;
+		};
+	};
+
 	i2c0_pins: i2c0 {
 		pinmux = <RZV2M_PORT_PINMUX(5, 0, 2)>, /* SDA */
 			 <RZV2M_PORT_PINMUX(5, 1, 2)>; /* SCL */
@@ -128,6 +196,48 @@ i2c2_pins: i2c2 {
 			 <RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */
 	};
 
+	sdhi0_pins: sd0 {
+		sd0_data {
+			pinmux = <RZV2M_PORT_PINMUX(8, 2, 1)>, /* SD0DAT0 */
+				 <RZV2M_PORT_PINMUX(8, 3, 1)>, /* SD0DAT1 */
+				 <RZV2M_PORT_PINMUX(8, 4, 1)>, /* SD0DAT2 */
+				 <RZV2M_PORT_PINMUX(8, 5, 1)>; /* SD0DAT3 */
+			power-source = <3300>;
+		};
+
+		sd0_ctrl {
+			pinmux = <RZV2M_PORT_PINMUX(8, 0, 1)>, /* SD0CMD */
+				 <RZV2M_PORT_PINMUX(8, 1, 1)>; /* SD0CLK */
+			power-source = <3300>;
+		};
+
+		sd0_cd {
+			pinmux = <RZV2M_PORT_PINMUX(8, 7, 1)>; /* SD0CD */
+			power-source = <3300>;
+		};
+	};
+
+	sdhi0_pins_uhs: sd0-uhs {
+		sd0_uhs_data {
+			pinmux = <RZV2M_PORT_PINMUX(8, 2, 1)>, /* SD0DAT0 */
+				 <RZV2M_PORT_PINMUX(8, 3, 1)>, /* SD0DAT1 */
+				 <RZV2M_PORT_PINMUX(8, 4, 1)>, /* SD0DAT2 */
+				 <RZV2M_PORT_PINMUX(8, 5, 1)>; /* SD0DAT3 */
+			power-source = <1800>;
+		};
+
+		sd0_uhs_ctrl {
+			pinmux = <RZV2M_PORT_PINMUX(8, 0, 1)>, /* SD0CMD */
+				 <RZV2M_PORT_PINMUX(8, 1, 1)>; /* SD0CLK */
+			power-source = <1800>;
+		};
+
+		sd0_uhs_cd {
+			pinmux = <RZV2M_PORT_PINMUX(8, 7, 1)>; /* SD0CD */
+			power-source = <1800>;
+		};
+	};
+
 	uart0_pins: uart0 {
 		pinmux = <RZV2M_PORT_PINMUX(3, 0, 2)>, /* UATX0 */
 			 <RZV2M_PORT_PINMUX(3, 1, 2)>, /* UARX0 */
@@ -141,6 +251,19 @@ &pwc {
 	status = "okay";
 };
 
+&sdhi0 {
+	pinctrl-0 = <&sdhi0_pins>;
+	pinctrl-1 = <&sdhi0_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
+
+	vmmc-supply = <&reg_3v3>;
+	vqmmc-supply = <&vccq_sdhi0>;
+	bus-width = <4>;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-0 = <&uart0_pins>;
 	pinctrl-names = "default";
-- 
2.25.1

RE: [PATCH 5.10.y-cip 0/5] Add SDHI support to the Renesas RZ/V2M

[nobuhiro1.iwamatsu]

Hi Fabrizio,

> -----Original Message-----
> From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Sent: Tuesday, July 4, 2023 2:17 AM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ□
> ＤＩＴ○ＯＳＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>
> Cc: Biju Das <biju.das@bp.renesas.com>; Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Fabrizio Castro
> <fabrizio.castro.jz@renesas.com>
> Subject: [PATCH 5.10.y-cip 0/5] Add SDHI support to the Renesas RZ/V2M
> 
> Dear All,
> 
> this series adds eMMC/SDHI support to the Renesas RZ/V2M SoC.
> 
> I would like to highlight that the driver patch looks fairly different from upstream,
> and the reason for it is that the SDHI IP found inside the RZ/V2M requires a
> couple of quirks.
> The SDHI quirks have been reworked quite a bit over time, and the
> implementation the upstream driver patch relies on depends on changes
> spanning the renesas sdhi core, the renesas internal DMAC implementation,
> and the CPG implemenation.
> Considering the amount of patches that would need backporting in order to get
> a similar solution to the one found upstream, and considering that the changes
> would affect several platforms, I thought that adapting the solution for the
> quirks found upstream to the solution currently available in v5.10.y-cip is the
> best way to go, as it adds the required support without introducing
> unnecessary risks.
> 
> Cheers,
> Fab
> 
> Fabrizio Castro (4):
>   dt-bindings: mmc: renesas,sdhi: Document RZ/V2M support
>   mmc: renesas_sdhi: Add RZ/V2M compatible string
>   arm64: dts: renesas: r9a09g011: Add eMMC and SDHI support
>   arm64: dts: renesas: rzv2mevk2: Add uSD card and eMMC support
> 
> Phil Edworthy (1):
>   clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries
> 

I reviewed the patch and found no issues.
I can apply, if there are no comments and issues.

Test: https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/919945015
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

Best regards,
  Nobuhiro

Re: [PATCH 5.10.y-cip 0/5] Add SDHI support to the Renesas RZ/V2M

[Pavel Machek]

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Hi!

> > Fabrizio Castro (4):
> >   dt-bindings: mmc: renesas,sdhi: Document RZ/V2M support
> >   mmc: renesas_sdhi: Add RZ/V2M compatible string
> >   arm64: dts: renesas: r9a09g011: Add eMMC and SDHI support
> >   arm64: dts: renesas: rzv2mevk2: Add uSD card and eMMC support
> > 
> > Phil Edworthy (1):
> >   clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries
> > 
> 
> I reviewed the patch and found no issues.
> I can apply, if there are no comments and issues.
> 
> Test: https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/919945015
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

There's an extra empty line in 2/5, but that's too minor detail to be
worth fixing.

Reviewed-by: Pavel Machek <pavel@denx.de>

We'll need similar series for 6.1, AFAICT.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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RE: [PATCH 5.10.y-cip 0/5] Add SDHI support to the Renesas RZ/V2M

[Fabrizio Castro]

Hi Pavel,

Thanks for your feedback.

> From: Pavel Machek <pavel@denx.de>
> Subject: Re: [PATCH 5.10.y-cip 0/5] Add SDHI support to the Renesas
> RZ/V2M
> 
> Hi!
> 
> > > Fabrizio Castro (4):
> > >   dt-bindings: mmc: renesas,sdhi: Document RZ/V2M support
> > >   mmc: renesas_sdhi: Add RZ/V2M compatible string
> > >   arm64: dts: renesas: r9a09g011: Add eMMC and SDHI support
> > >   arm64: dts: renesas: rzv2mevk2: Add uSD card and eMMC support
> > >
> > > Phil Edworthy (1):
> > >   clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries
> > >
> >
> > I reviewed the patch and found no issues.
> > I can apply, if there are no comments and issues.
> >
> > Test: https://gitlab.com/cip-project/cip-kernel/linux-cip/-
> /pipelines/919945015
> > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> 
> There's an extra empty line in 2/5, but that's too minor detail to be
> worth fixing.
> 
> Reviewed-by: Pavel Machek <pavel@denx.de>
> 
> We'll need similar series for 6.1, AFAICT.

Yes, I will send a similar series for 6.1 soon.

Cheers,
Fab

> 
> Best regards,
> 								Pavel
> --
> DENX Software Engineering GmbH,        Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

RE: [PATCH 5.10.y-cip 0/5] Add SDHI support to the Renesas RZ/V2M

[Fabrizio Castro]

Hi Iwamatsu-san,

Thanks your reply!

> From: nobuhiro1.iwamatsu@toshiba.co.jp
> Subject: RE: [PATCH 5.10.y-cip 0/5] Add SDHI support to the Renesas
> RZ/V2M
> 
> Hi Fabrizio,
> 
> > -----Original Message-----
> > From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > Sent: Tuesday, July 4, 2023 2:17 AM
> > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ
> □
> > ＤＩＴ○ＯＳＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> > <pavel@denx.de>
> > Cc: Biju Das <biju.das@bp.renesas.com>; Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com>; Chris Paterson
> > <Chris.Paterson2@renesas.com>; Fabrizio Castro
> > <fabrizio.castro.jz@renesas.com>
> > Subject: [PATCH 5.10.y-cip 0/5] Add SDHI support to the Renesas
> RZ/V2M
> >
> > Dear All,
> >
> > this series adds eMMC/SDHI support to the Renesas RZ/V2M SoC.
> >
> > I would like to highlight that the driver patch looks fairly
> different from upstream,
> > and the reason for it is that the SDHI IP found inside the RZ/V2M
> requires a
> > couple of quirks.
> > The SDHI quirks have been reworked quite a bit over time, and the
> > implementation the upstream driver patch relies on depends on
> changes
> > spanning the renesas sdhi core, the renesas internal DMAC
> implementation,
> > and the CPG implemenation.
> > Considering the amount of patches that would need backporting in
> order to get
> > a similar solution to the one found upstream, and considering that
> the changes
> > would affect several platforms, I thought that adapting the solution
> for the
> > quirks found upstream to the solution currently available in
> v5.10.y-cip is the
> > best way to go, as it adds the required support without introducing
> > unnecessary risks.
> >
> > Cheers,
> > Fab
> >
> > Fabrizio Castro (4):
> >   dt-bindings: mmc: renesas,sdhi: Document RZ/V2M support
> >   mmc: renesas_sdhi: Add RZ/V2M compatible string
> >   arm64: dts: renesas: r9a09g011: Add eMMC and SDHI support
> >   arm64: dts: renesas: rzv2mevk2: Add uSD card and eMMC support
> >
> > Phil Edworthy (1):
> >   clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries
> >
> 
> I reviewed the patch and found no issues.
> I can apply, if there are no comments and issues.

I think this series is safe to apply, as no issues have been highlighted
from the reviews.

Thanks,
Fab

> 
> 
> Best regards,
>   Nobuhiro

Re: [PATCH 5.10.y-cip 0/5] Add SDHI support to the Renesas RZ/V2M

[Pavel Machek]

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Hi!

> > I reviewed the patch and found no issues.
> > I can apply, if there are no comments and issues.
> 
> I think this series is safe to apply, as no issues have been highlighted
> from the reviews.

Let me take a look. Patches apply ok, I'm now running tests.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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Re: [PATCH 5.10.y-cip 0/5] Add SDHI support to the Renesas RZ/V2M

[Pavel Machek]

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Hi!

> > I reviewed the patch and found no issues.
> > I can apply, if there are no comments and issues.
> 
> I think this series is safe to apply, as no issues have been highlighted
> from the reviews.

Thank you, applied.

I'm not aware of any other patches in the pipeline; if there's
anything I am missing, let me know.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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