RE: [PATCH v3] clk: renesas: cpg-mssr: Add R7S9210 support

[Chris Brandt <Chris.Brandt@renesas.com>]

Hi Geert,

On Wednesday, September 05, 2018 1, Geert Uytterhoeven wrote:
> > So....I guess I didn't really have an issue after all.
> 
> You do want to:
>   1. Document the two register ranges in the DT bindings,
>   2. Update the driver to map both ranges on RZ/A2.

The driver does not need to be updated.

Given this mapping:

	cpg: clock-controller@fcfe0020 {
		compatible = "renesas,r7s9210-cpg-mssr";
		reg = <0xfcfe0010 0x455>;  /* FCFE0010 - FCFE0465 */
		clocks = <&extal_clk>;
		clock-names = "extal";
		#clock-cells = <2>;
		#power-domain-cells = <0>;
		#reset-cells = <1>;
	};

This covers all the CPG, MSTP, power down and reset registers.

So I'm just going to map them all at once.

And, you can see that some CPG and MSTP register are mixed together.
Here is the list of registers in address order:

 FRQCR   FCFE_0010  (CPG)
STBCR1   FCFE_0020  (MSTP)
STBCR2   FCFE_0024  (MSTP)
CKIOSEL  FCFE_0100  (CPG)
SCLKSEL  FCFE_0104  (CPG)
STBCR3   FCFE_0420  (MSTP)
STBCR4   FCFE_0424  (MSTP)
STBCR5   FCFE_0428  (MSTP)
STBCR6   FCFE_042C  (MSTP)
STBCR7   FCFE_0430  (MSTP)
STBCR8   FCFE_0434  (MSTP)
STBCR9   FCFE_0438  (MSTP)
STBCR10  FCFE_043C  (MSTP)
SWRSTCR1 FCFE_0460  (RESET)
SWRSTCR2 FCFE_0464  (RESET)
  etc...

So this should be all one memory block in this driver.

When you get to FCFF_C000+, that's where the 'specialty' registers are. 
I think FCFF_C000+ should be a separate block, maybe in a separate driver.


Chris