[PATCH v2 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support

[PATCH v2 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support

[Phil Edworthy]

Hello,

RZ/V2M has a dual-core Cortex-A53 (1.0 GHz) CPU and built-in AI
accelerator "DRP-AI" for vision, which is Renesas' original technology.
It also has a 32-bit LPDDR4 interface and video codec (H.264).

The RZ/V2M is used with ISP firmware that runs on one of the Cortex-A53
cores. The firmware is an integral part of the SoC such that the HW
User's Manual documents which of the peripheral modules are used by the
firmware.

Initial patches enables minimal peripherals on Renesas RZ/V2M EVK board
and booted via nfs. Ethernet is broadly compatible with the
etheravb-rcar-gen3 driver, but interrupts need some work so it's not
been included in this patch set.

Below blocks are enabled on Renesas RZ/V2M EVK board:
- memory
- External input clock
- CPG
- UART

Links for SoC and EVK:
[*] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output


Sorry for cross posting the patches to multiple subsystems, as these are
just the dt-binding patches included as part of initial bringup patches.

v2:
 * Removed SYS dt-bindings patch and corresponding SoC identification
   as we only used the LSI version register. This can be dealt with
   later on.
 * Fixed em-uart dt-bindings.
 * Included reviewed-by tags.

Thanks
Phil

[PATCH v2 01/13] dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK board

[Phil Edworthy]

Details of the SoC can be found here:
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output

The RZ/V2M Evaluation Kit (V2MEVK) consists of the RZ/V2M Main Board,
RZ/V2M Base Board, and CIS IMX415 Board (CIS).

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 Documentation/devicetree/bindings/arm/renesas.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index fa435d6fda77..9a9f16a58359 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -430,6 +430,12 @@ properties:
               - renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
           - const: renesas,r9a07g054
 
+      - description: RZ/V2M (R9A09G011)
+        items:
+          - enum:
+              - renesas,rzv2mevk2   # RZ/V2M Eval Board v2.0
+          - const: renesas,r9a09g011
+
 additionalProperties: true
 
 ...
-- 
2.32.0

Re: [PATCH v2 01/13] dt-bindings: arm: renesas: Document Renesas RZ/V2M SoC and EVK board

[Geert Uytterhoeven]

On Wed, Mar 30, 2022 at 5:40 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> Details of the SoC can be found here:
> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output
>
> The RZ/V2M Evaluation Kit (V2MEVK) consists of the RZ/V2M Main Board,
> RZ/V2M Base Board, and CIS IMX415 Board (CIS).
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Phil Edworthy]

The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with the
EMMA Mobile SoC.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2: Fix dtbs_check by adding missing alternative binding
---
 .../devicetree/bindings/serial/renesas,em-uart.yaml      | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
index e98ec48fee46..332c385618e1 100644
--- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
@@ -14,7 +14,14 @@ allOf:
 
 properties:
   compatible:
-    const: renesas,em-uart
+    oneOf:
+      - items:
+          - enum:
+              - renesas,r9a09g011-uart    # RZ/V2M
+          - const: renesas,em-uart        # generic EMMA Mobile compatible UART
+
+      - items:
+          - const: renesas,em-uart        # generic EMMA Mobile compatible UART
 
   reg:
     maxItems: 1
-- 
2.32.0

Re: [PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Rob Herring]

On Wed, 30 Mar 2022 16:40:13 +0100, Phil Edworthy wrote:
> The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with the
> EMMA Mobile SoC.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2: Fix dtbs_check by adding missing alternative binding
> ---
>  .../devicetree/bindings/serial/renesas,em-uart.yaml      | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Geert Uytterhoeven]

Hi Phil,

On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with the
> EMMA Mobile SoC.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2: Fix dtbs_check by adding missing alternative binding

Thanks for your patch, which is now commit 7bb301812b628099
("dt-bindings: serial: renesas,em-uart: Document r9a09g011
bindings") in tty/tty-next.

> --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> @@ -14,7 +14,14 @@ allOf:
>
>  properties:
>    compatible:
> -    const: renesas,em-uart
> +    oneOf:
> +      - items:
> +          - enum:
> +              - renesas,r9a09g011-uart    # RZ/V2M
> +          - const: renesas,em-uart        # generic EMMA Mobile compatible UART
> +
> +      - items:
> +          - const: renesas,em-uart        # generic EMMA Mobile compatible UART

The above looks good to me.

>
>    reg:
>      maxItems: 1

However, unlike EMEV2, RZ/V2M defines two clocks: pclk and sclk.
Hence please update the clocks section to reflect that.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Phil Edworthy]

Hi Geert,

(updated Krzysztof's email)

On 20 April 2022 22:26 Geert Uytterhoeven wrote:
> On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy <phil.edworthy@renesas.com>
> wrote:
> > The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with
> the
> > EMMA Mobile SoC.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2: Fix dtbs_check by adding missing alternative binding
> 
> Thanks for your patch, which is now commit 7bb301812b628099
> ("dt-bindings: serial: renesas,em-uart: Document r9a09g011
> bindings") in tty/tty-next.
> 
> > --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > @@ -14,7 +14,14 @@ allOf:
> >
> >  properties:
> >    compatible:
> > -    const: renesas,em-uart
> > +    oneOf:
> > +      - items:
> > +          - enum:
> > +              - renesas,r9a09g011-uart    # RZ/V2M
> > +          - const: renesas,em-uart        # generic EMMA Mobile
> compatible UART
> > +
> > +      - items:
> > +          - const: renesas,em-uart        # generic EMMA Mobile
> compatible UART
> 
> The above looks good to me.
> 
> >
> >    reg:
> >      maxItems: 1
> 
> However, unlike EMEV2, RZ/V2M defines two clocks: pclk and sclk.
> Hence please update the clocks section to reflect that.
You are right that the uart has two clocks.

Note though that pclk is shared by both uarts. The HW manual says:
"ch. 1 is for use with the ISP support package, so do not
use registers related to this channel.". Due to this, section
48.5.2.50 Clock ON/OFF Control Register 15 (CPG_CLK_ON15) says
that bit 20, CLK4_ONWEN (enable for URT_PCLK) should be written
as 0.

I took this to mean that the URT_PCLK is enabled by the ISP firmware
and software must not touch it. I am not sure if the DT bindings
should document a clock that is specified as do not touch in the
HW manual. This is a bit of a grey area.

Thanks
Phil

Re: [PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Geert Uytterhoeven]

Hi Phil,

On Fri, Apr 22, 2022 at 10:28 AM Phil Edworthy
<phil.edworthy@renesas.com> wrote:
> On 20 April 2022 22:26 Geert Uytterhoeven wrote:
> > On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy <phil.edworthy@renesas.com>
> > wrote:
> > > The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with
> > the
> > > EMMA Mobile SoC.
> > >
> > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > > v2: Fix dtbs_check by adding missing alternative binding
> >
> > Thanks for your patch, which is now commit 7bb301812b628099
> > ("dt-bindings: serial: renesas,em-uart: Document r9a09g011
> > bindings") in tty/tty-next.
> >
> > > --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > > +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > > @@ -14,7 +14,14 @@ allOf:
> > >
> > >  properties:
> > >    compatible:
> > > -    const: renesas,em-uart
> > > +    oneOf:
> > > +      - items:
> > > +          - enum:
> > > +              - renesas,r9a09g011-uart    # RZ/V2M
> > > +          - const: renesas,em-uart        # generic EMMA Mobile
> > compatible UART
> > > +
> > > +      - items:
> > > +          - const: renesas,em-uart        # generic EMMA Mobile
> > compatible UART
> >
> > The above looks good to me.
> >
> > >
> > >    reg:
> > >      maxItems: 1
> >
> > However, unlike EMEV2, RZ/V2M defines two clocks: pclk and sclk.
> > Hence please update the clocks section to reflect that.
> You are right that the uart has two clocks.
>
> Note though that pclk is shared by both uarts. The HW manual says:
> "ch. 1 is for use with the ISP support package, so do not
> use registers related to this channel.". Due to this, section
> 48.5.2.50 Clock ON/OFF Control Register 15 (CPG_CLK_ON15) says
> that bit 20, CLK4_ONWEN (enable for URT_PCLK) should be written
> as 0.
>
> I took this to mean that the URT_PCLK is enabled by the ISP firmware
> and software must not touch it. I am not sure if the DT bindings
> should document a clock that is specified as do not touch in the
> HW manual. This is a bit of a grey area.

"DT describes hardware, not software policy".

But I agree this is a grey area.

One option would be to mark URT_PCLK critical, so it won't be disabled.
But that would still mean it's enabled by Linux, i.e. Linux would set
CLK4_ONWEN to 1 while enabling the clock.

Another option would be to create URT_PCLK as a non-gateable clock,
so Linux won't ever touch the register bits.

Or just ignore URT_PCLK and do nothing, like you did ;-)
Would it be possible for a user to not use the ISP firmware at all,
and go full Linux, hence using both UART channels and URT_PCLK?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Phil Edworthy]

Hi Geert,

On 22 April 2022 09:45 Geert Uytterhoeven wrote:
> On Fri, Apr 22, 2022 at 10:28 AM Phil Edworthy wrote:
> > On 20 April 2022 22:26 Geert Uytterhoeven wrote:
> > > On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy wrote:
> > > > The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible
> with
> > > the
> > > > EMMA Mobile SoC.
> > > >
> > > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > ---
> > > > v2: Fix dtbs_check by adding missing alternative binding
> > >
> > > Thanks for your patch, which is now commit 7bb301812b628099
> > > ("dt-bindings: serial: renesas,em-uart: Document r9a09g011
> > > bindings") in tty/tty-next.
> > >
> > > > --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > > > +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > > > @@ -14,7 +14,14 @@ allOf:
> > > >
> > > >  properties:
> > > >    compatible:
> > > > -    const: renesas,em-uart
> > > > +    oneOf:
> > > > +      - items:
> > > > +          - enum:
> > > > +              - renesas,r9a09g011-uart    # RZ/V2M
> > > > +          - const: renesas,em-uart        # generic EMMA Mobile
> > > compatible UART
> > > > +
> > > > +      - items:
> > > > +          - const: renesas,em-uart        # generic EMMA Mobile
> > > compatible UART
> > >
> > > The above looks good to me.
> > >
> > > >
> > > >    reg:
> > > >      maxItems: 1
> > >
> > > However, unlike EMEV2, RZ/V2M defines two clocks: pclk and sclk.
> > > Hence please update the clocks section to reflect that.
> > You are right that the uart has two clocks.
> >
> > Note though that pclk is shared by both uarts. The HW manual says:
> > "ch. 1 is for use with the ISP support package, so do not
> > use registers related to this channel.". Due to this, section
> > 48.5.2.50 Clock ON/OFF Control Register 15 (CPG_CLK_ON15) says
> > that bit 20, CLK4_ONWEN (enable for URT_PCLK) should be written
> > as 0.
> >
> > I took this to mean that the URT_PCLK is enabled by the ISP firmware
> > and software must not touch it. I am not sure if the DT bindings
> > should document a clock that is specified as do not touch in the
> > HW manual. This is a bit of a grey area.
> 
> "DT describes hardware, not software policy".
> 
> But I agree this is a grey area.
I wish the HW manual either didn’t mention this clock that you should
not touch, or didn’t specify anything as "used by the ISP firmware" :)

> One option would be to mark URT_PCLK critical, so it won't be disabled.
> But that would still mean it's enabled by Linux, i.e. Linux would set
> CLK4_ONWEN to 1 while enabling the clock.
> 
> Another option would be to create URT_PCLK as a non-gateable clock,
> so Linux won't ever touch the register bits.
> 
> Or just ignore URT_PCLK and do nothing, like you did ;-)
> Would it be possible for a user to not use the ISP firmware at all,
> and go full Linux, hence using both UART channels and URT_PCLK?
It is possible to not use the ISP firmware, but them what do we do?
Ignore everything in the HW manual that says "ISP firmware"?

Ideally, we want to only enable a clock if it's not already enabled,
but not turn it off if it is enabled. Isn't that a critical clk?

Thanks
Phil

Re: [PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Geert Uytterhoeven]

Hi Phil,

On Fri, Apr 22, 2022 at 11:31 AM Phil Edworthy
<phil.edworthy@renesas.com> wrote:
> On 22 April 2022 09:45 Geert Uytterhoeven wrote:
> > On Fri, Apr 22, 2022 at 10:28 AM Phil Edworthy wrote:
> > > On 20 April 2022 22:26 Geert Uytterhoeven wrote:
> > > > On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy wrote:
> > > > > The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible
> > with
> > > > the
> > > > > EMMA Mobile SoC.
> > > > >
> > > > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > ---
> > > > > v2: Fix dtbs_check by adding missing alternative binding
> > > >
> > > > Thanks for your patch, which is now commit 7bb301812b628099
> > > > ("dt-bindings: serial: renesas,em-uart: Document r9a09g011
> > > > bindings") in tty/tty-next.
> > > >
> > > > > --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > > > > +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > > > However, unlike EMEV2, RZ/V2M defines two clocks: pclk and sclk.
> > > > Hence please update the clocks section to reflect that.
> > > You are right that the uart has two clocks.
> > >
> > > Note though that pclk is shared by both uarts. The HW manual says:
> > > "ch. 1 is for use with the ISP support package, so do not
> > > use registers related to this channel.". Due to this, section
> > > 48.5.2.50 Clock ON/OFF Control Register 15 (CPG_CLK_ON15) says
> > > that bit 20, CLK4_ONWEN (enable for URT_PCLK) should be written
> > > as 0.
> > >
> > > I took this to mean that the URT_PCLK is enabled by the ISP firmware
> > > and software must not touch it. I am not sure if the DT bindings
> > > should document a clock that is specified as do not touch in the
> > > HW manual. This is a bit of a grey area.
> >
> > "DT describes hardware, not software policy".
> >
> > But I agree this is a grey area.
> I wish the HW manual either didn’t mention this clock that you should
> not touch, or didn’t specify anything as "used by the ISP firmware" :)

Yeah, hardware manuals making too many assumptions about the software
that will run on it will lead to headaches...

> > One option would be to mark URT_PCLK critical, so it won't be disabled.
> > But that would still mean it's enabled by Linux, i.e. Linux would set
> > CLK4_ONWEN to 1 while enabling the clock.
> >
> > Another option would be to create URT_PCLK as a non-gateable clock,
> > so Linux won't ever touch the register bits.
> >
> > Or just ignore URT_PCLK and do nothing, like you did ;-)
> > Would it be possible for a user to not use the ISP firmware at all,
> > and go full Linux, hence using both UART channels and URT_PCLK?
> It is possible to not use the ISP firmware, but them what do we do?
> Ignore everything in the HW manual that says "ISP firmware"?
>
> Ideally, we want to only enable a clock if it's not already enabled,
> but not turn it off if it is enabled. Isn't that a critical clk?

__clk_core_init() explicitly enables clocks marked with
CLK_IS_CRITICAL.  I think it does so without checking the hardware
if the clock is already enabled or not, so probably it will access
the reserved hardware bits regardless.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 03/13] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions

[Phil Edworthy]

Define RZ/V2M (R9A09G011) Clock Pulse Generator core clocks, module clock
outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_*
registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware
User's Manual (Rev. 1.10, Sep. 2021).

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 include/dt-bindings/clock/r9a09g011-cpg.h | 337 ++++++++++++++++++++++
 1 file changed, 337 insertions(+)
 create mode 100644 include/dt-bindings/clock/r9a09g011-cpg.h

diff --git a/include/dt-bindings/clock/r9a09g011-cpg.h b/include/dt-bindings/clock/r9a09g011-cpg.h
new file mode 100644
index 000000000000..b88dbb0d8c49
--- /dev/null
+++ b/include/dt-bindings/clock/r9a09g011-cpg.h
@@ -0,0 +1,337 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* Module Clocks */
+#define R9A09G011_SYS_CLK		0
+#define R9A09G011_PFC_PCLK		1
+#define R9A09G011_PMC_CORE_CLOCK	2
+#define R9A09G011_GIC_CLK		3
+#define R9A09G011_RAMA_ACLK		4
+
+#define R9A09G011_SEC_ACLK		5
+#define R9A09G011_SEC_PCLK		6
+#define R9A09G011_SEC_TCLK		7
+#define R9A09G011_DMAA_ACLK		8
+#define R9A09G011_TSU0_PCLK		9
+#define R9A09G011_TSU1_PCLK		10
+
+#define R9A09G011_CST_TRACECLK		11
+#define R9A09G011_CST_SB_CLK		12
+#define R9A09G011_CST_AHB_CLK		13
+#define R9A09G011_CST_ATB_SB_CLK	14
+
+#define R9A09G011_SDI0_ACLK		15
+#define R9A09G011_SDI0_IMCLK		16
+#define R9A09G011_SDI0_IMCLK2		17
+#define R9A09G011_SDI0_CLK_HS		18
+#define R9A09G011_SDI1_ACLK		19
+#define R9A09G011_SDI1_IMCLK		20
+#define R9A09G011_SDI1_IMCLK2		21
+#define R9A09G011_SDI1_CLK_HS		22
+#define R9A09G011_EMM_ACLK		23
+#define R9A09G011_EMM_IMCLK		24
+#define R9A09G011_EMM_IMCLK2		25
+#define R9A09G011_EMM_CLK_HS		26
+#define R9A09G011_NFI_ACLK		27
+#define R9A09G011_NFI_NF_CLK		28
+
+#define R9A09G011_PCI_ACLK		29
+#define R9A09G011_PCI_CLK_PMU		30
+#define R9A09G011_PCI_APB_CLK		31
+#define R9A09G011_USB_ACLK_H		32
+#define R9A09G011_USB_ACLK_P		33
+#define R9A09G011_USB_PCLK		34
+#define R9A09G011_ETH_CLK_AXI		35
+#define R9A09G011_ETH_CLK_CHI		36
+#define R9A09G011_ETH_GPTP_EXT		37
+
+#define R9A09G011_SDT_CLK		38
+#define R9A09G011_SDT_CLKAPB		39
+#define R9A09G011_SDT_CLK48		40
+#define R9A09G011_GRP_CLK		41
+#define R9A09G011_CIF_P0_CLK		42
+#define R9A09G011_CIF_P1_CLK		43
+#define R9A09G011_CIF_APB_CLK		44
+#define R9A09G011_DCI_CLKAXI		45
+#define R9A09G011_DCI_CLKAPB		46
+#define R9A09G011_DCI_CLKDCI2		47
+
+#define R9A09G011_HMI_PCLK		48
+#define R9A09G011_LCI_PCLK		49
+#define R9A09G011_LCI_ACLK		50
+#define R9A09G011_LCI_VCLK		51
+#define R9A09G011_LCI_LPCLK		52
+
+#define R9A09G011_AUI_CLK		53
+#define R9A09G011_AUI_CLKAXI		54
+#define R9A09G011_AUI_CLKAPB		55
+#define R9A09G011_AUMCLK		56
+#define R9A09G011_GMCLK0		57
+#define R9A09G011_GMCLK1		58
+#define R9A09G011_MTR_CLK0		59
+#define R9A09G011_MTR_CLK1		60
+#define R9A09G011_MTR_CLKAPB		61
+#define R9A09G011_GFT_CLK		62
+#define R9A09G011_GFT_CLKAPB		63
+#define R9A09G011_GFT_MCLK		64
+
+#define R9A09G011_ATGA_CLK		65
+#define R9A09G011_ATGA_CLKAPB		66
+#define R9A09G011_ATGB_CLK		67
+#define R9A09G011_ATGB_CLKAPB		68
+#define R9A09G011_SYC_CNT_CLK		69
+
+#define R9A09G011_GRPA_PCLK		70
+#define R9A09G011_TIM0_CLK		71
+#define R9A09G011_TIM1_CLK		72
+#define R9A09G011_TIM2_CLK		73
+#define R9A09G011_TIM3_CLK		74
+#define R9A09G011_TIM4_CLK		75
+#define R9A09G011_TIM5_CLK		76
+#define R9A09G011_TIM6_CLK		77
+#define R9A09G011_TIM7_CLK		78
+#define R9A09G011_IIC01_PCLK		79
+
+#define R9A09G011_GRPB_PCLK		80
+#define R9A09G011_TIM8_CLK		81
+#define R9A09G011_TIM9_CLK		82
+#define R9A09G011_TIM10_CLK		83
+#define R9A09G011_TIM11_CLK		84
+#define R9A09G011_TIM12_CLK		85
+#define R9A09G011_TIM13_CLK		86
+#define R9A09G011_TIM14_CLK		87
+#define R9A09G011_TIM15_CLK		88
+#define R9A09G011_IIC23_PCLK		89
+
+#define R9A09G011_GRPC_PCLK		90
+#define R9A09G011_TIM16_CLK		91
+#define R9A09G011_TIM17_CLK		92
+#define R9A09G011_TIM18_CLK		93
+#define R9A09G011_TIM19_CLK		94
+#define R9A09G011_TIM20_CLK		95
+#define R9A09G011_TIM21_CLK		96
+#define R9A09G011_TIM22_CLK		97
+#define R9A09G011_TIM23_CLK		98
+#define R9A09G011_WDT0_PCLK		99
+#define R9A09G011_WDT0_CLK		100
+#define R9A09G011_WDT1_PCLK		101
+#define R9A09G011_WDT1_CLK		102
+
+#define R9A09G011_GRPD_PCLK		103
+#define R9A09G011_TIM24_CLK		104
+#define R9A09G011_TIM25_CLK		105
+#define R9A09G011_TIM26_CLK		106
+#define R9A09G011_TIM27_CLK		107
+#define R9A09G011_TIM28_CLK		108
+#define R9A09G011_TIM29_CLK		109
+#define R9A09G011_TIM30_CLK		110
+#define R9A09G011_TIM31_CLK		111
+
+#define R9A09G011_GRPE_PCLK		112
+#define R9A09G011_PWM0_CLK		113
+#define R9A09G011_PWM1_CLK		114
+#define R9A09G011_PWM2_CLK		115
+#define R9A09G011_PWM3_CLK		116
+#define R9A09G011_PWM4_CLK		117
+#define R9A09G011_PWM5_CLK		118
+#define R9A09G011_PWM6_CLK		119
+#define R9A09G011_PWM7_CLK		120
+
+#define R9A09G011_GRPF_PCLK		121
+#define R9A09G011_PWM8_CLK		122
+#define R9A09G011_PWM9_CLK		123
+#define R9A09G011_PWM10_CLK		124
+#define R9A09G011_PWM11_CLK		125
+#define R9A09G011_PWM12_CLK		126
+#define R9A09G011_PWM13_CLK		127
+#define R9A09G011_PWM14_CLK		128
+#define R9A09G011_PWM15_CLK		129
+
+#define R9A09G011_GRPG_PCLK		130
+#define R9A09G011_GRPH_PCLK		131
+#define R9A09G011_URT_PCLK		132
+#define R9A09G011_URT0_CLK		133
+#define R9A09G011_URT1_CLK		134
+#define R9A09G011_CSI0_CLK		135
+#define R9A09G011_CSI1_CLK		136
+#define R9A09G011_CSI2_CLK		137
+#define R9A09G011_CSI3_CLK		138
+#define R9A09G011_CSI4_CLK		139
+#define R9A09G011_CSI5_CLK		140
+
+#define R9A09G011_ICB_ACLK1		141
+#define R9A09G011_ICB_MPCLK1		142
+#define R9A09G011_ICB_SPCLK1		143
+#define R9A09G011_ICB_CLK48		144
+#define R9A09G011_ICB_CLK48_2		145
+#define R9A09G011_ICB_CLK48_3		146
+#define R9A09G011_ICB_CLK48_4L		147
+#define R9A09G011_ICB_CLK48_5		148
+#define R9A09G011_ICB_CST_ATB_SB_CLK	149
+#define R9A09G011_ICB_CST_CS_CLK	150
+#define R9A09G011_ICB_CLK100_1		151
+#define R9A09G011_ICB_ETH0_CLK_AXI	152
+#define R9A09G011_ICB_DCI_CLKAXI	153
+#define R9A09G011_ICB_SYC_CNT_CLK	154
+
+#define R9A09G011_ICB_DRPA_ACLK		155
+#define R9A09G011_ICB_RFX_ACLK		156
+#define R9A09G011_ICB_MMC_ACLK		157
+
+#define R9A09G011_ICB_MPCLK3		158
+#define R9A09G011_ICB_CIMA_CLK		159
+#define R9A09G011_ICB_CIMB_CLK		160
+#define R9A09G011_ICB_BIMA_CLK		161
+#define R9A09G011_ICB_FCD_CLKAXI	162
+#define R9A09G011_ICB_VD_ACLK4		163
+#define R9A09G011_ICB_MPCLK4		164
+#define R9A09G011_ICB_VCD_PCLK4		165
+
+#define R9A09G011_CA53_CLK		166
+#define R9A09G011_CA53_ACLK		167
+#define R9A09G011_CA53_APCLK_DBG	168
+#define R9A09G011_CA53_ATCLK		169
+#define R9A09G011_CA53_TSCLK		170
+#define R9A09G011_CA53_APCLK_REG	171
+
+#define R9A09G011_DRPA_ACLK		172
+#define R9A09G011_DRPA_DCLK		173
+#define R9A09G011_DRPA_INITCLK		174
+
+#define R9A09G011_RAMB_ACLK		175
+
+#define R9A09G011_CIMA_CLKAPB		176
+#define R9A09G011_CIMA_CLK		177
+#define R9A09G011_CIMB_CLK		178
+#define R9A09G011_FAFA_CLK		179
+#define R9A09G011_STG_CLKAXI		180
+#define R9A09G011_STG_CLK0		181
+
+#define R9A09G011_BIMA_CLKAPB		182
+#define R9A09G011_BIMA_CLK		183
+#define R9A09G011_FAFB_CLK		184
+#define R9A09G011_FCD_CLK		185
+#define R9A09G011_FCD_CLKAXI		186
+
+#define R9A09G011_RIM_CLK		187
+#define R9A09G011_VCD_ACLK		188
+#define R9A09G011_JPG0_CLK		189
+#define R9A09G011_JPG0_ACLK		190
+
+#define R9A09G011_MMC_CORE_DDRC_CLK	191
+#define R9A09G011_MMC_ACLK		192
+#define R9A09G011_MMC_PCLK		193
+#define R9A09G011_DDI_APBCLK		194
+
+/* Resets */
+#define R9A09G011_SYS_RST_N		0
+#define R9A09G011_PFC_PRESETN		1
+#define R9A09G011_RAMA_ARESETN		2
+#define R9A09G011_ROM_ARESETN		3
+#define R9A09G011_DMAA_ARESETN		4
+#define R9A09G011_SEC_ARESETN		5
+#define R9A09G011_SEC_PRESETN		6
+#define R9A09G011_SEC_RSTB		7
+#define R9A09G011_TSU0_RESETN		8
+#define R9A09G011_TSU1_RESETN		9
+#define R9A09G011_PMC_RESET_N		10
+
+#define R9A09G011_CST_NTRST		11
+#define R9A09G011_CST_NPOTRST		12
+#define R9A09G011_CST_CS_RESETN		13
+#define R9A09G011_CST_TS_RESETN		14
+#define R9A09G011_CST_TRESETN		15
+#define R9A09G011_CST_SB_RESETN		16
+#define R9A09G011_CST_AHB_RESETN	17
+#define R9A09G011_CST_TS_SB_RESETN	18
+#define R9A09G011_CST_APB_CA53_RESETN	19
+#define R9A09G011_CST_ATB_SB_RESETN	20
+
+#define R9A09G011_SDI0_IXRST		21
+#define R9A09G011_SDI1_IXRST		22
+#define R9A09G011_EMM_IXRST		23
+#define R9A09G011_NFI_MARESETN		24
+#define R9A09G011_NFI_REG_RST_N		25
+#define R9A09G011_USB_PRESET_N		26
+#define R9A09G011_USB_DRD_RESET		27
+#define R9A09G011_USB_ARESETN_P		28
+#define R9A09G011_USB_ARESETN_H		29
+#define R9A09G011_ETH0_RST_HW_N		30
+#define R9A09G011_PCI_ARESETN		31
+
+#define R9A09G011_SDT_RSTSYSAX		32
+#define R9A09G011_GRP_RESETN		33
+#define R9A09G011_CIF_RST_N		34
+#define R9A09G011_DCU_RSTSYSAX		35
+#define R9A09G011_HMI_RST_N		36
+#define R9A09G011_HMI_PRESETN		37
+#define R9A09G011_LCI_PRESETN		38
+#define R9A09G011_LCI_ARESETN		39
+
+#define R9A09G011_AUI_RSTSYSAX		40
+#define R9A09G011_MTR_RSTSYSAX		41
+#define R9A09G011_GFT_RSTSYSAX		42
+#define R9A09G011_ATGA_RSTSYSAX		43
+#define R9A09G011_ATGB_RSTSYSAX		44
+#define R9A09G011_SYC_RST_N		45
+
+#define R9A09G011_TIM_GPA_PRESETN	46
+#define R9A09G011_TIM_GPB_PRESETN	47
+#define R9A09G011_TIM_GPC_PRESETN	48
+#define R9A09G011_TIM_GPD_PRESETN	49
+#define R9A09G011_PWM_GPE_PRESETN	50
+#define R9A09G011_PWM_GPF_PRESETN	51
+#define R9A09G011_CSI_GPG_PRESETN	52
+#define R9A09G011_CSI_GPH_PRESETN	53
+#define R9A09G011_IIC_GPA_PRESETN	54
+#define R9A09G011_IIC_GPB_PRESETN	55
+#define R9A09G011_URT_PRESETN		56
+#define R9A09G011_WDT0_PRESETN		57
+#define R9A09G011_WDT1_PRESETN		58
+
+#define R9A09G011_ICB_PD_AWO_RST_N	59
+#define R9A09G011_ICB_PD_MMC_RST_N	60
+#define R9A09G011_ICB_PD_VD0_RST_N	61
+#define R9A09G011_ICB_PD_VD1_RST_N	62
+#define R9A09G011_ICB_PD_RFX_RST_N	63
+
+#define R9A09G011_CA53_NCPUPORESET0	64
+#define R9A09G011_CA53_NCPUPORESET1	65
+#define R9A09G011_CA53_NCORERESET0	66
+#define R9A09G011_CA53_NCORERESET1	67
+#define R9A09G011_CA53_NPRESETDBG	68
+#define R9A09G011_CA53_L2RESET		69
+#define R9A09G011_CA53_NMISCRESET_HM	70
+#define R9A09G011_CA53_NMISCRESET_SM	71
+#define R9A09G011_CA53_NARESET		72
+
+#define R9A09G011_DRPA_ARESETN		73
+
+#define R9A09G011_RAMB_ARESETN		74
+
+#define R9A09G011_CIMA_RSTSYSAX		75
+#define R9A09G011_CIMB_RSTSYSAX		76
+#define R9A09G011_FAFA_RSTSYSAX		77
+#define R9A09G011_STG_RSTSYSAX		78
+
+#define R9A09G011_BIMA_RSTSYSAX		79
+#define R9A09G011_FAFB_RSTSYSAX		80
+#define R9A09G011_FCD_RSTSYSAX		81
+#define R9A09G011_RIM_RSTSYSAX		82
+#define R9A09G011_VCD_RESETN		83
+#define R9A09G011_JPG_XRESET		84
+
+#define R9A09G011_MMC_CORE_DDRC_RSTN	85
+#define R9A09G011_MMC_ARESETN_N		86
+#define R9A09G011_MMC_PRESETN		87
+#define R9A09G011_DDI_PWROK		88
+#define R9A09G011_DDI_RESET		89
+#define R9A09G011_DDI_RESETN_APB	90
+
+#endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */
-- 
2.32.0

Re: [PATCH v2 03/13] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions

[Rob Herring]

On Wed, 30 Mar 2022 16:40:14 +0100, Phil Edworthy wrote:
> Define RZ/V2M (R9A09G011) Clock Pulse Generator core clocks, module clock
> outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_*
> registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware
> User's Manual (Rev. 1.10, Sep. 2021).
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  include/dt-bindings/clock/r9a09g011-cpg.h | 337 ++++++++++++++++++++++
>  1 file changed, 337 insertions(+)
>  create mode 100644 include/dt-bindings/clock/r9a09g011-cpg.h
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 03/13] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions

[Geert Uytterhoeven]

Hi Phil,

CC clock

Thanks for your patch!

On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> Define RZ/V2M (R9A09G011) Clock Pulse Generator core clocks, module clock

The definitions contain no core clocks, only module clocks and resets?
Perhaps you will need a core clock for the Ethernet reference clock,
like on RZ/G2L?

> outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_*
> registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware
> User's Manual (Rev. 1.10, Sep. 2021).
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  include/dt-bindings/clock/r9a09g011-cpg.h | 337 ++++++++++++++++++++++
>  1 file changed, 337 insertions(+)
>  create mode 100644 include/dt-bindings/clock/r9a09g011-cpg.h
>
> diff --git a/include/dt-bindings/clock/r9a09g011-cpg.h b/include/dt-bindings/clock/r9a09g011-cpg.h
> new file mode 100644
> index 000000000000..b88dbb0d8c49
> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a09g011-cpg.h
> @@ -0,0 +1,337 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* Module Clocks */
> +#define R9A09G011_SYS_CLK              0
> +#define R9A09G011_PFC_PCLK             1
> +#define R9A09G011_PMC_CORE_CLOCK       2
> +#define R9A09G011_GIC_CLK              3
> +#define R9A09G011_RAMA_ACLK            4

Missing ROM_ACLK?

> +

No need for this blank line, as this is not a register boundary.

> +#define R9A09G011_SEC_ACLK             5
> +#define R9A09G011_SEC_PCLK             6
> +#define R9A09G011_SEC_TCLK             7
> +#define R9A09G011_DMAA_ACLK            8
> +#define R9A09G011_TSU0_PCLK            9
> +#define R9A09G011_TSU1_PCLK            10
> +
> +#define R9A09G011_CST_TRACECLK         11
> +#define R9A09G011_CST_SB_CLK           12
> +#define R9A09G011_CST_AHB_CLK          13
> +#define R9A09G011_CST_ATB_SB_CLK       14

Missing CST_TS_SB_CLK?
Yes, it shares a bit with CST_ATB_SB_CLK, cfr.
ETH0_CLK_AXI and ETH1_CLK_AXI.

> +
> +#define R9A09G011_SDI0_ACLK            15
> +#define R9A09G011_SDI0_IMCLK           16
> +#define R9A09G011_SDI0_IMCLK2          17
> +#define R9A09G011_SDI0_CLK_HS          18
> +#define R9A09G011_SDI1_ACLK            19
> +#define R9A09G011_SDI1_IMCLK           20
> +#define R9A09G011_SDI1_IMCLK2          21
> +#define R9A09G011_SDI1_CLK_HS          22
> +#define R9A09G011_EMM_ACLK             23
> +#define R9A09G011_EMM_IMCLK            24
> +#define R9A09G011_EMM_IMCLK2           25
> +#define R9A09G011_EMM_CLK_HS           26
> +#define R9A09G011_NFI_ACLK             27
> +#define R9A09G011_NFI_NF_CLK           28
> +
> +#define R9A09G011_PCI_ACLK             29
> +#define R9A09G011_PCI_CLK_PMU          30
> +#define R9A09G011_PCI_APB_CLK          31
> +#define R9A09G011_USB_ACLK_H           32
> +#define R9A09G011_USB_ACLK_P           33
> +#define R9A09G011_USB_PCLK             34
> +#define R9A09G011_ETH_CLK_AXI          35
> +#define R9A09G011_ETH_CLK_CHI          36
> +#define R9A09G011_ETH_GPTP_EXT         37

s/ETH/ETH0/ for the three above?

> +
> +#define R9A09G011_SDT_CLK              38
> +#define R9A09G011_SDT_CLKAPB           39
> +#define R9A09G011_SDT_CLK48            40
> +#define R9A09G011_GRP_CLK              41
> +#define R9A09G011_CIF_P0_CLK           42
> +#define R9A09G011_CIF_P1_CLK           43
> +#define R9A09G011_CIF_APB_CLK          44
> +#define R9A09G011_DCI_CLKAXI           45
> +#define R9A09G011_DCI_CLKAPB           46
> +#define R9A09G011_DCI_CLKDCI2          47
> +
> +#define R9A09G011_HMI_PCLK             48
> +#define R9A09G011_LCI_PCLK             49
> +#define R9A09G011_LCI_ACLK             50
> +#define R9A09G011_LCI_VCLK             51
> +#define R9A09G011_LCI_LPCLK            52
> +
> +#define R9A09G011_AUI_CLK              53
> +#define R9A09G011_AUI_CLKAXI           54
> +#define R9A09G011_AUI_CLKAPB           55
> +#define R9A09G011_AUMCLK               56
> +#define R9A09G011_GMCLK0               57
> +#define R9A09G011_GMCLK1               58
> +#define R9A09G011_MTR_CLK0             59
> +#define R9A09G011_MTR_CLK1             60
> +#define R9A09G011_MTR_CLKAPB           61
> +#define R9A09G011_GFT_CLK              62
> +#define R9A09G011_GFT_CLKAPB           63
> +#define R9A09G011_GFT_MCLK             64
> +
> +#define R9A09G011_ATGA_CLK             65
> +#define R9A09G011_ATGA_CLKAPB          66
> +#define R9A09G011_ATGB_CLK             67
> +#define R9A09G011_ATGB_CLKAPB          68
> +#define R9A09G011_SYC_CNT_CLK          69
> +
> +#define R9A09G011_GRPA_PCLK            70

CPERI_GRPA_PCLK

> +#define R9A09G011_TIM0_CLK             71
> +#define R9A09G011_TIM1_CLK             72
> +#define R9A09G011_TIM2_CLK             73
> +#define R9A09G011_TIM3_CLK             74
> +#define R9A09G011_TIM4_CLK             75
> +#define R9A09G011_TIM5_CLK             76
> +#define R9A09G011_TIM6_CLK             77
> +#define R9A09G011_TIM7_CLK             78
> +#define R9A09G011_IIC01_PCLK           79

IIC0_PCLK?

> +
> +#define R9A09G011_GRPB_PCLK            80

CPERI_GRPB_PCLK

> +#define R9A09G011_TIM8_CLK             81
> +#define R9A09G011_TIM9_CLK             82
> +#define R9A09G011_TIM10_CLK            83
> +#define R9A09G011_TIM11_CLK            84
> +#define R9A09G011_TIM12_CLK            85
> +#define R9A09G011_TIM13_CLK            86
> +#define R9A09G011_TIM14_CLK            87
> +#define R9A09G011_TIM15_CLK            88
> +#define R9A09G011_IIC23_PCLK           89

IIC1_PCLK?

> +
> +#define R9A09G011_GRPC_PCLK            90

CPERI_GRPC_PCLK?

> +#define R9A09G011_TIM16_CLK            91
> +#define R9A09G011_TIM17_CLK            92
> +#define R9A09G011_TIM18_CLK            93
> +#define R9A09G011_TIM19_CLK            94
> +#define R9A09G011_TIM20_CLK            95
> +#define R9A09G011_TIM21_CLK            96
> +#define R9A09G011_TIM22_CLK            97
> +#define R9A09G011_TIM23_CLK            98
> +#define R9A09G011_WDT0_PCLK            99
> +#define R9A09G011_WDT0_CLK             100
> +#define R9A09G011_WDT1_PCLK            101
> +#define R9A09G011_WDT1_CLK             102
> +
> +#define R9A09G011_GRPD_PCLK            103

CPERI_GRPD_PCLK?

> +#define R9A09G011_TIM24_CLK            104
> +#define R9A09G011_TIM25_CLK            105
> +#define R9A09G011_TIM26_CLK            106
> +#define R9A09G011_TIM27_CLK            107
> +#define R9A09G011_TIM28_CLK            108
> +#define R9A09G011_TIM29_CLK            109
> +#define R9A09G011_TIM30_CLK            110
> +#define R9A09G011_TIM31_CLK            111
> +
> +#define R9A09G011_GRPE_PCLK            112

CPERI_GRPE_PCLK?

> +#define R9A09G011_PWM0_CLK             113
> +#define R9A09G011_PWM1_CLK             114
> +#define R9A09G011_PWM2_CLK             115
> +#define R9A09G011_PWM3_CLK             116
> +#define R9A09G011_PWM4_CLK             117
> +#define R9A09G011_PWM5_CLK             118
> +#define R9A09G011_PWM6_CLK             119
> +#define R9A09G011_PWM7_CLK             120
> +
> +#define R9A09G011_GRPF_PCLK            121

CPERI_GRPF_PCLK?

> +#define R9A09G011_PWM8_CLK             122
> +#define R9A09G011_PWM9_CLK             123
> +#define R9A09G011_PWM10_CLK            124
> +#define R9A09G011_PWM11_CLK            125
> +#define R9A09G011_PWM12_CLK            126
> +#define R9A09G011_PWM13_CLK            127
> +#define R9A09G011_PWM14_CLK            128
> +#define R9A09G011_PWM15_CLK            129
> +
> +#define R9A09G011_GRPG_PCLK            130

CPERI_GRPG_PCLK?

> +#define R9A09G011_GRPH_PCLK            131

CPERI_GRPH_PCLK?

> +#define R9A09G011_URT_PCLK             132
> +#define R9A09G011_URT0_CLK             133
> +#define R9A09G011_URT1_CLK             134
> +#define R9A09G011_CSI0_CLK             135
> +#define R9A09G011_CSI1_CLK             136
> +#define R9A09G011_CSI2_CLK             137
> +#define R9A09G011_CSI3_CLK             138
> +#define R9A09G011_CSI4_CLK             139
> +#define R9A09G011_CSI5_CLK             140
> +
> +#define R9A09G011_ICB_ACLK1            141

Missing (shared) ICB_GIC_CLK?

> +#define R9A09G011_ICB_MPCLK1           142
> +#define R9A09G011_ICB_SPCLK1           143
> +#define R9A09G011_ICB_CLK48            144
> +#define R9A09G011_ICB_CLK48_2          145
> +#define R9A09G011_ICB_CLK48_3          146
> +#define R9A09G011_ICB_CLK48_4L         147

Missing (shared) ICB_CLK48_4R?

> +#define R9A09G011_ICB_CLK48_5          148
> +#define R9A09G011_ICB_CST_ATB_SB_CLK   149
> +#define R9A09G011_ICB_CST_CS_CLK       150
> +#define R9A09G011_ICB_CLK100_1         151
> +#define R9A09G011_ICB_ETH0_CLK_AXI     152
> +#define R9A09G011_ICB_DCI_CLKAXI       153
> +#define R9A09G011_ICB_SYC_CNT_CLK      154
> +
> +#define R9A09G011_ICB_DRPA_ACLK                155
> +#define R9A09G011_ICB_RFX_ACLK         156

Missing (shared) ICB_RFX_PCLK5?

> +#define R9A09G011_ICB_MMC_ACLK         157
> +
> +#define R9A09G011_ICB_MPCLK3           158
> +#define R9A09G011_ICB_CIMA_CLK         159
> +#define R9A09G011_ICB_CIMB_CLK         160
> +#define R9A09G011_ICB_BIMA_CLK         161
> +#define R9A09G011_ICB_FCD_CLKAXI       162
> +#define R9A09G011_ICB_VD_ACLK4         163
> +#define R9A09G011_ICB_MPCLK4           164
> +#define R9A09G011_ICB_VCD_PCLK4                165
> +
> +#define R9A09G011_CA53_CLK             166
> +#define R9A09G011_CA53_ACLK            167
> +#define R9A09G011_CA53_APCLK_DBG       168

Missing (shared) CST_APB_CA53_CLK?

> +#define R9A09G011_CA53_ATCLK           169

Missing (shared) CST_CS_CLK?

> +#define R9A09G011_CA53_TSCLK           170

Missing (shared) CST_TS_CLK?

> +#define R9A09G011_CA53_APCLK_REG       171
> +
> +#define R9A09G011_DRPA_ACLK            172
> +#define R9A09G011_DRPA_DCLK            173
> +#define R9A09G011_DRPA_INITCLK         174
> +
> +#define R9A09G011_RAMB_ACLK            175

Would it make sense to decouple this into
RAMB0_ACLK, RAMB1_ACLK, RAMB2_ACLK, RAMB3_ACLK?

> +
> +#define R9A09G011_CIMA_CLKAPB          176
> +#define R9A09G011_CIMA_CLK             177
> +#define R9A09G011_CIMB_CLK             178
> +#define R9A09G011_FAFA_CLK             179
> +#define R9A09G011_STG_CLKAXI           180
> +#define R9A09G011_STG_CLK0             181
> +
> +#define R9A09G011_BIMA_CLKAPB          182
> +#define R9A09G011_BIMA_CLK             183
> +#define R9A09G011_FAFB_CLK             184
> +#define R9A09G011_FCD_CLK              185
> +#define R9A09G011_FCD_CLKAXI           186
> +
> +#define R9A09G011_RIM_CLK              187
> +#define R9A09G011_VCD_ACLK             188

Mising (shared) VCD_PCLK?

> +#define R9A09G011_JPG0_CLK             189
> +#define R9A09G011_JPG0_ACLK            190
> +
> +#define R9A09G011_MMC_CORE_DDRC_CLK    191
> +#define R9A09G011_MMC_ACLK             192
> +#define R9A09G011_MMC_PCLK             193
> +#define R9A09G011_DDI_APBCLK           194
> +
> +/* Resets */
> +#define R9A09G011_SYS_RST_N            0
> +#define R9A09G011_PFC_PRESETN          1
> +#define R9A09G011_RAMA_ARESETN         2
> +#define R9A09G011_ROM_ARESETN          3
> +#define R9A09G011_DMAA_ARESETN         4
> +#define R9A09G011_SEC_ARESETN          5
> +#define R9A09G011_SEC_PRESETN          6
> +#define R9A09G011_SEC_RSTB             7
> +#define R9A09G011_TSU0_RESETN          8
> +#define R9A09G011_TSU1_RESETN          9
> +#define R9A09G011_PMC_RESET_N          10
> +
> +#define R9A09G011_CST_NTRST            11
> +#define R9A09G011_CST_NPOTRST          12

Missing (shared) CST_NTRST?

> +#define R9A09G011_CST_CS_RESETN                13
> +#define R9A09G011_CST_TS_RESETN                14
> +#define R9A09G011_CST_TRESETN          15
> +#define R9A09G011_CST_SB_RESETN                16
> +#define R9A09G011_CST_AHB_RESETN       17
> +#define R9A09G011_CST_TS_SB_RESETN     18
> +#define R9A09G011_CST_APB_CA53_RESETN  19
> +#define R9A09G011_CST_ATB_SB_RESETN    20
> +
> +#define R9A09G011_SDI0_IXRST           21
> +#define R9A09G011_SDI1_IXRST           22
> +#define R9A09G011_EMM_IXRST            23
> +#define R9A09G011_NFI_MARESETN         24
> +#define R9A09G011_NFI_REG_RST_N                25
> +#define R9A09G011_USB_PRESET_N         26
> +#define R9A09G011_USB_DRD_RESET                27
> +#define R9A09G011_USB_ARESETN_P                28
> +#define R9A09G011_USB_ARESETN_H                29
> +#define R9A09G011_ETH0_RST_HW_N                30
> +#define R9A09G011_PCI_ARESETN          31
> +
> +#define R9A09G011_SDT_RSTSYSAX         32
> +#define R9A09G011_GRP_RESETN           33
> +#define R9A09G011_CIF_RST_N            34
> +#define R9A09G011_DCU_RSTSYSAX         35
> +#define R9A09G011_HMI_RST_N            36
> +#define R9A09G011_HMI_PRESETN          37
> +#define R9A09G011_LCI_PRESETN          38
> +#define R9A09G011_LCI_ARESETN          39
> +
> +#define R9A09G011_AUI_RSTSYSAX         40
> +#define R9A09G011_MTR_RSTSYSAX         41
> +#define R9A09G011_GFT_RSTSYSAX         42
> +#define R9A09G011_ATGA_RSTSYSAX                43
> +#define R9A09G011_ATGB_RSTSYSAX                44
> +#define R9A09G011_SYC_RST_N            45
> +
> +#define R9A09G011_TIM_GPA_PRESETN      46
> +#define R9A09G011_TIM_GPB_PRESETN      47
> +#define R9A09G011_TIM_GPC_PRESETN      48
> +#define R9A09G011_TIM_GPD_PRESETN      49
> +#define R9A09G011_PWM_GPE_PRESETN      50
> +#define R9A09G011_PWM_GPF_PRESETN      51
> +#define R9A09G011_CSI_GPG_PRESETN      52
> +#define R9A09G011_CSI_GPH_PRESETN      53
> +#define R9A09G011_IIC_GPA_PRESETN      54
> +#define R9A09G011_IIC_GPB_PRESETN      55
> +#define R9A09G011_URT_PRESETN          56
> +#define R9A09G011_WDT0_PRESETN         57
> +#define R9A09G011_WDT1_PRESETN         58
> +
> +#define R9A09G011_ICB_PD_AWO_RST_N     59
> +#define R9A09G011_ICB_PD_MMC_RST_N     60
> +#define R9A09G011_ICB_PD_VD0_RST_N     61
> +#define R9A09G011_ICB_PD_VD1_RST_N     62
> +#define R9A09G011_ICB_PD_RFX_RST_N     63
> +
> +#define R9A09G011_CA53_NCPUPORESET0    64
> +#define R9A09G011_CA53_NCPUPORESET1    65
> +#define R9A09G011_CA53_NCORERESET0     66
> +#define R9A09G011_CA53_NCORERESET1     67
> +#define R9A09G011_CA53_NPRESETDBG      68
> +#define R9A09G011_CA53_L2RESET         69
> +#define R9A09G011_CA53_NMISCRESET_HM   70
> +#define R9A09G011_CA53_NMISCRESET_SM   71
> +#define R9A09G011_CA53_NARESET         72
> +
> +#define R9A09G011_DRPA_ARESETN         73
> +
> +#define R9A09G011_RAMB_ARESETN         74

Would it make sense to decouple this into
RAMB0_ARESETN, RAMB1_ARESETN, RAMB2_ARESETN, RAMB3_ARESETN?

> +
> +#define R9A09G011_CIMA_RSTSYSAX                75
> +#define R9A09G011_CIMB_RSTSYSAX                76
> +#define R9A09G011_FAFA_RSTSYSAX                77
> +#define R9A09G011_STG_RSTSYSAX         78
> +
> +#define R9A09G011_BIMA_RSTSYSAX                79
> +#define R9A09G011_FAFB_RSTSYSAX                80
> +#define R9A09G011_FCD_RSTSYSAX         81
> +#define R9A09G011_RIM_RSTSYSAX         82
> +#define R9A09G011_VCD_RESETN           83
> +#define R9A09G011_JPG_XRESET           84
> +
> +#define R9A09G011_MMC_CORE_DDRC_RSTN   85
> +#define R9A09G011_MMC_ARESETN_N                86
> +#define R9A09G011_MMC_PRESETN          87
> +#define R9A09G011_DDI_PWROK            88
> +#define R9A09G011_DDI_RESET            89
> +#define R9A09G011_DDI_RESETN_APB       90
> +
> +#endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 03/13] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions

[Phil Edworthy]

Hi Geert,

On 20 April 2022 22:13 Geert Uytterhoeven wrote:
> On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy wrote:
> > Define RZ/V2M (R9A09G011) Clock Pulse Generator core clocks, module
> clock
> 
> The definitions contain no core clocks, only module clocks and resets?
> Perhaps you will need a core clock for the Ethernet reference clock,
> like on RZ/G2L?
It looks like rz/v2m has a gate for every clock, so no need for any core
clocks.


> > outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_*
> > registers) in Section 48.5 ("Register Description") of the RZ/V2M
> Hardware
> > User's Manual (Rev. 1.10, Sep. 2021).
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  include/dt-bindings/clock/r9a09g011-cpg.h | 337 ++++++++++++++++++++++
> >  1 file changed, 337 insertions(+)
> >  create mode 100644 include/dt-bindings/clock/r9a09g011-cpg.h
> >
> > diff --git a/include/dt-bindings/clock/r9a09g011-cpg.h b/include/dt-
> bindings/clock/r9a09g011-cpg.h
> > new file mode 100644
> > index 000000000000..b88dbb0d8c49
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r9a09g011-cpg.h
> > @@ -0,0 +1,337 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
> > +#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > +/* Module Clocks */
> > +#define R9A09G011_SYS_CLK              0
> > +#define R9A09G011_PFC_PCLK             1
> > +#define R9A09G011_PMC_CORE_CLOCK       2
> > +#define R9A09G011_GIC_CLK              3
> > +#define R9A09G011_RAMA_ACLK            4
> 
> Missing ROM_ACLK?
Yes, will add.

> > +
> 
> No need for this blank line, as this is not a register boundary.
Agreed

...
> > +#define R9A09G011_CST_ATB_SB_CLK       14
> 
> Missing CST_TS_SB_CLK?
> Yes, it shares a bit with CST_ATB_SB_CLK, cfr.
> ETH0_CLK_AXI and ETH1_CLK_AXI.
Ah, right, I will add.

...
> > +#define R9A09G011_ETH_CLK_AXI          35
> > +#define R9A09G011_ETH_CLK_CHI          36
> > +#define R9A09G011_ETH_GPTP_EXT         37
> 
> s/ETH/ETH0/ for the three above?
Will do, though there is only one eth, ETH0 matches the doc.

...
> > +#define R9A09G011_GRPA_PCLK            70
> 
> CPERI_GRPA_PCLK
Ok, I'll replace all GRP*_PCLK with CPERI_GRP*_PCLK

> > +#define R9A09G011_TIM0_CLK             71
> > +#define R9A09G011_TIM1_CLK             72
> > +#define R9A09G011_TIM2_CLK             73
> > +#define R9A09G011_TIM3_CLK             74
> > +#define R9A09G011_TIM4_CLK             75
> > +#define R9A09G011_TIM5_CLK             76
> > +#define R9A09G011_TIM6_CLK             77
> > +#define R9A09G011_TIM7_CLK             78
> > +#define R9A09G011_IIC01_PCLK           79
> 
> IIC0_PCLK?
There are four IIC peripherals, this pclk if for iic0 and iic1.
Would IIC0_1_PCLK be a better name for this?

> > +#define R9A09G011_IIC23_PCLK           89
> IIC1_PCLK?
and IIC2_3_PCLK?

...
> > +#define R9A09G011_ICB_ACLK1            141
> 
> Missing (shared) ICB_GIC_CLK?
I didn’t consider all these shared clocks and reset as useful
to anyone.
As far as I can tell, nothing will need to get the clock rates
and anything that needs to enable one of the clocks will need
to enable the other to use the HW.

Still, as the binding describes the HW, I will add all of them.

> > +#define R9A09G011_RAMB_ACLK            175
> 
> Would it make sense to decouple this into
> RAMB0_ACLK, RAMB1_ACLK, RAMB2_ACLK, RAMB3_ACLK?
Will do.

Thanks
Phil

Re: [PATCH v2 03/13] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions

[Geert Uytterhoeven]

Hi Phil,

On Fri, Apr 22, 2022 at 1:29 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> On 20 April 2022 22:13 Geert Uytterhoeven wrote:
> > On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy wrote:
> > > Define RZ/V2M (R9A09G011) Clock Pulse Generator core clocks, module
> > clock
> >
> > The definitions contain no core clocks, only module clocks and resets?
> > Perhaps you will need a core clock for the Ethernet reference clock,
> > like on RZ/G2L?
> It looks like rz/v2m has a gate for every clock, so no need for any core
> clocks.

OK. Then please remove "core clock," from the patch description.

> > > outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_*
> > > registers) in Section 48.5 ("Register Description") of the RZ/V2M
> > Hardware
> > > User's Manual (Rev. 1.10, Sep. 2021).
> > >
> > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>

> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/r9a09g011-cpg.h

> > > +#define R9A09G011_IIC01_PCLK           79
> >
> > IIC0_PCLK?
> There are four IIC peripherals, this pclk if for iic0 and iic1.

I know.

> Would IIC0_1_PCLK be a better name for this?
>
> > > +#define R9A09G011_IIC23_PCLK           89
> > IIC1_PCLK?
> and IIC2_3_PCLK?

Well, IIC0_PCLK andIIC1_PCLK match the Hardware Manual.

BTW, for resets, they avoided the confusion by naming the groups
A and B, instead of 0 and 1.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 03/13] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions

[Phil Edworthy]

Hi Geert,

On 22 April 2022 16:02 Geert Uytterhoeven wrote:
> On Fri, Apr 22, 2022 at 1:29 PM Phil Edworthy wrote:
> > On 20 April 2022 22:13 Geert Uytterhoeven wrote:
> > > On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy wrote:
> > > > Define RZ/V2M (R9A09G011) Clock Pulse Generator core clocks, module
> > > clock
> > >
> > > The definitions contain no core clocks, only module clocks and resets?
> > > Perhaps you will need a core clock for the Ethernet reference clock,
> > > like on RZ/G2L?
> > It looks like rz/v2m has a gate for every clock, so no need for any core
> > clocks.
> 
> OK. Then please remove "core clock," from the patch description.
Will do.

> > > > outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_*
> > > > registers) in Section 48.5 ("Register Description") of the RZ/V2M
> > > Hardware
> > > > User's Manual (Rev. 1.10, Sep. 2021).
> > > >
> > > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> 
> > > > --- /dev/null
> > > > +++ b/include/dt-bindings/clock/r9a09g011-cpg.h
> 
> > > > +#define R9A09G011_IIC01_PCLK           79
> > >
> > > IIC0_PCLK?
> > There are four IIC peripherals, this pclk if for iic0 and iic1.
> 
> I know.
> 
> > Would IIC0_1_PCLK be a better name for this?
> >
> > > > +#define R9A09G011_IIC23_PCLK           89
> > > IIC1_PCLK?
> > and IIC2_3_PCLK?
> 
> Well, IIC0_PCLK andIIC1_PCLK match the Hardware Manual.
> 
> BTW, for resets, they avoided the confusion by naming the groups
> A and B, instead of 0 and 1.
Since the HW manual describes these as IIC_PCLK[0] and IIC_PCLK[1],
and I've changed the names of clks so the module index comes after
the module name to match other Renesas SoCs, how about IIC_PCLK0
and IIC_PCLK1 to differentiate them?


<added this back in for discussion>
> > +#define R9A09G011_PMC_RESET_N          10
> > +
> > +#define R9A09G011_CST_NTRST            11
> > +#define R9A09G011_CST_NPOTRST          12

> Missing (shared) CST_NTRST?
Actually, CST_NTRST is already defined on the line before it.
However, the HW manual says "CST_NTRST" in both bit 0 and bit 1 of
CPG_RST2. I'll ask the HW people what the difference is.

Thanks
Phil

[PATCH v2 04/13] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC

[Phil Edworthy]

Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 .../bindings/clock/renesas,rzg2l-cpg.yaml           | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index bd3af8fc616b..b1145f9139d2 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -4,14 +4,15 @@
 $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
 
-title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
+title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
 
 maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
 
 description: |
   On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
-  Standby Mode share the same register block.
+  Standby Mode share the same register block. On RZ/V2M, the functionality is
+  similar, but does not have Clock Monitor Registers.
 
   They provide the following functionalities:
     - The CPG block generates various core clocks,
@@ -25,6 +26,7 @@ properties:
     enum:
       - renesas,r9a07g044-cpg  # RZ/G2{L,LC}
       - renesas,r9a07g054-cpg  # RZ/V2L
+      - renesas,r9a09g011-cpg  # RZ/V2M
 
   reg:
     maxItems: 1
@@ -42,9 +44,10 @@ properties:
     description: |
       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
         and a core clock reference, as defined in
-        <dt-bindings/clock/r9a07g*-cpg.h>
+        <dt-bindings/clock/r9a07g*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>
       - For module clocks, the two clock specifier cells must be "CPG_MOD" and
-        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
+        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
+        <dt-bindings/clock/r9a09g011-cpg.h>.
     const: 2
 
   '#power-domain-cells':
@@ -58,7 +61,7 @@ properties:
   '#reset-cells':
     description:
       The single reset specifier cell must be the module number, as defined in
-      the <dt-bindings/clock/r9a07g0*-cpg.h>.
+      the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
     const: 1
 
 required:
-- 
2.32.0

Re: [PATCH v2 04/13] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC

[Geert Uytterhoeven]

Hi Phil,

On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> @@ -42,9 +44,10 @@ properties:
>      description: |
>        - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
>          and a core clock reference, as defined in
> -        <dt-bindings/clock/r9a07g*-cpg.h>
> +        <dt-bindings/clock/r9a07g*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>

I guess we can simplify to dt-bindings/clock/r9a0*-cpg.h?

The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 04/13] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC

[Phil Edworthy]

Hi Geert,

On 26 April 2022 15:21
> On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy wrote:
> > Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> 
> Thanks for your patch!
> 
> > --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > @@ -42,9 +44,10 @@ properties:
> >      description: |
> >        - For CPG core clocks, the two clock specifier cells must be
> "CPG_CORE"
> >          and a core clock reference, as defined in
> > -        <dt-bindings/clock/r9a07g*-cpg.h>
> > +        <dt-bindings/clock/r9a07g*-cpg.h> or <dt-
> bindings/clock/r9a09g011-cpg.h>
> 
> I guess we can simplify to dt-bindings/clock/r9a0*-cpg.h?
We can, it was just to ensure we don't ever catch a file related
to rz/n1 (r9a06g032). However, r9a06g032 has -sysctrl.h suffix.

I'm easy either way...


> The rest LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
Thanks!
Phil

Re: [PATCH v2 04/13] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC

[Geert Uytterhoeven]

Hi Phil,

On Tue, Apr 26, 2022 at 4:39 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> On 26 April 2022 15:21
> > On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy wrote:
> > > Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.
> > >
> > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> >
> > > --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > > @@ -42,9 +44,10 @@ properties:
> > >      description: |
> > >        - For CPG core clocks, the two clock specifier cells must be
> > "CPG_CORE"
> > >          and a core clock reference, as defined in
> > > -        <dt-bindings/clock/r9a07g*-cpg.h>
> > > +        <dt-bindings/clock/r9a07g*-cpg.h> or <dt-
> > bindings/clock/r9a09g011-cpg.h>
> >
> > I guess we can simplify to dt-bindings/clock/r9a0*-cpg.h?
> We can, it was just to ensure we don't ever catch a file related
> to rz/n1 (r9a06g032). However, r9a06g032 has -sysctrl.h suffix.

Even if RZ/N1 had the -cpg.h suffix, it would fall under different
bindings. Not much we can do anyway, when people include the wrong
header file ;-)

> I'm easy either way...

I'm trying to avoid having to update (too) many places when
adding support for a new SoC.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 05/13] serial: 8250: Make SERIAL_8250_EM available for arm64 systems

[Phil Edworthy]

This is needed for the Renesas RZ/V2M (r9a09g011) SoC.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/tty/serial/8250/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
index cd93ea6eed65..fdb6c4188695 100644
--- a/drivers/tty/serial/8250/Kconfig
+++ b/drivers/tty/serial/8250/Kconfig
@@ -380,7 +380,7 @@ config SERIAL_8250_DW
 config SERIAL_8250_EM
 	tristate "Support for Emma Mobile integrated serial port"
 	depends on SERIAL_8250 && HAVE_CLK
-	depends on (ARM && ARCH_RENESAS) || COMPILE_TEST
+	depends on ARCH_RENESAS || COMPILE_TEST
 	help
 	  Selecting this option will add support for the integrated serial
 	  port hardware found on the Emma Mobile line of processors.
-- 
2.32.0

Re: [PATCH v2 05/13] serial: 8250: Make SERIAL_8250_EM available for arm64 systems

[Geert Uytterhoeven]

On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> This is needed for the Renesas RZ/V2M (r9a09g011) SoC.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 07/13] clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers

[Phil Edworthy]

All of the muxes and dividers that can be modified require the HIWORD
flags, so make the macros set them. It won't affect read only muxes and
dividers.
This will make the clock tables a little easier to read, particularly for
new SoCs coming.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g044-cpg.c | 16 +++++++---------
 drivers/clk/renesas/rzg2l-cpg.h     |  5 +++--
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index bdfabb992a20..b187d9ac47aa 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -121,7 +121,7 @@ static const struct {
 		DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
 			sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
 		DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
-			DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+			DIVPL3C, dtable_1_32, 0),
 
 		DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
 		DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
@@ -129,21 +129,20 @@ static const struct {
 			sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),
 
 		/* Core output clk */
-		DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
-			CLK_DIVIDER_HIWORD_MASK),
+		DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, 0),
 		DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
-			dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+			dtable_1_32, 0),
 		DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
 		DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
 		DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
-			DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+			DIVPL3B, dtable_1_32, 0),
 		DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
 		DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
-			DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+			DIVPL3A, dtable_1_32, 0),
 		DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
 		DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
 		DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,
-			sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
+			sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, 0),
 		DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
 		DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
 		DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0,
@@ -152,8 +151,7 @@ static const struct {
 			   sel_shdi, ARRAY_SIZE(sel_shdi)),
 		DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
 		DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
-		DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
-			CLK_DIVIDER_HIWORD_MASK),
+		DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, 0),
 	},
 #ifdef CONFIG_CLK_R9A07G054
 	.drp = {
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index ce657beaf160..592dd9515cfc 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -100,12 +100,13 @@ enum clk_types {
 	DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
 #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \
 	DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
-		 .parent = _parent, .dtable = _dtable, .flag = _flag)
+		 .parent = _parent, .dtable = _dtable, \
+		 .flag = CLK_DIVIDER_HIWORD_MASK | _flag)
 #define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \
 		_mux_flags) \
 	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
 		 .parent_names = _parent_names, .num_parents = _num_parents, \
-		 .flag = _flag, .mux_flags = _mux_flags)
+		 .flag = _flag, .mux_flags = CLK_MUX_HIWORD_MASK | _mux_flags)
 #define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \
 	DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \
 		 .parent_names = _parent_names, .num_parents = _num_parents)
-- 
2.32.0

Re: [PATCH v2 07/13] clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers

[Geert Uytterhoeven]

Hi Phil,

On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> All of the muxes and dividers that can be modified require the HIWORD
> flags, so make the macros set them. It won't affect read only muxes and
> dividers.
> This will make the clock tables a little easier to read, particularly for
> new SoCs coming.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> ---
>  drivers/clk/renesas/r9a07g044-cpg.c | 16 +++++++---------
>  drivers/clk/renesas/rzg2l-cpg.h     |  5 +++--
>  2 files changed, 10 insertions(+), 11 deletions(-)

This needs an update for the new drivers/clk/renesas/r9a07g043-cpg.c.

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 08/13] clk: renesas: rzg2l: Make use of CLK_MON registers optional

[Phil Edworthy]

The rz/v2m SoC doesn't use CLK_MON registers, so make it optional.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g044-cpg.c |  4 ++++
 drivers/clk/renesas/rzg2l-cpg.c     | 25 +++++++++++++++----------
 drivers/clk/renesas/rzg2l-cpg.h     |  3 +++
 3 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index b187d9ac47aa..3393754ffb5e 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -374,6 +374,8 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
 	/* Resets */
 	.resets = r9a07g044_resets,
 	.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
+
+	.has_clk_mon_regs = true,
 };
 
 #ifdef CONFIG_CLK_R9A07G054
@@ -396,5 +398,7 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = {
 	/* Resets */
 	.resets = r9a07g044_resets,
 	.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
+
+	.has_clk_mon_regs = true,
 };
 #endif
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 486d0656c58a..c357b0bfa119 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -498,16 +498,18 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
 	if (!enable)
 		return 0;
 
-	for (i = 1000; i > 0; --i) {
-		if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
-			break;
-		cpu_relax();
-	}
+	if (priv->info->has_clk_mon_regs) {
+		for (i = 1000; i > 0; --i) {
+			if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
+				break;
+			cpu_relax();
+		}
 
-	if (!i) {
-		dev_err(dev, "Failed to enable CLK_ON %p\n",
-			priv->base + CLK_ON_R(reg));
-		return -ETIMEDOUT;
+		if (!i) {
+			dev_err(dev, "Failed to enable CLK_ON %p\n",
+				priv->base + CLK_ON_R(reg));
+			return -ETIMEDOUT;
+		}
 	}
 
 	return 0;
@@ -568,7 +570,10 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
 	if (clock->sibling)
 		return clock->enabled;
 
-	value = readl(priv->base + CLK_MON_R(clock->off));
+	if (priv->info->has_clk_mon_regs)
+		value = readl(priv->base + CLK_MON_R(clock->off));
+	else
+		value = readl(priv->base + clock->off);
 
 	return value & bitmask;
 }
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 592dd9515cfc..f04671376af5 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -181,6 +181,7 @@ struct rzg2l_reset {
  * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
  *                 should not be disabled without a knowledgeable driver
  * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
+ * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
  */
 struct rzg2l_cpg_info {
 	/* Core Clocks */
@@ -201,6 +202,8 @@ struct rzg2l_cpg_info {
 	/* Critical Module Clocks that should not be disabled */
 	const unsigned int *crit_mod_clks;
 	unsigned int num_crit_mod_clks;
+
+	bool has_clk_mon_regs;
 };
 
 extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
-- 
2.32.0

Re: [PATCH v2 08/13] clk: renesas: rzg2l: Make use of CLK_MON registers optional

[Geert Uytterhoeven]

Hi Phil,

Thanks for your patch!

On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> The rz/v2m SoC doesn't use CLK_MON registers, so make it optional.

RZ/V2M ... them

>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

>  drivers/clk/renesas/r9a07g044-cpg.c |  4 ++++
>  drivers/clk/renesas/rzg2l-cpg.c     | 25 +++++++++++++++----------
>  drivers/clk/renesas/rzg2l-cpg.h     |  3 +++
>  3 files changed, 22 insertions(+), 10 deletions(-)

This needs an update for the new drivers/clk/renesas/r9a07g043-cpg.c.

> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -498,16 +498,18 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
>         if (!enable)
>                 return 0;
>
> -       for (i = 1000; i > 0; --i) {
> -               if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
> -                       break;
> -               cpu_relax();
> -       }
> +       if (priv->info->has_clk_mon_regs) {
> +               for (i = 1000; i > 0; --i) {
> +                       if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
> +                               break;
> +                       cpu_relax();
> +               }
>
> -       if (!i) {
> -               dev_err(dev, "Failed to enable CLK_ON %p\n",
> -                       priv->base + CLK_ON_R(reg));
> -               return -ETIMEDOUT;
> +               if (!i) {
> +                       dev_err(dev, "Failed to enable CLK_ON %p\n",
> +                               priv->base + CLK_ON_R(reg));
> +                       return -ETIMEDOUT;
> +               }

or just insert:

    if (!priv->info->has_clk_mon_regs)
            return 0;

and no more changes are needed to this function.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 09/13] clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg

[Phil Edworthy]

The RZ/V2M doesn't have a matching set of reset monitor regs for each reset
reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has a
single bit per module.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/rzg2l-cpg.c |  6 +++++-
 drivers/clk/renesas/rzg2l-cpg.h | 10 ++++++++--
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index c357b0bfa119..220955366538 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -748,8 +748,12 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
 	const struct rzg2l_cpg_info *info = priv->info;
 	unsigned int reg = info->resets[id].off;
 	u32 bitmask = BIT(info->resets[id].bit);
+	u32 monbitmask = BIT(info->resets[id].monbit);
 
-	return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
+	if (info->has_clk_mon_regs)
+		return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
+	else
+		return !!(readl(priv->base + CPG_RST_MON) & monbitmask);
 }
 
 static const struct reset_control_ops rzg2l_cpg_reset_ops = {
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index f04671376af5..d1d08669066b 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -18,6 +18,7 @@
 #define CPG_PL3_SSEL		(0x408)
 #define CPG_PL6_SSEL		(0x414)
 #define CPG_PL6_ETH_SSEL	(0x418)
+#define CPG_RST_MON		(0x680)
 
 #define CPG_CLKSTATUS_SELSDHI0_STS	BIT(28)
 #define CPG_CLKSTATUS_SELSDHI1_STS	BIT(29)
@@ -151,17 +152,22 @@ struct rzg2l_mod_clk {
  *
  * @off: register offset
  * @bit: reset bit
+ * @monbit: monitor bit in CPG_RST_MON register, -1 if none
  */
 struct rzg2l_reset {
 	u16 off;
 	u8 bit;
+	s8 monbit;
 };
 
-#define DEF_RST(_id, _off, _bit)	\
+#define DEF_RST_MON(_id, _off, _bit, _monbit)	\
 	[_id] = { \
 		.off = (_off), \
-		.bit = (_bit) \
+		.bit = (_bit), \
+		.monbit = (_monbit) \
 	}
+#define DEF_RST(_id, _off, _bit)	\
+	DEF_RST_MON(_id, _off, _bit, -1)
 
 /**
  * struct rzg2l_cpg_info - SoC-specific CPG Description
-- 
2.32.0

Re: [PATCH v2 09/13] clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg

[Geert Uytterhoeven]

Hi Phil,

On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> The RZ/V2M doesn't have a matching set of reset monitor regs for each reset
> reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has a
> single bit per module.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -748,8 +748,12 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
>         const struct rzg2l_cpg_info *info = priv->info;
>         unsigned int reg = info->resets[id].off;
>         u32 bitmask = BIT(info->resets[id].bit);
> +       u32 monbitmask = BIT(info->resets[id].monbit);

BIT(-1) is not defined...

>
> -       return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
> +       if (info->has_clk_mon_regs)
> +               return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
> +       else
> +               return !!(readl(priv->base + CPG_RST_MON) & monbitmask);

... hence the above may behave badly when the reset has no bit in
CPG_RST_MON (69 resets do not have a bit in CPG_RST_MON).

> --- a/drivers/clk/renesas/rzg2l-cpg.h
> +++ b/drivers/clk/renesas/rzg2l-cpg.h
> @@ -18,6 +18,7 @@
>  #define CPG_PL3_SSEL           (0x408)
>  #define CPG_PL6_SSEL           (0x414)
>  #define CPG_PL6_ETH_SSEL       (0x418)
> +#define CPG_RST_MON            (0x680)
>
>  #define CPG_CLKSTATUS_SELSDHI0_STS     BIT(28)
>  #define CPG_CLKSTATUS_SELSDHI1_STS     BIT(29)
> @@ -151,17 +152,22 @@ struct rzg2l_mod_clk {
>   *
>   * @off: register offset
>   * @bit: reset bit
> + * @monbit: monitor bit in CPG_RST_MON register, -1 if none
>   */
>  struct rzg2l_reset {
>         u16 off;
>         u8 bit;
> +       s8 monbit;
>  };
>
> -#define DEF_RST(_id, _off, _bit)       \
> +#define DEF_RST_MON(_id, _off, _bit, _monbit)  \
>         [_id] = { \
>                 .off = (_off), \
> -               .bit = (_bit) \
> +               .bit = (_bit), \
> +               .monbit = (_monbit) \
>         }
> +#define DEF_RST(_id, _off, _bit)       \
> +       DEF_RST_MON(_id, _off, _bit, -1)
>
>  /**
>   * struct rzg2l_cpg_info - SoC-specific CPG Description

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 09/13] clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg

[Phil Edworthy]

Hi Geert,

On  26 April 2022 16:37 Geert Uytterhoeven wrote:
> On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy wrote:
> > The RZ/V2M doesn't have a matching set of reset monitor regs for each
> reset
> > reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has
> a
> > single bit per module.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -748,8 +748,12 @@ static int rzg2l_cpg_status(struct
> reset_controller_dev *rcdev,
> >         const struct rzg2l_cpg_info *info = priv->info;
> >         unsigned int reg = info->resets[id].off;
> >         u32 bitmask = BIT(info->resets[id].bit);
> > +       u32 monbitmask = BIT(info->resets[id].monbit);
> 
> BIT(-1) is not defined...
> 
> >
> > -       return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
> > +       if (info->has_clk_mon_regs)
> > +               return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
> > +       else
> > +               return !!(readl(priv->base + CPG_RST_MON) & monbitmask);
> 
> ... hence the above may behave badly when the reset has no bit in
> CPG_RST_MON (69 resets do not have a bit in CPG_RST_MON).

Ah, right. The SoCs other than RZ/V2M have monbit = -1, but they all
have info->has_clk_mon_regs = 1.
Still, I take you point that it's not very good code.


> > --- a/drivers/clk/renesas/rzg2l-cpg.h
> > +++ b/drivers/clk/renesas/rzg2l-cpg.h
> > @@ -18,6 +18,7 @@
> >  #define CPG_PL3_SSEL           (0x408)
> >  #define CPG_PL6_SSEL           (0x414)
> >  #define CPG_PL6_ETH_SSEL       (0x418)
> > +#define CPG_RST_MON            (0x680)
> >
> >  #define CPG_CLKSTATUS_SELSDHI0_STS     BIT(28)
> >  #define CPG_CLKSTATUS_SELSDHI1_STS     BIT(29)
> > @@ -151,17 +152,22 @@ struct rzg2l_mod_clk {
> >   *
> >   * @off: register offset
> >   * @bit: reset bit
> > + * @monbit: monitor bit in CPG_RST_MON register, -1 if none
> >   */
> >  struct rzg2l_reset {
> >         u16 off;
> >         u8 bit;
> > +       s8 monbit;
> >  };
> >
> > -#define DEF_RST(_id, _off, _bit)       \
> > +#define DEF_RST_MON(_id, _off, _bit, _monbit)  \
> >         [_id] = { \
> >                 .off = (_off), \
> > -               .bit = (_bit) \
> > +               .bit = (_bit), \
> > +               .monbit = (_monbit) \
> >         }
> > +#define DEF_RST(_id, _off, _bit)       \
> > +       DEF_RST_MON(_id, _off, _bit, -1)
> >
> >  /**
> >   * struct rzg2l_cpg_info - SoC-specific CPG Description

Thanks
Phil

[PATCH v2 10/13] clk: renesas: Add RZ/V2M support using the rzg2l driver

[Phil Edworthy]

The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have
any CLK_MON registers.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/Kconfig         |   5 +
 drivers/clk/renesas/Makefile        |   1 +
 drivers/clk/renesas/r9a09g011-cpg.c | 164 ++++++++++++++++++++++++++++
 drivers/clk/renesas/rzg2l-cpg.c     |   6 +
 drivers/clk/renesas/rzg2l-cpg.h     |   7 ++
 5 files changed, 183 insertions(+)
 create mode 100644 drivers/clk/renesas/r9a09g011-cpg.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index c281f3af5716..83c5a9929936 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -35,6 +35,7 @@ config CLK_RENESAS
 	select CLK_R9A06G032 if ARCH_R9A06G032
 	select CLK_R9A07G044 if ARCH_R9A07G044
 	select CLK_R9A07G054 if ARCH_R9A07G054
+        select CLK_R9A09G011 if ARCH_R9A09G011
 	select CLK_SH73A0 if ARCH_SH73A0
 
 if CLK_RENESAS
@@ -168,6 +169,10 @@ config CLK_R9A07G054
 	bool "RZ/V2L clock support" if COMPILE_TEST
 	select CLK_RZG2L
 
+config CLK_R9A09G011
+       bool "RZ/V2M clock support" if COMPILE_TEST
+       select CLK_RZG2L
+
 config CLK_SH73A0
 	bool "SH-Mobile AG5 clock support" if COMPILE_TEST
 	select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index d5e571699a30..650dbe2bb5c6 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_CLK_R8A779F0)		+= r8a779f0-cpg-mssr.o
 obj-$(CONFIG_CLK_R9A06G032)		+= r9a06g032-clocks.o
 obj-$(CONFIG_CLK_R9A07G044)		+= r9a07g044-cpg.o
 obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o
+obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o
 obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
 
 # Family
diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c
new file mode 100644
index 000000000000..47b93c1dec11
--- /dev/null
+++ b/drivers/clk/renesas/r9a09g011-cpg.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/V2M Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ * Based on r9a07g044-cpg.c
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/clock/r9a09g011-cpg.h>
+
+#include "rzg2l-cpg.h"
+
+#define RZV2M_SAMPLL4_CLK1	0x104
+#define RZV2M_SAMPLL4_CLK2	0x108
+
+#define PLL4_CONF	(RZV2M_SAMPLL4_CLK1 << 22 | RZV2M_SAMPLL4_CLK2 << 12)
+
+#define DIV_A		DDIV_PACK(0x200, 0, 3)
+#define DIV_B		DDIV_PACK(0x204, 0, 2)
+#define DIV_E		DDIV_PACK(0x204, 8, 1)
+#define DIV_W		DDIV_PACK(0x328, 0, 3)
+
+#define SEL_B		SEL_PLL_PACK(0x214, 0, 1)
+#define SEL_E		SEL_PLL_PACK(0x214, 2, 1)
+#define SEL_W0		SEL_PLL_PACK(0x32C, 0, 1)
+
+enum clk_ids {
+	/* Core Clock Outputs exported to DT */
+	LAST_DT_CORE_CLK = 0,
+
+	/* External Input Clocks */
+	CLK_EXTAL,
+
+	/* Internal Core Clocks */
+	CLK_MAIN,
+	CLK_MAIN_24,
+	CLK_MAIN_2,
+	CLK_PLL1,
+	CLK_PLL2,
+	CLK_PLL2_800,
+	CLK_PLL2_400,
+	CLK_PLL2_200,
+	CLK_PLL2_100,
+	CLK_PLL4,
+	CLK_DIV_A,
+	CLK_DIV_B,
+	CLK_DIV_E,
+	CLK_DIV_W,
+	CLK_SEL_B,
+	CLK_SEL_B_D2,
+	CLK_SEL_E,
+	CLK_SEL_W0,
+
+	/* Module Clocks */
+	MOD_CLK_BASE
+};
+
+/* Divider tables */
+static const struct clk_div_table dtable_diva[] = {
+	{0, 1},
+	{1, 2},
+	{2, 3},
+	{3, 4},
+	{4, 6},
+	{5, 12},
+	{6, 24},
+	{0, 0},
+};
+
+static const struct clk_div_table dtable_divb[] = {
+	{0, 1},
+	{1, 2},
+	{2, 4},
+	{3, 8},
+	{0, 0},
+};
+
+static const struct clk_div_table dtable_divw[] = {
+	{0, 6},
+	{1, 7},
+	{2, 8},
+	{3, 9},
+	{4, 10},
+	{5, 11},
+	{6, 12},
+	{0, 0},
+};
+
+/* Mux clock tables */
+static const char * const sel_b[] = { ".main", ".divb" };
+static const char * const sel_e[] = { ".main", ".dive" };
+static const char * const sel_w[] = { ".main", ".divw" };
+
+static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
+	/* External Clock Inputs */
+	DEF_INPUT("extal",	CLK_EXTAL),
+
+	/* Internal Core Clocks */
+	DEF_FIXED(".main",	CLK_MAIN,	CLK_EXTAL,	1,	1),
+	DEF_FIXED(".main_24",	CLK_MAIN_24,	CLK_MAIN,	1,	2),
+	DEF_FIXED(".main_2",	CLK_MAIN_2,	CLK_MAIN,	1,	24),
+	DEF_FIXED(".pll1",	CLK_PLL1,	CLK_MAIN_2,	498,	1),
+	DEF_FIXED(".pll2",	CLK_PLL2,	CLK_MAIN_2,	800,	1),
+	DEF_FIXED(".pll2_800",	CLK_PLL2_800,	CLK_PLL2,	1,	2),
+	DEF_FIXED(".pll2_400",	CLK_PLL2_400,	CLK_PLL2_800,	1,	2),
+	DEF_FIXED(".pll2_200",	CLK_PLL2_200,	CLK_PLL2_800,	1,	4),
+	DEF_FIXED(".pll2_100",	CLK_PLL2_100,	CLK_PLL2_800,	1,	8),
+	DEF_SAMPLL(".pll4",	CLK_PLL4,	CLK_MAIN_2,	PLL4_CONF),
+
+	DEF_DIV_RO(".diva",	CLK_DIV_A,	CLK_PLL1,	DIV_A,	dtable_diva),
+	DEF_DIV_RO(".divb",	CLK_DIV_B,	CLK_PLL2_400,	DIV_B,	dtable_divb),
+	DEF_DIV_RO(".divw",	CLK_DIV_W,	CLK_PLL4,	DIV_W,	dtable_divw),
+
+	DEF_MUX2_RO(".selb",	CLK_SEL_B,	SEL_B,		sel_b,   0),
+	DEF_MUX2(".selw0",	CLK_SEL_W0,	SEL_W0,		sel_w,   0, 0),
+
+	DEF_FIXED(".selb_d2",	CLK_SEL_B_D2,	CLK_SEL_B,	1,	2),
+};
+
+static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
+	DEF_MOD("gic",		R9A09G011_GIC_CLK,	CLK_SEL_B_D2, 0x400, 5),
+	DEF_MOD("syc_cnt_clk",	R9A09G011_SYC_CNT_CLK,	CLK_MAIN_24,  0x41c, 12),
+	DEF_MOD("urt0_clk",	R9A09G011_URT0_CLK,	CLK_SEL_W0,   0x438, 5),
+	DEF_MOD("ca53",		R9A09G011_CA53_CLK,	CLK_DIV_A,    0x448, 0),
+};
+
+static const struct rzg2l_reset r9a09g011_resets[] = {
+	DEF_RST_MON(R9A09G011_SYC_RST_N,	0x610, 9,  13),
+};
+
+static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
+	MOD_CLK_BASE + R9A09G011_CA53_CLK,
+	MOD_CLK_BASE + R9A09G011_GIC_CLK,
+	MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK,
+};
+
+const struct rzg2l_cpg_info r9a09g011_cpg_info = {
+	/* Core Clocks */
+	.core_clks = r9a09g011_core_clks,
+	.num_core_clks = ARRAY_SIZE(r9a09g011_core_clks),
+	.last_dt_core_clk = LAST_DT_CORE_CLK,
+	.num_total_core_clks = MOD_CLK_BASE,
+
+	/* Critical Module Clocks */
+	.crit_mod_clks = r9a09g011_crit_mod_clks,
+	.num_crit_mod_clks = ARRAY_SIZE(r9a09g011_crit_mod_clks),
+
+	/* Module Clocks */
+	.mod_clks = r9a09g011_mod_clks,
+	.num_mod_clks = ARRAY_SIZE(r9a09g011_mod_clks),
+	.num_hw_mod_clks = R9A09G011_CA53_CLK + 1,
+
+	/* Resets */
+	.resets = r9a09g011_resets,
+	.num_resets = ARRAY_SIZE(r9a09g011_resets),
+
+	.has_clk_mon_regs = false,
+};
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 220955366538..04f2cfafe6b3 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -967,6 +967,12 @@ static const struct of_device_id rzg2l_cpg_match[] = {
 		.compatible = "renesas,r9a07g054-cpg",
 		.data = &r9a07g054_cpg_info,
 	},
+#endif
+#ifdef CONFIG_CLK_R9A09G011
+	{
+		.compatible = "renesas,r9a09g011-cpg",
+		.data = &r9a09g011_cpg_info,
+	},
 #endif
 	{ /* sentinel */ }
 };
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index d1d08669066b..b571d1f1c5f3 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -103,11 +103,17 @@ enum clk_types {
 	DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
 		 .parent = _parent, .dtable = _dtable, \
 		 .flag = CLK_DIVIDER_HIWORD_MASK | _flag)
+#define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \
+	DEF_DIV(_name, _id, _parent, _conf, _dtable, CLK_DIVIDER_READ_ONLY)
 #define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \
 		_mux_flags) \
 	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
 		 .parent_names = _parent_names, .num_parents = _num_parents, \
 		 .flag = _flag, .mux_flags = CLK_MUX_HIWORD_MASK | _mux_flags)
+#define DEF_MUX2(_name, _id, _conf, _parent_names, _flag, _mux_flags) \
+	DEF_MUX(_name, _id, _conf, _parent_names, 2, _flag, _mux_flags)
+#define DEF_MUX2_RO(_name, _id, _conf, _parent_names, _flag) \
+	DEF_MUX2(_name, _id, _conf, _parent_names, _flag, CLK_MUX_READ_ONLY)
 #define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \
 	DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \
 		 .parent_names = _parent_names, .num_parents = _num_parents)
@@ -214,5 +220,6 @@ struct rzg2l_cpg_info {
 
 extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
 extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
+extern const struct rzg2l_cpg_info r9a09g011_cpg_info;
 
 #endif
-- 
2.32.0

Re: [PATCH v2 10/13] clk: renesas: Add RZ/V2M support using the rzg2l driver

[Geert Uytterhoeven]

Hi Phil,

On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have
> any CLK_MON registers.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/Kconfig
> +++ b/drivers/clk/renesas/Kconfig
> @@ -35,6 +35,7 @@ config CLK_RENESAS
>         select CLK_R9A06G032 if ARCH_R9A06G032
>         select CLK_R9A07G044 if ARCH_R9A07G044
>         select CLK_R9A07G054 if ARCH_R9A07G054
> +        select CLK_R9A09G011 if ARCH_R9A09G011

Please use a single TAB for indentation, instead of 8 spaces.

>         select CLK_SH73A0 if ARCH_SH73A0
>
>  if CLK_RENESAS
> @@ -168,6 +169,10 @@ config CLK_R9A07G054
>         bool "RZ/V2L clock support" if COMPILE_TEST
>         select CLK_RZG2L
>
> +config CLK_R9A09G011
> +       bool "RZ/V2M clock support" if COMPILE_TEST
> +       select CLK_RZG2L

Please use a single TAB for indentation, instead of 7 spaces.

> --- /dev/null
> +++ b/drivers/clk/renesas/r9a09g011-cpg.c
> @@ -0,0 +1,164 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * RZ/V2M Clock Pulse Generator / Module Standby and Software Reset
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + *
> + * Based on r9a07g044-cpg.c
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +
> +#include <dt-bindings/clock/r9a09g011-cpg.h>
> +
> +#include "rzg2l-cpg.h"
> +
> +#define RZV2M_SAMPLL4_CLK1     0x104
> +#define RZV2M_SAMPLL4_CLK2     0x108
> +
> +#define PLL4_CONF      (RZV2M_SAMPLL4_CLK1 << 22 | RZV2M_SAMPLL4_CLK2 << 12)
> +
> +#define DIV_A          DDIV_PACK(0x200, 0, 3)
> +#define DIV_B          DDIV_PACK(0x204, 0, 2)
> +#define DIV_E          DDIV_PACK(0x204, 8, 1)
> +#define DIV_W          DDIV_PACK(0x328, 0, 3)
> +
> +#define SEL_B          SEL_PLL_PACK(0x214, 0, 1)
> +#define SEL_E          SEL_PLL_PACK(0x214, 2, 1)
> +#define SEL_W0         SEL_PLL_PACK(0x32C, 0, 1)
> +
> +enum clk_ids {
> +       /* Core Clock Outputs exported to DT */
> +       LAST_DT_CORE_CLK = 0,
> +
> +       /* External Input Clocks */
> +       CLK_EXTAL,
> +
> +       /* Internal Core Clocks */
> +       CLK_MAIN,
> +       CLK_MAIN_24,
> +       CLK_MAIN_2,
> +       CLK_PLL1,
> +       CLK_PLL2,
> +       CLK_PLL2_800,
> +       CLK_PLL2_400,
> +       CLK_PLL2_200,
> +       CLK_PLL2_100,
> +       CLK_PLL4,
> +       CLK_DIV_A,
> +       CLK_DIV_B,
> +       CLK_DIV_E,
> +       CLK_DIV_W,
> +       CLK_SEL_B,
> +       CLK_SEL_B_D2,
> +       CLK_SEL_E,
> +       CLK_SEL_W0,
> +
> +       /* Module Clocks */
> +       MOD_CLK_BASE
> +};

> +/* Mux clock tables */
> +static const char * const sel_b[] = { ".main", ".divb" };
> +static const char * const sel_e[] = { ".main", ".dive" };

While DIV_E and CLK_DIV_E are defined above, the actual clock
definition for ".dive" is missing.
Fortunately(?) sel_e[] itself is unused.

> +static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
> +       DEF_MOD("gic",          R9A09G011_GIC_CLK,      CLK_SEL_B_D2, 0x400, 5),
> +       DEF_MOD("syc_cnt_clk",  R9A09G011_SYC_CNT_CLK,  CLK_MAIN_24,  0x41c, 12),
> +       DEF_MOD("urt0_clk",     R9A09G011_URT0_CLK,     CLK_SEL_W0,   0x438, 5),

The second UART clock (urt_pclk, shared by UART0 and UART1) is missing.

> +       DEF_MOD("ca53",         R9A09G011_CA53_CLK,     CLK_DIV_A,    0x448, 0),
> +};

> --- a/drivers/clk/renesas/rzg2l-cpg.h
> +++ b/drivers/clk/renesas/rzg2l-cpg.h
> @@ -103,11 +103,17 @@ enum clk_types {
>         DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
>                  .parent = _parent, .dtable = _dtable, \
>                  .flag = CLK_DIVIDER_HIWORD_MASK | _flag)
> +#define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \
> +       DEF_DIV(_name, _id, _parent, _conf, _dtable, CLK_DIVIDER_READ_ONLY)

It feels a bit strange CLK_DIVIDER_HIWORD_MASK (or CLK_MUX_HIWORD_MASK
below) is set for a read-only clock, but I guess it doesn't hurt,
as the hiword flag won't be used anyway.

>  #define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \
>                 _mux_flags) \
>         DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
>                  .parent_names = _parent_names, .num_parents = _num_parents, \
>                  .flag = _flag, .mux_flags = CLK_MUX_HIWORD_MASK | _mux_flags)
> +#define DEF_MUX2(_name, _id, _conf, _parent_names, _flag, _mux_flags) \
> +       DEF_MUX(_name, _id, _conf, _parent_names, 2, _flag, _mux_flags)

Instead of adding a new variant for muxes with 2 parents, perhaps
it makes sense to move the ARRAY_SIZE() into the DEF_MUX() macro,
so the number of parents is always detected automatically?

> +#define DEF_MUX2_RO(_name, _id, _conf, _parent_names, _flag) \
> +       DEF_MUX2(_name, _id, _conf, _parent_names, _flag, CLK_MUX_READ_ONLY)

Same for CLK_MUX_HIWORD_MASK.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 11/13] arm64: defconfig: Enable Renesas RZ/V2M SoC

[Phil Edworthy]

Enable the Renesas RZ/V2M SoC and the uart it uses.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
 arch/arm64/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 813e644b6af1..cc8196c48029 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -428,6 +428,7 @@ CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_OMAP=y
 CONFIG_SERIAL_8250_MT6577=y
 CONFIG_SERIAL_8250_UNIPHIER=y
+CONFIG_SERIAL_8250_EM=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
@@ -1106,6 +1107,7 @@ CONFIG_ARCH_R8A774E1=y
 CONFIG_ARCH_R8A774A1=y
 CONFIG_ARCH_R8A774B1=y
 CONFIG_ARCH_R9A07G044=y
+CONFIG_ARCH_R9A09G011=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_ROCKCHIP_PM_DOMAINS=y
 CONFIG_ARCH_TEGRA_132_SOC=y
-- 
2.32.0

[PATCH v2 11/13] arm64: defconfig: Enable Renesas RZ/V2M SoC

[Phil Edworthy]

Enable the Renesas RZ/V2M SoC and the uart it uses.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
 arch/arm64/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 813e644b6af1..cc8196c48029 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -428,6 +428,7 @@ CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_OMAP=y
 CONFIG_SERIAL_8250_MT6577=y
 CONFIG_SERIAL_8250_UNIPHIER=y
+CONFIG_SERIAL_8250_EM=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
@@ -1106,6 +1107,7 @@ CONFIG_ARCH_R8A774E1=y
 CONFIG_ARCH_R8A774A1=y
 CONFIG_ARCH_R8A774B1=y
 CONFIG_ARCH_R9A07G044=y
+CONFIG_ARCH_R9A09G011=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_ROCKCHIP_PM_DOMAINS=y
 CONFIG_ARCH_TEGRA_132_SOC=y
-- 
2.32.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v2 11/13] arm64: defconfig: Enable Renesas RZ/V2M SoC

[Geert Uytterhoeven]

On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> Enable the Renesas RZ/V2M SoC and the uart it uses.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 11/13] arm64: defconfig: Enable Renesas RZ/V2M SoC

[Geert Uytterhoeven]

On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> Enable the Renesas RZ/V2M SoC and the uart it uses.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 12/13] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC

[Phil Edworthy]

Details of the SoC can be found here:
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 99 ++++++++++++++++++++++
 1 file changed, 99 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
new file mode 100644
index 000000000000..fe1f5107351f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2M SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a09g011-cpg.h>
+
+/ {
+	compatible = "renesas,r9a09g011";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			reg = <0>;
+			device_type = "cpu";
+			clocks = <&cpg CPG_CORE R9A09G011_CA53_CLK>;
+		};
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gic: interrupt-controller@82000000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0x82010000 0 0x1000>,
+			      <0x0 0x82020000 0 0x20000>,
+			      <0x0 0x82040000 0 0x20000>,
+			      <0x0 0x82060000 0 0x20000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		cpg: clock-controller@a3500000 {
+			compatible = "renesas,r9a09g011-cpg";
+			reg = <0 0xa3500000 0 0x10000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		sys: system-configuration@a3f03000 {
+			compatible = "renesas,r9a09g011-sys";
+			reg = <0 0xa3f03000 0 0x400>;
+			status = "disabled";
+		};
+
+		uart0: serial@a4040000 {
+			compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
+			reg = <0 0xa4040000 0 0x38>;
+			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>;
+			clock-names = "sclk";
+			status = "disabled";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+		clocks = <&cpg CPG_MOD R9A09G011_SYC_CNT_CLK>;
+		clock-names = "clk";
+		resets = <&cpg R9A09G011_SYC_RST_N>;
+	};
+};
-- 
2.32.0

Re: [PATCH v2 12/13] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC

[Geert Uytterhoeven]

Hi Phil,

On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> Details of the SoC can be found here:
> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
> @@ -0,0 +1,99 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/V2M SoC
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/r9a09g011-cpg.h>
> +
> +/ {
> +       compatible = "renesas,r9a09g011";
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> +       extal_clk: extal {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by the board */
> +               clock-frequency = <0>;
> +       };
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu-map {
> +                       cluster0 {
> +                               core0 {
> +                                       cpu = <&cpu0>;
> +                               };
> +                       };
> +               };
> +
> +               cpu0: cpu@0 {
> +                       compatible = "arm,cortex-a53";
> +                       reg = <0>;
> +                       device_type = "cpu";
> +                       clocks = <&cpg CPG_CORE R9A09G011_CA53_CLK>;

CPG_MOD?

> +               };
> +       };
> +
> +       soc: soc {
> +               compatible = "simple-bus";
> +               interrupt-parent = <&gic>;
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               gic: interrupt-controller@82000000 {
> +                       compatible = "arm,gic-400";
> +                       #interrupt-cells = <3>;
> +                       #address-cells = <0>;
> +                       interrupt-controller;
> +                       reg = <0x0 0x82010000 0 0x1000>,
> +                             <0x0 0x82020000 0 0x20000>,
> +                             <0x0 0x82040000 0 0x20000>,
> +                             <0x0 0x82060000 0 0x20000>;
> +                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;

clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
clock-names = "clk";

> +               };
> +
> +               cpg: clock-controller@a3500000 {
> +                       compatible = "renesas,r9a09g011-cpg";
> +                       reg = <0 0xa3500000 0 0x10000>;

Size should be 0x1000, according to the address map.

> +                       clocks = <&extal_clk>;
> +                       clock-names = "extal";
> +                       #clock-cells = <2>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <0>;
> +               };
> +
> +               sys: system-configuration@a3f03000 {
> +                       compatible = "renesas,r9a09g011-sys";

system-controller@a3f03000?

Pending acceptance of the DT bindings.

> +                       reg = <0 0xa3f03000 0 0x400>;
> +                       status = "disabled";

I think there is no need to keep this disabled.

> +               };
> +
> +               uart0: serial@a4040000 {
> +                       compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
> +                       reg = <0 0xa4040000 0 0x38>;

Register offsets are documented until and including 0x7c,
so size should be 0x80 (which matches the address map).

> +                       interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>;
> +                       clock-names = "sclk";
> +                       status = "disabled";
> +               };
> +       };
> +
> +       timer {
> +               compatible = "arm,armv8-timer";
> +               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
> +                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
> +                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
> +                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
> +               clocks = <&cpg CPG_MOD R9A09G011_SYC_CNT_CLK>;
> +               clock-names = "clk";
> +               resets = <&cpg R9A09G011_SYC_RST_N>;

The three properties above are not document, causing the following
"make dtbs_check" error message:

arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dtb: timer:
'clock-names', 'clocks', 'resets' do not match any of the regexes:
'pinctrl-[0-9]+'
        From schema: Documentation/devicetree/bindings/timer/arm,arch_timer.yaml

> +       };
> +};

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 12/13] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC

[Phil Edworthy]

Hi Geert,

On 26 April 2022 19:13 Geert Uytterhoeven wrote:
> On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy wrote:
> > Details of the SoC can be found here:
> > https://www.renesas.com/us/en/products/microcontrollers-
> microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-
> accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
> > @@ -0,0 +1,99 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/V2M SoC
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/clock/r9a09g011-cpg.h>
> > +
> > +/ {
> > +       compatible = "renesas,r9a09g011";
> > +       #address-cells = <2>;
> > +       #size-cells = <2>;
> > +
> > +       /* clock can be either from exclk or crystal oscillator
> (XIN/XOUT) */
> > +       extal_clk: extal {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* This value must be overridden by the board */
> > +               clock-frequency = <0>;
> > +       };
> > +
> > +       cpus {
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu-map {
> > +                       cluster0 {
> > +                               core0 {
> > +                                       cpu = <&cpu0>;
> > +                               };
> > +                       };
> > +               };
> > +
> > +               cpu0: cpu@0 {
> > +                       compatible = "arm,cortex-a53";
> > +                       reg = <0>;
> > +                       device_type = "cpu";
> > +                       clocks = <&cpg CPG_CORE R9A09G011_CA53_CLK>;
> 
> CPG_MOD?
Ok

> > +               };
> > +       };
> > +
> > +       soc: soc {
> > +               compatible = "simple-bus";
> > +               interrupt-parent = <&gic>;
> > +               #address-cells = <2>;
> > +               #size-cells = <2>;
> > +               ranges;
> > +
> > +               gic: interrupt-controller@82000000 {
> > +                       compatible = "arm,gic-400";
> > +                       #interrupt-cells = <3>;
> > +                       #address-cells = <0>;
> > +                       interrupt-controller;
> > +                       reg = <0x0 0x82010000 0 0x1000>,
> > +                             <0x0 0x82020000 0 0x20000>,
> > +                             <0x0 0x82040000 0 0x20000>,
> > +                             <0x0 0x82060000 0 0x20000>;
> > +                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1)
> | IRQ_TYPE_LEVEL_HIGH)>;
> 
> clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
> clock-names = "clk";
Yes

> > +               };
> > +
> > +               cpg: clock-controller@a3500000 {
> > +                       compatible = "renesas,r9a09g011-cpg";
> > +                       reg = <0 0xa3500000 0 0x10000>;
> 
> Size should be 0x1000, according to the address map.
Yes

> > +                       clocks = <&extal_clk>;
> > +                       clock-names = "extal";
> > +                       #clock-cells = <2>;
> > +                       #reset-cells = <1>;
> > +                       #power-domain-cells = <0>;
> > +               };
> > +
> > +               sys: system-configuration@a3f03000 {
> > +                       compatible = "renesas,r9a09g011-sys";
> 
> system-controller@a3f03000?
> 
> Pending acceptance of the DT bindings.
I'll remove this node for the time being.

> > +                       reg = <0 0xa3f03000 0 0x400>;
> > +                       status = "disabled";
> 
> I think there is no need to keep this disabled.
> 
> > +               };
> > +
> > +               uart0: serial@a4040000 {
> > +                       compatible = "renesas,r9a09g011-uart",
> "renesas,em-uart";
> > +                       reg = <0 0xa4040000 0 0x38>;
> 
> Register offsets are documented until and including 0x7c,
> so size should be 0x80 (which matches the address map).
Yes

> > +                       interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>;
> > +                       clock-names = "sclk";
> > +                       status = "disabled";
> > +               };
> > +       };
> > +
> > +       timer {
> > +               compatible = "arm,armv8-timer";
> > +               interrupts-extended = <&gic GIC_PPI 13
> (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
> > +                                     <&gic GIC_PPI 14
> (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
> > +                                     <&gic GIC_PPI 11
> (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
> > +                                     <&gic GIC_PPI 10
> (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
> > +               clocks = <&cpg CPG_MOD R9A09G011_SYC_CNT_CLK>;
> > +               clock-names = "clk";
> > +               resets = <&cpg R9A09G011_SYC_RST_N>;
> 
> The three properties above are not document, causing the following
> "make dtbs_check" error message:
> 
> arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dtb: timer:
> 'clock-names', 'clocks', 'resets' do not match any of the regexes:
> 'pinctrl-[0-9]+'
>         From schema:
> Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
Right.
I assume the correct action is to update the bindings, right?
Of course, not much will work without this clock enabled ;)

Btw, do you know of a way to run "make dtbs_check" for a single dtb?

> > +       };
> > +};

Thanks
Phil

Re: [PATCH v2 12/13] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC

[Geert Uytterhoeven]

Hi Phil,

On Wed, Apr 27, 2022 at 8:53 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> On 26 April 2022 19:13 Geert Uytterhoeven wrote:
> > On Wed, Mar 30, 2022 at 5:42 PM Phil Edworthy wrote:
> > > Details of the SoC can be found here:
> > > https://www.renesas.com/us/en/products/microcontrollers-
> > microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-
> > accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output
> > >
> > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi

> > > +       timer {
> > > +               compatible = "arm,armv8-timer";
> > > +               interrupts-extended = <&gic GIC_PPI 13
> > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
> > > +                                     <&gic GIC_PPI 14
> > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
> > > +                                     <&gic GIC_PPI 11
> > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
> > > +                                     <&gic GIC_PPI 10
> > (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
> > > +               clocks = <&cpg CPG_MOD R9A09G011_SYC_CNT_CLK>;
> > > +               clock-names = "clk";
> > > +               resets = <&cpg R9A09G011_SYC_RST_N>;
> >
> > The three properties above are not document, causing the following
> > "make dtbs_check" error message:
> >
> > arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dtb: timer:
> > 'clock-names', 'clocks', 'resets' do not match any of the regexes:
> > 'pinctrl-[0-9]+'
> >         From schema:
> > Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
> Right.
> I assume the correct action is to update the bindings, right?

Yes.

> Of course, not much will work without this clock enabled ;)

And that's why you have it (rightfully) marked as a critical clock
in the clock driver.

> Btw, do you know of a way to run "make dtbs_check" for a single dtb?

"make dtbs_check" only runs checks on DTBs created by "make dtbs".
Hence make sure your .config has only CONFIG_ARCH_R9A09G011
enabled?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 13/13] arm64: dts: renesas: Add initial device tree for RZ/V2M EVK

[Phil Edworthy]

Add basic support for RZ/V2M EVK (based on R9A09G011):
- memory
- External input clock
- UART

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |  2 +
 .../boot/dts/renesas/r9a09g011-v2mevk2.dts    | 45 +++++++++++++++++++
 2 files changed, 47 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index d000f6b131dc..06ba849d3db3 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -79,3 +79,5 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
 dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
 
 dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
+
+dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
new file mode 100644
index 000000000000..90172de7851f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g011.dtsi"
+
+/ {
+	model = "RZ/V2M Evaluation Kit 2.0";
+	compatible = "renesas,rzv2mevk2", "renesas,r9a09g011";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@58000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x58000000 0x0 0x28000000>;
+	};
+
+	memory@180000000 {
+		device_type = "memory";
+		reg = <0x1 0x80000000 0x0 0x80000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <48000000>;
+};
+
+&sys {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.32.0

Re: [PATCH v2 13/13] arm64: dts: renesas: Add initial device tree for RZ/V2M EVK

[Geert Uytterhoeven]

Hi Phil,

On Wed, Mar 30, 2022 at 5:43 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> Add basic support for RZ/V2M EVK (based on R9A09G011):
> - memory
> - External input clock
> - UART
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +#include "r9a09g011.dtsi"
> +
> +/ {
> +       model = "RZ/V2M Evaluation Kit 2.0";
> +       compatible = "renesas,rzv2mevk2", "renesas,r9a09g011";
> +
> +       aliases {
> +               serial0 = &uart0;
> +       };
> +
> +       chosen {
> +               stdout-path = "serial0:115200n8";
> +       };
> +
> +       memory@58000000 {
> +               device_type = "memory";
> +               /* first 128MB is reserved for secure area. */

I guess there's much more reserved for the ISP firmware (1408 MiB?).

> +               reg = <0x0 0x58000000 0x0 0x28000000>;
> +       };
> +
> +       memory@180000000 {
> +               device_type = "memory";
> +               reg = <0x1 0x80000000 0x0 0x80000000>;
> +       };
> +};
> +
> +&extal_clk {
> +       clock-frequency = <48000000>;
> +};
> +
> +&sys {
> +       status = "okay";
> +};

No need to enable sys if it would be enabled by default.

> +
> +&uart0 {
> +       status = "okay";
> +};

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support

[Geert Uytterhoeven]

Hi Phil,

On Wed, Mar 30, 2022 at 5:40 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> RZ/V2M has a dual-core Cortex-A53 (1.0 GHz) CPU and built-in AI
> accelerator "DRP-AI" for vision, which is Renesas' original technology.
> It also has a 32-bit LPDDR4 interface and video codec (H.264).
>
> The RZ/V2M is used with ISP firmware that runs on one of the Cortex-A53
> cores. The firmware is an integral part of the SoC such that the HW
> User's Manual documents which of the peripheral modules are used by the
> firmware.
>
> Initial patches enables minimal peripherals on Renesas RZ/V2M EVK board
> and booted via nfs. Ethernet is broadly compatible with the
> etheravb-rcar-gen3 driver, but interrupts need some work so it's not
> been included in this patch set.
>
> Below blocks are enabled on Renesas RZ/V2M EVK board:
> - memory
> - External input clock
> - CPG
> - UART

Thanks for your series!

> v2:
>  * Removed SYS dt-bindings patch and corresponding SoC identification
>    as we only used the LSI version register. This can be dealt with
>    later on.

That patch[1] also introduced the ARCH_R9A09G011 config symbol,
without which none of the new code in this series is built.

[1] [PATCH 07/14] soc: renesas: Identify RZ/V2M SoC
    https://lore.kernel.org/all/20220321154232.56315-8-phil.edworthy@renesas.com/

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support

[Phil Edworthy]

Hi Geert,

On 20 April 2022 21:11 Geert Uytterhoeven wrote:
> Hi Phil,
> 
> On Wed, Mar 30, 2022 at 5:40 PM Phil Edworthy <phil.edworthy@renesas.com>
> wrote:
> > RZ/V2M has a dual-core Cortex-A53 (1.0 GHz) CPU and built-in AI
> > accelerator "DRP-AI" for vision, which is Renesas' original technology.
> > It also has a 32-bit LPDDR4 interface and video codec (H.264).
> >
> > The RZ/V2M is used with ISP firmware that runs on one of the Cortex-A53
> > cores. The firmware is an integral part of the SoC such that the HW
> > User's Manual documents which of the peripheral modules are used by the
> > firmware.
> >
> > Initial patches enables minimal peripherals on Renesas RZ/V2M EVK board
> > and booted via nfs. Ethernet is broadly compatible with the
> > etheravb-rcar-gen3 driver, but interrupts need some work so it's not
> > been included in this patch set.
> >
> > Below blocks are enabled on Renesas RZ/V2M EVK board:
> > - memory
> > - External input clock
> > - CPG
> > - UART
> 
> Thanks for your series!
> 
> > v2:
> >  * Removed SYS dt-bindings patch and corresponding SoC identification
> >    as we only used the LSI version register. This can be dealt with
> >    later on.
> 
> That patch[1] also introduced the ARCH_R9A09G011 config symbol,
> without which none of the new code in this series is built.
> 
> [1] [PATCH 07/14] soc: renesas: Identify RZ/V2M SoC
> 
> https://lore.kernel.org/all/20220321154232.56315-8-phil.edworthy@renesas.com/

Ah, right. I should have said that I replaced that patch with
"[PATCH v2 06/13] soc: renesas: Add RZ/V2M (R9A09G011) config option".
However, looking back I managed to send that patch only to myself.
Doh!

Thanks
Phil


> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But
> when I'm talking to journalists I just say "programmer" or something like
> that.
>                                 -- Linus Torvalds

[PATCH v2 06/13] soc: renesas: Add RZ/V2M (R9A09G011) config option

[Phil Edworthy]

Add a configuration option for the RZ/V2M SoC.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
---
 drivers/soc/renesas/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index fdc99a05a7e0..9440d4e510c0 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -308,6 +308,13 @@ config ARCH_R9A07G054
 	help
 	  This enables support for the Renesas RZ/V2L SoC variants.
 
+config ARCH_R9A09G011
+	bool "ARM64 Platform support for RZ/V2M"
+	select PM
+	select PM_GENERIC_DOMAINS
+	help
+	  This enables support for the Renesas RZ/V2M SoC.
+
 endif # ARM64
 
 config RST_RCAR
-- 
2.32.0

Re: [PATCH v2 06/13] soc: renesas: Add RZ/V2M (R9A09G011) config option

[Geert Uytterhoeven]

On Wed, Apr 20, 2022 at 10:43 PM Phil Edworthy
<phil.edworthy@renesas.com> wrote:
> Add a configuration option for the RZ/V2M SoC.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds