[PATCH v2 00/12] Add label to pcie nodes

[PATCH v2 00/12] Add label to pcie nodes

[Wasim Khan]

This patch series
- Adds label to pcie nodes in dts file for NXP's layerscape SoCs 
- Print the pcie controller number starting from 1 to match RMs
- Add checks for config resource size and fix indendation.

Changes in V2:
- Enable CONFIG_PCIE_LAYERSCAPE_GEN4 to make LX2160A-Rev1 work
- Fix CheckPatch issues
- Change 1KB size check to 4KB size check for ls_pcie_g4.
- Commit description updates

Wasim Khan (12):
  configs: lx2160a: Enable CONFIG_PCIE_LAYERSCAPE_GEN4
  pci: layerscape: Print pcie controller number starting from 1
  pci: ls_pcie_g4: Print pcie controller number starting from 1
  arm: dts: lx2160a: add label to pcie nodes in dts
  arm: dts: ls1046a: add label to pcie nodes in dts
  arm: dts: ls2080a: add label to pcie nodes in dts
  arm: dts: ls1088a: add label to pcie nodes in dts
  arm: dts: ls1012a: add label to pcie nodes in dts
  arm: dts: ls1043a: add label to pcie nodes in dts
  arm: dts: ls1028a: add label to pcie nodes in dts
  pci: layerscape: Add size check for config resource
  pci: ls_pcie_g4: Add size check for config resource

 arch/arm/dts/fsl-ls1012a.dtsi                |  3 ++-
 arch/arm/dts/fsl-ls1028a.dtsi                |  6 +++---
 arch/arm/dts/fsl-ls1043a.dtsi                |  9 +++++----
 arch/arm/dts/fsl-ls1046a.dtsi                | 12 ++++++------
 arch/arm/dts/fsl-ls1088a.dtsi                |  8 ++++----
 arch/arm/dts/fsl-ls2080a.dtsi                | 11 ++++++-----
 arch/arm/dts/fsl-lx2160a.dtsi                | 12 ++++++------
 configs/lx2160aqds_tfa_SECURE_BOOT_defconfig |  1 +
 configs/lx2160aqds_tfa_defconfig             |  1 +
 configs/lx2160ardb_tfa_SECURE_BOOT_defconfig |  1 +
 configs/lx2160ardb_tfa_defconfig             |  1 +
 configs/lx2160ardb_tfa_stmm_defconfig        |  1 +
 drivers/pci/pcie_layerscape_ep.c             |  4 +++-
 drivers/pci/pcie_layerscape_gen4.c           | 19 +++++++++++++++----
 drivers/pci/pcie_layerscape_rc.c             | 14 +++++++++++---
 15 files changed, 66 insertions(+), 37 deletions(-)

-- 
2.7.4

[PATCH v2 01/12] configs: lx2160a: Enable CONFIG_PCIE_LAYERSCAPE_GEN4

[Wasim Khan]

LX2160A-Rev1 uses PCIe layerscape Gen4 controller.
Enable CONFIG_PCIE_LAYERSCAPE_GEN4 for lx2160a.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- Added as new commit in V2

 configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 +
 configs/lx2160aqds_tfa_defconfig             | 1 +
 configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 +
 configs/lx2160ardb_tfa_defconfig             | 1 +
 configs/lx2160ardb_tfa_stmm_defconfig        | 1 +
 5 files changed, 5 insertions(+)

diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index f2faf7b..3aa5793 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -68,6 +68,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index b6a099b..27951b7 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -75,6 +75,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index a225f21..8e8bef0 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -59,6 +59,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index d147453..ac6b5bf 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -66,6 +66,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig
index 799fc12..c6b7230 100644
--- a/configs/lx2160ardb_tfa_stmm_defconfig
+++ b/configs/lx2160ardb_tfa_stmm_defconfig
@@ -68,6 +68,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_LAYERSCAPE_RC=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_PCF2127=y
 CONFIG_DM_SCSI=y
-- 
2.7.4

[PATCH v2 02/12] pci: layerscape: Print pcie controller number starting from 1

[Wasim Khan]

Print pcie controller number starting from 1

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- No Change

 drivers/pci/pcie_layerscape_ep.c | 4 +++-
 drivers/pci/pcie_layerscape_rc.c | 6 ++++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index eba230e..26c04a9 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/fsl_serdes.h>
 #include <dm.h>
 #include <dm/devres.h>
 #include <errno.h>
@@ -294,7 +295,8 @@ static int ls_pcie_ep_probe(struct udevice *dev)
 	pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 					      "num-ob-windows", 8);
 
-	printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+	printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+	       "Endpoint");
 	ls_pcie_setup_ep(pcie_ep);
 
 	if (!ls_pcie_link_up(pcie)) {
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index 25c6dde..f9e3089 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -273,7 +273,8 @@ static int ls_pcie_probe(struct udevice *dev)
 
 	pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
 	if (!pcie_rc->enabled) {
-		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+		printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+		       dev->name);
 		return 0;
 	}
 
@@ -342,7 +343,8 @@ static int ls_pcie_probe(struct udevice *dev)
 	      (unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
 	      pcie->big_endian);
 
-	printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+	printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+	       "Root Complex");
 	ls_pcie_setup_ctrl(pcie_rc);
 
 	if (!ls_pcie_link_up(pcie)) {
-- 
2.7.4

[PATCH v2 02/12] pci: layerscape: Print pcie controller number starting from 1

[Wasim Khan]

Print pcie controller number starting from 1

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 drivers/pci/pcie_layerscape_ep.c | 4 +++-
 drivers/pci/pcie_layerscape_rc.c | 6 ++++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index eba230e..35bb726 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/fsl_serdes.h>
 #include <dm.h>
 #include <dm/devres.h>
 #include <errno.h>
@@ -294,7 +295,8 @@ static int ls_pcie_ep_probe(struct udevice *dev)
 	pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 					      "num-ob-windows", 8);
 
-	printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+	printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+		"Endpoint");
 	ls_pcie_setup_ep(pcie_ep);
 
 	if (!ls_pcie_link_up(pcie)) {
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index 25c6dde..f9e3089 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -273,7 +273,8 @@ static int ls_pcie_probe(struct udevice *dev)
 
 	pcie_rc->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
 	if (!pcie_rc->enabled) {
-		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+		printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+		       dev->name);
 		return 0;
 	}
 
@@ -342,7 +343,8 @@ static int ls_pcie_probe(struct udevice *dev)
 	      (unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
 	      pcie->big_endian);
 
-	printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+	printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+	       "Root Complex");
 	ls_pcie_setup_ctrl(pcie_rc);
 
 	if (!ls_pcie_link_up(pcie)) {
-- 
2.7.4

[PATCH v2 03/12] pci: ls_pcie_g4: Print pcie controller number starting from 1

[Wasim Khan]

Print pcie controller number starting from 1

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- No Change

 drivers/pci/pcie_layerscape_gen4.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
index 428bfca..0226bde 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
  *
  * PCIe Gen4 driver for NXP Layerscape SoCs
  * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
@@ -472,7 +472,8 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 
 	pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
 	if (!pcie->enabled) {
-		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+		printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+		       dev->name);
 		return 0;
 	}
 
@@ -522,10 +523,12 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 	pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
 
 	if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
-		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+		printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+		       "Endpoint");
 		ls_pcie_g4_setup_ep(pcie);
 	} else {
-		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+		printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+		       "Root Complex");
 		ls_pcie_g4_setup_ctrl(pcie);
 	}
 
-- 
2.7.4

[PATCH v2 04/12] arm: dts: lx2160a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- Updated commit description

 arch/arm/dts/fsl-lx2160a.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index dee1e2f..69fcc0c 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -286,7 +286,7 @@
 
 	};
 
-	pcie at 3400000 {
+	pcie1: pcie at 3400000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03400000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03480000 0x0 0x40000   /* LUT registers */
@@ -300,7 +300,7 @@
 		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
 	};
 
-	pcie at 3500000 {
+	pcie2: pcie at 3500000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03500000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03580000 0x0 0x40000   /* LUT registers */
@@ -315,7 +315,7 @@
 		ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
 	};
 
-	pcie at 3600000 {
+	pcie3: pcie at 3600000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03600000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03680000 0x0 0x40000   /* LUT registers */
@@ -329,7 +329,7 @@
 		ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
 	};
 
-	pcie at 3700000 {
+	pcie4: pcie at 3700000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03700000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03780000 0x0 0x40000   /* LUT registers */
@@ -343,7 +343,7 @@
 		ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
 	};
 
-	pcie at 3800000 {
+	pcie5: pcie at 3800000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03800000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03880000 0x0 0x40000   /* LUT registers */
@@ -357,7 +357,7 @@
 		ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
 	};
 
-	pcie at 3900000 {
+	pcie6: pcie at 3900000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03900000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03980000 0x0 0x40000   /* LUT registers */
-- 
2.7.4

[PATCH v2 05/12] arm: dts: ls1046a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- Updated commit description

 arch/arm/dts/fsl-ls1046a.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 3f11d6c..155455d 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -241,7 +241,7 @@
 			dr_mode = "host";
 		};
 
-		pcie at 3400000 {
+		pcie1: pcie at 3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03480000 0x0 0x40000   /* lut registers */
@@ -257,7 +257,7 @@
 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie_ep at 3400000 {
+		pcie_ep1: pcie_ep at 3400000 {
 			compatible = "fsl,ls-pcie-ep";
 			reg = <0x00 0x03400000 0x0 0x80000
 			       0x00 0x034c0000 0x0 0x40000
@@ -268,7 +268,7 @@
 			big-endian;
 		};
 
-		pcie at 3500000 {
+		pcie2: pcie@3500000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03580000 0x0 0x40000   /* lut registers */
@@ -285,7 +285,7 @@
 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie_ep at 3500000 {
+		pcie_ep2: pcie_ep at 3500000 {
 			compatible = "fsl,ls-pcie-ep";
 			reg = <0x00 0x03500000 0x0 0x80000
 			       0x00 0x035c0000 0x0 0x40000
@@ -296,7 +296,7 @@
 			big-endian;
 		};
 
-		pcie at 3600000 {
+		pcie3: pcie@3600000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03680000 0x0 0x40000   /* lut registers */
@@ -312,7 +312,7 @@
 				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie_ep at 3600000 {
+		pcie_ep3: pcie_ep at 3600000 {
 			compatible = "fsl,ls-pcie-ep";
 			reg = <0x00 0x03600000 0x0 0x80000
 			       0x00 0x036c0000 0x0 0x40000
-- 
2.7.4

[PATCH v2 06/12] arm: dts: ls2080a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- Updated commit description

 arch/arm/dts/fsl-ls2080a.dtsi | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 90a0a3f..fae46c4 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Freescale ls2080a SOC common device tree source
+ * NXP ls2080a SOC common device tree source
  *
+ * Copyright 2020 NXP
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
  */
 
@@ -127,7 +128,7 @@
 		dr_mode = "host";
 	};
 
-	pcie at 3400000 {
+	pcie1: pcie at 3400000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03480000 0x0 0x80000   /* lut registers */
@@ -142,7 +143,7 @@
 			  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie at 3500000 {
+	pcie2: pcie at 3500000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03580000 0x0 0x80000   /* lut registers */
@@ -157,7 +158,7 @@
 			  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie at 3600000 {
+	pcie3: pcie at 3600000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03680000 0x0 0x80000   /* lut registers */
@@ -172,7 +173,7 @@
 			  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie at 3700000 {
+	pcie4: pcie at 3700000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03700000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03780000 0x0 0x80000   /* lut registers */
-- 
2.7.4

[PATCH v2 07/12] arm: dts: ls1088a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- Updated commit description

 arch/arm/dts/fsl-ls1088a.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index bf303c6..8de7998 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP ls1088a SOC common device tree source
  *
- * Copyright 2017 NXP
+ * Copyright 2017, 2020 NXP
  */
 
 / {
@@ -129,7 +129,7 @@
 		dr_mode = "host";
 	};
 
-	pcie at 3400000 {
+	pcie1: pcie at 3400000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03480000 0x0 0x80000   /* lut registers */
@@ -145,7 +145,7 @@
 			  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie at 3500000 {
+	pcie2: pcie at 3500000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03580000 0x0 0x80000   /* lut registers */
@@ -161,7 +161,7 @@
 			  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie at 3600000 {
+	pcie3: pcie at 3600000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03680000 0x0 0x80000   /* lut registers */
-- 
2.7.4

[PATCH v2 08/12] arm: dts: ls1012a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- Updated commit description

 arch/arm/dts/fsl-ls1012a.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 2d70c82..c401ba3 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
+ * Copyright 2020 NXP
  * Copyright 2016 Freescale Semiconductor
  */
 
@@ -116,7 +117,7 @@
 			status = "disabled";
 		};
 
-		pcie at 3400000 {
+		pcie1: pcie at 3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03480000 0x0 0x40000   /* lut registers */
-- 
2.7.4

[PATCH v2 09/12] arm: dts: ls1043a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- Updated commit description

 arch/arm/dts/fsl-ls1043a.dtsi | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index f7db44c..8ca57ea 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ * Device Tree Include file for NXP Layerscape-1043A family SoC.
  *
+ * Copyright 2020 NXP
  * Copyright (C) 2014-2015, Freescale Semiconductor
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
@@ -240,7 +241,7 @@
 			dr_mode = "host";
 		};
 
-		pcie at 3400000 {
+		pcie1: pcie at 3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
 			       0x00 0x03410000 0x0 0x10000   /* lut registers */
@@ -255,7 +256,7 @@
 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie at 3500000 {
+		pcie2: pcie at 3500000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
 			       0x00 0x03510000 0x0 0x10000   /* lut registers */
@@ -271,7 +272,7 @@
 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie at 3600000 {
+		pcie3: pcie at 3600000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
 			       0x00 0x03610000 0x0 0x10000   /* lut registers */
-- 
2.7.4

[PATCH v2 10/12] arm: dts: ls1028a: add label to pcie nodes in dts

[Wasim Khan]

Add label to pcie nodes in dts so that these nodes
are easy to refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- Updated commit description

 arch/arm/dts/fsl-ls1028a.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 9911690..ccf1a8d 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP ls1028a SOC common device tree source
  *
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  *
  */
 
@@ -85,7 +85,7 @@
 		status = "disabled";
 	};
 
-	pcie at 3400000 {
+	pcie1: pcie at 3400000 {
 	       compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
 	       reg = <0x00 0x03400000 0x0 0x80000
 		       0x00 0x03480000 0x0 0x40000   /* lut registers */
@@ -101,7 +101,7 @@
 		       0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie at 3500000 {
+	pcie2: pcie at 3500000 {
 	       compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
 	       reg = <0x00 0x03500000 0x0 0x80000
 		       0x00 0x03580000 0x0 0x40000   /* lut registers */
-- 
2.7.4

[PATCH v2 11/12] pci: layerscape: Add size check for config resource

[Wasim Khan]

resource "config" is required to have minimum 8KB space
as per hardware documentation.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- Updated commit description
- Fix CheckPatch issue

 drivers/pci/pcie_layerscape_rc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index f9e3089..7e232be 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -314,6 +314,13 @@ static int ls_pcie_probe(struct udevice *dev)
 		return ret;
 	}
 
+	cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
+	if (cfg_size < SZ_8K) {
+		printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n",
+		       PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_8K);
+		return 0;
+	}
+
 	/*
 	 * Fix the pcie memory map address and PF control registers address
 	 * for LS2088A series SoCs
@@ -323,7 +330,6 @@ static int ls_pcie_probe(struct udevice *dev)
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
 	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
 	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
-		cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
 		pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
 					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 		pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
-- 
2.7.4

[PATCH v2 12/12] pci: ls_pcie_g4: Add size check for config resource

[Wasim Khan]

resource "config" is required to have minimum 4KB space
to access all config space of PCI Express EP.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- Updated commit description
- Fix CheckPatch issue
- Change size check to 4KB to access PCIe config space

 drivers/pci/pcie_layerscape_gen4.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
index 0226bde..6e71173 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -455,6 +455,7 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 	u32 link_ctrl_sta;
 	u32 val;
 	int ret;
+	fdt_size_t cfg_size;
 
 	pcie->bus = dev;
 
@@ -488,6 +489,13 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 		return ret;
 	}
 
+	cfg_size = fdt_resource_size(&pcie->cfg_res);
+	if (cfg_size < SZ_4K) {
+		printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n",
+		       PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_4K);
+		return 0;
+	}
+
 	pcie->cfg = map_physmem(pcie->cfg_res.start,
 				fdt_resource_size(&pcie->cfg_res),
 				MAP_NOCACHE);
-- 
2.7.4

[PATCH v2 11/12] pci: layerscape: Add size check for config resource

[Priyanka Jain]

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Wasim Khan
>Sent: Tuesday, August 4, 2020 4:48 PM
>To: Priyanka Jain <priyanka.jain@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
>Z.q. Hou <zhiqiang.hou@nxp.com>
>Cc: u-boot at lists.denx.de; Wasim Khan <wasim.khan@nxp.com>
>Subject: [PATCH v2 11/12] pci: layerscape: Add size check for config resource
>
>resource "config" is required to have minimum 8KB space as per hardware
>documentation.
>
>Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
>---
>Changes in V2:
>- Updated commit description
>- Fix CheckPatch issue
>
> drivers/pci/pcie_layerscape_rc.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
>index f9e3089..7e232be 100644
>--- a/drivers/pci/pcie_layerscape_rc.c
>+++ b/drivers/pci/pcie_layerscape_rc.c
>@@ -314,6 +314,13 @@ static int ls_pcie_probe(struct udevice *dev)
> 		return ret;
> 	}
>
>+	cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
>+	if (cfg_size < SZ_8K) {
>+		printf("PCIe%d: %s Invalid size(0x%llx) for resource
>\"config\",expected minimum 0x%x\n",
>+		       PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_8K);
>+		return 0;
>+	}
>+
> 	/*
> 	 * Fix the pcie memory map address and PF control registers address
> 	 * for LS2088A series SoCs
>@@ -323,7 +330,6 @@ static int ls_pcie_probe(struct udevice *dev)
> 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
> 	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
> 	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
>-		cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
> 		pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
> 					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
> 		pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
>--
>2.7.4

Kindly fix build error on ls1021 platforms like ls1021aiot_qspi
https://travis-ci.org/github/p-priyanka-jain/u-boot/jobs/729630555

Regards
Priyanka

[PATCH v2 11/12] pci: layerscape: Add size check for config resource

[Wasim Khan]

resource "config" is required to have minimum 8KB space
as per hardware documentation.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- Updated commit description
- Fix CheckPatch issue

Changes in V3:
- Fix compilation issue with ls102xa platforms

 drivers/pci/pcie_layerscape_rc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index f9e3089..cdfcad6 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -314,6 +314,13 @@ static int ls_pcie_probe(struct udevice *dev)
 		return ret;
 	}
 
+	cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
+	if (cfg_size < SZ_8K) {
+		printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n",
+		       PCIE_SRDS_PRTCL(pcie->idx), dev->name, (u64)cfg_size, SZ_8K);
+		return 0;
+	}
+
 	/*
 	 * Fix the pcie memory map address and PF control registers address
 	 * for LS2088A series SoCs
@@ -323,7 +330,6 @@ static int ls_pcie_probe(struct udevice *dev)
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
 	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
 	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
-		cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
 		pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
 					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 		pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;
-- 
2.7.4