* [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus
@ 2017-02-23 10:33 Ashish Kumar
2017-02-23 10:33 ` [U-Boot] [PATCH v2] armv8: fsl-lsch3: Conditionally Remove errata a0009203 from lsch3 init Ashish Kumar
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Ashish Kumar @ 2017-02-23 10:33 UTC (permalink / raw)
To: u-boot
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
provides full cache coherency between two clusters of multi-core
CPUs and I/O coherency for devices and I/O masters.
This patch add new CONFIG defination and move existing register
space definaton of CCI-400 bus from from immap_lsch2 to fsl_immap,
so that it can be used for both chasis 2 and chasis 3.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
---
v2:
Add new Kconfig in alphabetic order
README | 9 ++++
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 1 +
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 48 --------------------
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
include/fsl_immap.h | 51 ++++++++++++++++++++++
7 files changed, 69 insertions(+), 48 deletions(-)
diff --git a/README b/README
index 4f0dbd4..34f5bd3 100644
--- a/README
+++ b/README
@@ -315,6 +315,15 @@ Many of the options are named exactly as the corresponding Linux
kernel configuration options. The intention is to make it easier to
build a config tool - later.
+- ARM Platform Bus Type(CCI):
+ CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
+ provides full cache coherency between two clusters of multi-core
+ CPUs and I/O coherency for devices and I/O masters
+
+ CONFIG_SYS_FSL_HAS_CCI400
+
+ Defined For SoC that has cache coherent interconnect
+ CCN-400
The following options need to be configured:
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index adccdf1..64fae17 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -7,6 +7,7 @@ config ARCH_LS1012A
select SYS_FSL_ERRATUM_A010315
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
+ select SYS_FSL_HAS_CCI400
config ARCH_LS1043A
bool
@@ -26,6 +27,7 @@ config ARCH_LS1043A
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
+ select SYS_FSL_HAS_CCI400
config ARCH_LS1046A
bool
@@ -45,6 +47,7 @@ config ARCH_LS1046A
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
+ select SYS_FSL_HAS_CCI400
config ARCH_LS2080A
bool
@@ -182,6 +185,9 @@ config SYS_FSL_IFC_BANK_COUNT
default 4 if ARCH_LS1046A
default 8 if ARCH_LS2080A
+config SYS_FSL_HAS_CCI400
+ bool
+
config SYS_FSL_HAS_DP_DDR
bool
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 335f225..a1ac4a0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -29,6 +29,7 @@
#ifdef CONFIG_SYS_FSL_DDR
#include <fsl_ddr.h>
#endif
+#include <fsl_immap.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 9489f85..d64fe7b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <fsl_immap.h>
#include <fsl_ifc.h>
#include <ahci.h>
#include <scsi.h>
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8ad199f..5210b8c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -543,54 +543,6 @@ struct ccsr_serdes {
u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
};
-#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
-#define CCI400_CTRLORD_EN_BARRIER 0
-#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
-#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
-#define CCI400_SNOOP_REQ_EN 0x00000001
-
-/* CCI-400 registers */
-struct ccsr_cci400 {
- u32 ctrl_ord; /* Control Override */
- u32 spec_ctrl; /* Speculation Control */
- u32 secure_access; /* Secure Access */
- u32 status; /* Status */
- u32 impr_err; /* Imprecise Error */
- u8 res_14[0x100 - 0x14];
- u32 pmcr; /* Performance Monitor Control */
- u8 res_104[0xfd0 - 0x104];
- u32 pid[8]; /* Peripheral ID */
- u32 cid[4]; /* Component ID */
- struct {
- u32 snoop_ctrl; /* Snoop Control */
- u32 sha_ord; /* Shareable Override */
- u8 res_1008[0x1100 - 0x1008];
- u32 rc_qos_ord; /* read channel QoS Value Override */
- u32 wc_qos_ord; /* read channel QoS Value Override */
- u8 res_1108[0x110c - 0x1108];
- u32 qos_ctrl; /* QoS Control */
- u32 max_ot; /* Max OT */
- u8 res_1114[0x1130 - 0x1114];
- u32 target_lat; /* Target Latency */
- u32 latency_regu; /* Latency Regulation */
- u32 qos_range; /* QoS Range */
- u8 res_113c[0x2000 - 0x113c];
- } slave[5]; /* Slave Interface */
- u8 res_6000[0x9004 - 0x6000];
- u32 cycle_counter; /* Cycle counter */
- u32 count_ctrl; /* Count Control */
- u32 overflow_status; /* Overflow Flag Status */
- u8 res_9010[0xa000 - 0x9010];
- struct {
- u32 event_select; /* Event Select */
- u32 event_count; /* Event Count */
- u32 counter_ctrl; /* Counter Control */
- u32 overflow_status; /* Overflow Flag Status */
- u8 res_a010[0xb000 - 0xa010];
- } pcounter[4]; /* Performance Counter */
- u8 res_e004[0x10000 - 0xe004];
-};
-
/* MMU 500 */
#define SMMU_SCR0 (SMMU_BASE + 0x0)
#define SMMU_SCR1 (SMMU_BASE + 0x4)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 0678fba..04add3b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -10,6 +10,7 @@
#define __ARCH_FSL_LSCH3_IMMAP_H_
#define CONFIG_SYS_IMMR 0x01000000
+#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x3090000)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
diff --git a/include/fsl_immap.h b/include/fsl_immap.h
index b1c4fe7..4f5a19c 100644
--- a/include/fsl_immap.h
+++ b/include/fsl_immap.h
@@ -133,4 +133,55 @@ struct ccsr_ddr {
u8 res_e5c[164];
u32 debug[64]; /* debug_1 to debug_64 */
};
+
+#ifdef CONFIG_SYS_FSL_HAS_CCI400
+#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
+#define CCI400_CTRLORD_EN_BARRIER 0
+#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
+#define CCI400_SNOOP_REQ_EN 0x00000001
+
+/* CCI-400 registers */
+struct ccsr_cci400 {
+ u32 ctrl_ord; /* Control Override */
+ u32 spec_ctrl; /* Speculation Control */
+ u32 secure_access; /* Secure Access */
+ u32 status; /* Status */
+ u32 impr_err; /* Imprecise Error */
+ u8 res_14[0x100 - 0x14];
+ u32 pmcr; /* Performance Monitor Control */
+ u8 res_104[0xfd0 - 0x104];
+ u32 pid[8]; /* Peripheral ID */
+ u32 cid[4]; /* Component ID */
+ struct {
+ u32 snoop_ctrl; /* Snoop Control */
+ u32 sha_ord; /* Shareable Override */
+ u8 res_1008[0x1100 - 0x1008];
+ u32 rc_qos_ord; /* read channel QoS Value Override */
+ u32 wc_qos_ord; /* read channel QoS Value Override */
+ u8 res_1108[0x110c - 0x1108];
+ u32 qos_ctrl; /* QoS Control */
+ u32 max_ot; /* Max OT */
+ u8 res_1114[0x1130 - 0x1114];
+ u32 target_lat; /* Target Latency */
+ u32 latency_regu; /* Latency Regulation */
+ u32 qos_range; /* QoS Range */
+ u8 res_113c[0x2000 - 0x113c];
+ } slave[5]; /* Slave Interface */
+ u8 res_6000[0x9004 - 0x6000];
+ u32 cycle_counter; /* Cycle counter */
+ u32 count_ctrl; /* Count Control */
+ u32 overflow_status; /* Overflow Flag Status */
+ u8 res_9010[0xa000 - 0x9010];
+ struct {
+ u32 event_select; /* Event Select */
+ u32 event_count; /* Event Count */
+ u32 counter_ctrl; /* Counter Control */
+ u32 overflow_status; /* Overflow Flag Status */
+ u8 res_a010[0xb000 - 0xa010];
+ } pcounter[4]; /* Performance Counter */
+ u8 res_e004[0x10000 - 0xe004];
+};
+#endif
+
#endif /* __FSL_IMMAP_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v2] armv8: fsl-lsch3: Conditionally Remove errata a0009203 from lsch3 init
2017-02-23 10:33 [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus Ashish Kumar
@ 2017-02-23 10:33 ` Ashish Kumar
2017-03-28 17:59 ` york sun
2017-02-23 10:33 ` [U-Boot] [PATCH v2] armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups Ashish Kumar
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Ashish Kumar @ 2017-02-23 10:33 UTC (permalink / raw)
To: u-boot
This i2c errata is only valid for LS2080A and its variants,
namely LS2080A, LS2085A and LS2088A
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
---
v2:
Change Descristion to make it more specific about impacted SoC
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 64fae17..29bc756 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -72,6 +72,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
+ select SYS_FSL_ERRATUM_A009203
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
@@ -279,6 +280,9 @@ config SYS_FSL_SDHC_CLK_DIV
clock, in another word SDHC_clk = Platform_clk / this_divider.
endmenu
+config SYS_FSL_ERRATUM_A009203
+ bool
+
config SYS_FSL_ERRATUM_A008336
bool
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d64fe7b..1e95540 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -153,6 +153,7 @@ static void erratum_rcw_src(void)
* This erratum requires setting glitch_en bit to enable
* digital glitch filter to improve clock stability.
*/
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
static void erratum_a009203(void)
{
u8 __iomem *ptr;
@@ -179,6 +180,7 @@ static void erratum_a009203(void)
#endif
#endif
}
+#endif
void bypass_smmu(void)
{
@@ -192,7 +194,9 @@ void fsl_lsch3_early_init_f(void)
{
erratum_rcw_src();
init_early_memctl_regs(); /* tighten IFC timing */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
erratum_a009203();
+#endif
erratum_a008514();
erratum_a008336();
#ifdef CONFIG_CHAIN_OF_TRUST
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v2] armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups
2017-02-23 10:33 [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus Ashish Kumar
2017-02-23 10:33 ` [U-Boot] [PATCH v2] armv8: fsl-lsch3: Conditionally Remove errata a0009203 from lsch3 init Ashish Kumar
@ 2017-02-23 10:33 ` Ashish Kumar
2017-03-25 16:35 ` york sun
2017-03-25 16:32 ` [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus york sun
2017-03-25 16:34 ` york sun
3 siblings, 1 reply; 7+ messages in thread
From: Ashish Kumar @ 2017-02-23 10:33 UTC (permalink / raw)
To: u-boot
Number of TZASC instances may vary across NXP SoCs.
So put TZASC configuration under instance specific defines.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
---
v2:
Change description to make it more appropriate
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ++++++++
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 24 +++++++++++++-----------
2 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 29bc756..9eaafba 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -62,6 +62,8 @@ config ARCH_LS2080A
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_2
+ select FSL_TZASC_1
+ select FSL_TZASC_2
select SYS_FSL_ERRATUM_A008336
select SYS_FSL_ERRATUM_A008511
select SYS_FSL_ERRATUM_A008514
@@ -201,6 +203,12 @@ config SYS_FSL_SRDS_2
config SYS_HAS_SERDES
bool
+config FSL_TZASC_1
+ bool
+
+config FSL_TZASC_2
+ bool
+
endmenu
menu "Layerscape clock tree configuration"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index a2185f2..79d1637 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -229,38 +229,40 @@ ENTRY(lowlevel_init)
* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
* placeholders.
*/
+#ifdef CONFIG_FSL_TZASC_1
ldr x1, =TZASC_GATE_KEEPER(0)
ldr w0, [x1] /* Filter 0 Gate Keeper Register */
orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
str w0, [x1]
- ldr x1, =TZASC_GATE_KEEPER(1)
- ldr w0, [x1] /* Filter 0 Gate Keeper Register */
- orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
- str w0, [x1]
-
ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
ldr w0, [x1] /* Region-0 Attributes Register */
orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
str w0, [x1]
+ ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
+ ldr w0, [x1] /* Region-0 Access Register */
+ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
+ str w0, [x1]
+#endif
+#ifdef CONFIG_FSL_TZASC_2
+ ldr x1, =TZASC_GATE_KEEPER(1)
+ ldr w0, [x1] /* Filter 0 Gate Keeper Register */
+ orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
+ str w0, [x1]
+
ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
ldr w0, [x1] /* Region-1 Attributes Register */
orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
str w0, [x1]
- ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
- ldr w0, [x1] /* Region-0 Access Register */
- mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
- str w0, [x1]
-
ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
ldr w0, [x1] /* Region-1 Attributes Register */
mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
str w0, [x1]
-
+#endif
isb
dsb sy
#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus
2017-02-23 10:33 [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus Ashish Kumar
2017-02-23 10:33 ` [U-Boot] [PATCH v2] armv8: fsl-lsch3: Conditionally Remove errata a0009203 from lsch3 init Ashish Kumar
2017-02-23 10:33 ` [U-Boot] [PATCH v2] armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups Ashish Kumar
@ 2017-03-25 16:32 ` york sun
2017-03-25 16:34 ` york sun
3 siblings, 0 replies; 7+ messages in thread
From: york sun @ 2017-03-25 16:32 UTC (permalink / raw)
To: u-boot
On 02/23/2017 02:27 AM, Ashish Kumar wrote:
> CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
> provides full cache coherency between two clusters of multi-core
> CPUs and I/O coherency for devices and I/O masters.
>
> This patch add new CONFIG defination and move existing register
> space definaton of CCI-400 bus from from immap_lsch2 to fsl_immap,
> so that it can be used for both chasis 2 and chasis 3.
>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
> ---
> v2:
> Add new Kconfig in alphabetic order
>
> README | 9 ++++
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++
> arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 +
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 1 +
> .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 48 --------------------
> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
> include/fsl_immap.h | 51 ++++++++++++++++++++++
> 7 files changed, 69 insertions(+), 48 deletions(-)
>
<snip>
> #define SMMU_SCR1 (SMMU_BASE + 0x4)
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index 0678fba..04add3b 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -10,6 +10,7 @@
> #define __ARCH_FSL_LSCH3_IMMAP_H_
>
> #define CONFIG_SYS_IMMR 0x01000000
> +#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x3090000)
Can you move this macro to Kconfig and clean up existing use?
York
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus
2017-02-23 10:33 [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus Ashish Kumar
` (2 preceding siblings ...)
2017-03-25 16:32 ` [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus york sun
@ 2017-03-25 16:34 ` york sun
3 siblings, 0 replies; 7+ messages in thread
From: york sun @ 2017-03-25 16:34 UTC (permalink / raw)
To: u-boot
On 02/23/2017 02:27 AM, Ashish Kumar wrote:
> CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
> provides full cache coherency between two clusters of multi-core
> CPUs and I/O coherency for devices and I/O masters.
>
> This patch add new CONFIG defination and move existing register
> space definaton of CCI-400 bus from from immap_lsch2 to fsl_immap,
> so that it can be used for both chasis 2 and chasis 3.
>
All of your patches have the (sometime inconsistent) indentation in
commit message. Please fix.
York
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v2] armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups
2017-02-23 10:33 ` [U-Boot] [PATCH v2] armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups Ashish Kumar
@ 2017-03-25 16:35 ` york sun
0 siblings, 0 replies; 7+ messages in thread
From: york sun @ 2017-03-25 16:35 UTC (permalink / raw)
To: u-boot
On 02/23/2017 02:27 AM, Ashish Kumar wrote:
> Number of TZASC instances may vary across NXP SoCs.
> So put TZASC configuration under instance specific defines.
>
Please fix the indentation. Otherwise this patch looks OK.
York
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH v2] armv8: fsl-lsch3: Conditionally Remove errata a0009203 from lsch3 init
2017-02-23 10:33 ` [U-Boot] [PATCH v2] armv8: fsl-lsch3: Conditionally Remove errata a0009203 from lsch3 init Ashish Kumar
@ 2017-03-28 17:59 ` york sun
0 siblings, 0 replies; 7+ messages in thread
From: york sun @ 2017-03-28 17:59 UTC (permalink / raw)
To: u-boot
On 02/23/2017 02:27 AM, Ashish Kumar wrote:
> This i2c errata is only valid for LS2080A and its variants,
> namely LS2080A, LS2085A and LS2088A
>
> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
> ---
> v2:
> Change Descristion to make it more specific about impacted SoC
Minor adjustment to subject and commit message. Applied to fsl-qoriq
master, awaiting upstream. Thanks.
York
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-03-28 17:59 UTC | newest]
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2017-02-23 10:33 [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus Ashish Kumar
2017-02-23 10:33 ` [U-Boot] [PATCH v2] armv8: fsl-lsch3: Conditionally Remove errata a0009203 from lsch3 init Ashish Kumar
2017-03-28 17:59 ` york sun
2017-02-23 10:33 ` [U-Boot] [PATCH v2] armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups Ashish Kumar
2017-03-25 16:35 ` york sun
2017-03-25 16:32 ` [U-Boot] [PATCH v2] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus york sun
2017-03-25 16:34 ` york sun
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