[U-Boot] [PATCH v2 1/6] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h

[U-Boot] [PATCH v2 1/6] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h

[Bharat Bhushan]

The stream ID allocation for Chasis3.0 devices,
LS1088, LS2088 and LS2080, can be shared.

This patch renames this accordingly.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
---
 .../asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h}  | 0
 include/configs/ls2080a_common.h                                        | 2 +-
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename arch/arm/include/asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h} (100%)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
similarity index 100%
rename from arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h
rename to arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 5072e20..427f623 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -13,7 +13,7 @@
 #define CONFIG_GICV3
 #define CONFIG_FSL_TZPC_BP147
 
-#include <asm/arch/ls2080a_stream_id.h>
+#include <asm/arch/stream_id_lsch3.h>
 #include <asm/arch/config.h>
 
 /* Link Definitions */
-- 
1.9.3

[U-Boot] [PATCH v2 2/6] fsl-lsch3: Rewording to support other Chassis-3 Socs

[Bharat Bhushan]

LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3
and shared same stream-id partitioning. This patch
rewords the definition to support all these SOCs.

Also have changes in description about iommu-map property
updates in PCI node.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
---
 .../arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index ee28323..d7d527d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -8,11 +8,11 @@
 #define __FSL_STREAM_ID_H
 
 /*
- * Stream IDs on ls2080a devices are not hardwired and are
- * programmed by sw.  There are a limited number of stream IDs
- * available, and the partitioning of them is scenario dependent.
- * This header defines the partitioning between legacy, PCI,
- * and DPAA2 devices.
+ * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a)
+ * devices are not hardwired and are programmed by sw. There are a limited
+ * number of stream IDs available, and the partitioning of them is scenario
+ * dependent. This header defines the partitioning between legacy,
+ * PCI, and DPAA2 devices.
  *
  * This partitioning can be customized in this file depending
  * on the specific hardware config:
@@ -29,6 +29,9 @@
  *         -set a msi-map entry in the PEXn controller node in the
  *          device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
  *          for more info on the msi-map definition)
+ *         -set a iommu-map entry in the PEXn controller node in the
+ *          device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
+ *          for more info on the iommu-map definition)
  *
  *  -DPAA2
  *     -u-boot will allocate a range of stream IDs to be used by the Management
@@ -36,7 +39,7 @@
  *     -the MC is responsible for allocating and setting up 'isolation context
  *      IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
  *
- * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for
+ * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for
  * each of the different bus masters.  The relationship between
  * the AMQ registers and stream IDs is defined in the table below:
  *          AMQ bit    streamID bit
-- 
1.9.3

[U-Boot] [PATCH v2 3/6] pcie-layerscape: Define stream-ids for Layerscape Chassis-2

[Bharat Bhushan]

Layerscape Chassis-2 have PCIe device, some platform devices and
DPAA1 devices which will use stream-ids for iommu level isolation as
they lies behind SMMU.

This patch defines the stream-ids for Chassis-2 devices.
stream-ids for DPAA1 are reserved for future use.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
---
 .../asm/arch-fsl-layerscape/stream_id_lsch2.h      | 63 ++++++++++++++++++++++
 include/configs/ls1043a_common.h                   |  1 +
 2 files changed, 64 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
new file mode 100644
index 0000000..b326fe5
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 NXP Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+#ifndef __FSL_STREAM_ID_H
+#define __FSL_STREAM_ID_H
+
+/*
+ * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices
+ * are not hardwired and are programmed by sw.  There are a limited number
+ * of stream IDs available, and the partitioning of them is scenario
+ * dependent. This header defines the partitioning between legacy, PCI,
+ * and DPAA1 devices.
+ *
+ * This partitioning can be customized in this file depending
+ * on the specific hardware config:
+ *
+ *  -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc)
+ *     -all legacy devices get a unique stream ID assigned and programmed in
+ *      their AMQR registers by u-boot
+ *
+ *  -PCIe
+ *     -there is a range of stream IDs set aside for PCI in this
+ *      file.  U-boot will scan the PCI bus and for each device discovered:
+ *         -allocate a streamID
+ *         -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
+ *         -set a msi-map entry in the PEXn controller node in the
+ *          device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
+ *          for more info on the msi-map definition)
+ *         -set a iommu-map entry in the PEXn controller node in the
+ *          device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
+ *          for more info on the iommu-map definition)
+ *
+ *  -DPAA1
+ *     - Stream ids for DPAA1 use are reserved for future usecase.
+ *
+ */
+
+
+#define FSL_INVALID_STREAM_ID		0
+
+/* legacy devices */
+#define FSL_USB1_STREAM_ID		1
+#define FSL_USB2_STREAM_ID		2
+#define FSL_USB3_STREAM_ID		3
+#define FSL_SDHC_STREAM_ID		4
+#define FSL_SATA_STREAM_ID		5
+#define FSL_QE_STREAM_ID		6
+#define FSL_QDMA_STREAM_ID		7
+#define FSL_EDMA_STREAM_ID		8
+#define FSL_ETR_STREAM_ID		9
+
+/* PCI - programmed in PEXn_LUT */
+#define FSL_PEX_STREAM_ID_START		11
+#define FSL_PEX_STREAM_ID_END		26
+
+/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */
+#define FSL_DPAA1_STREAM_ID_START	27
+#define FSL_DPAA1_STREAM_ID_END		63
+
+#endif
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 5a5f951..c9d4fd7 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -13,6 +13,7 @@
 #define CONFIG_MP
 #define CONFIG_GICV2
 
+#include <asm/arch/stream_id_lsch2.h>
 #include <asm/arch/config.h>
 
 /* Link Definitions */
-- 
1.9.3

[U-Boot] [PATCH v2 4/6] fsl-lsch2: Use Chassis-2 streamid definition for ls1046a

[Bharat Bhushan]

As ls1046a is Chassis-2 type SOC and shares same streamid
definition, this patch adds using streamids for ls1046

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
---
 include/configs/ls1046a_common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 1ed7517..cb79296 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -13,6 +13,7 @@
 #define CONFIG_GICV2
 
 #include <asm/arch/config.h>
+#include <asm/arch/stream_id_lsch2.h>
 
 /* Link Definitions */
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
-- 
1.9.3

[U-Boot] [PATCH v2 5/6] fsl-lsch2: Use Chassis-2 streamid definition for ls1012a

[Bharat Bhushan]

As ls1012a is Chassis-2 type SOC and shares same streamid
definition, this patch adds using streamids for ls1012a

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
---
 include/configs/ls1012a_common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index af07672..1a0c7f8 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -11,6 +11,7 @@
 #define CONFIG_GICV2
 
 #include <asm/arch/config.h>
+#include <asm/arch/stream_id_lsch2.h>
 
 #define CONFIG_SUPPORT_RAW_INITRD
 
-- 
1.9.3

[U-Boot] [PATCH v2 6/6] pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs

[Bharat Bhushan]

From: Bharat Bhushan <bharat.bhushan@nxp.com>

Layerscape Chasis-2 also uses same PCIe controller
as used in Chasis-3 and have similar PCI-Lut.

We need to initialize the pcie-lut for Chasis-2 also
as in Chasis-3.

Signed-off-by: Bharat Bhushan <bharat.bhushan@nxp.com>
---
 drivers/pci/pcie_layerscape_fixup.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 19ede2f..8f8f6b6 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -15,7 +15,7 @@
 #include <fdt_support.h>
 #include "pcie_layerscape.h"
 
-#ifdef CONFIG_FSL_LSCH3
+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
 /*
  * Return next available LUT index.
  */
@@ -175,7 +175,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
 	list_for_each_entry(pcie, &ls_pcie_list, list)
 		ft_pcie_ls_setup(blob, pcie);
 
-#ifdef CONFIG_FSL_LSCH3
+#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
 	fdt_fixup_pcie(blob);
 #endif
 }
-- 
1.9.3

[U-Boot] [PATCH v2 1/6] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h

[york sun]

On 03/21/2017 11:38 PM, Bharat Bhushan wrote:
> The stream ID allocation for Chasis3.0 devices,
> LS1088, LS2088 and LS2080, can be shared.
>
> This patch renames this accordingly.
>
> Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
> ---

You missed the change log. What change did you make for this version?
I didn't see your respond to Diana's comment for patch 3 of version 1.

York

[U-Boot] [PATCH v2 1/6] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h

[Bharat Bhushan]

> -----Original Message-----
> From: york sun
> Sent: Wednesday, March 22, 2017 9:50 PM
> To: Bharat Bhushan <bharat.bhushan@nxp.com>; u-boot at lists.denx.de
> Cc: M.H. Lian <minghuan.lian@nxp.com>; sjg at chromium.org; Z.Q. Hou
> <zhiqiang.hou@nxp.com>; Diana Madalina Craciun
> <diana.craciun@nxp.com>
> Subject: Re: [PATCH v2 1/6] fsl-lsch3: rename ls2080a_stream_id.h to
> stream_id_lsch3.h
> 
> On 03/21/2017 11:38 PM, Bharat Bhushan wrote:
> > The stream ID allocation for Chasis3.0 devices, LS1088, LS2088 and
> > LS2080, can be shared.
> >
> > This patch renames this accordingly.
> >
> > Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
> > ---
> 
> You missed the change log. What change did you make for this version?
> I didn't see your respond to Diana's comment for patch 3 of version 1.

Patch 0/6 (cover letter) describes that only change in this series are in 3/6 and 4/6 and that describe the change as well (which is what Diana's comment)


Thanks
-Bharat

> 
> York

[U-Boot] [PATCH v2 1/6] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h

[york sun]

On 03/22/2017 10:08 AM, Bharat Bhushan wrote:
>
>
>> -----Original Message-----
>> From: york sun
>> Sent: Wednesday, March 22, 2017 9:50 PM
>> To: Bharat Bhushan <bharat.bhushan@nxp.com>; u-boot at lists.denx.de
>> Cc: M.H. Lian <minghuan.lian@nxp.com>; sjg at chromium.org; Z.Q. Hou
>> <zhiqiang.hou@nxp.com>; Diana Madalina Craciun
>> <diana.craciun@nxp.com>
>> Subject: Re: [PATCH v2 1/6] fsl-lsch3: rename ls2080a_stream_id.h to
>> stream_id_lsch3.h
>>
>> On 03/21/2017 11:38 PM, Bharat Bhushan wrote:
>>> The stream ID allocation for Chasis3.0 devices, LS1088, LS2088 and
>>> LS2080, can be shared.
>>>
>>> This patch renames this accordingly.
>>>
>>> Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
>>> ---
>>
>> You missed the change log. What change did you make for this version?
>> I didn't see your respond to Diana's comment for patch 3 of version 1.
>
> Patch 0/6 (cover letter) describes that only change in this series are in 3/6 and 4/6 and that describe the change as well (which is what Diana's comment)
>

I see. Thanks.

York

[U-Boot] [PATCH v2 1/6] fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h

[york sun]

On 03/21/2017 11:38 PM, Bharat Bhushan wrote:
> The stream ID allocation for Chasis3.0 devices,
> LS1088, LS2088 and LS2080, can be shared.
>
> This patch renames this accordingly.
>
> Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
> ---

Rewrote commit message. Applied to fsl-qoriq master, awaiting upstream. 
Thanks.

York

[U-Boot] [PATCH v2 2/6] fsl-lsch3: Rewording to support other Chassis-3 Socs

[york sun]

On 03/21/2017 11:38 PM, Bharat Bhushan wrote:
> LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3
> and shared same stream-id partitioning. This patch
> rewords the definition to support all these SOCs.
>
> Also have changes in description about iommu-map property
> updates in PCI node.
>
> Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
> ---
>  .../arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | 15 +++++++++------
>  1 file changed, 9 insertions(+), 6 deletions(-)

Reformat commit message. Applied to fsl-qoriq master, awaiting upstream. 
Thanks.

York

[U-Boot] [PATCH v2 3/6] pcie-layerscape: Define stream-ids for Layerscape Chassis-2

[york sun]

On 03/21/2017 11:39 PM, Bharat Bhushan wrote:
> Layerscape Chassis-2 have PCIe device, some platform devices and
> DPAA1 devices which will use stream-ids for iommu level isolation as
> they lies behind SMMU.
>
> This patch defines the stream-ids for Chassis-2 devices.
> stream-ids for DPAA1 are reserved for future use.
>
> Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
> ---

Reformat commit message. Applied to fsl-qoriq master, awaiting upstream. 
Thanks.

York

[U-Boot] [PATCH v2 4/6] fsl-lsch2: Use Chassis-2 streamid definition for ls1046a

[york sun]

On 03/21/2017 11:39 PM, Bharat Bhushan wrote:
> As ls1046a is Chassis-2 type SOC and shares same streamid
> definition, this patch adds using streamids for ls1046
>
> Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
> ---

Minor adjustment to commit message. Applied to fsl-qoriq master, 
awaiting upstream. Thanks.

York

[U-Boot] [PATCH v2 5/6] fsl-lsch2: Use Chassis-2 streamid definition for ls1012a

[york sun]

On 03/21/2017 11:39 PM, Bharat Bhushan wrote:
> As ls1012a is Chassis-2 type SOC and shares same streamid
> definition, this patch adds using streamids for ls1012a
>
> Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
> ---

Applied to fsl-qoriq master, awaiting upstream. Thanks.

York

[U-Boot] [PATCH v2 6/6] pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs

[york sun]

On 03/21/2017 11:38 PM, Bharat Bhushan wrote:
> From: Bharat Bhushan <bharat.bhushan@nxp.com>
>
> Layerscape Chasis-2 also uses same PCIe controller
> as used in Chasis-3 and have similar PCI-Lut.
>
> We need to initialize the pcie-lut for Chasis-2 also
> as in Chasis-3.
>
> Signed-off-by: Bharat Bhushan <bharat.bhushan@nxp.com>
> ---

Minor adjustment in commit message. Applied to fsl-qoriq master, 
awaiting upstream. Thanks.

York