* [U-Boot] [PATCH] pci: layerscape: enable PCIe config ready
@ 2017-02-10 7:42 Zhiqiang Hou
2017-03-28 17:58 ` york sun
0 siblings, 1 reply; 2+ messages in thread
From: Zhiqiang Hou @ 2017-02-10 7:42 UTC (permalink / raw)
To: u-boot
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
In EP mode, to enable accesses from the Root Complex, the
CONFIG_READY bit must be set, otherwise any config attempts
from the Root Complex will be returned with config retry
status (CRS).
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
drivers/pci/pcie_layerscape.c | 7 +++++++
drivers/pci/pcie_layerscape.h | 2 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 90b9fe2..e597a75 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -409,6 +409,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base)
ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
}
+static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
+{
+ ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
+}
+
static void ls_pcie_setup_ep(struct ls_pcie *pcie)
{
u32 sriov;
@@ -432,6 +437,8 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie)
ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
ls_pcie_ep_setup_atu(pcie);
}
+
+ ls_pcie_ep_enable_cfg(pcie);
}
static int ls_pcie_probe(struct udevice *dev)
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 1e635ef..0f9d2fe6 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -94,8 +94,10 @@
#define PCIE_LUT_ENTRY_COUNT 32
/* PF Controll registers */
+#define PCIE_PF_CONFIG 0x14
#define PCIE_PF_VF_CTRL 0x7F8
#define PCIE_PF_DBG 0x7FC
+#define PCIE_CONFIG_READY (1 << 0)
#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx))
#define PCIE_SYS_BASE_ADDR 0x3400000
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH] pci: layerscape: enable PCIe config ready
2017-02-10 7:42 [U-Boot] [PATCH] pci: layerscape: enable PCIe config ready Zhiqiang Hou
@ 2017-03-28 17:58 ` york sun
0 siblings, 0 replies; 2+ messages in thread
From: york sun @ 2017-03-28 17:58 UTC (permalink / raw)
To: u-boot
On 02/09/2017 11:55 PM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> In EP mode, to enable accesses from the Root Complex, the
> CONFIG_READY bit must be set, otherwise any config attempts
> from the Root Complex will be returned with config retry
> status (CRS).
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
Applied to fsl-qoriq master, awaiting upstream. Thanks.
York
^ permalink raw reply [flat|nested] 2+ messages in thread
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2017-02-10 7:42 [U-Boot] [PATCH] pci: layerscape: enable PCIe config ready Zhiqiang Hou
2017-03-28 17:58 ` york sun
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