[U-Boot] [PATCH 1/2][v2] armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support

[U-Boot] [PATCH 1/2][v2] armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support

[Priyanka Jain]

The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A-72 CPUs and
is built on layerscape architecture.

It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A).
So feature-wise it is same as LS2084A.

LS2081A has one more similar personality which
has four CPUs: LS2041A

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
---
 Changes for v2: Uddated copyright
 
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c          |    4 +++-
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc |   11 +++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h   |    3 +++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h   |    3 +++
 drivers/pci/pcie_layerscape.c                    |    7 +++++--
 drivers/pci/pcie_layerscape.h                    |    3 +++
 drivers/pci/pcie_layerscape_fixup.c              |    7 +++++--
 7 files changed, 33 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index c24f3f1..970e759 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -102,7 +103,8 @@ static void fix_pcie_mmu_map(void)
 
 	/* Fix PCIE base and size for LS2088A */
 	if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
-	    (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) {
+	    (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
+	    (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 		for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 			switch (final_map[i].phys) {
 			case CONFIG_SYS_PCIE1_PHYS_ADDR:
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index c7496c0..3ae16ae 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -5,6 +5,7 @@ SoC overview
 	3. LS1012A
 	4. LS1046A
 	5. LS2088A
+	6. LS2081A
 
 LS1043A
 ---------
@@ -227,3 +228,13 @@ LS2088A SoC has 3 more similar SoC personalities
 
 3)LS2044A, few difference w.r.t. LS2084A:
        a) Four 64-bit ARM v8 Cortex-A72 CPUs
+
+LS2081A
+--------
+LS2081A is 40-pin derivative of LS2084A.
+So feature-wise it is same as LS2084A.
+Refer to LS2084A(LS2088A) section above for details.
+
+It has one more similar SoC personality
+1)LS2041A, few difference w.r.t. LS2081A:
+       a) Four 64-bit ARM v8 Cortex-A72 CPUs
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 95c3e2f..d0e42c5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015, Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -15,6 +16,8 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
 	CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
 	CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
+	CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
+	CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
 	CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
 	CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
 	CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 426fe8e..6ac534e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -54,6 +55,8 @@ struct cpu_type {
 #define SVR_LS2084A		0x870910
 #define SVR_LS2048A		0x870920
 #define SVR_LS2044A		0x870930
+#define SVR_LS2081A		0x870919
+#define SVR_LS2041A		0x870915
 
 #define SVR_DEV_LS2080A		0x8701
 
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 1c5a33a..5b5651a 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  *
@@ -170,7 +171,8 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie)
 	/* Fix the pcie memory map for LS2088A series SoCs */
 	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-	    svr == SVR_LS2048A || svr == SVR_LS2044A) {
+	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
 		if (io)
 			io->phys_start = (io->phys_start &
 					 (PCIE_PHYS_SIZE - 1)) +
@@ -531,7 +533,8 @@ static int ls_pcie_probe(struct udevice *dev)
 	svr = get_svr();
 	svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-	    svr == SVR_LS2048A || svr == SVR_LS2044A) {
+	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
 		pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
 					LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 		pcie->ctrl = pcie->lut + 0x40000;
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index e3324a5..07a7014 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  *
@@ -117,6 +118,8 @@
 #define SVR_LS2084A		0x870910
 #define SVR_LS2048A		0x870920
 #define SVR_LS2044A		0x870930
+#define SVR_LS2081A		0x870919
+#define SVR_LS2041A		0x870915
 
 /* LS1021a PCIE space */
 #define LS1021_PCIE_SPACE_OFFSET	0x4000000000ULL
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index d504bbd..f08c152 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  *
@@ -82,7 +83,8 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-		    svr == SVR_LS2048A || svr == SVR_LS2044A)
+		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+		    svr == SVR_LS2081A || svr == SVR_LS2041A)
 			compat = "fsl,ls2088a-pcie";
 		else
 			compat = CONFIG_FSL_PCIE_COMPAT;
@@ -217,7 +219,8 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 		svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 		if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
-		    svr == SVR_LS2048A || svr == SVR_LS2044A)
+		    svr == SVR_LS2048A || svr == SVR_LS2044A ||
+		    svr == SVR_LS2081A || svr == SVR_LS2041A)
 			compat = "fsl,ls2088a-pcie";
 		else
 			compat = CONFIG_FSL_PCIE_COMPAT;
-- 
1.7.4.1

[U-Boot] [PATCH 2/2][v2] board: ls2080ardb: Add LS2081ARDB board support

[Priyanka Jain]

LS2081ARDB board is similar to LS2080ARDB board
with few differences like
 It hosts LS2081A SoC
 Default boot source is QSPI-boot
 It does not have IFC interface
 RTC and QSPI flash device are different
 It provides QIXIS access via I2C

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
---
Depends on 
  https://patchwork.ozlabs.org/patch/755824/
  https://patchwork.ozlabs.org/patch/755823/
  https://patchwork.ozlabs.org/patch/754576/
 
Changes for v2: Rebased on top of Depends on patches

 arch/arm/Kconfig                        |   14 +++++++
 arch/arm/cpu/armv8/Kconfig              |    1 +
 arch/arm/dts/Makefile                   |    1 +
 arch/arm/dts/fsl-ls2081a-rdb.dts        |   59 +++++++++++++++++++++++++++++++
 board/freescale/ls2080ardb/Kconfig      |   18 +++++++++
 board/freescale/ls2080ardb/MAINTAINERS  |    5 +++
 board/freescale/ls2080ardb/README       |   20 +++++++++--
 board/freescale/ls2080ardb/ls2080ardb.c |   52 +++++++++++++++++++++++++++
 configs/ls2081ardb_defconfig            |   46 ++++++++++++++++++++++++
 drivers/usb/host/xhci-fsl.c             |    3 +-
 include/configs/ls2080ardb.h            |   31 ++++++++++++++++
 11 files changed, 246 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/dts/fsl-ls2081a-rdb.dts
 create mode 100644 configs/ls2081ardb_defconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 42f93b4..f5462ab 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -950,6 +950,20 @@ config TARGET_LS2080ARDB
 	  development platform that supports the QorIQ LS2080A
 	  Layerscape Architecture processor.
 
+config TARGET_LS2081ARDB
+	bool "Support ls2081ardb"
+	select ARCH_LS2080A
+	select ARM64
+	select ARMV8_MULTIENTRY
+	select BOARD_LATE_INIT
+	select SUPPORT_SPL
+	select ARCH_MISC_INIT
+	help
+	  Support for Freescale LS2081ARDB platform.
+	  The LS2081A Reference design board (RDB) is a high-performance
+	  development platform that supports the QorIQ LS2081A/LS2041A
+	  Layerscape Architecture processor.
+
 config TARGET_HIKEY
 	bool "Support HiKey 96boards Consumer Edition Platform"
 	select ARM64
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 0188b95..d5b692e 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -91,6 +91,7 @@ config PSCI_RESET
 		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
 		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
+		   !TARGET_LS2081ARDB && \
 		   !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB
 	help
 	  Most armv8 systems have PSCI support enabled in EL3, either through
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 143e33f..92dfb05 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -172,6 +172,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
 	ls1021a-iot-duart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls2080a-rdb.dtb \
+	fsl-ls2081a-rdb.dtb \
 	fsl-ls2088a-rdb-qspi.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
diff --git a/arch/arm/dts/fsl-ls2081a-rdb.dts b/arch/arm/dts/fsl-ls2081a-rdb.dts
new file mode 100644
index 0000000..9ed1157
--- /dev/null
+++ b/arch/arm/dts/fsl-ls2081a-rdb.dts
@@ -0,0 +1,59 @@
+/*
+ * NXP LS2081A RDB board device tree source for QSPI-boot
+ *
+ * Author: Priyanka Jain <priyanka.jain@nxp.com>
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2080a.dtsi"
+
+/ {
+	model = "Freescale Layerscape 2081a RDB Board";
+	compatible = "fsl,ls2081a-rdb", "fsl,ls2080a";
+
+	aliases {
+		spi0 = &qspi;
+		spi1 = &dspi;
+	};
+};
+
+&dspi {
+	bus-num = <0>;
+	status = "okay";
+
+	dflash0: n25q512a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <3000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: n25q512a at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <0>;
+	};
+
+	qflash1: n25q512a at 1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <50000000>;
+		reg = <1>;
+	};
+};
diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig
index 2f0465f..8f64642 100644
--- a/board/freescale/ls2080ardb/Kconfig
+++ b/board/freescale/ls2080ardb/Kconfig
@@ -16,3 +16,21 @@ config SYS_CONFIG_NAME
 source "board/freescale/common/Kconfig"
 
 endif
+
+if TARGET_LS2081ARDB
+
+config SYS_BOARD
+	default "ls2080ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls2080ardb"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index 3175ba3..91f13ea 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -12,6 +12,11 @@ M:	Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	configs/ls2088ardb_qspi_defconfig
 
+LS2081ARDB BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	configs/ls2081ardb_defconfig
+
 LS2080A_SECURE_BOOT BOARD
 M:	Saksham Jain <saksham.jain@nxp.freescale.com>
 S:	Maintained
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 5bf2635..c4da896 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -4,10 +4,14 @@ The LS2080A Reference Design (RDB) is a high-performance computing,
 evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
 Layerscape Architecture processor.
 
-LS2080A, LS2088A SoC Overview
---------------------
+The LS2081A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2081A
+Layerscape Architecture processor.More details in below sections
+
+LS2080A, LS2088A, LS2081A SoC Overview
+--------------------------------------
 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
-LS2088A SoC overview.
+LS2081A, LS2088A SoC overview.
 
  LS2080ARDB board Overview
  -----------------------
@@ -38,6 +42,16 @@ LS2088A SoC overview.
  - UART
  - ARM JTAG support
 
+ LS2081ARDB board Overview
+ -------------------------
+ LS2081ARDB board is similar to LS2080ARDB board
+ with few differences like
+  - Hosts LS2081A SoC
+  - Default boot source is QSPI-boot
+  - Does not have IFC interface
+  - RTC and QSPI flash devices are different
+  - Provides QIXIS access via I2C
+
 Memory map from core's view
 ----------------------------
 0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 10e8ea4..df2d768 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -68,6 +68,44 @@ int checkboard(void)
 	cpu_name(buf);
 	printf("Board: %s-RDB, ", buf);
 
+#ifdef CONFIG_TARGET_LS2081ARDB
+#ifdef CONFIG_FSL_QIXIS
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, ", (sw & 0xf) + 'A');
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
+	switch (sw) {
+	case 0:
+		puts("boot from QSPI DEV#0\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
+		break;
+	case 1:
+		puts("boot from QSPI DEV#1\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
+		break;
+	case 2:
+		puts("boot from QSPI EMU\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
+		break;
+	case 3:
+		puts("boot from QSPI EMU\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
+		break;
+	case 4:
+		puts("boot from QSPI DEV#0\n");
+		puts("QSPI_CSA_1 mapped to QSPI EMU\n");
+		break;
+	default:
+		printf("invalid setting of SW%u\n", sw);
+		break;
+	}
+#endif
+	puts("SERDES1 Reference : ");
+	printf("Clock1 = 100MHz ");
+	printf("Clock2 = 161.13MHz");
+#else
 #ifdef CONFIG_FSL_QIXIS
 	sw = QIXIS_READ(arch);
 	printf("Board Arch: V%d, ", sw >> 4);
@@ -88,6 +126,7 @@ int checkboard(void)
 	puts("SERDES1 Reference : ");
 	printf("Clock1 = 156.25MHz ");
 	printf("Clock2 = 156.25MHz");
+#endif
 
 	puts("\nSERDES2 Reference : ");
 	printf("Clock1 = 100MHz ");
@@ -209,6 +248,9 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
 	fsl_lsch3_early_init_f();
 	return 0;
 }
@@ -216,6 +258,11 @@ int board_early_init_f(void)
 int misc_init_r(void)
 {
 #ifdef CONFIG_FSL_QIXIS
+	/*
+	 * LS2081ARDB has smart voltage translator which needs
+	 * to be programmed as below
+	 */
+#ifndef CONFIG_TARGET_LS2081ARDB
 	u8 sw;
 
 	sw = QIXIS_READ(arch);
@@ -225,12 +272,15 @@ int misc_init_r(void)
 	 * by setting GPIO4_10 output to zero
 	 */
 	if ((sw & 0xf) == 0x5) {
+#endif
 		out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
 					    in_le32(GPIO4_GPDIR_ADDR)));
 		out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
 					    in_le32(GPIO4_GPDAT_ADDR)));
+#ifndef CONFIG_TARGET_LS2081ARDB
 	}
 #endif
+#endif
 
 	if (hwconfig("sdhc"))
 		config_board_mux(MUX_TYPE_SDHC);
@@ -350,6 +400,7 @@ void update_spd_address(unsigned int ctrl_num,
 			unsigned int slot,
 			unsigned int *addr)
 {
+#ifndef CONFIG_TARGET_LS2081ARDB
 #ifdef CONFIG_FSL_QIXIS
 	u8 sw;
 
@@ -361,4 +412,5 @@ void update_spd_address(unsigned int ctrl_num,
 			*addr = SPD_EEPROM_ADDRESS3;
 	}
 #endif
+#endif
 }
diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
new file mode 100644
index 0000000..0d1730f
--- /dev/null
+++ b/configs/ls2081ardb_defconfig
@@ -0,0 +1,46 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2081ARDB=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2081a-rdb"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 798c358..3a16624 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -40,7 +40,8 @@ __weak int __board_usb_init(int index, enum usb_init_type init)
 
 static int erratum_a008751(void)
 {
-#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB)
+#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB) ||\
+					defined(CONFIG_TARGET_LS2080AQDS)
 	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
 	writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
 	return 0;
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index dd72aa0..2040c50 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -14,6 +14,9 @@
 #define CONFIG_CONS_INDEX       2
 
 #ifdef CONFIG_FSL_QSPI
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_QIXIS_I2C_ACCESS
+#endif
 #define CONFIG_SYS_I2C_EARLY_INIT
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 #endif
@@ -259,9 +262,28 @@ unsigned long get_board_sys_clk(void);
 #endif
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_QMAP_MASK			0x07
+#define QIXIS_QMAP_SHIFT		5
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_QSPI		0x62
+#define QIXIS_LBMAP_ALTBANK		0x20
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_RST_CTL_RESET_EN		0x30
+#endif
+
 /*
  * I2C
  */
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#endif
 #define I2C_MUX_PCA_ADDR		0x75
 #define I2C_MUX_PCA_ADDR_PRI		0x75 /* Primary Mux*/
 
@@ -276,7 +298,11 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SPI_FLASH_STMICRO
 #endif
 #ifdef CONFIG_FSL_QSPI
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_SPI_FLASH_STMICRO
+#else
 #define CONFIG_SPI_FLASH_SPANSION
+#endif
 #define FSL_QSPI_FLASH_SIZE		(1 << 26) /* 64MB */
 #define FSL_QSPI_FLASH_NUM		2
 #endif
@@ -286,8 +312,13 @@ unsigned long get_board_sys_clk(void);
  * RTC configuration
  */
 #define RTC
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_RTC_PCF8563		1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x51
+#else
 #define CONFIG_RTC_DS3231               1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#endif
 #define CONFIG_CMD_DATE
 
 /* EEPROM */
-- 
1.7.4.1

[U-Boot] [PATCH 1/2][v2] armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support

[york sun]

On 04/27/2017 02:38 AM, Priyanka Jain wrote:
> The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A-72 CPUs and
> is built on layerscape architecture.
>
> It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A).
> So feature-wise it is same as LS2084A.

Please clarify what is 40-pin derivative?

York

[U-Boot] [PATCH 1/2][v2] armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support

[york sun]

On 04/27/2017 02:38 AM, Priyanka Jain wrote:
> The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A-72 CPUs and
> is built on layerscape architecture.
>
> It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A).
> So feature-wise it is same as LS2084A.
>
> LS2081A has one more similar personality which
> has four CPUs: LS2041A
>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
> ---
>  Changes for v2: Uddated copyright

Reformatted commit message. Applied to fsl-qoriq master, awaiting 
upstream. Thanks.

York

[U-Boot] [PATCH 2/2][v2] board: ls2080ardb: Add LS2081ARDB board support

[york sun]

On 04/27/2017 02:38 AM, Priyanka Jain wrote:
> LS2081ARDB board is similar to LS2080ARDB board
> with few differences like
>  It hosts LS2081A SoC
>  Default boot source is QSPI-boot
>  It does not have IFC interface
>  RTC and QSPI flash device are different
>  It provides QIXIS access via I2C
>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
> ---
> Depends on
>   https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F755824%2F&data=01%7C01%7Cyork.sun%40nxp.com%7C42e54d83e9c34ac471d708d48d51265b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdata=VNu6NPCk%2BaR5gllkg1ejWKQl7x986%2Fi%2Bo8wFtg2YzI8%3D&reserved=0
>   https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F755823%2F&data=01%7C01%7Cyork.sun%40nxp.com%7C42e54d83e9c34ac471d708d48d51265b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdata=hnAbsz0jkoihjCPTJh1CwcOdDOVSgt88HVItq%2B7zEbw%3D&reserved=0
>   https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F754576%2F&data=01%7C01%7Cyork.sun%40nxp.com%7C42e54d83e9c34ac471d708d48d51265b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdata=r3K9i5caRimJyIvX3kpV2miCiFVSFLDiPdhhaPwERPQ%3D&reserved=0
>
> Changes for v2: Rebased on top of Depends on patches

Minor adjustment to commit message. Applied to fsl-qoriq master, 
awaiting upstream. Thanks.

York