From: Horia Geanta <horia.geanta@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/2] armv8: ls1088a: add icid setup for platform devices
Date: Thu, 21 Mar 2019 15:10:14 +0000 [thread overview]
Message-ID: <VI1PR0402MB34854BA3802B2D676D1FB1FA98420@VI1PR0402MB3485.eurprd04.prod.outlook.com> (raw)
In-Reply-To: ac7b1570-a56b-71e4-c1fe-67917ad90ff0@nxp.com
On 3/21/2019 2:42 PM, Tudor Laurentiu-B10716 wrote:
> Hi Horia,
>
> On 21.03.2019 12:36, Horia Geanta wrote:
>> On 3/20/2019 4:31 PM, laurentiu.tudor at nxp.com wrote:
>>> #define SET_SEC_QI_ICID(streamid) \
>>> - SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
>>> + SET_ICID_ENTRY("fsl,sec-v4.0", SEC_ICID_REG_VAL(streamid), \
>> Is this a fix for LS104x? Then it should be a separate patch.
>
> Not really. I added an intermediate macro, SEC_ICID_REG_VAL(streamid)
> that forms the correct register value starting from ICID, depending on
> the chip version (the register layouts are different between the two).
>
This is the define
#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
Thus the QI ICID for LS104x changes.
>>> +#else /* CONFIG_FSL_LSCH2 */
>> [...]
>>> +#define SEC_ICID_REG_VAL(streamid) ((streamid) << 24)
>> ICID is in lower 6:0 bits, not in 31:24.
>
> That was also my initial impression but it didn't work (smmu global
> faults with icid 0). Probably there's an ambiguity related to endianness
> in the documentation.
>
Note that on DPAA 2.x both the core and device (CAAM) are little endian.
Probably the problem is with the I/O accessors writing the CAAM registers.
Instead of out_be32() use either sec_out32() (but this means splitting
CAAM-specific code) or out_le32().
CAAM endianness can be detected using CONFIG_SYS_FSL_SEC_LE / CONFIG_SYS_FSL_SEC_BE.
Horia
next prev parent reply other threads:[~2019-03-21 15:10 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-20 14:31 [U-Boot] [PATCH 1/2] armv8: fsl-layerscape: add missing sec jr base address defines laurentiu.tudor at nxp.com
2019-03-20 14:31 ` [U-Boot] [PATCH 2/2] armv8: ls1088a: add icid setup for platform devices laurentiu.tudor at nxp.com
2019-03-21 10:36 ` Horia Geanta
2019-03-21 12:42 ` Laurentiu Tudor
2019-03-21 15:10 ` Horia Geanta [this message]
2019-03-21 15:37 ` Laurentiu Tudor
2019-03-21 12:47 ` Laurentiu Tudor
2019-03-21 13:03 ` Laurentiu Tudor
2019-03-20 14:31 ` [U-Boot] [PATCH v2 1/3] fsl_sec: fix register layout on Layerscape architectures laurentiu.tudor at nxp.com
2019-03-20 15:04 ` Laurentiu Tudor
2019-03-20 14:31 ` [U-Boot] [PATCH v2 2/3] armv8: fsl-layerscape: fix SEC QI ICID setup laurentiu.tudor at nxp.com
2019-03-20 14:31 ` [U-Boot] [PATCH v2 3/3] armv8: fsl-layerscape: avoid DT fixup warning laurentiu.tudor at nxp.com
2019-03-21 10:39 ` [U-Boot] [PATCH 1/2] armv8: fsl-layerscape: add missing sec jr base address defines Horia Geanta
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