* [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines
@ 2019-10-18 9:01 Laurentiu Tudor
2019-10-18 9:01 ` [U-Boot] [PATCH v2 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled Laurentiu Tudor
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Laurentiu Tudor @ 2019-10-18 9:01 UTC (permalink / raw)
To: u-boot
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
These macros should only be used when CONFIG_FSL_CAAM is present.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geant?? <horia.geanta@nxp.com>
---
Changes in v2:
- added Reviewed-by tag
arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 ++
arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
index d9d125e8ba..9462298fbf 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
@@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = {
SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
@@ -28,6 +29,7 @@ struct icid_id_table icid_tbl[] = {
SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
index 49e27553b1..23743ae10c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
@@ -13,6 +13,7 @@ struct icid_id_table icid_tbl[] = {
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
@@ -25,6 +26,7 @@ struct icid_id_table icid_tbl[] = {
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v2 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled
2019-10-18 9:01 [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor
@ 2019-10-18 9:01 ` Laurentiu Tudor
2019-10-18 14:01 ` Horia Geanta
2019-10-18 9:01 ` [U-Boot] [PATCH v2 3/6] armv8: ls2088a: add icid setup for platform devices Laurentiu Tudor
` (5 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Laurentiu Tudor @ 2019-10-18 9:01 UTC (permalink / raw)
To: u-boot
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this
compilation error happens:
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error:
'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function)
Fix it by wrapping with CONFIG_IS_ENABLED().
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
Changes in v2:
- use CONFIG_IS_ENABLED() (Horia)
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 37e2fe4e66..3c06a55cb8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -166,7 +166,7 @@ extern int fman_icid_tbl_sz;
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
SET_ICID_ENTRY( \
- (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \
+ (CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
(FSL_SEC_JR##jr_num##_OFFSET == \
SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
? NULL \
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v2 3/6] armv8: ls2088a: add icid setup for platform devices
2019-10-18 9:01 [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor
2019-10-18 9:01 ` [U-Boot] [PATCH v2 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled Laurentiu Tudor
@ 2019-10-18 9:01 ` Laurentiu Tudor
2019-10-18 14:01 ` Horia Geanta
2019-10-18 9:01 ` [U-Boot] [PATCH v2 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses Laurentiu Tudor
` (4 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Laurentiu Tudor @ 2019-10-18 9:01 UTC (permalink / raw)
To: u-boot
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
Changes in v2:
- setup ICIDs for all 6 DECOs not only 4 (Horia)
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 +
.../arm/cpu/armv8/fsl-layerscape/ls2088_ids.c | 35 +++++++++++++++++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +-
board/freescale/ls2080aqds/ls2080aqds.c | 3 ++
board/freescale/ls2080ardb/ls2080ardb.c | 3 ++
5 files changed, 44 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index efecbc07e7..f00ef817b1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,6 +28,7 @@ endif
ifneq ($(CONFIG_ARCH_LS2080A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
+obj-y += icid.o ls2088_ids.o
endif
ifneq ($(CONFIG_ARCH_LS1043A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c
new file mode 100644
index 0000000000..e6403b7952
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/arch-fsl-layerscape/fsl_portals.h>
+
+struct icid_id_table icid_tbl[] = {
+ SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_SATA_ICID(1, "fsl,ls2080a-ahci", FSL_SATA1_STREAM_ID),
+ SET_SATA_ICID(2, "fsl,ls2080a-ahci", FSL_SATA2_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID),
+#endif
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 3fd34e3a43..924f5f3fe8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -341,7 +341,8 @@ void fsl_lsch3_early_init_f(void)
bypass_smmu();
#endif
-#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
+#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
+ defined(CONFIG_ARCH_LS2080A)
set_icids();
#endif
}
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 91c80353ed..25e80c8ac6 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -20,6 +20,7 @@
#include <hwconfig.h>
#include <fsl_sec.h>
#include <asm/arch/ppa.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/qixis.h"
@@ -358,6 +359,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
+ fdt_fixup_icid(blob);
+
return 0;
}
#endif
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index e20267f27c..6a1b8e3f53 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -22,6 +22,7 @@
#include <asm/arch/soc.h>
#include <asm/arch/ppa.h>
#include <fsl_sec.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#ifdef CONFIG_FSL_QIXIS
#include "../common/qixis.h"
@@ -478,6 +479,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
+ fdt_fixup_icid(blob);
+
return 0;
}
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v2 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses
2019-10-18 9:01 [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor
2019-10-18 9:01 ` [U-Boot] [PATCH v2 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled Laurentiu Tudor
2019-10-18 9:01 ` [U-Boot] [PATCH v2 3/6] armv8: ls2088a: add icid setup for platform devices Laurentiu Tudor
@ 2019-10-18 9:01 ` Laurentiu Tudor
2019-10-18 9:01 ` [U-Boot] [PATCH v2 5/6] armv8: lx2160a: add icid setup for platform devices Laurentiu Tudor
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Laurentiu Tudor @ 2019-10-18 9:01 UTC (permalink / raw)
To: u-boot
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
LX2160A chips have 4 sata controllers. Add missing base addresses for
SATA3 and SATA4.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
Changes in v2:
- explicitly mention the chip on which these are needed (Priyanka)
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 4f050470dd..0e4bf331fd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -87,6 +87,8 @@
/* SATA */
#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
+#define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000)
+#define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000)
/* QDMA */
#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v2 5/6] armv8: lx2160a: add icid setup for platform devices
2019-10-18 9:01 [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor
` (2 preceding siblings ...)
2019-10-18 9:01 ` [U-Boot] [PATCH v2 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses Laurentiu Tudor
@ 2019-10-18 9:01 ` Laurentiu Tudor
2019-10-18 9:01 ` [U-Boot] [PATCH v2 6/6] armv8: ls1028a: add erratum A-050382 workaround Laurentiu Tudor
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Laurentiu Tudor @ 2019-10-18 9:01 UTC (permalink / raw)
To: u-boot
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geant?? <horia.geanta@nxp.com>
---
Changes in v2:
- added Reviewed-by tag
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 +
.../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++++++++++++++++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
.../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +-
.../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 +
board/freescale/lx2160a/lx2160a.c | 2 +
include/fsl_sec.h | 3 +-
7 files changed, 58 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index f00ef817b1..e398aecd12 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -24,6 +24,7 @@ endif
ifneq ($(CONFIG_ARCH_LX2160A),)
obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
+obj-y += icid.o lx2160_ids.o
endif
ifneq ($(CONFIG_ARCH_LS2080A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
new file mode 100644
index 0000000000..3a0ed1fa55
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/arch-fsl-layerscape/fsl_portals.h>
+
+struct icid_id_table icid_tbl[] = {
+ SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
+ SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID),
+ SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID),
+ SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID),
+ SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID),
+ SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID),
+#endif
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 924f5f3fe8..4dea8361fc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void)
#endif
#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
- defined(CONFIG_ARCH_LS2080A)
+ defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
set_icids();
#endif
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 0e4bf331fd..d46477d96e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -447,7 +447,9 @@ struct ccsr_gur {
u8 res_538[0x550 - 0x538]; /* add more registers when needed */
u32 sata1_amqr;
u32 sata2_amqr;
- u8 res_558[0x570-0x558]; /* add more registers when needed */
+ u32 sata3_amqr;
+ u32 sata4_amqr;
+ u8 res_560[0x570 - 0x560]; /* add more registers when needed */
u32 misc1_amqr;
u8 res_574[0x590-0x574]; /* add more registers when needed */
u32 spare1_amqr;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index 93bdcc4caa..0b36416ad3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -108,5 +108,7 @@
#define FSL_EDMA_STREAM_ID 70
#define FSL_GPU_STREAM_ID 71
#define FSL_DISPLAY_STREAM_ID 72
+#define FSL_SATA3_STREAM_ID 73
+#define FSL_SATA4_STREAM_ID 74
#endif
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index b509c0312e..eff12747b4 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -27,6 +27,7 @@
#include "../common/qixis.h"
#include "../common/vid.h"
#include <fsl_immap.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#ifdef CONFIG_EMC2305
#include "../common/emc2305.h"
@@ -684,6 +685,7 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fsl_mc_fixup_iommu_map_entry(blob);
fdt_fixup_board_enet(blob);
#endif
+ fdt_fixup_icid(blob);
return 0;
}
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index be08a2b88b..c0d2c7e866 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -93,8 +93,7 @@ typedef struct ccsr_sec {
struct {
u32 ms; /* DECO LIODN Register, MS */
u32 ls; /* DECO LIODN Register, LS */
- } decoliodnr[8];
- u8 res4[0x40];
+ } decoliodnr[16];
u32 dar; /* DECO Avail Register */
u32 drr; /* DECO Reset Register */
u8 res5[0x4d8];
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v2 6/6] armv8: ls1028a: add erratum A-050382 workaround
2019-10-18 9:01 [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor
` (3 preceding siblings ...)
2019-10-18 9:01 ` [U-Boot] [PATCH v2 5/6] armv8: lx2160a: add icid setup for platform devices Laurentiu Tudor
@ 2019-10-18 9:01 ` Laurentiu Tudor
2019-10-18 14:03 ` [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor
2019-11-11 8:56 ` Priyanka Jain
6 siblings, 0 replies; 11+ messages in thread
From: Laurentiu Tudor @ 2019-10-18 9:01 UTC (permalink / raw)
To: u-boot
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR
register in DCFG is not correctly forwarded to the SMMU.
The workaround consists in programming the eDMA ICID in the eDMA_AMQR
register in DCFG to 40.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
Changes in v2:
- reworded commit message and comment (Priyanka)
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++
.../asm/arch-fsl-layerscape/stream_id_lsch3.h | 15 +++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 24c606a232..046dcf539e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -45,6 +45,7 @@ config ARCH_LS1028A
select SYS_FSL_ERRATUM_A008514 if !TFABOOT
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+ select SYS_FSL_ERRATUM_A050382
imply PANIC_HANG
config ARCH_LS1043A
@@ -584,6 +585,8 @@ config SYS_FSL_ERRATUM_A009660
config SYS_FSL_ERRATUM_A009929
bool
+config SYS_FSL_ERRATUM_A050382
+ bool
config SYS_FSL_HAS_RGMII
bool
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index 0b36416ad3..94ea99a349 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -105,7 +105,22 @@
#define FSL_SEC_JR4_STREAM_ID 68
#define FSL_SDMMC2_STREAM_ID 69
+
+/*
+ * Erratum A-050382 workaround
+ *
+ * Description:
+ * The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not
+ * correctly forwarded to the SMMU.
+ * Workaround:
+ * Program eDMA ICID in the eDMA_AMQR register in DCFG to 40.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A050382
+#define FSL_EDMA_STREAM_ID 40
+#else
#define FSL_EDMA_STREAM_ID 70
+#endif
+
#define FSL_GPU_STREAM_ID 71
#define FSL_DISPLAY_STREAM_ID 72
#define FSL_SATA3_STREAM_ID 73
--
2.17.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v2 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled
2019-10-18 9:01 ` [U-Boot] [PATCH v2 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled Laurentiu Tudor
@ 2019-10-18 14:01 ` Horia Geanta
0 siblings, 0 replies; 11+ messages in thread
From: Horia Geanta @ 2019-10-18 14:01 UTC (permalink / raw)
To: u-boot
On 10/18/2019 12:01 PM, Laurentiu Tudor wrote:
> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>
> If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this
> compilation error happens:
> arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error:
> 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function)
>
> Fix it by wrapping with CONFIG_IS_ENABLED().
>
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Thanks,
Horia
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v2 3/6] armv8: ls2088a: add icid setup for platform devices
2019-10-18 9:01 ` [U-Boot] [PATCH v2 3/6] armv8: ls2088a: add icid setup for platform devices Laurentiu Tudor
@ 2019-10-18 14:01 ` Horia Geanta
0 siblings, 0 replies; 11+ messages in thread
From: Horia Geanta @ 2019-10-18 14:01 UTC (permalink / raw)
To: u-boot
On 10/18/2019 12:01 PM, Laurentiu Tudor wrote:
> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>
> Add ICID setup for the platform devices contained on this chip: usb,
> sata, sdhc, sec.
>
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Thanks,
Horia
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines
2019-10-18 9:01 [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor
` (4 preceding siblings ...)
2019-10-18 9:01 ` [U-Boot] [PATCH v2 6/6] armv8: ls1028a: add erratum A-050382 workaround Laurentiu Tudor
@ 2019-10-18 14:03 ` Laurentiu Tudor
2019-10-21 5:27 ` Priyanka Jain
2019-11-11 8:56 ` Priyanka Jain
6 siblings, 1 reply; 11+ messages in thread
From: Laurentiu Tudor @ 2019-10-18 14:03 UTC (permalink / raw)
To: u-boot
Hi Priyanka,
On 18.10.2019 12:01, Laurentiu Tudor wrote:
> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>
> These macros should only be used when CONFIG_FSL_CAAM is present.
>
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> Reviewed-by: Horia Geant?? <horia.geanta@nxp.com>
Looks like our mail server messed Horia's name here. Do you think you
could fix by hand when you'll pick up the patch?
---
Thanks & Best Regards, Laurentiu
> ---
> Changes in v2:
> - added Reviewed-by tag
>
> arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 ++
> arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
> index d9d125e8ba..9462298fbf 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
> @@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = {
> SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
> SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
> SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
> +#ifdef CONFIG_FSL_CAAM
> SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
> SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
> SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
> @@ -28,6 +29,7 @@ struct icid_id_table icid_tbl[] = {
> SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
> SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
> SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
> +#endif
> };
>
> int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
> index 49e27553b1..23743ae10c 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
> @@ -13,6 +13,7 @@ struct icid_id_table icid_tbl[] = {
> SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
> SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
> SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
> +#ifdef CONFIG_FSL_CAAM
> SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
> SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
> SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
> @@ -25,6 +26,7 @@ struct icid_id_table icid_tbl[] = {
> SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
> SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
> SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
> +#endif
> };
>
> int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines
2019-10-18 14:03 ` [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor
@ 2019-10-21 5:27 ` Priyanka Jain
0 siblings, 0 replies; 11+ messages in thread
From: Priyanka Jain @ 2019-10-21 5:27 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Laurentiu Tudor
>Sent: Friday, October 18, 2019 7:34 PM
>To: u-boot at lists.denx.de; Priyanka Jain <priyanka.jain@nxp.com>
>Cc: Horia Geanta <horia.geanta@nxp.com>
>Subject: Re: [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines
>
>Hi Priyanka,
>
>On 18.10.2019 12:01, Laurentiu Tudor wrote:
>> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>>
>> These macros should only be used when CONFIG_FSL_CAAM is present.
>>
>> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>> Reviewed-by: Horia Geant?? <horia.geanta@nxp.com>
>
>Looks like our mail server messed Horia's name here. Do you think you could
>fix by hand when you'll pick up the patch?
Will take care
<snip>
--priyankajain
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines
2019-10-18 9:01 [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor
` (5 preceding siblings ...)
2019-10-18 14:03 ` [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor
@ 2019-11-11 8:56 ` Priyanka Jain
6 siblings, 0 replies; 11+ messages in thread
From: Priyanka Jain @ 2019-11-11 8:56 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>Sent: Friday, October 18, 2019 2:32 PM
>To: u-boot at lists.denx.de; Priyanka Jain <priyanka.jain@nxp.com>
>Cc: Horia Geanta <horia.geanta@nxp.com>; Laurentiu Tudor
><laurentiu.tudor@nxp.com>
>Subject: [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines
>
>From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>
>These macros should only be used when CONFIG_FSL_CAAM is present.
>
>Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>Reviewed-by: Horia Geant?? <horia.geanta@nxp.com>
>---
>Changes in v2:
> - added Reviewed-by tag
>
> arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 ++
>arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 ++
> 2 files changed, 4 insertions(+)
>
>diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
>b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
>index d9d125e8ba..9462298fbf 100644
>--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
>+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
>@@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = {
> SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
> SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
> SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
>+#ifdef CONFIG_FSL_CAAM
> SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
> SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
> SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), @@ -28,6 +29,7
>@@ struct icid_id_table icid_tbl[] = {
> SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
> SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
> SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
>+#endif
> };
>
> int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-
>layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
>index 49e27553b1..23743ae10c 100644
>--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
>+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
>@@ -13,6 +13,7 @@ struct icid_id_table icid_tbl[] = {
> SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
> SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
> SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
>+#ifdef CONFIG_FSL_CAAM
> SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
> SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
> SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), @@ -25,6 +26,7
>@@ struct icid_id_table icid_tbl[] = {
> SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
> SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
> SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
>+#endif
> };
>
> int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
>--
>2.17.1
Slight updates in subject and/or description of few patches done.
Series applied to fsl-qoriq master, awaiting upstream.
Thanks
priyankajain
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-11-11 8:56 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-18 9:01 [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor
2019-10-18 9:01 ` [U-Boot] [PATCH v2 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled Laurentiu Tudor
2019-10-18 14:01 ` Horia Geanta
2019-10-18 9:01 ` [U-Boot] [PATCH v2 3/6] armv8: ls2088a: add icid setup for platform devices Laurentiu Tudor
2019-10-18 14:01 ` Horia Geanta
2019-10-18 9:01 ` [U-Boot] [PATCH v2 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses Laurentiu Tudor
2019-10-18 9:01 ` [U-Boot] [PATCH v2 5/6] armv8: lx2160a: add icid setup for platform devices Laurentiu Tudor
2019-10-18 9:01 ` [U-Boot] [PATCH v2 6/6] armv8: ls1028a: add erratum A-050382 workaround Laurentiu Tudor
2019-10-18 14:03 ` [U-Boot] [PATCH v2 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor
2019-10-21 5:27 ` Priyanka Jain
2019-11-11 8:56 ` Priyanka Jain
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