* [U-Boot] [PATCH v4 2/8] armv8: Add workaround for USB erratum A-009798
2017-08-28 9:15 [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008 Ran Wang
@ 2017-08-28 9:15 ` Ran Wang
2017-08-28 9:15 ` [U-Boot] [PATCH v4 3/8] armv8: Add workaround for USB erratum A-008997 Ran Wang
` (6 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2017-08-28 9:15 UTC (permalink / raw)
To: u-boot
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Change in v4:
Update commit message about register setting.
Clean up the math in set_usb_sqrxtune().
Rename USB_TXVREFTUNE to SCFG_USB_TXVREFTUNE.
Change in v3:
Use inline function to make code cleaner.
Change in v2:
In function erratum_a009798():
1.Put a blank line after variable declaration.
2.Move common code together.
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 5 ++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 27 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
4 files changed, 34 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index d8936a4334..6677f2309a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -23,6 +23,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -46,6 +47,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -83,6 +85,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009203
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
@@ -229,6 +232,8 @@ config SYS_FSL_ERRATUM_A010539
config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
+config SYS_FSL_ERRATUM_A009798
+ bool "Workaround for USB PHY erratum A009798"
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 52a7abd13c..c00f732dc8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -66,6 +66,7 @@ static void erratum_a009008(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
@@ -76,6 +77,30 @@ static void erratum_a009008(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
+static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
+{
+ u32 val;
+
+ val = scfg_in32(scfg + offset / 4);
+ val &= ~(SCFG_USB_SQRXTUNE_MASK << 23);
+ scfg_out32(scfg + offset / 4, val);
+}
+
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
+#elif defined(CONFIG_ARCH_LS2080A)
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
@@ -223,6 +248,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+ erratum_a009798();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -499,6 +525,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+ erratum_a009798();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index c60d8ddfa2..323c098888 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -343,6 +343,7 @@ struct ccsr_gur {
#define SCFG_USB3PRM1CR_USB2 0x07C
#define SCFG_USB3PRM1CR_USB3 0x088
#define SCFG_USB_TXVREFTUNE 0x9
+#define SCFG_USB_SQRXTUNE_MASK 0x7
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 01b24d03f1..3b2e9eaa8b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -134,6 +134,7 @@
#define SCFG_USB3PRM1CR 0x000
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
#define SCFG_USB_TXVREFTUNE 0x9
+#define SCFG_USB_SQRXTUNE_MASK 0x7
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v4 3/8] armv8: Add workaround for USB erratum A-008997
2017-08-28 9:15 [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008 Ran Wang
2017-08-28 9:15 ` [U-Boot] [PATCH v4 2/8] armv8: Add workaround for USB erratum A-009798 Ran Wang
@ 2017-08-28 9:15 ` Ran Wang
2017-08-30 18:06 ` York Sun
2017-08-28 9:15 ` [U-Boot] [PATCH v4 4/8] armv8: Add workaround for USB erratum A-009007 Ran Wang
` (5 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Ran Wang @ 2017-08-28 9:15 UTC (permalink / raw)
To: u-boot
Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter
settings
Change config of transmitter signal swings by setting register
PCSTXSWINGFULL to 0x47 to pass compliance tests.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Change in v4:
Update commit message about register setting.
Clean up the math in set_usb_pcstxswingfull().
Rename USB_PCSTXSWINGFULL to SCFG_USB_PCSTXSWINGFULL.
Change in v3:
Use inline function to make code cleaner.
Correct typo of 'CONFIG_ARCH_LS1043A'.
Change in v2:
In function erratum_a008997():
1.Put a blank line after variable declaration.
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 27 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 ++++
3 files changed, 37 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 6677f2309a..9449d629ea 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -24,6 +24,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -48,6 +49,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -86,6 +88,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009203
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
@@ -235,6 +238,9 @@ config SYS_FSL_ERRATUM_A009008
config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
+config SYS_FSL_ERRATUM_A008997
+ bool "Workaround for USB PHY erratum A008997"
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index c00f732dc8..78be5853cb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -101,6 +101,31 @@ static void erratum_a009798(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
+{
+ u32 val;
+
+ val = scfg_in32(scfg + offset / 4);
+ val &= ~(0x7F << 9);
+ val |= (SCFG_USB_PCSTXSWINGFULL << 9);
+ scfg_out32(scfg + offset / 4, val);
+}
+#endif
+
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+ set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
+ set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
+ set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
@@ -249,6 +274,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008336();
erratum_a009008();
erratum_a009798();
+ erratum_a008997();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -526,6 +552,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a010539();
erratum_a009008();
erratum_a009798();
+ erratum_a008997();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 323c098888..1601ec6baa 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -340,10 +340,14 @@ struct ccsr_gur {
#define SCFG_BASE 0x01570000
#define SCFG_USB3PRM1CR_USB1 0x070
+#define SCFG_USB3PRM2CR_USB1 0x074
#define SCFG_USB3PRM1CR_USB2 0x07C
+#define SCFG_USB3PRM2CR_USB2 0x080
#define SCFG_USB3PRM1CR_USB3 0x088
+#define SCFG_USB3PRM2CR_USB3 0x08c
#define SCFG_USB_TXVREFTUNE 0x9
#define SCFG_USB_SQRXTUNE_MASK 0x7
+#define SCFG_USB_PCSTXSWINGFULL 0x47
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v4 3/8] armv8: Add workaround for USB erratum A-008997
2017-08-28 9:15 ` [U-Boot] [PATCH v4 3/8] armv8: Add workaround for USB erratum A-008997 Ran Wang
@ 2017-08-30 18:06 ` York Sun
2017-08-31 2:10 ` Ran Wang
0 siblings, 1 reply; 12+ messages in thread
From: York Sun @ 2017-08-30 18:06 UTC (permalink / raw)
To: u-boot
On 08/28/2017 02:33 AM, Ran Wang wrote:
> Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential
> Output Voltage Test Compliance fails using default transmitter
> settings
>
> Change config of transmitter signal swings by setting register
> PCSTXSWINGFULL to 0x47 to pass compliance tests.
>
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
> ---
> Change in v4:
> Update commit message about register setting.
> Clean up the math in set_usb_pcstxswingfull().
> Rename USB_PCSTXSWINGFULL to SCFG_USB_PCSTXSWINGFULL.
>
> Change in v3:
> Use inline function to make code cleaner.
> Correct typo of 'CONFIG_ARCH_LS1043A'.
>
> Change in v2:
> In function erratum_a008997():
> 1.Put a blank line after variable declaration.
<snip>
> +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
> +static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
> +{
> + u32 val;
> +
> + val = scfg_in32(scfg + offset / 4);
> + val &= ~(0x7F << 9);
> + val |= (SCFG_USB_PCSTXSWINGFULL << 9);
> + scfg_out32(scfg + offset / 4, val);
> +}
> +#endif
> +
> +static void erratum_a008997(void)
> +{
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
> +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
I didn't notice this before. Why checking LS1043A or LS1046A? I don't
see "else" below.
York
^ permalink raw reply [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v4 3/8] armv8: Add workaround for USB erratum A-008997
2017-08-30 18:06 ` York Sun
@ 2017-08-31 2:10 ` Ran Wang
0 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2017-08-31 2:10 UTC (permalink / raw)
To: u-boot
Hi York
> -----Original Message-----
> From: York Sun
> Sent: Thursday, August 31, 2017 2:07 AM
> To: Ran Wang <ran.wang_1@nxp.com>; open list <u-boot@lists.denx.de>
> Cc: Suresh Gupta <suresh.bhagat@nxp.com>; Sriram Dash
> <sriram.dash@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Simon Glass <sjg@chromium.org>; Rajesh
> Bhagat <rajesh.bhagat@nxp.com>; Andy Tang <andy.tang@nxp.com>; Priyanka
> Jain <priyanka.jain@nxp.com>
> Subject: Re: [PATCH v4 3/8] armv8: Add workaround for USB erratum A-008997
>
> On 08/28/2017 02:33 AM, Ran Wang wrote:
> > Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential
> > Output Voltage Test Compliance fails using default transmitter
> > settings
> >
> > Change config of transmitter signal swings by setting register
> > PCSTXSWINGFULL to 0x47 to pass compliance tests.
> >
> > Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> > Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> > Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
> > Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
> > ---
> > Change in v4:
> > Update commit message about register setting.
> > Clean up the math in set_usb_pcstxswingfull().
> > Rename USB_PCSTXSWINGFULL to SCFG_USB_PCSTXSWINGFULL.
> >
> > Change in v3:
> > Use inline function to make code cleaner.
> > Correct typo of 'CONFIG_ARCH_LS1043A'.
> >
> > Change in v2:
> > In function erratum_a008997():
> > 1.Put a blank line after variable declaration.
>
> <snip>
>
> > +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
> > +static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32
> > +offset) {
> > + u32 val;
> > +
> > + val = scfg_in32(scfg + offset / 4);
> > + val &= ~(0x7F << 9);
> > + val |= (SCFG_USB_PCSTXSWINGFULL << 9);
> > + scfg_out32(scfg + offset / 4, val);
> > +}
> > +#endif
> > +
> > +static void erratum_a008997(void)
> > +{
> > +#ifdef CONFIG_SYS_FSL_ERRATUM_A008997 #if
> > +defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
>
> I didn't notice this before. Why checking LS1043A or LS1046A? I don't see "else"
> below.
Because so far errata A008997 in armv8 part is only for these 2 SoCs, other SoC such as LS2088A have fixed this chip issue by HW.
Ran
^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v4 4/8] armv8: Add workaround for USB erratum A-009007
2017-08-28 9:15 [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008 Ran Wang
2017-08-28 9:15 ` [U-Boot] [PATCH v4 2/8] armv8: Add workaround for USB erratum A-009798 Ran Wang
2017-08-28 9:15 ` [U-Boot] [PATCH v4 3/8] armv8: Add workaround for USB erratum A-008997 Ran Wang
@ 2017-08-28 9:15 ` Ran Wang
2017-08-28 9:15 ` [U-Boot] [PATCH v4 5/8] armv7: Add workaround for USB erratum A-009008 Ran Wang
` (4 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2017-08-28 9:15 UTC (permalink / raw)
To: u-boot
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values.
Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Change in v4:
Update commit message about register setting.
Rename some registers which belong to SCFG.
Change in v3:
- none
Change in v2:
In function erratum_a009007():
1.Put a blank line after variable declaration.
2.Create a mcro to run for each USB for easier to read and maintain.
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12 ++++++-
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 40 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 8 +++++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 +++++
4 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 9449d629ea..c5c5f4e130 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -25,6 +25,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -50,6 +51,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -89,6 +91,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
@@ -239,7 +242,14 @@ config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
config SYS_FSL_ERRATUM_A008997
- bool "Workaround for USB PHY erratum A008997"
+ bool
+ help
+ Workaround for USB PHY erratum A008997
+
+config SYS_FSL_ERRATUM_A009007
+ bool
+ help
+ Workaround for USB PHY erratum A009007
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 78be5853cb..f92ff7733c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -126,6 +126,44 @@ static void erratum_a008997(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+
+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
+ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
+ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
+ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
+ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
+
+#elif defined(CONFIG_ARCH_LS2080A)
+
+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
+ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
+ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
+ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
+ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
+
+#endif
+
+static void erratum_a009007(void)
+{
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
+
+ PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+
+ usb_phy = (void __iomem *)SCFG_USB_PHY2;
+ PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+
+ usb_phy = (void __iomem *)SCFG_USB_PHY3;
+ PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+#elif defined(CONFIG_ARCH_LS2080A)
+ void __iomem *dcsr = (void __iomem *)DCSR_BASE;
+
+ PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
+ PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
@@ -275,6 +313,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+ erratum_a009007();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -553,6 +592,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+ erratum_a009007();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 1601ec6baa..130dc4bfbe 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -348,6 +348,14 @@ struct ccsr_gur {
#define SCFG_USB_TXVREFTUNE 0x9
#define SCFG_USB_SQRXTUNE_MASK 0x7
#define SCFG_USB_PCSTXSWINGFULL 0x47
+#define SCFG_USB_PHY1 0x084F0000
+#define SCFG_USB_PHY2 0x08500000
+#define SCFG_USB_PHY3 0x08510000
+#define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x0080
+#define USB_PHY_RX_EQ_VAL_3 0x0380
+#define USB_PHY_RX_EQ_VAL_4 0x0b80
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3b2e9eaa8b..3e03d7b4c3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -137,6 +137,15 @@
#define SCFG_USB_SQRXTUNE_MASK 0x7
#define SCFG_QSPICLKCTLR 0x10
+#define DCSR_BASE 0x700000000ULL
+#define DCSR_USB_PHY1 0x4600000
+#define DCSR_USB_PHY2 0x4610000
+#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x0080
+#define USB_PHY_RX_EQ_VAL_3 0x0380
+#define USB_PHY_RX_EQ_VAL_4 0x0b80
+
#define TP_ITYP_AV 0x00000001 /* Initiator available */
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
#define TP_ITYP_TYPE_ARM 0x0
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v4 5/8] armv7: Add workaround for USB erratum A-009008
2017-08-28 9:15 [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008 Ran Wang
` (2 preceding siblings ...)
2017-08-28 9:15 ` [U-Boot] [PATCH v4 4/8] armv8: Add workaround for USB erratum A-009007 Ran Wang
@ 2017-08-28 9:15 ` Ran Wang
2017-08-28 9:15 ` [U-Boot] [PATCH v4 6/8] armv7: Add workaround for USB erratum A-009798 Ran Wang
` (3 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2017-08-28 9:15 UTC (permalink / raw)
To: u-boot
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Change in v4:
Change 1001 to 0x9 in the commit message to match the code.
Clean up the math in register setting.
Rename USB_TXVREFTUNE TO SCFG_USB_TXVREFTUNE.
Change in v3:
- none
Change in v2:
In function erratum_a009008():
1.Put a blank line after variable declaration.
arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++
arch/arm/cpu/armv7/ls102xa/soc.c | 16 ++++++++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++++
3 files changed, 26 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index fadfce4f05..599cc28249 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_ERRATUM_A009008
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -52,6 +53,11 @@ config SECURE_BOOT
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_ERRATUM_A009008
+ bool
+ help
+ Workaround for USB erratum A009008
+
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index b84a1a686a..0cdc625380 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,19 @@ unsigned int get_soc_major_rev(void)
return major;
}
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+
+ val &= ~(0xF << 6);
+ val |= (SCFG_USB_TXVREFTUNE << 6);
+ out_be32(scfg + SCFG_USB3PRM1CR / 4, val);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
+
void s_init(void)
{
}
@@ -146,6 +159,9 @@ int arch_soc_init(void)
*/
out_be32(&scfg->eddrtqcfg, 0x63b20042);
+ /* Erratum */
+ erratum_a009008();
+
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63e66..ba59f40382 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -173,6 +173,10 @@ struct ccsr_gur {
#define SCFG_PMCINTECR_ETSECERRG1 0x00040000
#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
+#define SCFG_BASE 0x01570000
+#define SCFG_USB3PRM1CR 0x070
+#define SCFG_USB_TXVREFTUNE 0x9
+
/* Supplemental Configuration Unit */
struct ccsr_scfg {
u32 dpslpcr;
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v4 6/8] armv7: Add workaround for USB erratum A-009798
2017-08-28 9:15 [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008 Ran Wang
` (3 preceding siblings ...)
2017-08-28 9:15 ` [U-Boot] [PATCH v4 5/8] armv7: Add workaround for USB erratum A-009008 Ran Wang
@ 2017-08-28 9:15 ` Ran Wang
2017-08-28 9:15 ` [U-Boot] [PATCH v4 7/8] armv7: Add workaround for USB erratum A-008997 Ran Wang
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2017-08-28 9:15 UTC (permalink / raw)
To: u-boot
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.
Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Change in v4:
Update commit message about register setting.
Clean up the math in register setting.
Redefine SQRXTUNE to make code clearer.
Change in v3:
- none
Change in v2:
In function erratum_a009798():
1.Put a blank line after variable declaration.
arch/arm/cpu/armv7/ls102xa/Kconfig | 8 +++++++-
arch/arm/cpu/armv7/ls102xa/soc.c | 11 +++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 599cc28249..f09766cf03 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -6,6 +6,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -56,7 +57,12 @@ config SYS_FSL_ERRATUM_A010315
config SYS_FSL_ERRATUM_A009008
bool
help
- Workaround for USB erratum A009008
+ Workaround for USB PHY erratum A009008
+
+config SYS_FSL_ERRATUM_A009798
+ bool
+ help
+ Workaround for USB PHY erratum A009798
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 0cdc625380..487b5cf0ec 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -72,6 +72,16 @@ static void erratum_a009008(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+
+ val &= ~(SCFG_USB_SQRXTUNE_MASK << 23);
+ out_be32(scfg + SCFG_USB3PRM1CR / 4, val);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
void s_init(void)
{
@@ -161,6 +171,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
+ erratum_a009798();
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index ba59f40382..5762d3308a 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,7 @@ struct ccsr_gur {
#define SCFG_BASE 0x01570000
#define SCFG_USB3PRM1CR 0x070
#define SCFG_USB_TXVREFTUNE 0x9
+#define SCFG_USB_SQRXTUNE_MASK 0x7
/* Supplemental Configuration Unit */
struct ccsr_scfg {
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v4 7/8] armv7: Add workaround for USB erratum A-008997
2017-08-28 9:15 [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008 Ran Wang
` (4 preceding siblings ...)
2017-08-28 9:15 ` [U-Boot] [PATCH v4 6/8] armv7: Add workaround for USB erratum A-009798 Ran Wang
@ 2017-08-28 9:15 ` Ran Wang
2017-08-28 9:15 ` [U-Boot] [PATCH v4 8/8] armv7: Add workaround for USB erratum A-009007 Ran Wang
2017-08-30 18:06 ` [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008 York Sun
7 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2017-08-28 9:15 UTC (permalink / raw)
To: u-boot
Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change config of transmitter signal swings by setting register
PCSTXSWINGFULL to 0x47 to pass compliance tests.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Change in v4:
Update commit message about register setting.
Rename USB_PCSTXSWINGFULL to SCFG_USB_PCSTXSWINGFULL.
Change in v3:
- none
Change in v2:
In function erratum_a008997():
1.Put a blank line after variable declaration.
arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++
arch/arm/cpu/armv7/ls102xa/soc.c | 14 ++++++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++
3 files changed, 23 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index f09766cf03..ee09dd6fed 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -7,6 +7,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -64,6 +65,11 @@ config SYS_FSL_ERRATUM_A009798
help
Workaround for USB PHY erratum A009798
+config SYS_FSL_ERRATUM_A008997
+ bool
+ help
+ Workaround for USB PHY erratum A008997
+
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 487b5cf0ec..ee9eb59f59 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -83,6 +83,19 @@ static void erratum_a009798(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = in_be32(scfg + SCFG_USB3PRM2CR / 4);
+
+ val &= ~SCFG_USB_PCSTXSWINGFULL_MASK;
+ val |= SCFG_USB_PCSTXSWINGFULL_VAL;
+ out_be32(scfg + SCFG_USB3PRM2CR / 4, val);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
+
void s_init(void)
{
}
@@ -172,6 +185,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
erratum_a009798();
+ erratum_a008997();
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 5762d3308a..e5c06170da 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -177,6 +177,9 @@ struct ccsr_gur {
#define SCFG_USB3PRM1CR 0x070
#define SCFG_USB_TXVREFTUNE 0x9
#define SCFG_USB_SQRXTUNE_MASK 0x7
+#define SCFG_USB3PRM2CR 0x074
+#define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00
+#define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00
/* Supplemental Configuration Unit */
struct ccsr_scfg {
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v4 8/8] armv7: Add workaround for USB erratum A-009007
2017-08-28 9:15 [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008 Ran Wang
` (5 preceding siblings ...)
2017-08-28 9:15 ` [U-Boot] [PATCH v4 7/8] armv7: Add workaround for USB erratum A-008997 Ran Wang
@ 2017-08-28 9:15 ` Ran Wang
2017-08-30 18:06 ` [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008 York Sun
7 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2017-08-28 9:15 UTC (permalink / raw)
To: u-boot
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Change in v4:
Update commit message about register setting.
Change in v3:
- none
Change in v2:
In function erratum_a009007():
1.Put a blank line after variable declaration.
arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++
arch/arm/cpu/armv7/ls102xa/soc.c | 12 ++++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 7 +++++++
3 files changed, 25 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index ee09dd6fed..a77bb06cf9 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -70,6 +71,11 @@ config SYS_FSL_ERRATUM_A008997
help
Workaround for USB PHY erratum A008997
+config SYS_FSL_ERRATUM_A009007
+ bool
+ help
+ Workaround for USB PHY erratum A009007
+
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index ee9eb59f59..520ac84857 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -95,6 +95,17 @@ static void erratum_a008997(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+ void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+
+ out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
+ out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
+ out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
+ out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
void s_init(void)
{
@@ -186,6 +197,7 @@ int arch_soc_init(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+ erratum_a009007();
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index e5c06170da..157643eb91 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -181,6 +181,13 @@ struct ccsr_gur {
#define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00
#define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00
+#define USB_PHY_BASE 0x08510000
+#define USB_PHY_RX_OVRD_IN_HI 0x200c
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8004
+#define USB_PHY_RX_EQ_VAL_4 0x800C
+
/* Supplemental Configuration Unit */
struct ccsr_scfg {
u32 dpslpcr;
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008
2017-08-28 9:15 [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008 Ran Wang
` (6 preceding siblings ...)
2017-08-28 9:15 ` [U-Boot] [PATCH v4 8/8] armv7: Add workaround for USB erratum A-009007 Ran Wang
@ 2017-08-30 18:06 ` York Sun
2017-08-31 2:25 ` Ran Wang
7 siblings, 1 reply; 12+ messages in thread
From: York Sun @ 2017-08-30 18:06 UTC (permalink / raw)
To: u-boot
On 08/28/2017 02:32 AM, Ran Wang wrote:
> USB High Speed (HS) EYE Height Adjustment
> USB HS speed eye diagram fails with the default value at
> many corners, particularly at a high temperature
>
> Optimal eye at TXREFTUNE value to 0x9 is observed, change
> set the same value.
>
> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
> ---
> Change in v4:
> Change 1001 to 0x9 in the commit message to match the code.
> Clean up the math in set_usb_txvreftune().
> Rename USB_TXVREFTUNE to SCFG_USB_TXVREFTUNE.
>
> Change in v3:
> Use inline function to make code cleaner.
>
> Change in v2:
> In function erratum_a009008():
> 1.Put a blank line after variable declaration.
> 2.Move common code together.
>
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++++
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 26 ++++++++++++++++++++++
> .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 +++++
> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
> 4 files changed, 40 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index cdeef26fe5..d8936a4334 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -22,6 +22,7 @@ config ARCH_LS1043A
> select SYS_FSL_ERRATUM_A009942
> select SYS_FSL_ERRATUM_A010315
> select SYS_FSL_ERRATUM_A010539
> + select SYS_FSL_ERRATUM_A009008
> select SYS_FSL_HAS_DDR3
> select SYS_FSL_HAS_DDR4
> select ARCH_EARLY_INIT_R
> @@ -44,6 +45,7 @@ config ARCH_LS1046A
> select SYS_FSL_ERRATUM_A009942
> select SYS_FSL_ERRATUM_A010165
> select SYS_FSL_ERRATUM_A010539
> + select SYS_FSL_ERRATUM_A009008
> select SYS_FSL_HAS_DDR4
> select SYS_FSL_SRDS_2
> select ARCH_EARLY_INIT_R
> @@ -80,6 +82,7 @@ config ARCH_LS2080A
> select SYS_FSL_ERRATUM_A009942
> select SYS_FSL_ERRATUM_A010165
> select SYS_FSL_ERRATUM_A009203
> + select SYS_FSL_ERRATUM_A009008
> select ARCH_EARLY_INIT_R
> select BOARD_EARLY_INIT_F
>
> @@ -223,6 +226,10 @@ config SYS_FSL_ERRATUM_A010315
> config SYS_FSL_ERRATUM_A010539
> bool "Workaround for PIN MUX erratum A010539"
>
> +config SYS_FSL_ERRATUM_A009008
> + bool "Workaround for USB PHY erratum A009008"
> +
> +
> config MAX_CPUS
> int "Maximum number of CPUs permitted for Layerscape"
> default 4 if ARCH_LS1043A
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index 639e9d2ddc..52a7abd13c 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -52,6 +52,30 @@ bool soc_has_aiop(void)
> return false;
> }
>
> +static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
> +{
> + u32 val;
> +
> + val = scfg_in32(scfg + offset / 4);
> + val &= ~(0xF << 6);
> + val |= SCFG_USB_TXVREFTUNE << 6;
> + scfg_out32(scfg + offset / 4, val);
> +}
As Marek suggested, can we use this?
+static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
+{
+ scfg_clrsetbits_32(scfg + offset / 4,
+ 0xF << 6,
+ SCFG_USB_TXVREFTUNE << 6);
+}
This means a new macro is added in soc.h.
I still prefer to keep "inline" here to avoid using stack frame for this
simple but repeated call.
York
^ permalink raw reply [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008
2017-08-30 18:06 ` [U-Boot] [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008 York Sun
@ 2017-08-31 2:25 ` Ran Wang
0 siblings, 0 replies; 12+ messages in thread
From: Ran Wang @ 2017-08-31 2:25 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: York Sun
> Sent: Thursday, August 31, 2017 2:07 AM
> To: Ran Wang <ran.wang_1@nxp.com>; open list <u-boot@lists.denx.de>
> Cc: Suresh Gupta <suresh.bhagat@nxp.com>; Sriram Dash
> <sriram.dash@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Simon Glass <sjg@chromium.org>; Rajesh
> Bhagat <rajesh.bhagat@nxp.com>; Andy Tang <andy.tang@nxp.com>; Priyanka
> Jain <priyanka.jain@nxp.com>
> Subject: Re: [PATCH v4 1/8] armv8: Add workaround for USB erratum A-009008
>
> On 08/28/2017 02:32 AM, Ran Wang wrote:
> > USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram
> > fails with the default value at many corners, particularly at a high
> > temperature
> >
> > Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same
> > value.
> >
> > Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
> > ---
> > Change in v4:
> > Change 1001 to 0x9 in the commit message to match the code.
> > Clean up the math in set_usb_txvreftune().
> > Rename USB_TXVREFTUNE to SCFG_USB_TXVREFTUNE.
> >
> > Change in v3:
> > Use inline function to make code cleaner.
> >
> > Change in v2:
> > In function erratum_a009008():
> > 1.Put a blank line after variable declaration.
> > 2.Move common code together.
> >
> > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++++
> > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 26
> ++++++++++++++++++++++
> > .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 +++++
> > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
> > 4 files changed, 40 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > index cdeef26fe5..d8936a4334 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > @@ -22,6 +22,7 @@ config ARCH_LS1043A
> > select SYS_FSL_ERRATUM_A009942
> > select SYS_FSL_ERRATUM_A010315
> > select SYS_FSL_ERRATUM_A010539
> > + select SYS_FSL_ERRATUM_A009008
> > select SYS_FSL_HAS_DDR3
> > select SYS_FSL_HAS_DDR4
> > select ARCH_EARLY_INIT_R
> > @@ -44,6 +45,7 @@ config ARCH_LS1046A
> > select SYS_FSL_ERRATUM_A009942
> > select SYS_FSL_ERRATUM_A010165
> > select SYS_FSL_ERRATUM_A010539
> > + select SYS_FSL_ERRATUM_A009008
> > select SYS_FSL_HAS_DDR4
> > select SYS_FSL_SRDS_2
> > select ARCH_EARLY_INIT_R
> > @@ -80,6 +82,7 @@ config ARCH_LS2080A
> > select SYS_FSL_ERRATUM_A009942
> > select SYS_FSL_ERRATUM_A010165
> > select SYS_FSL_ERRATUM_A009203
> > + select SYS_FSL_ERRATUM_A009008
> > select ARCH_EARLY_INIT_R
> > select BOARD_EARLY_INIT_F
> >
> > @@ -223,6 +226,10 @@ config SYS_FSL_ERRATUM_A010315
> > config SYS_FSL_ERRATUM_A010539
> > bool "Workaround for PIN MUX erratum A010539"
> >
> > +config SYS_FSL_ERRATUM_A009008
> > + bool "Workaround for USB PHY erratum A009008"
> > +
> > +
> > config MAX_CPUS
> > int "Maximum number of CPUs permitted for Layerscape"
> > default 4 if ARCH_LS1043A
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 639e9d2ddc..52a7abd13c 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -52,6 +52,30 @@ bool soc_has_aiop(void)
> > return false;
> > }
> >
> > +static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
> > +{
> > + u32 val;
> > +
> > + val = scfg_in32(scfg + offset / 4);
> > + val &= ~(0xF << 6);
> > + val |= SCFG_USB_TXVREFTUNE << 6;
> > + scfg_out32(scfg + offset / 4, val);
> > +}
>
> As Marek suggested, can we use this?
>
> +static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset) {
> + scfg_clrsetbits_32(scfg + offset / 4,
> + 0xF << 6,
> + SCFG_USB_TXVREFTUNE << 6);
> +}
>
> This means a new macro is added in soc.h.
OK, will work out v5 and re-test, thanks for sample code.
>
> I still prefer to keep "inline" here to avoid using stack frame for this simple but
> repeated call.
Agree,
>
> York
^ permalink raw reply [flat|nested] 12+ messages in thread