* [PATCH v8 00/15] Add CAAM driver model support
@ 2022-01-10 12:26 Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
` (14 more replies)
0 siblings, 15 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:26 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
This patchset adds the support for following:
1) CAAM Driver model for all i.MX, layerscape, PPC platforms.
2) Added crypto node in device tree files.
3) fix build issue for mx6sabre: Remove SPL DTB related configs and SPL_OF_CONTROL.
4) improve hwrng performance in kernel.
i.MX platforms:
i.MX6, i.MX7, i.MX7ULP, i.MX8MM/MN/MP/MQ, i.MX8QM/QXP
Layerscape platforms:
LS1021, LS1012, LS1028, LS1043, LS1046, LS1088, LS2088, LX2160, LX2162
Powerpc platforms:
P3041, P4080, P5040, P2041, T1024, T1042, T2080, T4240
changes since v7:
- rebase to latest master
- corrected the order of include files as per coding style in jr.c.
https://www.denx.de/wiki/U-Boot/CodingStyle
- added brackets around #defines for -ve number in jr.h
- added comments for struct caam_regs added in jr.h
changes since v6:
- rebase to latest master
- added caam_jr_ioctl() operation which calls run_descriptor_jr().
- removed CONFIG_ARCH_IMX8 config from JR driver.
- removed FSL_BLOB config
changes since v5:
- rebase to latest master
- updated BIT() macro for JRDID in drivers/crypto/fsl/jr.h
- removed auto select FSL_BLOB from CMD_BLOB config.
- removed patch for blob key encryption key(bkek), random number generation.
- updated patch description for improving hwrng performance in kernel.
- removed sec_init() from kontron/sl28.
- for LS1028A architecture, enable CAAM only for LS1028AQDS and LS1028ARDB.
changes since v4:
- rebase to latest master
- updated caam_jr_probe() with livetree APIs.
- imx8m: moved jr0 disable code to *-uboot.dtsi files.
changes since v3:
- rebase to latest master
- fixed build error when new file arch/powerpc/include/asm/u-boot-ppc.h is
included from assembly files.
- removed arch/arm/dts/fsl-ls1028a.dtsi as it is conflicting with the series
https://lore.kernel.org/u-boot/20211013161427.612033-1-michael@walle.cc/
Gaurav Jain (13):
crypto/fsl: Add support for CAAM Job ring driver model
i.MX8M: crypto: updated device tree for supporting DM in SPL
crypto/fsl: i.MX8M: Enable Job ring driver model.
i.MX6: Enable Job ring driver model.
i.MX7: Enable Job ring driver model.
i.MX7ULP: Enable Job ring driver model.
i.MX8: Add crypto node in device tree
crypto/fsl: i.MX8: Enable Job ring driver model.
Layerscape: Add crypto node in device tree
Layerscape: Enable Job ring driver model.
PPC: Add crypto node in device tree
PPC: Enable Job ring driver model.
update CAAM MAINTAINER
Ye Li (2):
mx6sabre: Remove unnecessary SPL configs
crypto/fsl: Improve hwrng performance in kernel
MAINTAINERS | 6 +
arch/arm/Kconfig | 13 +-
arch/arm/cpu/armv7/ls102xa/Kconfig | 3 +
arch/arm/cpu/armv7/ls102xa/cpu.c | 16 +
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 17 +
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 10 +-
arch/arm/dts/fsl-imx8dx.dtsi | 61 ++-
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 34 +-
arch/arm/dts/fsl-imx8qm.dtsi | 61 ++-
arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 34 +-
arch/arm/dts/fsl-ls1012a.dtsi | 46 +-
arch/arm/dts/fsl-ls1043a.dtsi | 45 +-
arch/arm/dts/fsl-ls1046a.dtsi | 44 ++
arch/arm/dts/fsl-ls1088a.dtsi | 39 ++
arch/arm/dts/fsl-ls2080a.dtsi | 39 ++
arch/arm/dts/fsl-lx2160a.dtsi | 41 +-
arch/arm/dts/imx7ulp.dtsi | 24 +
arch/arm/dts/imx8mm-evk-u-boot.dtsi | 19 +-
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 +-
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 19 +-
arch/arm/dts/imx8mq-evk-u-boot.dtsi | 4 +
arch/arm/dts/ls1021a.dtsi | 40 ++
arch/arm/include/asm/arch-imx8/imx-regs.h | 5 +-
arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 +
arch/arm/mach-imx/cmd_dek.c | 1 +
arch/arm/mach-imx/imx8/Kconfig | 7 +
arch/arm/mach-imx/imx8/cpu.c | 16 +-
arch/arm/mach-imx/imx8m/Kconfig | 18 +
arch/arm/mach-imx/imx8m/soc.c | 10 +-
arch/arm/mach-imx/mx6/Kconfig | 15 +
arch/arm/mach-imx/mx6/soc.c | 12 +-
arch/arm/mach-imx/mx7/Kconfig | 2 +
arch/arm/mach-imx/mx7/soc.c | 11 +-
arch/arm/mach-imx/mx7ulp/Kconfig | 3 +
arch/arm/mach-imx/mx7ulp/soc.c | 16 +
arch/powerpc/cpu/mpc85xx/Kconfig | 33 ++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +-
arch/powerpc/dts/p2041si-post.dtsi | 1 +
arch/powerpc/dts/p3041si-post.dtsi | 1 +
arch/powerpc/dts/p4080si-post.dtsi | 1 +
arch/powerpc/dts/p5040si-post.dtsi | 1 +
arch/powerpc/dts/qoriq-sec4.0-0.dtsi | 74 +++
arch/powerpc/dts/qoriq-sec4.2-0.dtsi | 83 +++
arch/powerpc/dts/qoriq-sec5.2-0.dtsi | 92 ++++
arch/powerpc/dts/t1023si-post.dtsi | 1 +
arch/powerpc/dts/t1042si-post.dtsi | 1 +
arch/powerpc/dts/t2080si-post.dtsi | 1 +
arch/powerpc/dts/t4240si-post.dtsi | 1 +
arch/powerpc/include/asm/u-boot-ppc.h | 17 +
arch/powerpc/include/asm/u-boot.h | 1 +
board/freescale/imx8mm_evk/spl.c | 9 +-
board/freescale/imx8mn_evk/spl.c | 8 +-
board/freescale/imx8mp_evk/spl.c | 13 +-
board/freescale/imx8mq_evk/spl.c | 9 +-
board/freescale/imx8qm_mek/spl.c | 6 +-
board/freescale/imx8qxp_mek/spl.c | 6 +-
board/freescale/ls1012afrdm/ls1012afrdm.c | 7 +-
board/freescale/ls1012aqds/ls1012aqds.c | 6 +-
board/freescale/ls1012ardb/ls1012ardb.c | 6 +-
board/freescale/ls1021aiot/ls1021aiot.c | 6 +-
board/freescale/ls1021aqds/ls1021aqds.c | 6 +-
board/freescale/ls1021atsn/ls1021atsn.c | 7 +-
board/freescale/ls1021atwr/ls1021atwr.c | 8 +-
board/freescale/ls1028a/ls1028a.c | 6 +-
board/freescale/ls1043ardb/ls1043ardb.c | 6 +-
board/freescale/ls1046afrwy/ls1046afrwy.c | 7 +-
board/freescale/ls1046aqds/ls1046aqds.c | 7 +-
board/freescale/ls1046ardb/ls1046ardb.c | 6 +-
board/freescale/ls1088a/ls1088a.c | 6 +-
board/freescale/ls2080aqds/ls2080aqds.c | 6 +-
board/freescale/ls2080ardb/ls2080ardb.c | 9 +-
board/freescale/lx2160a/lx2160a.c | 5 -
board/kontron/sl28/sl28.c | 3 -
configs/P2041RDB_defconfig | 1 -
configs/P3041DS_defconfig | 1 -
configs/P4080DS_defconfig | 1 -
configs/P5040DS_defconfig | 1 -
configs/T1024RDB_defconfig | 1 -
configs/T1042D4RDB_defconfig | 1 -
configs/T2080QDS_defconfig | 1 -
configs/T2080RDB_defconfig | 1 -
configs/T2080RDB_revD_defconfig | 1 -
configs/T4240RDB_defconfig | 1 -
configs/ls1021aiot_qspi_defconfig | 1 -
configs/ls1021aqds_nor_defconfig | 1 -
configs/ls1021aqds_qspi_defconfig | 1 -
configs/ls1021atsn_qspi_defconfig | 1 -
configs/ls1021atwr_nor_defconfig | 1 -
...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
configs/ls1028ardb_tfa_defconfig | 1 -
configs/ls1043ardb_tfa_defconfig | 1 -
configs/ls1046afrwy_tfa_defconfig | 1 -
configs/ls1046aqds_tfa_defconfig | 1 -
configs/ls1046ardb_tfa_defconfig | 1 -
configs/ls2088aqds_tfa_defconfig | 1 -
configs/ls2088ardb_tfa_defconfig | 1 -
configs/lx2160aqds_tfa_defconfig | 1 -
configs/lx2160ardb_tfa_defconfig | 1 -
configs/lx2162aqds_tfa_defconfig | 1 -
configs/mx6sabreauto_defconfig | 2 -
configs/mx6sabresd_defconfig | 4 -
drivers/crypto/fsl/Kconfig | 2 +-
drivers/crypto/fsl/jr.c | 476 +++++++++++++-----
drivers/crypto/fsl/jr.h | 31 +-
include/fsl_sec.h | 13 +-
scripts/config_whitelist.txt | 1 +
106 files changed, 1493 insertions(+), 296 deletions(-)
create mode 100644 arch/powerpc/dts/qoriq-sec4.0-0.dtsi
create mode 100644 arch/powerpc/dts/qoriq-sec4.2-0.dtsi
create mode 100644 arch/powerpc/dts/qoriq-sec5.2-0.dtsi
create mode 100644 arch/powerpc/include/asm/u-boot-ppc.h
--
2.17.1
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-02-05 14:16 ` Stefano Babic
2022-01-10 12:27 ` [PATCH v8 02/15] i.MX8M: crypto: updated device tree for supporting DM in SPL Gaurav Jain
` (13 subsequent siblings)
14 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
added device tree support for job ring driver.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++++--------------
drivers/crypto/fsl/jr.h | 31 +++-
2 files changed, 240 insertions(+), 114 deletions(-)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 22b649219e..8103987425 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
* Based on CAAM driver in drivers/crypto/caam in Linux
*/
@@ -11,7 +11,6 @@
#include <linux/kernel.h>
#include <log.h>
#include <malloc.h>
-#include "fsl_sec.h"
#include "jr.h"
#include "jobdesc.h"
#include "desc_constr.h"
@@ -21,7 +20,10 @@
#include <asm/cache.h>
#include <asm/fsl_pamu.h>
#endif
+#include <dm.h>
#include <dm/lists.h>
+#include <dm/root.h>
+#include <dm/device-internal.h>
#include <linux/delay.h>
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
@@ -35,20 +37,29 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
#endif
};
+#if CONFIG_IS_ENABLED(DM)
+struct udevice *caam_dev;
+#else
#define SEC_ADDR(idx) \
(ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
#define SEC_JR0_ADDR(idx) \
(ulong)(SEC_ADDR(idx) + \
(CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+struct caam_regs caam_st;
+#endif
-struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+static inline u32 jr_start_reg(u8 jrid)
+{
+ return (1 << jrid);
+}
-static inline void start_jr0(uint8_t sec_idx)
+static inline void start_jr(struct caam_regs *caam)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+ ccsr_sec_t *sec = caam->sec;
u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
u32 scfgr = sec_in32(&sec->scfgr);
+ u32 jrstart = jr_start_reg(caam->jrid);
if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
@@ -56,23 +67,16 @@ static inline void start_jr0(uint8_t sec_idx)
*/
if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
(scfgr & SEC_SCFGR_VIRT_EN))
- sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+ sec_out32(&sec->jrstartr, jrstart);
} else {
/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
- sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+ sec_out32(&sec->jrstartr, jrstart);
}
}
-static inline void jr_reset_liodn(uint8_t sec_idx)
+static inline void jr_disable_irq(struct jr_regs *regs)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
- sec_out32(&sec->jrliodnr[0].ls, 0);
-}
-
-static inline void jr_disable_irq(uint8_t sec_idx)
-{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
uint32_t jrcfg = sec_in32(®s->jrcfg1);
jrcfg = jrcfg | JR_INTMASK;
@@ -80,10 +84,10 @@ static inline void jr_disable_irq(uint8_t sec_idx)
sec_out32(®s->jrcfg1, jrcfg);
}
-static void jr_initregs(uint8_t sec_idx)
+static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
@@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx)
sec_out32(®s->irs, JR_SIZE);
if (!jr->irq)
- jr_disable_irq(sec_idx);
+ jr_disable_irq(regs);
}
-static int jr_init(uint8_t sec_idx)
+static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
{
- struct jobring *jr = &jr0[sec_idx];
+ struct jobring *jr = &caam->jr[sec_idx];
memset(jr, 0, sizeof(struct jobring));
- jr->jq_id = DEFAULT_JR_ID;
+ jr->jq_id = caam->jrid;
jr->irq = DEFAULT_IRQ;
#ifdef CONFIG_FSL_CORENET
@@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx)
memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
memset(jr->output_ring, 0, jr->op_size);
- start_jr0(sec_idx);
-
- jr_initregs(sec_idx);
-
- return 0;
-}
-
-static int jr_sw_cleanup(uint8_t sec_idx)
-{
- struct jobring *jr = &jr0[sec_idx];
-
- jr->head = 0;
- jr->tail = 0;
- jr->read_idx = 0;
- jr->write_idx = 0;
- memset(jr->info, 0, sizeof(jr->info));
- memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
- memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
-
- return 0;
-}
-
-static int jr_hw_reset(uint8_t sec_idx)
-{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- uint32_t timeout = 100000;
- uint32_t jrint, jrcr;
-
- sec_out32(®s->jrcr, JRCR_RESET);
- do {
- jrint = sec_in32(®s->jrint);
- } while (((jrint & JRINT_ERR_HALT_MASK) ==
- JRINT_ERR_HALT_INPROGRESS) && --timeout);
-
- jrint = sec_in32(®s->jrint);
- if (((jrint & JRINT_ERR_HALT_MASK) !=
- JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
- return -1;
-
- timeout = 100000;
- sec_out32(®s->jrcr, JRCR_RESET);
- do {
- jrcr = sec_in32(®s->jrcr);
- } while ((jrcr & JRCR_RESET) && --timeout);
-
- if (timeout == 0)
- return -1;
+ start_jr(caam);
+ jr_initregs(sec_idx, caam);
return 0;
}
@@ -188,10 +147,10 @@ static int jr_hw_reset(uint8_t sec_idx)
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
void (*callback)(uint32_t status, void *arg),
- void *arg, uint8_t sec_idx)
+ void *arg, uint8_t sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
int head = jr->head;
uint32_t desc_word;
int length = desc_len(desc_addr);
@@ -263,10 +222,10 @@ static int jr_enqueue(uint32_t *desc_addr,
return 0;
}
-static int jr_dequeue(int sec_idx)
+static int jr_dequeue(int sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
int head = jr->head;
int tail = jr->tail;
int idx, i, found;
@@ -349,14 +308,18 @@ static void desc_done(uint32_t status, void *arg)
{
struct result *x = arg;
x->status = status;
-#ifndef CONFIG_SPL_BUILD
caam_jr_strstatus(status);
-#endif
x->done = 1;
}
static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
{
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ caam = dev_get_priv(caam_dev);
+#else
+ caam = &caam_st;
+#endif
unsigned long long timeval = 0;
unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
struct result op;
@@ -364,7 +327,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
memset(&op, 0, sizeof(op));
- ret = jr_enqueue(desc, desc_done, &op, sec_idx);
+ ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
if (ret) {
debug("Error in SEC enq\n");
ret = JQ_ENQ_ERR;
@@ -375,7 +338,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
udelay(1);
timeval += 1;
- ret = jr_dequeue(sec_idx);
+ ret = jr_dequeue(sec_idx, caam);
if (ret) {
debug("Error in SEC deq\n");
ret = JQ_DEQ_ERR;
@@ -402,13 +365,62 @@ int run_descriptor_jr(uint32_t *desc)
return run_descriptor_jr_idx(desc, 0);
}
+static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam)
+{
+ struct jobring *jr = &caam->jr[sec_idx];
+
+ jr->head = 0;
+ jr->tail = 0;
+ jr->read_idx = 0;
+ jr->write_idx = 0;
+ memset(jr->info, 0, sizeof(jr->info));
+ memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
+ memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
+
+ return 0;
+}
+
+static int jr_hw_reset(struct jr_regs *regs)
+{
+ uint32_t timeout = 100000;
+ uint32_t jrint, jrcr;
+
+ sec_out32(®s->jrcr, JRCR_RESET);
+ do {
+ jrint = sec_in32(®s->jrint);
+ } while (((jrint & JRINT_ERR_HALT_MASK) ==
+ JRINT_ERR_HALT_INPROGRESS) && --timeout);
+
+ jrint = sec_in32(®s->jrint);
+ if (((jrint & JRINT_ERR_HALT_MASK) !=
+ JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
+ return -1;
+
+ timeout = 100000;
+ sec_out32(®s->jrcr, JRCR_RESET);
+ do {
+ jrcr = sec_in32(®s->jrcr);
+ } while ((jrcr & JRCR_RESET) && --timeout);
+
+ if (timeout == 0)
+ return -1;
+
+ return 0;
+}
+
static inline int jr_reset_sec(uint8_t sec_idx)
{
- if (jr_hw_reset(sec_idx) < 0)
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ caam = dev_get_priv(caam_dev);
+#else
+ caam = &caam_st;
+#endif
+ if (jr_hw_reset(caam->regs) < 0)
return -1;
/* Clean up the jobring structure maintained by software */
- jr_sw_cleanup(sec_idx);
+ jr_sw_cleanup(sec_idx, caam);
return 0;
}
@@ -418,9 +430,15 @@ int jr_reset(void)
return jr_reset_sec(0);
}
-static inline int sec_reset_idx(uint8_t sec_idx)
+int sec_reset(void)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ caam = dev_get_priv(caam_dev);
+#else
+ caam = &caam_st;
+#endif
+ ccsr_sec_t *sec = caam->sec;
uint32_t mcfgr = sec_in32(&sec->mcfgr);
uint32_t timeout = 100000;
@@ -446,11 +464,7 @@ static inline int sec_reset_idx(uint8_t sec_idx)
return 0;
}
-int sec_reset(void)
-{
- return sec_reset_idx(0);
-}
-#ifndef CONFIG_SPL_BUILD
+
static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
{
u32 *desc;
@@ -496,12 +510,11 @@ static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
return ret;
}
-static int instantiate_rng(u8 sec_idx, int gen_sk)
+static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int gen_sk)
{
u32 *desc;
u32 rdsta_val;
int ret = 0, sh_idx, size;
- ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
@@ -554,9 +567,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk)
return ret;
}
-static u8 get_rng_vid(uint8_t sec_idx)
+static u8 get_rng_vid(ccsr_sec_t *sec)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
u8 vid;
if (caam_get_era() < 10) {
@@ -574,9 +586,8 @@ static u8 get_rng_vid(uint8_t sec_idx)
* By default, the TRNG runs for 200 clocks per sample;
* 1200 clocks per sample generates better entropy.
*/
-static void kick_trng(int ent_delay, uint8_t sec_idx)
+static void kick_trng(int ent_delay, ccsr_sec_t *sec)
{
- ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
u32 val;
@@ -603,10 +614,9 @@ static void kick_trng(int ent_delay, uint8_t sec_idx)
sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
}
-static int rng_init(uint8_t sec_idx)
+static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
{
int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
- ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
u32 inst_handles;
@@ -624,7 +634,7 @@ static int rng_init(uint8_t sec_idx)
* the TRNG parameters.
*/
if (!inst_handles) {
- kick_trng(ent_delay, sec_idx);
+ kick_trng(ent_delay, sec);
ent_delay += 400;
}
/*
@@ -634,7 +644,7 @@ static int rng_init(uint8_t sec_idx)
* interval, leading to a sucessful initialization of
* the RNG.
*/
- ret = instantiate_rng(sec_idx, gen_sk);
+ ret = instantiate_rng(sec_idx, sec, gen_sk);
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
if (ret) {
printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
@@ -646,13 +656,28 @@ static int rng_init(uint8_t sec_idx)
return ret;
}
-#endif
+
int sec_init_idx(uint8_t sec_idx)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
- uint32_t mcr = sec_in32(&sec->mcfgr);
int ret = 0;
-
+ struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+ if (!caam_dev) {
+ printf("caam_jr: caam not found\n");
+ return -1;
+ }
+ caam = dev_get_priv(caam_dev);
+#else
+ caam_st.sec = (void *)SEC_ADDR(sec_idx);
+ caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+ caam_st.jrid = 0;
+ caam = &caam_st;
+#endif
+ ccsr_sec_t *sec = caam->sec;
+ uint32_t mcr = sec_in32(&sec->mcfgr);
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
+ uint32_t jrdid_ms = 0;
+#endif
#ifdef CONFIG_FSL_CORENET
uint32_t liodnr;
uint32_t liodn_ns;
@@ -682,6 +707,11 @@ int sec_init_idx(uint8_t sec_idx)
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
sec_out32(&sec->mcfgr, mcr);
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
+ jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID;
+ sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms);
+#endif
+ jr_reset();
#ifdef CONFIG_FSL_CORENET
#ifdef CONFIG_SPL_BUILD
@@ -693,20 +723,19 @@ int sec_init_idx(uint8_t sec_idx)
liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
- liodnr = sec_in32(&sec->jrliodnr[0].ls) &
+ liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
~(JRNSLIODN_MASK | JRSLIODN_MASK);
liodnr = liodnr |
(liodn_ns << JRNSLIODN_SHIFT) |
(liodn_s << JRSLIODN_SHIFT);
- sec_out32(&sec->jrliodnr[0].ls, liodnr);
+ sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
#else
- liodnr = sec_in32(&sec->jrliodnr[0].ls);
+ liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
#endif
#endif
-
- ret = jr_init(sec_idx);
+ ret = jr_init(sec_idx, caam);
if (ret < 0) {
printf("SEC%u: initialization failed\n", sec_idx);
return -1;
@@ -719,9 +748,9 @@ int sec_init_idx(uint8_t sec_idx)
pamu_enable();
#endif
-#ifndef CONFIG_SPL_BUILD
- if (get_rng_vid(sec_idx) >= 4) {
- if (rng_init(sec_idx) < 0) {
+
+ if (get_rng_vid(caam->sec) >= 4) {
+ if (rng_init(sec_idx, caam->sec) < 0) {
printf("SEC%u: RNG instantiation failed\n", sec_idx);
return -1;
}
@@ -735,7 +764,6 @@ int sec_init_idx(uint8_t sec_idx)
printf("SEC%u: RNG instantiated\n", sec_idx);
}
-#endif
return ret;
}
@@ -743,3 +771,76 @@ int sec_init(void)
{
return sec_init_idx(0);
}
+
+#if CONFIG_IS_ENABLED(DM)
+static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf)
+{
+ if (request != CAAM_JR_RUN_DESC)
+ return -ENOSYS;
+
+ return run_descriptor_jr(buf);
+}
+
+static int caam_jr_probe(struct udevice *dev)
+{
+ struct caam_regs *caam = dev_get_priv(dev);
+ fdt_addr_t addr;
+ ofnode node;
+ unsigned int jr_node = 0;
+
+ caam_dev = dev;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE) {
+ printf("caam_jr: crypto not found\n");
+ return -EINVAL;
+ }
+ caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
+ caam->regs = (struct jr_regs *)caam->sec;
+
+ /* Check for enabled job ring node */
+ ofnode_for_each_subnode(node, dev_ofnode(dev)) {
+ if (!ofnode_is_available(node))
+ continue;
+
+ jr_node = ofnode_read_u32_default(node, "reg", -1);
+ if (jr_node > 0) {
+ caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
+ while (!(jr_node & 0x0F))
+ jr_node = jr_node >> 4;
+
+ caam->jrid = jr_node - 1;
+ break;
+ }
+ }
+
+ if (sec_init())
+ printf("\nsec_init failed!\n");
+
+ return 0;
+}
+
+static int caam_jr_bind(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct misc_ops caam_jr_ops = {
+ .ioctl = caam_jr_ioctl,
+};
+
+static const struct udevice_id caam_jr_match[] = {
+ { .compatible = "fsl,sec-v4.0" },
+ { }
+};
+
+U_BOOT_DRIVER(caam_jr) = {
+ .name = "caam_jr",
+ .id = UCLASS_MISC,
+ .of_match = caam_jr_match,
+ .ops = &caam_jr_ops,
+ .bind = caam_jr_bind,
+ .probe = caam_jr_probe,
+ .priv_auto = sizeof(struct caam_regs),
+};
+#endif
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 1047aa772c..3eb7be79da 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*
*/
@@ -8,7 +9,9 @@
#define __JR_H
#include <linux/compiler.h>
+#include "fsl_sec.h"
#include "type.h"
+#include <misc.h>
#define JR_SIZE 4
/* Timeout currently defined as 10 sec */
@@ -35,12 +38,21 @@
#define JRSLIODN_SHIFT 0
#define JRSLIODN_MASK 0x00000fff
-#define JQ_DEQ_ERR -1
-#define JQ_DEQ_TO_ERR -2
-#define JQ_ENQ_ERR -3
+#define JRDID_MS_PRIM_DID BIT(0)
+#define JRDID_MS_PRIM_TZ BIT(4)
+#define JRDID_MS_TZ_OWN BIT(15)
+
+#define JQ_DEQ_ERR (-1)
+#define JQ_DEQ_TO_ERR (-2)
+#define JQ_ENQ_ERR (-3)
#define RNG4_MAX_HANDLES 2
+enum {
+ /* Run caam jobring descriptor(in buf) */
+ CAAM_JR_RUN_DESC,
+};
+
struct op_ring {
caam_dma_addr_t desc;
uint32_t status;
@@ -102,6 +114,19 @@ struct result {
uint32_t status;
};
+/*
+ * struct caam_regs - CAAM initialization register interface
+ *
+ * Interface to caam memory map, jobring register, jobring storage.
+ */
+struct caam_regs {
+ ccsr_sec_t *sec; /*caam initialization registers*/
+ struct jr_regs *regs; /*jobring configuration registers*/
+ u8 jrid; /*id to identify a jobring*/
+ /*Private sub-storage for a single JobR*/
+ struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+};
+
void caam_jr_strstatus(u32 status);
int run_descriptor_jr(uint32_t *desc);
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 02/15] i.MX8M: crypto: updated device tree for supporting DM in SPL
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 03/15] crypto/fsl: i.MX8M: Enable Job ring driver model Gaurav Jain
` (12 subsequent siblings)
14 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
disabled use of JR0 in SPL and uboot, as JR0 is reserved
for secure boot.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/dts/imx8mm-evk-u-boot.dtsi | 19 ++++++++++++++++++-
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 ++++++++++++++++++-
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 19 ++++++++++++++++++-
arch/arm/dts/imx8mq-evk-u-boot.dtsi | 4 ++++
4 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 6b459831e7..e5682ca165 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include "imx8mm-u-boot.dtsi"
@@ -68,6 +68,23 @@
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+ status = "disabled";
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 1d3844437d..d8df863083 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
/ {
@@ -104,6 +104,23 @@
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+ status = "disabled";
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index ab849ebaac..f3f83ba303 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include "imx8mp-u-boot.dtsi"
@@ -67,6 +67,23 @@
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+ status = "disabled";
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&i2c1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
index 6f9c81462e..8f1f942215 100644
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@@ -10,3 +10,7 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&sec_jr0 {
+ status = "disabled";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 03/15] crypto/fsl: i.MX8M: Enable Job ring driver model.
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 02/15] i.MX8M: crypto: updated device tree for supporting DM in SPL Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 04/15] mx6sabre: Remove unnecessary SPL configs Gaurav Jain
` (11 subsequent siblings)
14 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
i.MX8MM/MN/MP/MQ - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 +
arch/arm/mach-imx/imx8m/Kconfig | 18 ++++++++++++++++++
arch/arm/mach-imx/imx8m/soc.c | 10 +++++++++-
board/freescale/imx8mm_evk/spl.c | 9 ++++++++-
board/freescale/imx8mn_evk/spl.c | 8 ++++++--
board/freescale/imx8mp_evk/spl.c | 13 +++++++++++--
board/freescale/imx8mq_evk/spl.c | 9 +++++++--
drivers/crypto/fsl/jr.c | 14 +++++++++++---
scripts/config_whitelist.txt | 1 +
10 files changed, 73 insertions(+), 12 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f7f03837fe..550f884077 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -815,7 +815,7 @@ config ARCH_IMX8M
select ARM64
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select SYS_I2C_MXC
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index b800da13a1..ff8de53f67 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -72,6 +72,7 @@
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
+#define CONFIG_SYS_FSL_JR1_OFFSET (0x2000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index d6a869068a..95506afd17 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -39,6 +39,10 @@ config TARGET_IMX8MQ_EVK
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
@@ -52,6 +56,10 @@ config TARGET_IMX8MM_EVK
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MM_ICORE_MX8MM
bool "Engicam i.Core MX8M Mini SOM"
@@ -91,6 +99,9 @@ config TARGET_IMX8MN_EVK
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select MISC
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
@@ -98,6 +109,9 @@ config TARGET_IMX8MN_DDR4_EVK
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
+ select FSL_CAAM
+ select MISC
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board"
@@ -105,6 +119,10 @@ config TARGET_IMX8MP_EVK
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 863508776d..0f9bd77354 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2019, 2021 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
@@ -20,6 +20,7 @@
#include <asm/ptrace.h>
#include <asm/armv8/mmu.h>
#include <dm/uclass.h>
+#include <dm/device.h>
#include <efi_loader.h>
#include <env.h>
#include <env_internal.h>
@@ -1197,6 +1198,13 @@ static void acquire_buildinfo(void)
int arch_misc_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
acquire_buildinfo();
return 0;
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 4ef7f6f180..c81128f442 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -51,6 +51,13 @@ static void spl_dram_init(void)
void spl_board_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
puts("Normal Boot\n");
}
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index 03f2a56e80..ab19dabf7b 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -49,6 +49,10 @@ void spl_board_init(void)
struct udevice *dev;
int ret;
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
puts("Normal Boot\n");
ret = uclass_get_device_by_name(UCLASS_CLK,
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index eca42c756e..bcef96caa3 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -20,6 +20,8 @@
#include <asm/arch/ddr.h>
#include <power/pmic.h>
#include <power/pca9450.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -35,6 +37,13 @@ void spl_dram_init(void)
void spl_board_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
/*
* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
* not allow to change it. Should set the clock after PMIC
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index 67d069b2b0..8a47dd01a5 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -1,8 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -22,6 +21,7 @@
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc_imx.h>
+#include <fsl_sec.h>
#include <mmc.h>
#include <linux/delay.h>
#include <power/pmic.h>
@@ -199,6 +199,11 @@ int power_init_board(void)
void spl_board_init(void)
{
+#ifdef CONFIG_FSL_CAAM
+ if (sec_init())
+ printf("\nsec_init failed!\n");
+
+#endif
puts("Normal Boot\n");
}
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 8103987425..4e7accfb89 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -43,9 +43,17 @@ struct udevice *caam_dev;
#define SEC_ADDR(idx) \
(ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
-#define SEC_JR0_ADDR(idx) \
+#ifndef CONFIG_IMX8M
+#define SEC_JR_ADDR(idx) \
(ulong)(SEC_ADDR(idx) + \
(CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+#define JR_ID 0
+#else
+#define SEC_JR_ADDR(idx) \
+ (ulong)(SEC_ADDR(idx) + \
+ (CONFIG_SYS_FSL_JR1_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+#define JR_ID 1
+#endif
struct caam_regs caam_st;
#endif
@@ -669,8 +677,8 @@ int sec_init_idx(uint8_t sec_idx)
caam = dev_get_priv(caam_dev);
#else
caam_st.sec = (void *)SEC_ADDR(sec_idx);
- caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- caam_st.jrid = 0;
+ caam_st.regs = (struct jr_regs *)SEC_JR_ADDR(sec_idx);
+ caam_st.jrid = JR_ID;
caam = &caam_st;
#endif
ccsr_sec_t *sec = caam->sec;
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index b9c1c61e13..81de1a3793 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -1848,6 +1848,7 @@ CONFIG_SYS_FSL_IFC_SIZE2
CONFIG_SYS_FSL_ISBC_VER
CONFIG_SYS_FSL_JR0_ADDR
CONFIG_SYS_FSL_JR0_OFFSET
+CONFIG_SYS_FSL_JR1_OFFSET
CONFIG_SYS_FSL_LS1_CLK_ADDR
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
CONFIG_SYS_FSL_MAX_NUM_OF_SEC
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 04/15] mx6sabre: Remove unnecessary SPL configs
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
` (2 preceding siblings ...)
2022-01-10 12:27 ` [PATCH v8 03/15] crypto/fsl: i.MX8M: Enable Job ring driver model Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 05/15] i.MX6: Enable Job ring driver model Gaurav Jain
` (10 subsequent siblings)
14 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean
From: Ye Li <ye.li@nxp.com>
Because we don't use SPL_DM on mx6sabresd and mx6sabreauto, so it is
unnecessary to have SPL DTB related configs and SPL_OF_CONTROL enabled.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
---
configs/mx6sabreauto_defconfig | 2 --
configs/mx6sabresd_defconfig | 4 ----
2 files changed, 6 deletions(-)
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index c5cdc3ac17..2b8b4f6b9f 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -60,10 +60,8 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6dl-sabreauto imx6q-sabreauto imx6qp-sabreauto"
CONFIG_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 6733038060..f40401d279 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -63,12 +63,8 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6q-sabresd imx6qp-sabresd imx6dl-sabresd"
CONFIG_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd"
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 05/15] i.MX6: Enable Job ring driver model.
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
` (3 preceding siblings ...)
2022-01-10 12:27 ` [PATCH v8 04/15] mx6sabre: Remove unnecessary SPL configs Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 06/15] i.MX7: " Gaurav Jain
` (9 subsequent siblings)
14 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
i.MX6,i.MX6SX,i.MX6UL - added support for JR driver model.
removed sec_init() call, sec is initialized based on
job ring information processed from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/mach-imx/mx6/Kconfig | 15 +++++++++++++++
arch/arm/mach-imx/mx6/soc.c | 12 ++++++++----
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 98df4d4e42..05d3fab6cb 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -354,6 +354,9 @@ config TARGET_MX6SABREAUTO
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_MX6SABRESD
bool "mx6sabresd"
@@ -364,6 +367,9 @@ config TARGET_MX6SABRESD
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_MX6SLEVK
bool "mx6slevk"
@@ -386,6 +392,9 @@ config TARGET_MX6SXSABRESD
select DM
select DM_THERMAL
select SUPPORT_SPL
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_MX6SXSABREAUTO
bool "mx6sxsabreauto"
@@ -404,6 +413,9 @@ config TARGET_MX6UL_9X9_EVK
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_MX6UL_14X14_EVK
bool "mx6ul_14x14_evk"
@@ -413,6 +425,9 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_MX6UL_ENGICAM
bool "Support Engicam GEAM6UL/Is.IoT"
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index aacfc854a2..fa6c3778bb 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -4,6 +4,7 @@
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -23,7 +24,6 @@
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
-#include <fsl_sec.h>
#include <imx_thermal.h>
#include <mmc.h>
@@ -734,9 +734,13 @@ static void setup_serial_number(void)
int arch_misc_init(void)
{
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
setup_serial_number();
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 06/15] i.MX7: Enable Job ring driver model.
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
` (4 preceding siblings ...)
2022-01-10 12:27 ` [PATCH v8 05/15] i.MX6: Enable Job ring driver model Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 07/15] i.MX7ULP: " Gaurav Jain
` (8 subsequent siblings)
14 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
i.MX7D - added support for JR driver model.
removed sec_init() call, sec is initialized based on
job ring information processed from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-imx/mx7/Kconfig | 2 ++
arch/arm/mach-imx/mx7/soc.c | 11 +++++++----
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 550f884077..516e1b5a8f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -883,7 +883,7 @@ config ARCH_MX7
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
imply BOARD_EARLY_INIT_F
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 0cad825287..b2d532dacd 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -68,6 +68,8 @@ config TARGET_MX7DSABRESD
select DM_THERMAL
select MX7D
imply CMD_DM
+ select FSL_CAAM
+ select MISC
config TARGET_PICO_IMX7D
bool "pico-imx7d"
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 21690072e1..6c991a6cb1 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -19,7 +20,6 @@
#include <dm.h>
#include <env.h>
#include <imx_thermal.h>
-#include <fsl_sec.h>
#include <asm/setup.h>
#include <linux/delay.h>
@@ -337,6 +337,9 @@ int arch_cpu_init(void)
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
+ struct udevice *dev;
+ int ret;
+
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
struct tag_serialnr serialnr;
char serial_string[0x20];
@@ -353,9 +356,9 @@ int arch_misc_init(void)
env_set("serial#", serial_string);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 07/15] i.MX7ULP: Enable Job ring driver model.
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
` (5 preceding siblings ...)
2022-01-10 12:27 ` [PATCH v8 06/15] i.MX7: " Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 08/15] i.MX8: Add crypto node in device tree Gaurav Jain
` (7 subsequent siblings)
14 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
added crypto node in device tree.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/dts/imx7ulp.dtsi | 24 ++++++++++++++++++++++++
arch/arm/mach-imx/mx7ulp/Kconfig | 3 +++
arch/arm/mach-imx/mx7ulp/soc.c | 16 ++++++++++++++++
4 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 516e1b5a8f..524a2204eb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -870,7 +870,7 @@ config ARCH_MX7ULP
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select ROM_UNIFIED_SECTIONS
diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi
index 7bcd2cc346..494b9d98b2 100644
--- a/arch/arm/dts/imx7ulp.dtsi
+++ b/arch/arm/dts/imx7ulp.dtsi
@@ -1,5 +1,6 @@
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -198,6 +199,29 @@
};
};
+ crypto: crypto@40240000 {
+ compatible = "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40240000 0x10000>;
+ ranges = <0 0x40240000 0x10000>;
+ clocks = <&clks IMX7ULP_CLK_CAAM>,
+ <&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
+ clock-names = "aclk", "ipg";
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
tpm5: tpm@40260000 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x40260000 0x1000>;
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index 2ffac9cf7c..fbd2de5e3d 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -25,6 +25,9 @@ config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
select MX7ULP
select SYS_ARCH_TIMER
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
endchoice
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index c90ce22404..c1e55e7260 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -15,6 +16,7 @@
#include <asm/mach-imx/hab.h>
#include <asm/setup.h>
#include <linux/bitops.h>
+#include <dm.h>
#define PMC0_BASE_ADDR 0x410a1000
#define PMC0_CTRL 0x28
@@ -80,6 +82,20 @@ int arch_cpu_init(void)
return 0;
}
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 08/15] i.MX8: Add crypto node in device tree
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
` (6 preceding siblings ...)
2022-01-10 12:27 ` [PATCH v8 07/15] i.MX7ULP: " Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 09/15] crypto/fsl: i.MX8: Enable Job ring driver model Gaurav Jain
` (6 subsequent siblings)
14 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
i.MX8(QM/QXP) - updated device tree for supporting DM in SPL.
disabled use of JR1 in SPL and uboot, as JR1 is reserved
for SECO FW.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/dts/fsl-imx8dx.dtsi | 61 +++++++++++++++++++++++-
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 34 ++++++++++++-
arch/arm/dts/fsl-imx8qm.dtsi | 61 +++++++++++++++++++++++-
arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 34 ++++++++++++-
4 files changed, 186 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
index 7d95cf0b7d..63a56699b5 100644
--- a/arch/arm/dts/fsl-imx8dx.dtsi
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -261,6 +261,30 @@
power-domains = <&pd_dma>;
};
};
+
+ pd_caam: PD_CAAM {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_NONE>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_caam_jr1: PD_CAAM_JR1 {
+ reg = <SC_R_CAAM_JR1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr2: PD_CAAM_JR2 {
+ reg = <SC_R_CAAM_JR2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr3: PD_CAAM_JR3 {
+ reg = <SC_R_CAAM_JR3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ };
};
i2c0: i2c@5a800000 {
@@ -609,6 +633,41 @@
};
};
};
+
+ crypto: caam@0x31400000 {
+ compatible = "fsl,sec-v4.0";
+ reg = <0 0x31400000 0 0x400000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x31400000 0x400000>;
+ fsl,first-jr-index = <2>;
+ fsl,sec-era = <9>;
+
+ sec_jr1: jr1@0x20000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x1000>;
+ interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr1>;
+ status = "disabled";
+ };
+
+ sec_jr2: jr2@30000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x1000>;
+ interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr2>;
+ status = "okay";
+ };
+
+ sec_jr3: jr3@40000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x1000>;
+ interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr3>;
+ status = "okay";
+ };
+ };
};
&A35_0 {
diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
index 9e0d264b71..a95209e141 100644
--- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
&{/imx8qm-pm} {
@@ -80,6 +80,22 @@
u-boot,dm-spl;
};
+&pd_caam {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+ u-boot,dm-spl;
+};
+
&gpio0 {
u-boot,dm-spl;
};
@@ -126,3 +142,19 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&sec_jr3 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
index 88aeaf65b3..517fb13cad 100644
--- a/arch/arm/dts/fsl-imx8qm.dtsi
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -235,6 +235,30 @@
wakeup-irq = <349>;
};
};
+
+ pd_caam: PD_CAAM {
+ compatible = "nxp,imx8-pd";
+ reg = <SC_R_NONE>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_caam_jr1: PD_CAAM_JR1 {
+ reg = <SC_R_CAAM_JR1>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr2: PD_CAAM_JR2 {
+ reg = <SC_R_CAAM_JR2>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr3: PD_CAAM_JR3 {
+ reg = <SC_R_CAAM_JR3>;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ };
};
i2c0: i2c@5a800000 {
@@ -556,6 +580,41 @@
power-domains = <&pd_conn_enet1>;
status = "disabled";
};
+
+ crypto: caam@0x31400000 {
+ compatible = "fsl,sec-v4.0";
+ reg = <0 0x31400000 0 0x400000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x31400000 0x400000>;
+ fsl,first-jr-index = <2>;
+ fsl,sec-era = <9>;
+
+ sec_jr1: jr1@0x20000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x1000>;
+ interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr1>;
+ status = "disabled";
+ };
+
+ sec_jr2: jr2@30000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x1000>;
+ interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr2>;
+ status = "okay";
+ };
+
+ sec_jr3: jr3@40000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x1000>;
+ interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd_caam_jr3>;
+ status = "okay";
+ };
+ };
};
&A53_0 {
diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
index 701af4434d..ae037c7550 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
&{/imx8qx-pm} {
@@ -80,6 +80,22 @@
u-boot,dm-spl;
};
+&pd_caam {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+ u-boot,dm-spl;
+};
+
&gpio0 {
u-boot,dm-spl;
};
@@ -126,3 +142,19 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&sec_jr3 {
+ u-boot,dm-spl;
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 09/15] crypto/fsl: i.MX8: Enable Job ring driver model.
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
` (7 preceding siblings ...)
2022-01-10 12:27 ` [PATCH v8 08/15] i.MX8: Add crypto node in device tree Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in kernel Gaurav Jain
` (5 subsequent siblings)
14 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
i.MX8(QM/QXP) - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
arch/arm/Kconfig | 3 ++
arch/arm/include/asm/arch-imx8/imx-regs.h | 5 ++-
arch/arm/mach-imx/cmd_dek.c | 1 +
arch/arm/mach-imx/imx8/Kconfig | 7 ++++
arch/arm/mach-imx/imx8/cpu.c | 16 +++++++-
board/freescale/imx8qm_mek/spl.c | 6 ++-
board/freescale/imx8qxp_mek/spl.c | 6 ++-
drivers/crypto/fsl/Kconfig | 2 +-
drivers/crypto/fsl/jr.c | 47 ++++++++++++++++++++++-
include/fsl_sec.h | 12 +++---
10 files changed, 89 insertions(+), 16 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 524a2204eb..7ce2bbc954 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -804,6 +804,9 @@ config ARCH_LPC32XX
config ARCH_IMX8
bool "NXP i.MX8 platform"
select ARM64
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
select DM
select GPIO_EXTRA_HEADER
select MACH_IMX
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index ed6e05e556..2d64b0604b 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#ifndef __ASM_ARCH_IMX8_REGS_H__
@@ -47,4 +47,7 @@
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
+#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 89da89c51d..04c4b20a84 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -9,6 +9,7 @@
#include <command.h>
#include <log.h>
#include <malloc.h>
+#include <memalign.h>
#include <asm/byteorder.h>
#include <linux/compiler.h>
#include <fsl_sec.h>
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index b43739e5c6..f969833bab 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -8,6 +8,7 @@ config AHAB_BOOT
config IMX8
bool
+ select HAS_CAAM
config MU_BASE_SPL
hex "MU base address used in SPL"
@@ -72,6 +73,9 @@ config TARGET_IMX8QM_MEK
bool "Support i.MX8QM MEK board"
select BOARD_LATE_INIT
select IMX8QM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_CONGA_QMX8
bool "Support congatec conga-QMX8 board"
@@ -89,6 +93,9 @@ config TARGET_IMX8QXP_MEK
bool "Support i.MX8QXP MEK board"
select BOARD_LATE_INIT
select IMX8QXP
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
endchoice
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index ee5cc47903..5140c93a37 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include <common.h>
@@ -89,6 +89,20 @@ int arch_cpu_init_dm(void)
return 0;
}
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
+ return 0;
+}
+#endif
+
int print_bootinfo(void)
{
enum boot_device bt_dev = get_boot_device();
diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c
index 944ba745c0..332a662dee 100644
--- a/board/freescale/imx8qm_mek/spl.c
+++ b/board/freescale/imx8qm_mek/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -24,6 +24,8 @@ void spl_board_init(void)
{
struct udevice *dev;
+ uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c
index ae6b64ff6e..2fa6840056 100644
--- a/board/freescale/imx8qxp_mek/spl.c
+++ b/board/freescale/imx8qxp_mek/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
@@ -39,6 +39,8 @@ void spl_board_init(void)
{
struct udevice *dev;
+ uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 94ff540111..82f929c294 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -11,7 +11,7 @@ config FSL_CAAM
config CAAM_64BIT
bool
- default y if PHYS_64BIT && !ARCH_IMX8M
+ default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8
help
Select Crypto driver for 64 bits CAAM version
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 4e7accfb89..a84440ab10 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -11,6 +11,7 @@
#include <linux/kernel.h>
#include <log.h>
#include <malloc.h>
+#include <power-domain.h>
#include "jr.h"
#include "jobdesc.h"
#include "desc_constr.h"
@@ -121,7 +122,9 @@ static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
{
struct jobring *jr = &caam->jr[sec_idx];
-
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+#endif
memset(jr, 0, sizeof(struct jobring));
jr->jq_id = caam->jrid;
@@ -146,7 +149,11 @@ static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
memset(jr->output_ring, 0, jr->op_size);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ if (!ofnode_valid(scu_node))
+#endif
start_jr(caam);
+
jr_initregs(sec_idx, caam);
return 0;
@@ -681,6 +688,13 @@ int sec_init_idx(uint8_t sec_idx)
caam_st.jrid = JR_ID;
caam = &caam_st;
#endif
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+
+ if (ofnode_valid(scu_node))
+ goto init;
+#endif
+
ccsr_sec_t *sec = caam->sec;
uint32_t mcr = sec_in32(&sec->mcfgr);
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
@@ -742,12 +756,19 @@ int sec_init_idx(uint8_t sec_idx)
liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
#endif
+#endif
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+init:
#endif
ret = jr_init(sec_idx, caam);
if (ret < 0) {
printf("SEC%u: initialization failed\n", sec_idx);
return -1;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ if (ofnode_valid(scu_node))
+ return ret;
+#endif
#ifdef CONFIG_FSL_CORENET
ret = sec_config_pamu_table(liodn_ns, liodn_s);
@@ -781,6 +802,23 @@ int sec_init(void)
}
#if CONFIG_IS_ENABLED(DM)
+static int jr_power_on(ofnode node)
+{
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+ struct udevice __maybe_unused jr_dev;
+ struct power_domain pd;
+
+ dev_set_ofnode(&jr_dev, node);
+
+ /* Power on Job Ring before access it */
+ if (!power_domain_get(&jr_dev, &pd)) {
+ if (power_domain_on(&pd))
+ return -EINVAL;
+ }
+#endif
+ return 0;
+}
+
static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf)
{
if (request != CAAM_JR_RUN_DESC)
@@ -793,7 +831,7 @@ static int caam_jr_probe(struct udevice *dev)
{
struct caam_regs *caam = dev_get_priv(dev);
fdt_addr_t addr;
- ofnode node;
+ ofnode node, scu_node;
unsigned int jr_node = 0;
caam_dev = dev;
@@ -818,6 +856,11 @@ static int caam_jr_probe(struct udevice *dev)
jr_node = jr_node >> 4;
caam->jrid = jr_node - 1;
+ scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+ if (ofnode_valid(scu_node)) {
+ if (jr_power_on(node))
+ return -EINVAL;
+ }
break;
}
}
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index c4121696f8..7b6e3e2c20 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -3,7 +3,7 @@
* Common internal memory map for some Freescale SoCs
*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#ifndef __FSL_SEC_H
@@ -194,12 +194,10 @@ typedef struct ccsr_sec {
#define SEC_CHAVID_LS_RNG_SHIFT 16
#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
-#define CONFIG_JRSTARTR_JR0 0x00000001
-
struct jr_regs {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
u32 irba_l;
u32 irba_h;
#else
@@ -214,7 +212,7 @@ struct jr_regs {
u32 irja;
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
u32 orba_l;
u32 orba_h;
#else
@@ -248,7 +246,7 @@ struct jr_regs {
struct sg_entry {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8))
uint32_t addr_lo; /* Memory Address - lo */
uint32_t addr_hi; /* Memory Address of start of buffer - hi */
#else
@@ -268,7 +266,7 @@ struct sg_entry {
};
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
- defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)
+ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
/* Job Ring Base Address */
#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
/* Secure Memory Offset varies accross versions */
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in kernel
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
` (8 preceding siblings ...)
2022-01-10 12:27 ` [PATCH v8 09/15] crypto/fsl: i.MX8: Enable Job ring driver model Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 14:01 ` ZHIZHIKIN Andrey
2022-01-10 12:27 ` [PATCH v8 11/15] Layerscape: Add crypto node in device tree Gaurav Jain
` (4 subsequent siblings)
14 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean
From: Ye Li <ye.li@nxp.com>
RNG parameters are reconfigured.
- For TRNG to generate 256 bits of entropy, RNG TRNG Seed Control register
is configured to have reduced SAMP_SIZE from default 2500 to 512. it is
number of entropy samples that will be taken during Entropy generation.
- self-test registers(Monobit Limit, Poker Range, Run Length Limit)
are synchronized with new RTSDCTL[SAMP_SIZE] of 512.
TRNG time is caluculated based on sample size.
time required to generate entropy is reduced and
hwrng performance improved from 0.3 kB/s to 1.3 kB/s.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Gaurav Jain <gaurav.jain@nxp.com>>
---
drivers/crypto/fsl/jr.c | 102 +++++++++++++++++++++++++++++++++-------
include/fsl_sec.h | 1 +
2 files changed, 87 insertions(+), 16 deletions(-)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index a84440ab10..e5346a84a4 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -603,30 +603,100 @@ static u8 get_rng_vid(ccsr_sec_t *sec)
*/
static void kick_trng(int ent_delay, ccsr_sec_t *sec)
{
+ u32 samples = 512; /* number of bits to generate and test */
+ u32 mono_min = 195;
+ u32 mono_max = 317;
+ u32 mono_range = mono_max - mono_min;
+ u32 poker_min = 1031;
+ u32 poker_max = 1600;
+ u32 poker_range = poker_max - poker_min + 1;
+ u32 retries = 2;
+ u32 lrun_max = 32;
+ s32 run_1_min = 27;
+ s32 run_1_max = 107;
+ s32 run_1_range = run_1_max - run_1_min;
+ s32 run_2_min = 7;
+ s32 run_2_max = 62;
+ s32 run_2_range = run_2_max - run_2_min;
+ s32 run_3_min = 0;
+ s32 run_3_max = 39;
+ s32 run_3_range = run_3_max - run_3_min;
+ s32 run_4_min = -1;
+ s32 run_4_max = 26;
+ s32 run_4_range = run_4_max - run_4_min;
+ s32 run_5_min = -1;
+ s32 run_5_max = 18;
+ s32 run_5_range = run_5_max - run_5_min;
+ s32 run_6_min = -1;
+ s32 run_6_max = 17;
+ s32 run_6_range = run_6_max - run_6_min;
+ u32 val;
+
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
- u32 val;
- /* put RNG4 into program mode */
- sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
- /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
- * length (in system clocks) of each Entropy sample taken
- * */
+ /* Put RNG in program mode */
+ /* Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
+ * properly invalidate the entropy in the entropy register and
+ * force re-generation.
+ */
+ sec_setbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
+
+ /* Configure the RNG Entropy Delay
+ * Performance-wise, it does not make sense to
+ * set the delay to a value that is lower
+ * than the last one that worked (i.e. the state handles
+ * were instantiated properly. Thus, instead of wasting
+ * time trying to set the values controlling the sample
+ * frequency, the function simply returns.
+ */
val = sec_in32(&rng->rtsdctl);
- val = (val & ~RTSDCTL_ENT_DLY_MASK) |
- (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
+ val &= RTSDCTL_ENT_DLY_MASK;
+ val >>= RTSDCTL_ENT_DLY_SHIFT;
+ if (ent_delay < val) {
+ /* Put RNG4 into run mode */
+ sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
+ return;
+ }
+
+ val = (ent_delay << RTSDCTL_ENT_DLY_SHIFT) | samples;
sec_out32(&rng->rtsdctl, val);
- /* min. freq. count, equal to 1/4 of the entropy sample length */
- sec_out32(&rng->rtfreqmin, ent_delay >> 2);
- /* disable maximum frequency count */
- sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
+
+ /*
+ * Recommended margins (min,max) for freq. count:
+ * freq_mul = RO_freq / TRNG_clk_freq
+ * rtfrqmin = (ent_delay x freq_mul) >> 1;
+ * rtfrqmax = (ent_delay x freq_mul) << 3;
+ * Given current deployments of CAAM in i.MX SoCs, and to simplify
+ * the configuration, we consider [1,16] to be a safe interval
+ * for the freq_mul and the limits of the interval are used to compute
+ * rtfrqmin, rtfrqmax
+ */
+ sec_out32(&rng->rtfreqmin, ent_delay >> 1);
+ sec_out32(&rng->rtfreqmax, ent_delay << 7);
+
+ sec_out32(&rng->rtscmisc, (retries << 16) | lrun_max);
+ sec_out32(&rng->rtpkrmax, poker_max);
+ sec_out32(&rng->rtpkrrng, poker_range);
+ sec_out32(&rng->rsvd1[0], (mono_range << 16) | mono_max);
+ sec_out32(&rng->rsvd1[1], (run_1_range << 16) | run_1_max);
+ sec_out32(&rng->rsvd1[2], (run_2_range << 16) | run_2_max);
+ sec_out32(&rng->rsvd1[3], (run_3_range << 16) | run_3_max);
+ sec_out32(&rng->rsvd1[4], (run_4_range << 16) | run_4_max);
+ sec_out32(&rng->rsvd1[5], (run_5_range << 16) | run_5_max);
+ sec_out32(&rng->rsvd1[6], (run_6_range << 16) | run_6_max);
+
+ val = sec_in32(&rng->rtmctl);
/*
- * select raw sampling in both entropy shifter
+ * Select raw sampling in both entropy shifter
* and statistical checker
*/
- sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
- /* put RNG4 into run mode */
- sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
+ val &= ~RTMCTL_SAMP_MODE_INVALID;
+ val |= RTMCTL_SAMP_MODE_RAW_ES_SC;
+ /* Put RNG4 into run mode */
+ val &= ~(RTMCTL_PRGM | RTMCTL_ACC);
+ /*test with sample mode only */
+ sec_out32(&rng->rtmctl, val);
}
static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index 7b6e3e2c20..2b3239414a 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -34,6 +34,7 @@
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
/* RNG4 TRNG test registers */
struct rng4tst {
+#define RTMCTL_ACC 0x20
#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
both entropy shifter and
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 11/15] Layerscape: Add crypto node in device tree
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
` (9 preceding siblings ...)
2022-01-10 12:27 ` [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in kernel Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 12/15] Layerscape: Enable Job ring driver model Gaurav Jain
` (3 subsequent siblings)
14 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
LS(1021/1012/1028/1043/1046/1088/2088), LX2160 - updated device tree
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/arm/dts/fsl-ls1012a.dtsi | 46 ++++++++++++++++++++++++++++++++++-
arch/arm/dts/fsl-ls1043a.dtsi | 45 +++++++++++++++++++++++++++++++++-
arch/arm/dts/fsl-ls1046a.dtsi | 44 +++++++++++++++++++++++++++++++++
arch/arm/dts/fsl-ls1088a.dtsi | 39 +++++++++++++++++++++++++++++
arch/arm/dts/fsl-ls2080a.dtsi | 39 +++++++++++++++++++++++++++++
arch/arm/dts/fsl-lx2160a.dtsi | 41 ++++++++++++++++++++++++++++++-
arch/arm/dts/ls1021a.dtsi | 40 ++++++++++++++++++++++++++++++
7 files changed, 291 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 0ea899c7d7..1cdcc99c1e 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright 2016 Freescale Semiconductor
*/
@@ -71,6 +71,50 @@
bus-width = <4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 52dc5a9638..72877d2ff5 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1043A family SoC.
*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* Mingkai Hu <Mingkai.hu@freescale.com>
@@ -125,6 +125,49 @@
interrupts = <0 43 0x4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index a60cbf11fc..c655e002aa 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright (C) 2016, Freescale Semiconductor
+ * Copyright 2021 NXP
*
* Mingkai Hu <mingkai.hu@nxp.com>
*/
@@ -124,6 +125,49 @@
interrupts = <0 43 0x4>;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+ "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x1700000 0x100000>;
+ reg = <0x00 0x1700000 0x0 0x100000>;
+ interrupts = <0 75 0x4>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.4-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index f73fdfda8b..9b7c54b260 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -174,6 +174,45 @@
dr_mode = "host";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
pcie1: pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 72ba52594a..a1837454f4 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -239,6 +239,45 @@
status = "disabled";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <0 139 0x4>; /* Level high type */
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <0 140 0x4>; /* Level high type */
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <0 141 0x4>; /* Level high type */
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <0 142 0x4>; /* Level high type */
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <0 143 0x4>; /* Level high type */
+ };
+ };
+
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc", "simple-mfd";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 52e4d7205a..57c7d3ef71 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
/*
* NXP lx2160a SOC common device tree source
*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
*
*/
@@ -27,6 +27,45 @@
clock-output-names = "sysclk";
};
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
clockgen: clocking@1300000 {
compatible = "fsl,ls2080a-clockgen";
reg = <0 0x1300000 0 0xa0000>;
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 86192cbb7f..be330c130f 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -3,6 +3,7 @@
* Freescale ls1021a SOC common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include "skeleton.dtsi"
@@ -144,6 +145,45 @@
big-endian;
};
+ crypto: crypto@1700000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <7>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1700000 0x100000>;
+ ranges = <0x0 0x1700000 0x100000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ };
+
clockgen: clocking@1ee1000 {
#address-cells = <1>;
#size-cells = <1>;
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 12/15] Layerscape: Enable Job ring driver model.
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
` (10 preceding siblings ...)
2022-01-10 12:27 ` [PATCH v8 11/15] Layerscape: Add crypto node in device tree Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 12:42 ` Michael Walle
2022-01-10 12:27 ` [PATCH v8 13/15] PPC: Add crypto node in device tree Gaurav Jain
` (2 subsequent siblings)
14 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162
platforms are enabled with JR driver model.
removed sec_init() call from board files.
removed CONFIG_FSL_CAAM from defconfig files.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/arm/Kconfig | 4 ++++
arch/arm/cpu/armv7/ls102xa/Kconfig | 3 +++
arch/arm/cpu/armv7/ls102xa/cpu.c | 16 ++++++++++++++++
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 17 +++++++++++++++++
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 10 +++++++++-
board/freescale/ls1012afrdm/ls1012afrdm.c | 7 +------
board/freescale/ls1012aqds/ls1012aqds.c | 6 +-----
board/freescale/ls1012ardb/ls1012ardb.c | 6 +-----
board/freescale/ls1021aiot/ls1021aiot.c | 6 ++----
board/freescale/ls1021aqds/ls1021aqds.c | 6 +-----
board/freescale/ls1021atsn/ls1021atsn.c | 7 ++-----
board/freescale/ls1021atwr/ls1021atwr.c | 8 ++------
board/freescale/ls1028a/ls1028a.c | 6 +-----
board/freescale/ls1043ardb/ls1043ardb.c | 6 +-----
board/freescale/ls1046afrwy/ls1046afrwy.c | 7 +------
board/freescale/ls1046aqds/ls1046aqds.c | 7 +------
board/freescale/ls1046ardb/ls1046ardb.c | 6 +-----
board/freescale/ls1088a/ls1088a.c | 6 +-----
board/freescale/ls2080aqds/ls2080aqds.c | 6 +-----
board/freescale/ls2080ardb/ls2080ardb.c | 9 +--------
board/freescale/lx2160a/lx2160a.c | 5 -----
board/kontron/sl28/sl28.c | 3 ---
configs/ls1021aiot_qspi_defconfig | 1 -
configs/ls1021aqds_nor_defconfig | 1 -
configs/ls1021aqds_qspi_defconfig | 1 -
configs/ls1021atsn_qspi_defconfig | 1 -
configs/ls1021atwr_nor_defconfig | 1 -
.../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
configs/ls1028ardb_tfa_defconfig | 1 -
configs/ls1043ardb_tfa_defconfig | 1 -
configs/ls1046afrwy_tfa_defconfig | 1 -
configs/ls1046aqds_tfa_defconfig | 1 -
configs/ls1046ardb_tfa_defconfig | 1 -
configs/ls2088aqds_tfa_defconfig | 1 -
configs/ls2088ardb_tfa_defconfig | 1 -
configs/lx2160aqds_tfa_defconfig | 1 -
configs/lx2160ardb_tfa_defconfig | 1 -
configs/lx2162aqds_tfa_defconfig | 1 -
38 files changed, 68 insertions(+), 105 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7ce2bbc954..30a34bdd08 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1504,6 +1504,8 @@ config TARGET_LS1028AQDS
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select MISC
help
Support for Freescale LS1028AQDS platform
The LS1028A Development System (QDS) is a high-performance
@@ -1518,6 +1520,8 @@ config TARGET_LS1028ARDB
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select MISC
help
Support for Freescale LS1028ARDB platform
The LS1028A Development System (RDB) is a high-performance
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index f919d02db4..ca006e069f 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -21,6 +21,9 @@ config ARCH_LS1021A
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_I2C_MXC
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_PCI
imply SCSI
imply SCSI_AHCI
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index d863c9625a..4904592703 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -20,6 +21,7 @@
#include <config.h>
#include <fsl_wdog.h>
#include <linux/delay.h>
+#include <dm.h>
#include "fsl_epu.h"
@@ -397,3 +399,17 @@ void arch_preboot_os(void)
ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 1a057f7059..75d9876dfc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -20,6 +20,9 @@ config ARCH_LS1012A
select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1 if !DM_I2C
select SYS_I2C_MXC_I2C2 if !DM_I2C
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply PANIC_HANG
config ARCH_LS1028A
@@ -88,6 +91,9 @@ config ARCH_LS1043A
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_PCI
imply ID_EEPROM
@@ -125,6 +131,9 @@ config ARCH_LS1046A
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply ID_EEPROM
imply SCSI
imply SCSI_AHCI
@@ -170,6 +179,8 @@ config ARCH_LS1088A
select SYS_I2C_MXC_I2C3 if !TFABOOT
select SYS_I2C_MXC_I2C4 if !TFABOOT
select RESV_RAM if GIC_V3_ITS
+ select FSL_CAAM
+ select MISC
imply ID_EEPROM
imply SCSI
imply SPL_SYS_I2C_LEGACY
@@ -225,6 +236,8 @@ config ARCH_LS2080A
select SYS_I2C_MXC_I2C3 if !TFABOOT
select SYS_I2C_MXC_I2C4 if !TFABOOT
select RESV_RAM if GIC_V3_ITS
+ select FSL_CAAM
+ select MISC
imply DISTRO_DEFAULTS
imply ID_EEPROM
imply PANIC_HANG
@@ -258,6 +271,8 @@ config ARCH_LX2162A
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select RESV_RAM if GIC_V3_ITS
+ select FSL_CAAM
+ select MISC
imply DISTRO_DEFAULTS
imply PANIC_HANG
imply SCSI
@@ -294,6 +309,8 @@ config ARCH_LX2160A
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select RESV_RAM if GIC_V3_ITS
+ select FSL_CAAM
+ select MISC
imply DISTRO_DEFAULTS
imply ID_EEPROM
imply PANIC_HANG
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 1a359d060e..ccd9116ff8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
@@ -48,6 +48,7 @@
#endif
#endif
#include <linux/mii.h>
+#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -1649,6 +1650,13 @@ __weak int serdes_misc_init(void)
int arch_misc_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
serdes_misc_init();
return 0;
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index 5dd19cfcd9..bc37c553a5 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2021 NXP
*/
#include <common.h>
@@ -22,7 +22,6 @@
#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -172,10 +171,6 @@ int board_init(void)
if (current_el() == 3)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 68578e81a5..361bd5c582 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -28,7 +29,6 @@
#include <fsl_mmdc.h>
#include <spl.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
#include "ls1012aqds_pfe.h"
@@ -150,10 +150,6 @@ int board_init(void)
erratum_a010315();
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 064fb4d39f..456609d993 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -27,7 +28,6 @@
#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -173,10 +173,6 @@ int board_init(void)
erratum_a010315();
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
index bfe6137604..5ab03b3340 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -209,10 +210,7 @@ int misc_init_r(void)
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index fbbd27d9d7..f84b94d946 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -20,7 +20,6 @@
#include <mmc.h>
#include <fsl_csu.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include <spl.h>
#include <fsl_devdis.h>
#include <fsl_validate.h>
@@ -386,9 +385,6 @@ int misc_init_r(void)
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
-#endif
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
#endif
return 0;
}
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index f31e16c419..f016088670 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2019 NXP
+/* Copyright 2016-2019, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@@ -238,10 +238,7 @@ int misc_init_r(void)
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index f0b441db63..a2a87eaf35 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -26,7 +26,6 @@
#include <netdev.h>
#include <fsl_mdio.h>
#include <tsec.h>
-#include <fsl_sec.h>
#include <fsl_devdis.h>
#include <spl.h>
#include <linux/delay.h>
@@ -555,10 +554,7 @@ int misc_init_r(void)
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_board_mux();
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index 486a544d35..71a086ef67 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -73,10 +73,6 @@ u32 get_lpuart_clk(void)
int board_init(void)
{
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index beef26b084..c7f214c236 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -20,7 +21,6 @@
#include <fm_eth.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include "cpld.h"
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
@@ -211,10 +211,6 @@ int board_init(void)
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
index f1c08a13f7..5a298cd311 100644
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
@@ -20,7 +20,6 @@
#include <fm_eth.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
-#include <fsl_sec.h>
#include <fsl_dspi.h>
#include "../common/i2c_mux.h"
@@ -135,10 +134,6 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return 0;
}
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index cc95d441b6..79658693ab 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
*/
#include <common.h>
@@ -27,7 +27,6 @@
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include <spl.h>
#include "../common/i2c_mux.h"
@@ -420,10 +419,6 @@ int board_init(void)
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
return 0;
}
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index 93ef903f29..2e9a6d44eb 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
@@ -23,7 +24,6 @@
#include <fsl_esdhc.h>
#include <power/mc34vr500_pmic.h>
#include "cpld.h"
-#include <fsl_sec.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -85,10 +85,6 @@ int board_init(void)
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 7046fbaeb5..b8bc8f0d5a 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2021 NXP
*/
#include <common.h>
#include <env.h>
@@ -12,7 +12,6 @@
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
-#include <fsl_sec.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
@@ -815,9 +814,6 @@ int board_init(void)
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 2f0139edef..5cc5d06823 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <env.h>
@@ -20,7 +21,6 @@
#include <rtc.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
-#include <fsl_sec.h>
#include <asm/arch/ppa.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
@@ -221,10 +221,6 @@ int board_init(void)
#endif
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index bf660a8e65..e657097ba7 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
- * Copyright 2017 NXP
+ * Copyright 2017, 2021 NXP
*/
#include <common.h>
#include <env.h>
@@ -23,7 +23,6 @@
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <asm/arch/ppa.h>
-#include <fsl_sec.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
@@ -287,9 +286,6 @@ int board_init(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
@@ -298,9 +294,6 @@ int board_init(void)
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index bda665624d..c8a47c6bae 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -14,7 +14,6 @@
#include <errno.h>
#include <netdev.h>
#include <fsl_ddr.h>
-#include <fsl_sec.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/bitops.h>
@@ -596,10 +595,6 @@ int board_init(void)
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#endif
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c
index c8ed7ac81a..d86cf308f6 100644
--- a/board/kontron/sl28/sl28.c
+++ b/board/kontron/sl28/sl28.c
@@ -28,9 +28,6 @@ int board_early_init_f(void)
int board_init(void)
{
- if (CONFIG_IS_ENABLED(FSL_CAAM))
- sec_init();
-
return 0;
}
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
index 2a999e8798..c59ccd37f3 100644
--- a/configs/ls1021aiot_qspi_defconfig
+++ b/configs/ls1021aiot_qspi_defconfig
@@ -36,7 +36,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 3a2fe03139..f0236e35d8 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -50,7 +50,6 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index a787ce0b7c..73c78753f9 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -50,7 +50,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index d92fdf4a15..5abf6cdbb9 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -36,7 +36,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 548ec897bc..10026d0549 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -44,7 +44,6 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 404b33f938..e6c12c9104 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -61,6 +61,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_SPL_OF_CONTROL=y
# CONFIG_SPL_BLK is not set
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index 035974afd8..d447358107 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -48,7 +48,6 @@ CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 7e741c7183..a0474ac2e3 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -41,7 +41,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_ADDR=0x60500000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index 85db989f96..9d60bd199a 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -39,7 +39,6 @@ CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index 4bf413c0eb..0a2d317c8b 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -55,7 +55,6 @@ CONFIG_ENV_ADDR=0x60500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 3501764e6f..10093b59d4 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -44,7 +44,6 @@ CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index 6821ed1a45..fb2fc3d0f7 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -51,7 +51,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index 8e76f59b92..6a99143e54 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -49,7 +49,6 @@ CONFIG_ENV_ADDR=0x580500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index ddcf681255..9b6c7323cb 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -51,7 +51,6 @@ CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index d81a4b10b1..9bf92881be 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -50,7 +50,6 @@ CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig
index 2028bfc524..441932417a 100644
--- a/configs/lx2162aqds_tfa_defconfig
+++ b/configs/lx2162aqds_tfa_defconfig
@@ -53,7 +53,6 @@ CONFIG_ENV_ADDR=0x20500000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 13/15] PPC: Add crypto node in device tree
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
` (11 preceding siblings ...)
2022-01-10 12:27 ` [PATCH v8 12/15] Layerscape: Enable Job ring driver model Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 14/15] PPC: Enable Job ring driver model Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 15/15] update CAAM MAINTAINER Gaurav Jain
14 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
device tree imported from linux kernel.
c500bee1c5b2 (tag: v5.14-rc4) Linux 5.14-rc4
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/powerpc/dts/p2041si-post.dtsi | 1 +
arch/powerpc/dts/p3041si-post.dtsi | 1 +
arch/powerpc/dts/p4080si-post.dtsi | 1 +
arch/powerpc/dts/p5040si-post.dtsi | 1 +
arch/powerpc/dts/qoriq-sec4.0-0.dtsi | 74 ++++++++++++++++++++++
arch/powerpc/dts/qoriq-sec4.2-0.dtsi | 83 +++++++++++++++++++++++++
arch/powerpc/dts/qoriq-sec5.2-0.dtsi | 92 ++++++++++++++++++++++++++++
arch/powerpc/dts/t1023si-post.dtsi | 1 +
arch/powerpc/dts/t1042si-post.dtsi | 1 +
arch/powerpc/dts/t2080si-post.dtsi | 1 +
arch/powerpc/dts/t4240si-post.dtsi | 1 +
11 files changed, 257 insertions(+)
create mode 100644 arch/powerpc/dts/qoriq-sec4.0-0.dtsi
create mode 100644 arch/powerpc/dts/qoriq-sec4.2-0.dtsi
create mode 100644 arch/powerpc/dts/qoriq-sec5.2-0.dtsi
diff --git a/arch/powerpc/dts/p2041si-post.dtsi b/arch/powerpc/dts/p2041si-post.dtsi
index 01ab395950..8819199646 100644
--- a/arch/powerpc/dts/p2041si-post.dtsi
+++ b/arch/powerpc/dts/p2041si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p3041si-post.dtsi b/arch/powerpc/dts/p3041si-post.dtsi
index 21f322f06f..a3e8088d25 100644
--- a/arch/powerpc/dts/p3041si-post.dtsi
+++ b/arch/powerpc/dts/p3041si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p4080si-post.dtsi b/arch/powerpc/dts/p4080si-post.dtsi
index 7c3f2fb92e..56b79b14f4 100644
--- a/arch/powerpc/dts/p4080si-post.dtsi
+++ b/arch/powerpc/dts/p4080si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.0-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p5040si-post.dtsi b/arch/powerpc/dts/p5040si-post.dtsi
index 1efad2d017..fae3ed31a5 100644
--- a/arch/powerpc/dts/p5040si-post.dtsi
+++ b/arch/powerpc/dts/p5040si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/qoriq-sec4.0-0.dtsi b/arch/powerpc/dts/qoriq-sec4.0-0.dtsi
new file mode 100644
index 0000000000..ff348d70f1
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec4.0-0.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v4.0";
+ fsl,sec-era = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-sec4.2-0.dtsi b/arch/powerpc/dts/qoriq-sec4.2-0.dtsi
new file mode 100644
index 0000000000..57a0bc5c56
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec4.2-0.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+ fsl,sec-era = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v4.2-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v4.2-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v4.2-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-sec5.2-0.dtsi b/arch/powerpc/dts/qoriq-sec5.2-0.dtsi
new file mode 100644
index 0000000000..e5f87effd3
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec5.2-0.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <5>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v5.2-rtic",
+ "fsl,sec-v5.0-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/t1023si-post.dtsi b/arch/powerpc/dts/t1023si-post.dtsi
index 7284eb9791..6f666a1554 100644
--- a/arch/powerpc/dts/t1023si-post.dtsi
+++ b/arch/powerpc/dts/t1023si-post.dtsi
@@ -14,6 +14,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman3l-0.dtsi"
diff --git a/arch/powerpc/dts/t1042si-post.dtsi b/arch/powerpc/dts/t1042si-post.dtsi
index 5c60944e60..eebbbaf0e1 100644
--- a/arch/powerpc/dts/t1042si-post.dtsi
+++ b/arch/powerpc/dts/t1042si-post.dtsi
@@ -12,6 +12,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
/include/ "qoriq-fman3l-0.dtsi"
/include/ "qoriq-fman3-0-1g-0.dtsi"
diff --git a/arch/powerpc/dts/t2080si-post.dtsi b/arch/powerpc/dts/t2080si-post.dtsi
index d8ef579cb7..c06526b3db 100644
--- a/arch/powerpc/dts/t2080si-post.dtsi
+++ b/arch/powerpc/dts/t2080si-post.dtsi
@@ -13,6 +13,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
/include/ "qoriq-fman3-0.dtsi"
/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi"
diff --git a/arch/powerpc/dts/t4240si-post.dtsi b/arch/powerpc/dts/t4240si-post.dtsi
index a596f48b54..9fa99ae771 100644
--- a/arch/powerpc/dts/t4240si-post.dtsi
+++ b/arch/powerpc/dts/t4240si-post.dtsi
@@ -12,6 +12,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
/include/ "qoriq-fman3-0.dtsi"
/include/ "qoriq-fman3-0-1g-0.dtsi"
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 14/15] PPC: Enable Job ring driver model.
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
` (12 preceding siblings ...)
2022-01-10 12:27 ` [PATCH v8 13/15] PPC: Add crypto node in device tree Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 15/15] update CAAM MAINTAINER Gaurav Jain
14 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
removed sec_init() call and CONFIG_FSL_CAAM from defconfig.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 33 +++++++++++++++++++++++++++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 ++++++++++++--
arch/powerpc/include/asm/u-boot-ppc.h | 17 ++++++++++++++
arch/powerpc/include/asm/u-boot.h | 1 +
configs/P2041RDB_defconfig | 1 -
configs/P3041DS_defconfig | 1 -
configs/P4080DS_defconfig | 1 -
configs/P5040DS_defconfig | 1 -
configs/T1024RDB_defconfig | 1 -
configs/T1042D4RDB_defconfig | 1 -
configs/T2080QDS_defconfig | 1 -
configs/T2080RDB_defconfig | 1 -
configs/T2080RDB_revD_defconfig | 1 -
configs/T4240RDB_defconfig | 1 -
14 files changed, 66 insertions(+), 12 deletions(-)
create mode 100644 arch/powerpc/include/asm/u-boot-ppc.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 836aeddbe2..b05c372086 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -25,6 +25,9 @@ config TARGET_P3041DS
select PHYS_64BIT
select ARCH_P3041
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -33,6 +36,9 @@ config TARGET_P4080DS
select PHYS_64BIT
select ARCH_P4080
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -41,6 +47,9 @@ config TARGET_P5040DS
select PHYS_64BIT
select ARCH_P5040
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -102,6 +111,9 @@ config TARGET_P2041RDB
select ARCH_P2041
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply FSL_SATA
@@ -117,6 +129,9 @@ config TARGET_T1024RDB
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_EEPROM
imply PANIC_HANG
@@ -126,6 +141,9 @@ config TARGET_T1042RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_T1042D4RDB
bool "Support T1042D4RDB"
@@ -133,6 +151,9 @@ config TARGET_T1042D4RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply PANIC_HANG
config TARGET_T1042RDB_PI
@@ -141,6 +162,9 @@ config TARGET_T1042RDB_PI
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply PANIC_HANG
config TARGET_T2080QDS
@@ -151,6 +175,9 @@ config TARGET_T2080QDS
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
config TARGET_T2080RDB
@@ -159,6 +186,9 @@ config TARGET_T2080RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -168,6 +198,9 @@ config TARGET_T4240RDB
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e920e01b25..728c6447a8 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -56,6 +56,7 @@
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
#endif
+#include <dm.h>
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
/*
@@ -974,8 +975,6 @@ int cpu_init_r(void)
#endif
#ifdef CONFIG_FSL_CAAM
- sec_init();
-
#if defined(CONFIG_ARCH_C29X)
if ((SVR_SOC_VER(svr) == SVR_C292) ||
(SVR_SOC_VER(svr) == SVR_C293))
@@ -1014,6 +1013,20 @@ int cpu_init_r(void)
return 0;
}
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
+ return 0;
+}
+#endif
+
void arch_preboot_os(void)
{
u32 msr;
diff --git a/arch/powerpc/include/asm/u-boot-ppc.h b/arch/powerpc/include/asm/u-boot-ppc.h
new file mode 100644
index 0000000000..372ca3e037
--- /dev/null
+++ b/arch/powerpc/include/asm/u-boot-ppc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2021 NXP
+ *
+ * Gaurav Jain <gaurav.jain@nxp.com>
+ */
+
+#ifndef _U_BOOT_PPC_H_
+#define _U_BOOT_PPC_H_
+
+#ifndef __ASSEMBLY__
+
+int arch_misc_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _U_BOOT_PPC_H_ */
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index 19b3c0db5f..36af8e5403 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -21,5 +21,6 @@
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
#include <asm/ppc.h>
+#include <asm/u-boot-ppc.h>
#endif /* __U_BOOT_H__ */
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 7b430f69e2..7c82812b28 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -34,7 +34,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 821a7c3bc1..fcd0214c71 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -32,7 +32,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 564f28caba..723ef1c457 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -32,7 +32,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 79c6e466c7..0a13763d71 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -32,7 +32,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 3ed1c6db4b..f8fbee2e4c 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -44,7 +44,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index f1ec400636..62cb8c4a37 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -35,7 +35,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index d76547ab63..c5b0c28391 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -33,7 +33,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 610f706473..cb8d5eb69b 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -38,7 +38,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index f8f459f27b..b3712be552 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -39,7 +39,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133330000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index c66b152d20..b57410bf58 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -30,7 +30,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
-CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v8 15/15] update CAAM MAINTAINER
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
` (13 preceding siblings ...)
2022-01-10 12:27 ` [PATCH v8 14/15] PPC: Enable Job ring driver model Gaurav Jain
@ 2022-01-10 12:27 ` Gaurav Jain
14 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-10 12:27 UTC (permalink / raw)
To: u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Gaurav Jain
updated CAAM driver files maintainer.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 90666ce376..622725aa64 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1312,3 +1312,9 @@ T: git https://source.denx.de/u-boot/u-boot.git
F: configs/tools-only_defconfig
F: *
F: */
+
+CAAM
+M: Gaurav Jain <gaurav.jain@nxp.com>
+S: Maintained
+F: drivers/crypto/fsl/
+F: include/fsl_sec.h
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread
* Re: [PATCH v8 12/15] Layerscape: Enable Job ring driver model.
2022-01-10 12:27 ` [PATCH v8 12/15] Layerscape: Enable Job ring driver model Gaurav Jain
@ 2022-01-10 12:42 ` Michael Walle
2022-01-11 5:41 ` [EXT] " Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: Michael Walle @ 2022-01-10 12:42 UTC (permalink / raw)
To: gaurav.jain
Cc: Shengzhou.Liu, V.Sethi, adrian.alonso, alison.wang, andy.tang,
festevam, franck.lenormand, horia.geanta, ji.luo,
meenakshi.aggarwal, mingkai.hu, olteanv, pankaj.gupta, peng.fan,
pramod.kumar_1, priyanka.jain, rajesh.bhagat, sahil.malhotra,
sbabic, silvano.dininno, sjg, u-boot, uboot-imx, wasim.khan,
ye.li, Michael Walle
Hi,
please keep me on CC for these series, as there were comments
from me on previous versions. Thanks.
..
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 7ce2bbc954..30a34bdd08 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1504,6 +1504,8 @@ config TARGET_LS1028AQDS
> select ARCH_SUPPORT_TFABOOT
> select BOARD_LATE_INIT
> select GPIO_EXTRA_HEADER
> + select FSL_CAAM
> + select MISC
This looks wrong. FSL_CAAM should depend on MISC, no?
> help
> Support for Freescale LS1028AQDS platform
> The LS1028A Development System (QDS) is a high-performance
> @@ -1518,6 +1520,8 @@ config TARGET_LS1028ARDB
> select ARCH_SUPPORT_TFABOOT
> select BOARD_LATE_INIT
> select GPIO_EXTRA_HEADER
> + select FSL_CAAM
> + select MISC
> help
> Support for Freescale LS1028ARDB platform
> The LS1028A Development System (RDB) is a high-performance
> diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
> index f919d02db4..ca006e069f 100644
> --- a/arch/arm/cpu/armv7/ls102xa/Kconfig
> +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
> @@ -21,6 +21,9 @@ config ARCH_LS1021A
> select SYS_FSL_SRDS_1
> select SYS_HAS_SERDES
> select SYS_I2C_MXC
> + select FSL_CAAM
While above you added that dependency to an indivdual board,
here you are adding that dependency to all boards using this
architecture. The same is true for all the other "config
ARCH_*" symbols. What if someone wants to build a bootloader
without CAAM support? This should really go into the
defconfigs for these boards.
-michael
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in kernel
2022-01-10 12:27 ` [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in kernel Gaurav Jain
@ 2022-01-10 14:01 ` ZHIZHIKIN Andrey
2022-01-11 5:44 ` [EXT] " Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: ZHIZHIKIN Andrey @ 2022-01-10 14:01 UTC (permalink / raw)
To: Gaurav Jain, u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, michael
Hello Gaurav,
Cc: Michael Walle
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Gaurav Jain
> Sent: Monday, January 10, 2022 1:27 PM
> To: u-boot@lists.denx.de
> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan
> <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Priyanka Jain
> <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
> <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> <franck.lenormand@nxp.com>; Silvano Di Ninno <silvano.dininno@nxp.com>; Sahil
> malhotra <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun
> Sethi <V.Sethi@nxp.com>; NXP i . MX U-Boot Team <uboot-imx@nxp.com>; Shengzhou
> Liu <Shengzhou.Liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat
> <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim
> Khan <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>; Tang Yuantian <andy.tang@nxp.com>; Adrian Alonso
> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in kernel
>
> From: Ye Li <ye.li@nxp.com>
>
> RNG parameters are reconfigured.
> - For TRNG to generate 256 bits of entropy, RNG TRNG Seed Control register
> is configured to have reduced SAMP_SIZE from default 2500 to 512. it is
> number of entropy samples that will be taken during Entropy generation.
> - self-test registers(Monobit Limit, Poker Range, Run Length Limit)
> are synchronized with new RTSDCTL[SAMP_SIZE] of 512.
>
> TRNG time is caluculated based on sample size.
Typo: caluculated -> calculated
> time required to generate entropy is reduced and
> hwrng performance improved from 0.3 kB/s to 1.3 kB/s.
Is there any degradation in passed/failed FIPS 140-2 test count? Can you
provide some results from at least rngtest run?
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Acked-by: Gaurav Jain <gaurav.jain@nxp.com>>
> ---
> drivers/crypto/fsl/jr.c | 102 +++++++++++++++++++++++++++++++++-------
> include/fsl_sec.h | 1 +
> 2 files changed, 87 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
> index a84440ab10..e5346a84a4 100644
> --- a/drivers/crypto/fsl/jr.c
> +++ b/drivers/crypto/fsl/jr.c
> @@ -603,30 +603,100 @@ static u8 get_rng_vid(ccsr_sec_t *sec)
> */
> static void kick_trng(int ent_delay, ccsr_sec_t *sec)
> {
> + u32 samples = 512; /* number of bits to generate and test */
> + u32 mono_min = 195;
> + u32 mono_max = 317;
> + u32 mono_range = mono_max - mono_min;
> + u32 poker_min = 1031;
> + u32 poker_max = 1600;
> + u32 poker_range = poker_max - poker_min + 1;
> + u32 retries = 2;
> + u32 lrun_max = 32;
> + s32 run_1_min = 27;
> + s32 run_1_max = 107;
> + s32 run_1_range = run_1_max - run_1_min;
> + s32 run_2_min = 7;
> + s32 run_2_max = 62;
> + s32 run_2_range = run_2_max - run_2_min;
> + s32 run_3_min = 0;
> + s32 run_3_max = 39;
> + s32 run_3_range = run_3_max - run_3_min;
> + s32 run_4_min = -1;
> + s32 run_4_max = 26;
> + s32 run_4_range = run_4_max - run_4_min;
> + s32 run_5_min = -1;
> + s32 run_5_max = 18;
> + s32 run_5_range = run_5_max - run_5_min;
> + s32 run_6_min = -1;
> + s32 run_6_max = 17;
> + s32 run_6_range = run_6_max - run_6_min;
I have a feeling that this whole block of local variables can be
simplified. I'm not sure it is required to list this so detailed.
You can attempt to define those values in header file and use
macros to compute bound conditions, rather than allocating this on
the stack here.
> + u32 val;
> +
> struct rng4tst __iomem *rng =
> (struct rng4tst __iomem *)&sec->rng;
> - u32 val;
>
> - /* put RNG4 into program mode */
> - sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
> - /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
> - * length (in system clocks) of each Entropy sample taken
> - * */
> + /* Put RNG in program mode */
> + /* Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
> + * properly invalidate the entropy in the entropy register and
> + * force re-generation.
> + */
> + sec_setbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
> +
> + /* Configure the RNG Entropy Delay
> + * Performance-wise, it does not make sense to
> + * set the delay to a value that is lower
> + * than the last one that worked (i.e. the state handles
> + * were instantiated properly. Thus, instead of wasting
> + * time trying to set the values controlling the sample
> + * frequency, the function simply returns.
> + */
> val = sec_in32(&rng->rtsdctl);
> - val = (val & ~RTSDCTL_ENT_DLY_MASK) |
> - (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
> + val &= RTSDCTL_ENT_DLY_MASK;
> + val >>= RTSDCTL_ENT_DLY_SHIFT;
> + if (ent_delay < val) {
> + /* Put RNG4 into run mode */
> + sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
> + return;
> + }
> +
> + val = (ent_delay << RTSDCTL_ENT_DLY_SHIFT) | samples;
> sec_out32(&rng->rtsdctl, val);
> - /* min. freq. count, equal to 1/4 of the entropy sample length */
> - sec_out32(&rng->rtfreqmin, ent_delay >> 2);
> - /* disable maximum frequency count */
> - sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
> +
> + /*
> + * Recommended margins (min,max) for freq. count:
> + * freq_mul = RO_freq / TRNG_clk_freq
> + * rtfrqmin = (ent_delay x freq_mul) >> 1;
> + * rtfrqmax = (ent_delay x freq_mul) << 3;
> + * Given current deployments of CAAM in i.MX SoCs, and to simplify
> + * the configuration, we consider [1,16] to be a safe interval
Statement "... we consider ..." should be perhaps extended with justification
on how this conclusion was made. Some test results (either here in the comment
or in commit message) would be beneficial to see.
> + * for the freq_mul and the limits of the interval are used to compute
> + * rtfrqmin, rtfrqmax
> + */
> + sec_out32(&rng->rtfreqmin, ent_delay >> 1);
> + sec_out32(&rng->rtfreqmax, ent_delay << 7);
> +
> + sec_out32(&rng->rtscmisc, (retries << 16) | lrun_max);
> + sec_out32(&rng->rtpkrmax, poker_max);
> + sec_out32(&rng->rtpkrrng, poker_range);
> + sec_out32(&rng->rsvd1[0], (mono_range << 16) | mono_max);
> + sec_out32(&rng->rsvd1[1], (run_1_range << 16) | run_1_max);
> + sec_out32(&rng->rsvd1[2], (run_2_range << 16) | run_2_max);
> + sec_out32(&rng->rsvd1[3], (run_3_range << 16) | run_3_max);
> + sec_out32(&rng->rsvd1[4], (run_4_range << 16) | run_4_max);
> + sec_out32(&rng->rsvd1[5], (run_5_range << 16) | run_5_max);
> + sec_out32(&rng->rsvd1[6], (run_6_range << 16) | run_6_max);
Writing in reserved area is not a good idea. Those registers are defined
in HW, can you please define them also in the header file?
> +
> + val = sec_in32(&rng->rtmctl);
> /*
> - * select raw sampling in both entropy shifter
> + * Select raw sampling in both entropy shifter
This change is not needed, otherwise please adjust all comments in
original file, as for example comment below also starts with small
letter...
> * and statistical checker
> */
> - sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
The only usage of RTMCTL_SAMP_MODE_RAW_ES_SC is dropped here, please
remove it from include/fsl_sec.h as well.
> - /* put RNG4 into run mode */
> - sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
> + val &= ~RTMCTL_SAMP_MODE_INVALID;
> + val |= RTMCTL_SAMP_MODE_RAW_ES_SC;
> + /* Put RNG4 into run mode */
> + val &= ~(RTMCTL_PRGM | RTMCTL_ACC);
BIT() macro for both new and existing defines?
> + /*test with sample mode only */
> + sec_out32(&rng->rtmctl, val);
> }
>
> static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
> diff --git a/include/fsl_sec.h b/include/fsl_sec.h
> index 7b6e3e2c20..2b3239414a 100644
> --- a/include/fsl_sec.h
> +++ b/include/fsl_sec.h
> @@ -34,6 +34,7 @@
> #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
> /* RNG4 TRNG test registers */
> struct rng4tst {
> +#define RTMCTL_ACC 0x20
> #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
> #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
> both entropy shifter and
> --
> 2.17.1
-- andrey
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 12/15] Layerscape: Enable Job ring driver model.
2022-01-10 12:42 ` Michael Walle
@ 2022-01-11 5:41 ` Gaurav Jain
2022-01-11 7:22 ` Michael Walle
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-01-11 5:41 UTC (permalink / raw)
To: Michael Walle
Cc: Shengzhou Liu, Varun Sethi, Adrian Alonso, Alison Wang,
Andy Tang, festevam, Franck Lenormand, Horia Geanta, Ji Luo,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
sbabic, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx, Wasim Khan,
Ye Li
Hi Michael
> -----Original Message-----
> From: Michael Walle <michael@walle.cc>
> Sent: Monday, January 10, 2022 6:13 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>
> Cc: Shengzhou Liu <shengzhou.liu@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Alison Wang
> <alison.wang@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> festevam@gmail.com; Franck Lenormand <franck.lenormand@nxp.com>; Horia
> Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Meenakshi
> Aggarwal <meenakshi.aggarwal@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Rajesh
> Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> sbabic@denx.de; Silvano Di Ninno <silvano.dininno@nxp.com>;
> sjg@chromium.org; u-boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>;
> Wasim Khan <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>; Michael Walle
> <michael@walle.cc>
> Subject: [EXT] Re: [PATCH v8 12/15] Layerscape: Enable Job ring driver model.
>
> Caution: EXT Email
>
> Hi,
>
> please keep me on CC for these series, as there were comments from me on
> previous versions. Thanks.
>
> ..
>
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index
> > 7ce2bbc954..30a34bdd08 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1504,6 +1504,8 @@ config TARGET_LS1028AQDS
> > select ARCH_SUPPORT_TFABOOT
> > select BOARD_LATE_INIT
> > select GPIO_EXTRA_HEADER
> > + select FSL_CAAM
> > + select MISC
>
> This looks wrong. FSL_CAAM should depend on MISC, no?
FSL_CAAM is to enable the CAAM driver.
Caam driver is developed using misc uclass and MISC config is required to enable DM for misc uclass.
Some platforms do not have driver model support so in that case CAAM can function without misc.
>
> > help
> > Support for Freescale LS1028AQDS platform
> > The LS1028A Development System (QDS) is a high-performance @@
> > -1518,6 +1520,8 @@ config TARGET_LS1028ARDB
> > select ARCH_SUPPORT_TFABOOT
> > select BOARD_LATE_INIT
> > select GPIO_EXTRA_HEADER
> > + select FSL_CAAM
> > + select MISC
> > help
> > Support for Freescale LS1028ARDB platform
> > The LS1028A Development System (RDB) is a high-performance
> > diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig
> > b/arch/arm/cpu/armv7/ls102xa/Kconfig
> > index f919d02db4..ca006e069f 100644
> > --- a/arch/arm/cpu/armv7/ls102xa/Kconfig
> > +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
> > @@ -21,6 +21,9 @@ config ARCH_LS1021A
> > select SYS_FSL_SRDS_1
> > select SYS_HAS_SERDES
> > select SYS_I2C_MXC
> > + select FSL_CAAM
>
> While above you added that dependency to an indivdual board, here you are
> adding that dependency to all boards using this architecture. The same is true
> for all the other "config ARCH_*" symbols. What if someone wants to build a
> bootloader without CAAM support? This should really go into the defconfigs for
> these boards.
CAAM is only initialized at boot which does not imply to use caam in every operation.
Regards
Gaurav Jain
>
> -michael
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] RE: [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in kernel
2022-01-10 14:01 ` ZHIZHIKIN Andrey
@ 2022-01-11 5:44 ` Gaurav Jain
0 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-11 5:44 UTC (permalink / raw)
To: ZHIZHIKIN Andrey, u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil Malhotra, Pankaj Gupta, Varun Sethi,
dl-uboot-imx, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Andy Tang, Adrian Alonso, Vladimir Oltean, michael
Hi Andrey
For now I will remove this particular patch from my series and will send a separate patch addressing your comments.
Regards
Gaurav Jain
> -----Original Message-----
> From: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>
> Sent: Monday, January 10, 2022 7:31 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>; u-boot@lists.denx.de
> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>;
> Peng Fan <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Priyanka
> Jain <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
> <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> <franck.lenormand@nxp.com>; Silvano Di Ninno <silvano.dininno@nxp.com>;
> Sahil Malhotra <sahil.malhotra@nxp.com>; Pankaj Gupta
> <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-uboot-imx
> <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>; Meenakshi
> Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean
> <olteanv@gmail.com>; michael@walle.cc
> Subject: [EXT] RE: [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in
> kernel
>
> Caution: EXT Email
>
> Hello Gaurav,
>
> Cc: Michael Walle
>
> > -----Original Message-----
> > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Gaurav Jain
> > Sent: Monday, January 10, 2022 1:27 PM
> > To: u-boot@lists.denx.de
> > Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
> > <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> > <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> > <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> > <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano
> > Di Ninno <silvano.dininno@nxp.com>; Sahil malhotra
> > <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun
> > Sethi <V.Sethi@nxp.com>; NXP i . MX U-Boot Team <uboot-imx@nxp.com>;
> > Shengzhou Liu <Shengzhou.Liu@nxp.com>; Mingkai Hu
> > <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> Meenakshi
> > Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> > <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar
> > <pramod.kumar_1@nxp.com>; Tang Yuantian <andy.tang@nxp.com>; Adrian
> > Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> > Subject: [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in
> > kernel
> >
> > From: Ye Li <ye.li@nxp.com>
> >
> > RNG parameters are reconfigured.
> > - For TRNG to generate 256 bits of entropy, RNG TRNG Seed Control register
> > is configured to have reduced SAMP_SIZE from default 2500 to 512. it is
> > number of entropy samples that will be taken during Entropy generation.
> > - self-test registers(Monobit Limit, Poker Range, Run Length Limit)
> > are synchronized with new RTSDCTL[SAMP_SIZE] of 512.
> >
> > TRNG time is caluculated based on sample size.
>
> Typo: caluculated -> calculated
>
> > time required to generate entropy is reduced and hwrng performance
> > improved from 0.3 kB/s to 1.3 kB/s.
>
> Is there any degradation in passed/failed FIPS 140-2 test count? Can you provide
> some results from at least rngtest run?
>
> >
> > Signed-off-by: Ye Li <ye.li@nxp.com>
> > Acked-by: Gaurav Jain <gaurav.jain@nxp.com>>
> > ---
> > drivers/crypto/fsl/jr.c | 102 +++++++++++++++++++++++++++++++++-------
> > include/fsl_sec.h | 1 +
> > 2 files changed, 87 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index
> > a84440ab10..e5346a84a4 100644
> > --- a/drivers/crypto/fsl/jr.c
> > +++ b/drivers/crypto/fsl/jr.c
> > @@ -603,30 +603,100 @@ static u8 get_rng_vid(ccsr_sec_t *sec)
> > */
> > static void kick_trng(int ent_delay, ccsr_sec_t *sec) {
> > + u32 samples = 512; /* number of bits to generate and test */
> > + u32 mono_min = 195;
> > + u32 mono_max = 317;
> > + u32 mono_range = mono_max - mono_min;
> > + u32 poker_min = 1031;
> > + u32 poker_max = 1600;
> > + u32 poker_range = poker_max - poker_min + 1;
> > + u32 retries = 2;
> > + u32 lrun_max = 32;
> > + s32 run_1_min = 27;
> > + s32 run_1_max = 107;
> > + s32 run_1_range = run_1_max - run_1_min;
> > + s32 run_2_min = 7;
> > + s32 run_2_max = 62;
> > + s32 run_2_range = run_2_max - run_2_min;
> > + s32 run_3_min = 0;
> > + s32 run_3_max = 39;
> > + s32 run_3_range = run_3_max - run_3_min;
> > + s32 run_4_min = -1;
> > + s32 run_4_max = 26;
> > + s32 run_4_range = run_4_max - run_4_min;
> > + s32 run_5_min = -1;
> > + s32 run_5_max = 18;
> > + s32 run_5_range = run_5_max - run_5_min;
> > + s32 run_6_min = -1;
> > + s32 run_6_max = 17;
> > + s32 run_6_range = run_6_max - run_6_min;
>
> I have a feeling that this whole block of local variables can be simplified. I'm not
> sure it is required to list this so detailed.
>
> You can attempt to define those values in header file and use macros to
> compute bound conditions, rather than allocating this on the stack here.
>
> > + u32 val;
> > +
> > struct rng4tst __iomem *rng =
> > (struct rng4tst __iomem *)&sec->rng;
> > - u32 val;
> >
> > - /* put RNG4 into program mode */
> > - sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
> > - /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
> > - * length (in system clocks) of each Entropy sample taken
> > - * */
> > + /* Put RNG in program mode */
> > + /* Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
> > + * properly invalidate the entropy in the entropy register and
> > + * force re-generation.
> > + */
> > + sec_setbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
> > +
> > + /* Configure the RNG Entropy Delay
> > + * Performance-wise, it does not make sense to
> > + * set the delay to a value that is lower
> > + * than the last one that worked (i.e. the state handles
> > + * were instantiated properly. Thus, instead of wasting
> > + * time trying to set the values controlling the sample
> > + * frequency, the function simply returns.
> > + */
> > val = sec_in32(&rng->rtsdctl);
> > - val = (val & ~RTSDCTL_ENT_DLY_MASK) |
> > - (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
> > + val &= RTSDCTL_ENT_DLY_MASK;
> > + val >>= RTSDCTL_ENT_DLY_SHIFT;
> > + if (ent_delay < val) {
> > + /* Put RNG4 into run mode */
> > + sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
> > + return;
> > + }
> > +
> > + val = (ent_delay << RTSDCTL_ENT_DLY_SHIFT) | samples;
> > sec_out32(&rng->rtsdctl, val);
> > - /* min. freq. count, equal to 1/4 of the entropy sample length */
> > - sec_out32(&rng->rtfreqmin, ent_delay >> 2);
> > - /* disable maximum frequency count */
> > - sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
> > +
> > + /*
> > + * Recommended margins (min,max) for freq. count:
> > + * freq_mul = RO_freq / TRNG_clk_freq
> > + * rtfrqmin = (ent_delay x freq_mul) >> 1;
> > + * rtfrqmax = (ent_delay x freq_mul) << 3;
> > + * Given current deployments of CAAM in i.MX SoCs, and to simplify
> > + * the configuration, we consider [1,16] to be a safe interval
>
> Statement "... we consider ..." should be perhaps extended with justification on
> how this conclusion was made. Some test results (either here in the comment or
> in commit message) would be beneficial to see.
>
> > + * for the freq_mul and the limits of the interval are used to compute
> > + * rtfrqmin, rtfrqmax
> > + */
> > + sec_out32(&rng->rtfreqmin, ent_delay >> 1);
> > + sec_out32(&rng->rtfreqmax, ent_delay << 7);
> > +
> > + sec_out32(&rng->rtscmisc, (retries << 16) | lrun_max);
> > + sec_out32(&rng->rtpkrmax, poker_max);
> > + sec_out32(&rng->rtpkrrng, poker_range);
> > + sec_out32(&rng->rsvd1[0], (mono_range << 16) | mono_max);
> > + sec_out32(&rng->rsvd1[1], (run_1_range << 16) | run_1_max);
> > + sec_out32(&rng->rsvd1[2], (run_2_range << 16) | run_2_max);
> > + sec_out32(&rng->rsvd1[3], (run_3_range << 16) | run_3_max);
> > + sec_out32(&rng->rsvd1[4], (run_4_range << 16) | run_4_max);
> > + sec_out32(&rng->rsvd1[5], (run_5_range << 16) | run_5_max);
> > + sec_out32(&rng->rsvd1[6], (run_6_range << 16) | run_6_max);
>
> Writing in reserved area is not a good idea. Those registers are defined in HW,
> can you please define them also in the header file?
>
> > +
> > + val = sec_in32(&rng->rtmctl);
> > /*
> > - * select raw sampling in both entropy shifter
> > + * Select raw sampling in both entropy shifter
>
> This change is not needed, otherwise please adjust all comments in original file,
> as for example comment below also starts with small letter...
>
> > * and statistical checker
> > */
> > - sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
>
> The only usage of RTMCTL_SAMP_MODE_RAW_ES_SC is dropped here, please
> remove it from include/fsl_sec.h as well.
>
> > - /* put RNG4 into run mode */
> > - sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
> > + val &= ~RTMCTL_SAMP_MODE_INVALID;
> > + val |= RTMCTL_SAMP_MODE_RAW_ES_SC;
> > + /* Put RNG4 into run mode */
> > + val &= ~(RTMCTL_PRGM | RTMCTL_ACC);
>
> BIT() macro for both new and existing defines?
>
> > + /*test with sample mode only */
> > + sec_out32(&rng->rtmctl, val);
> > }
> >
> > static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec) diff --git
> > a/include/fsl_sec.h b/include/fsl_sec.h index 7b6e3e2c20..2b3239414a
> > 100644
> > --- a/include/fsl_sec.h
> > +++ b/include/fsl_sec.h
> > @@ -34,6 +34,7 @@
> > #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
> > /* RNG4 TRNG test registers */
> > struct rng4tst {
> > +#define RTMCTL_ACC 0x20
> > #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode
> */
> > #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von
> Neumann data in
> > both entropy shifter
> > and
> > --
> > 2.17.1
>
> -- andrey
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 12/15] Layerscape: Enable Job ring driver model.
2022-01-11 5:41 ` [EXT] " Gaurav Jain
@ 2022-01-11 7:22 ` Michael Walle
2022-01-11 11:34 ` Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: Michael Walle @ 2022-01-11 7:22 UTC (permalink / raw)
To: Gaurav Jain
Cc: Shengzhou Liu, Varun Sethi, Adrian Alonso, Alison Wang,
Andy Tang, festevam, Franck Lenormand, Horia Geanta, Ji Luo,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
sbabic, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx, Wasim Khan,
Ye Li
Hi Guarav,
Am 2022-01-11 06:41, schrieb Gaurav Jain:
>> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index
>> > 7ce2bbc954..30a34bdd08 100644
>> > --- a/arch/arm/Kconfig
>> > +++ b/arch/arm/Kconfig
>> > @@ -1504,6 +1504,8 @@ config TARGET_LS1028AQDS
>> > select ARCH_SUPPORT_TFABOOT
>> > select BOARD_LATE_INIT
>> > select GPIO_EXTRA_HEADER
>> > + select FSL_CAAM
>> > + select MISC
>>
>> This looks wrong. FSL_CAAM should depend on MISC, no?
> FSL_CAAM is to enable the CAAM driver.
> Caam driver is developed using misc uclass and MISC config is required
> to enable DM for misc uclass.
> Some platforms do not have driver model support so in that case CAAM
> can function without misc.
then it's "select MISC if DM" in "config FSL_CAAM".
>>
>> > help
>> > Support for Freescale LS1028AQDS platform
>> > The LS1028A Development System (QDS) is a high-performance @@
>> > -1518,6 +1520,8 @@ config TARGET_LS1028ARDB
>> > select ARCH_SUPPORT_TFABOOT
>> > select BOARD_LATE_INIT
>> > select GPIO_EXTRA_HEADER
>> > + select FSL_CAAM
>> > + select MISC
>> > help
>> > Support for Freescale LS1028ARDB platform
>> > The LS1028A Development System (RDB) is a high-performance
>> > diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig
>> > b/arch/arm/cpu/armv7/ls102xa/Kconfig
>> > index f919d02db4..ca006e069f 100644
>> > --- a/arch/arm/cpu/armv7/ls102xa/Kconfig
>> > +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
>> > @@ -21,6 +21,9 @@ config ARCH_LS1021A
>> > select SYS_FSL_SRDS_1
>> > select SYS_HAS_SERDES
>> > select SYS_I2C_MXC
>> > + select FSL_CAAM
>>
>> While above you added that dependency to an indivdual board, here you
>> are
>> adding that dependency to all boards using this architecture. The same
>> is true
>> for all the other "config ARCH_*" symbols. What if someone wants to
>> build a
>> bootloader without CAAM support? This should really go into the
>> defconfigs for
>> these boards.
> CAAM is only initialized at boot which does not imply to use caam in
> every operation.
I don't understand. You're including the CAAM driver here
unconditionally,
even if it's not needed. That is, it is increasing the binary size for
every board which is using one of these SoCs. Please move it to the
defconfigs.
-michael
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 12/15] Layerscape: Enable Job ring driver model.
2022-01-11 7:22 ` Michael Walle
@ 2022-01-11 11:34 ` Gaurav Jain
0 siblings, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-01-11 11:34 UTC (permalink / raw)
To: Michael Walle
Cc: Shengzhou Liu, Varun Sethi, Adrian Alonso, Alison Wang,
Andy Tang, festevam, Franck Lenormand, Horia Geanta, Ji Luo,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
sbabic, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx, Wasim Khan,
Ye Li
Hi Michael
> -----Original Message-----
> From: Michael Walle <michael@walle.cc>
> Sent: Tuesday, January 11, 2022 12:52 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>
> Cc: Shengzhou Liu <shengzhou.liu@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Alison Wang
> <alison.wang@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> festevam@gmail.com; Franck Lenormand <franck.lenormand@nxp.com>; Horia
> Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Meenakshi
> Aggarwal <meenakshi.aggarwal@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Rajesh
> Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> sbabic@denx.de; Silvano Di Ninno <silvano.dininno@nxp.com>;
> sjg@chromium.org; u-boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>;
> Wasim Khan <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>
> Subject: Re: [EXT] Re: [PATCH v8 12/15] Layerscape: Enable Job ring driver
> model.
>
> Caution: EXT Email
>
> Hi Guarav,
>
> Am 2022-01-11 06:41, schrieb Gaurav Jain:
> >> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index
> >> > 7ce2bbc954..30a34bdd08 100644
> >> > --- a/arch/arm/Kconfig
> >> > +++ b/arch/arm/Kconfig
> >> > @@ -1504,6 +1504,8 @@ config TARGET_LS1028AQDS
> >> > select ARCH_SUPPORT_TFABOOT
> >> > select BOARD_LATE_INIT
> >> > select GPIO_EXTRA_HEADER
> >> > + select FSL_CAAM
> >> > + select MISC
> >>
> >> This looks wrong. FSL_CAAM should depend on MISC, no?
> > FSL_CAAM is to enable the CAAM driver.
> > Caam driver is developed using misc uclass and MISC config is required
> > to enable DM for misc uclass.
> > Some platforms do not have driver model support so in that case CAAM
> > can function without misc.
>
> then it's "select MISC if DM" in "config FSL_CAAM".
Done in version 9.
>
> >>
> >> > help
> >> > Support for Freescale LS1028AQDS platform
> >> > The LS1028A Development System (QDS) is a high-performance
> >> > @@
> >> > -1518,6 +1520,8 @@ config TARGET_LS1028ARDB
> >> > select ARCH_SUPPORT_TFABOOT
> >> > select BOARD_LATE_INIT
> >> > select GPIO_EXTRA_HEADER
> >> > + select FSL_CAAM
> >> > + select MISC
> >> > help
> >> > Support for Freescale LS1028ARDB platform
> >> > The LS1028A Development System (RDB) is a high-performance
> >> > diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig
> >> > b/arch/arm/cpu/armv7/ls102xa/Kconfig
> >> > index f919d02db4..ca006e069f 100644
> >> > --- a/arch/arm/cpu/armv7/ls102xa/Kconfig
> >> > +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
> >> > @@ -21,6 +21,9 @@ config ARCH_LS1021A
> >> > select SYS_FSL_SRDS_1
> >> > select SYS_HAS_SERDES
> >> > select SYS_I2C_MXC
> >> > + select FSL_CAAM
> >>
> >> While above you added that dependency to an indivdual board, here you
> >> are adding that dependency to all boards using this architecture. The
> >> same is true for all the other "config ARCH_*" symbols. What if
> >> someone wants to build a bootloader without CAAM support? This should
> >> really go into the defconfigs for these boards.
> > CAAM is only initialized at boot which does not imply to use caam in
> > every operation.
>
> I don't understand. You're including the CAAM driver here unconditionally, even
> if it's not needed. That is, it is increasing the binary size for every board which is
> using one of these SoCs. Please move it to the defconfigs.
Done in version 9.
>
> -michael
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-01-10 12:27 ` [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
@ 2022-02-05 14:16 ` Stefano Babic
2022-02-07 7:13 ` [EXT] " Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: Stefano Babic @ 2022-02-05 14:16 UTC (permalink / raw)
To: Gaurav Jain, u-boot
Cc: Stefano Babic, Fabio Estevam, Peng Fan, Simon Glass,
Priyanka Jain, Ye Li, Horia Geanta, Ji Luo, Franck Lenormand,
Silvano Di Ninno, Sahil malhotra, Pankaj Gupta, Varun Sethi,
NXP i . MX U-Boot Team, Shengzhou Liu, Mingkai Hu, Rajesh Bhagat,
Meenakshi Aggarwal, Wasim Khan, Alison Wang, Pramod Kumar,
Tang Yuantian, Adrian Alonso, Vladimir Oltean, Marek Vasut
Hi Gaurav,
rather I still have issues to run CI with this applied. The reason is
that this adds an overhead to SPL and it breaks the board imx6dl_mamoj
because SPL exceeds the maximum size for a DL SOC.
See https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/387370
I do not know if it is possible to drop some features from SPL for this
board (Added Marek as board maintainer).
Best regards,
Stefano
On 10.01.22 13:27, Gaurav Jain wrote:
> added device tree support for job ring driver.
> sec is initialized based on job ring information processed
> from device tree.
>
> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> ---
> drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++++--------------
> drivers/crypto/fsl/jr.h | 31 +++-
> 2 files changed, 240 insertions(+), 114 deletions(-)
>
> diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
> index 22b649219e..8103987425 100644
> --- a/drivers/crypto/fsl/jr.c
> +++ b/drivers/crypto/fsl/jr.c
> @@ -1,7 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> * Copyright 2008-2014 Freescale Semiconductor, Inc.
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
> *
> * Based on CAAM driver in drivers/crypto/caam in Linux
> */
> @@ -11,7 +11,6 @@
> #include <linux/kernel.h>
> #include <log.h>
> #include <malloc.h>
> -#include "fsl_sec.h"
> #include "jr.h"
> #include "jobdesc.h"
> #include "desc_constr.h"
> @@ -21,7 +20,10 @@
> #include <asm/cache.h>
> #include <asm/fsl_pamu.h>
> #endif
> +#include <dm.h>
> #include <dm/lists.h>
> +#include <dm/root.h>
> +#include <dm/device-internal.h>
> #include <linux/delay.h>
>
> #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
> @@ -35,20 +37,29 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
> #endif
> };
>
> +#if CONFIG_IS_ENABLED(DM)
> +struct udevice *caam_dev;
> +#else
> #define SEC_ADDR(idx) \
> (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
>
> #define SEC_JR0_ADDR(idx) \
> (ulong)(SEC_ADDR(idx) + \
> (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
> +struct caam_regs caam_st;
> +#endif
>
> -struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> +static inline u32 jr_start_reg(u8 jrid)
> +{
> + return (1 << jrid);
> +}
>
> -static inline void start_jr0(uint8_t sec_idx)
> +static inline void start_jr(struct caam_regs *caam)
> {
> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> + ccsr_sec_t *sec = caam->sec;
> u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
> u32 scfgr = sec_in32(&sec->scfgr);
> + u32 jrstart = jr_start_reg(caam->jrid);
>
> if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
> /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
> @@ -56,23 +67,16 @@ static inline void start_jr0(uint8_t sec_idx)
> */
> if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
> (scfgr & SEC_SCFGR_VIRT_EN))
> - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
> + sec_out32(&sec->jrstartr, jrstart);
> } else {
> /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
> if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
> - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
> + sec_out32(&sec->jrstartr, jrstart);
> }
> }
>
> -static inline void jr_reset_liodn(uint8_t sec_idx)
> +static inline void jr_disable_irq(struct jr_regs *regs)
> {
> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> - sec_out32(&sec->jrliodnr[0].ls, 0);
> -}
> -
> -static inline void jr_disable_irq(uint8_t sec_idx)
> -{
> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> uint32_t jrcfg = sec_in32(®s->jrcfg1);
>
> jrcfg = jrcfg | JR_INTMASK;
> @@ -80,10 +84,10 @@ static inline void jr_disable_irq(uint8_t sec_idx)
> sec_out32(®s->jrcfg1, jrcfg);
> }
>
> -static void jr_initregs(uint8_t sec_idx)
> +static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
> {
> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> - struct jobring *jr = &jr0[sec_idx];
> + struct jr_regs *regs = caam->regs;
> + struct jobring *jr = &caam->jr[sec_idx];
> caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
> caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
>
> @@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx)
> sec_out32(®s->irs, JR_SIZE);
>
> if (!jr->irq)
> - jr_disable_irq(sec_idx);
> + jr_disable_irq(regs);
> }
>
> -static int jr_init(uint8_t sec_idx)
> +static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
> {
> - struct jobring *jr = &jr0[sec_idx];
> + struct jobring *jr = &caam->jr[sec_idx];
>
> memset(jr, 0, sizeof(struct jobring));
>
> - jr->jq_id = DEFAULT_JR_ID;
> + jr->jq_id = caam->jrid;
> jr->irq = DEFAULT_IRQ;
>
> #ifdef CONFIG_FSL_CORENET
> @@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx)
> memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
> memset(jr->output_ring, 0, jr->op_size);
>
> - start_jr0(sec_idx);
> -
> - jr_initregs(sec_idx);
> -
> - return 0;
> -}
> -
> -static int jr_sw_cleanup(uint8_t sec_idx)
> -{
> - struct jobring *jr = &jr0[sec_idx];
> -
> - jr->head = 0;
> - jr->tail = 0;
> - jr->read_idx = 0;
> - jr->write_idx = 0;
> - memset(jr->info, 0, sizeof(jr->info));
> - memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
> - memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
> -
> - return 0;
> -}
> -
> -static int jr_hw_reset(uint8_t sec_idx)
> -{
> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> - uint32_t timeout = 100000;
> - uint32_t jrint, jrcr;
> -
> - sec_out32(®s->jrcr, JRCR_RESET);
> - do {
> - jrint = sec_in32(®s->jrint);
> - } while (((jrint & JRINT_ERR_HALT_MASK) ==
> - JRINT_ERR_HALT_INPROGRESS) && --timeout);
> -
> - jrint = sec_in32(®s->jrint);
> - if (((jrint & JRINT_ERR_HALT_MASK) !=
> - JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
> - return -1;
> -
> - timeout = 100000;
> - sec_out32(®s->jrcr, JRCR_RESET);
> - do {
> - jrcr = sec_in32(®s->jrcr);
> - } while ((jrcr & JRCR_RESET) && --timeout);
> -
> - if (timeout == 0)
> - return -1;
> + start_jr(caam);
> + jr_initregs(sec_idx, caam);
>
> return 0;
> }
> @@ -188,10 +147,10 @@ static int jr_hw_reset(uint8_t sec_idx)
> /* -1 --- error, can't enqueue -- no space available */
> static int jr_enqueue(uint32_t *desc_addr,
> void (*callback)(uint32_t status, void *arg),
> - void *arg, uint8_t sec_idx)
> + void *arg, uint8_t sec_idx, struct caam_regs *caam)
> {
> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> - struct jobring *jr = &jr0[sec_idx];
> + struct jr_regs *regs = caam->regs;
> + struct jobring *jr = &caam->jr[sec_idx];
> int head = jr->head;
> uint32_t desc_word;
> int length = desc_len(desc_addr);
> @@ -263,10 +222,10 @@ static int jr_enqueue(uint32_t *desc_addr,
> return 0;
> }
>
> -static int jr_dequeue(int sec_idx)
> +static int jr_dequeue(int sec_idx, struct caam_regs *caam)
> {
> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> - struct jobring *jr = &jr0[sec_idx];
> + struct jr_regs *regs = caam->regs;
> + struct jobring *jr = &caam->jr[sec_idx];
> int head = jr->head;
> int tail = jr->tail;
> int idx, i, found;
> @@ -349,14 +308,18 @@ static void desc_done(uint32_t status, void *arg)
> {
> struct result *x = arg;
> x->status = status;
> -#ifndef CONFIG_SPL_BUILD
> caam_jr_strstatus(status);
> -#endif
> x->done = 1;
> }
>
> static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
> {
> + struct caam_regs *caam;
> +#if CONFIG_IS_ENABLED(DM)
> + caam = dev_get_priv(caam_dev);
> +#else
> + caam = &caam_st;
> +#endif
> unsigned long long timeval = 0;
> unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
> struct result op;
> @@ -364,7 +327,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
>
> memset(&op, 0, sizeof(op));
>
> - ret = jr_enqueue(desc, desc_done, &op, sec_idx);
> + ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
> if (ret) {
> debug("Error in SEC enq\n");
> ret = JQ_ENQ_ERR;
> @@ -375,7 +338,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
> udelay(1);
> timeval += 1;
>
> - ret = jr_dequeue(sec_idx);
> + ret = jr_dequeue(sec_idx, caam);
> if (ret) {
> debug("Error in SEC deq\n");
> ret = JQ_DEQ_ERR;
> @@ -402,13 +365,62 @@ int run_descriptor_jr(uint32_t *desc)
> return run_descriptor_jr_idx(desc, 0);
> }
>
> +static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam)
> +{
> + struct jobring *jr = &caam->jr[sec_idx];
> +
> + jr->head = 0;
> + jr->tail = 0;
> + jr->read_idx = 0;
> + jr->write_idx = 0;
> + memset(jr->info, 0, sizeof(jr->info));
> + memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
> + memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
> +
> + return 0;
> +}
> +
> +static int jr_hw_reset(struct jr_regs *regs)
> +{
> + uint32_t timeout = 100000;
> + uint32_t jrint, jrcr;
> +
> + sec_out32(®s->jrcr, JRCR_RESET);
> + do {
> + jrint = sec_in32(®s->jrint);
> + } while (((jrint & JRINT_ERR_HALT_MASK) ==
> + JRINT_ERR_HALT_INPROGRESS) && --timeout);
> +
> + jrint = sec_in32(®s->jrint);
> + if (((jrint & JRINT_ERR_HALT_MASK) !=
> + JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
> + return -1;
> +
> + timeout = 100000;
> + sec_out32(®s->jrcr, JRCR_RESET);
> + do {
> + jrcr = sec_in32(®s->jrcr);
> + } while ((jrcr & JRCR_RESET) && --timeout);
> +
> + if (timeout == 0)
> + return -1;
> +
> + return 0;
> +}
> +
> static inline int jr_reset_sec(uint8_t sec_idx)
> {
> - if (jr_hw_reset(sec_idx) < 0)
> + struct caam_regs *caam;
> +#if CONFIG_IS_ENABLED(DM)
> + caam = dev_get_priv(caam_dev);
> +#else
> + caam = &caam_st;
> +#endif
> + if (jr_hw_reset(caam->regs) < 0)
> return -1;
>
> /* Clean up the jobring structure maintained by software */
> - jr_sw_cleanup(sec_idx);
> + jr_sw_cleanup(sec_idx, caam);
>
> return 0;
> }
> @@ -418,9 +430,15 @@ int jr_reset(void)
> return jr_reset_sec(0);
> }
>
> -static inline int sec_reset_idx(uint8_t sec_idx)
> +int sec_reset(void)
> {
> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> + struct caam_regs *caam;
> +#if CONFIG_IS_ENABLED(DM)
> + caam = dev_get_priv(caam_dev);
> +#else
> + caam = &caam_st;
> +#endif
> + ccsr_sec_t *sec = caam->sec;
> uint32_t mcfgr = sec_in32(&sec->mcfgr);
> uint32_t timeout = 100000;
>
> @@ -446,11 +464,7 @@ static inline int sec_reset_idx(uint8_t sec_idx)
>
> return 0;
> }
> -int sec_reset(void)
> -{
> - return sec_reset_idx(0);
> -}
> -#ifndef CONFIG_SPL_BUILD
> +
> static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
> {
> u32 *desc;
> @@ -496,12 +510,11 @@ static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
> return ret;
> }
>
> -static int instantiate_rng(u8 sec_idx, int gen_sk)
> +static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int gen_sk)
> {
> u32 *desc;
> u32 rdsta_val;
> int ret = 0, sh_idx, size;
> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
> struct rng4tst __iomem *rng =
> (struct rng4tst __iomem *)&sec->rng;
>
> @@ -554,9 +567,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk)
> return ret;
> }
>
> -static u8 get_rng_vid(uint8_t sec_idx)
> +static u8 get_rng_vid(ccsr_sec_t *sec)
> {
> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> u8 vid;
>
> if (caam_get_era() < 10) {
> @@ -574,9 +586,8 @@ static u8 get_rng_vid(uint8_t sec_idx)
> * By default, the TRNG runs for 200 clocks per sample;
> * 1200 clocks per sample generates better entropy.
> */
> -static void kick_trng(int ent_delay, uint8_t sec_idx)
> +static void kick_trng(int ent_delay, ccsr_sec_t *sec)
> {
> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
> struct rng4tst __iomem *rng =
> (struct rng4tst __iomem *)&sec->rng;
> u32 val;
> @@ -603,10 +614,9 @@ static void kick_trng(int ent_delay, uint8_t sec_idx)
> sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
> }
>
> -static int rng_init(uint8_t sec_idx)
> +static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
> {
> int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
> struct rng4tst __iomem *rng =
> (struct rng4tst __iomem *)&sec->rng;
> u32 inst_handles;
> @@ -624,7 +634,7 @@ static int rng_init(uint8_t sec_idx)
> * the TRNG parameters.
> */
> if (!inst_handles) {
> - kick_trng(ent_delay, sec_idx);
> + kick_trng(ent_delay, sec);
> ent_delay += 400;
> }
> /*
> @@ -634,7 +644,7 @@ static int rng_init(uint8_t sec_idx)
> * interval, leading to a sucessful initialization of
> * the RNG.
> */
> - ret = instantiate_rng(sec_idx, gen_sk);
> + ret = instantiate_rng(sec_idx, sec, gen_sk);
> } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
> if (ret) {
> printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
> @@ -646,13 +656,28 @@ static int rng_init(uint8_t sec_idx)
>
> return ret;
> }
> -#endif
> +
> int sec_init_idx(uint8_t sec_idx)
> {
> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> - uint32_t mcr = sec_in32(&sec->mcfgr);
> int ret = 0;
> -
> + struct caam_regs *caam;
> +#if CONFIG_IS_ENABLED(DM)
> + if (!caam_dev) {
> + printf("caam_jr: caam not found\n");
> + return -1;
> + }
> + caam = dev_get_priv(caam_dev);
> +#else
> + caam_st.sec = (void *)SEC_ADDR(sec_idx);
> + caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> + caam_st.jrid = 0;
> + caam = &caam_st;
> +#endif
> + ccsr_sec_t *sec = caam->sec;
> + uint32_t mcr = sec_in32(&sec->mcfgr);
> +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> + uint32_t jrdid_ms = 0;
> +#endif
> #ifdef CONFIG_FSL_CORENET
> uint32_t liodnr;
> uint32_t liodn_ns;
> @@ -682,6 +707,11 @@ int sec_init_idx(uint8_t sec_idx)
> mcr |= (1 << MCFGR_PS_SHIFT);
> #endif
> sec_out32(&sec->mcfgr, mcr);
> +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> + jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID;
> + sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms);
> +#endif
> + jr_reset();
>
> #ifdef CONFIG_FSL_CORENET
> #ifdef CONFIG_SPL_BUILD
> @@ -693,20 +723,19 @@ int sec_init_idx(uint8_t sec_idx)
> liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
> liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
>
> - liodnr = sec_in32(&sec->jrliodnr[0].ls) &
> + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
> ~(JRNSLIODN_MASK | JRSLIODN_MASK);
> liodnr = liodnr |
> (liodn_ns << JRNSLIODN_SHIFT) |
> (liodn_s << JRSLIODN_SHIFT);
> - sec_out32(&sec->jrliodnr[0].ls, liodnr);
> + sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
> #else
> - liodnr = sec_in32(&sec->jrliodnr[0].ls);
> + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
> liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
> liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
> #endif
> #endif
> -
> - ret = jr_init(sec_idx);
> + ret = jr_init(sec_idx, caam);
> if (ret < 0) {
> printf("SEC%u: initialization failed\n", sec_idx);
> return -1;
> @@ -719,9 +748,9 @@ int sec_init_idx(uint8_t sec_idx)
>
> pamu_enable();
> #endif
> -#ifndef CONFIG_SPL_BUILD
> - if (get_rng_vid(sec_idx) >= 4) {
> - if (rng_init(sec_idx) < 0) {
> +
> + if (get_rng_vid(caam->sec) >= 4) {
> + if (rng_init(sec_idx, caam->sec) < 0) {
> printf("SEC%u: RNG instantiation failed\n", sec_idx);
> return -1;
> }
> @@ -735,7 +764,6 @@ int sec_init_idx(uint8_t sec_idx)
>
> printf("SEC%u: RNG instantiated\n", sec_idx);
> }
> -#endif
> return ret;
> }
>
> @@ -743,3 +771,76 @@ int sec_init(void)
> {
> return sec_init_idx(0);
> }
> +
> +#if CONFIG_IS_ENABLED(DM)
> +static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf)
> +{
> + if (request != CAAM_JR_RUN_DESC)
> + return -ENOSYS;
> +
> + return run_descriptor_jr(buf);
> +}
> +
> +static int caam_jr_probe(struct udevice *dev)
> +{
> + struct caam_regs *caam = dev_get_priv(dev);
> + fdt_addr_t addr;
> + ofnode node;
> + unsigned int jr_node = 0;
> +
> + caam_dev = dev;
> +
> + addr = dev_read_addr(dev);
> + if (addr == FDT_ADDR_T_NONE) {
> + printf("caam_jr: crypto not found\n");
> + return -EINVAL;
> + }
> + caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
> + caam->regs = (struct jr_regs *)caam->sec;
> +
> + /* Check for enabled job ring node */
> + ofnode_for_each_subnode(node, dev_ofnode(dev)) {
> + if (!ofnode_is_available(node))
> + continue;
> +
> + jr_node = ofnode_read_u32_default(node, "reg", -1);
> + if (jr_node > 0) {
> + caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
> + while (!(jr_node & 0x0F))
> + jr_node = jr_node >> 4;
> +
> + caam->jrid = jr_node - 1;
> + break;
> + }
> + }
> +
> + if (sec_init())
> + printf("\nsec_init failed!\n");
> +
> + return 0;
> +}
> +
> +static int caam_jr_bind(struct udevice *dev)
> +{
> + return 0;
> +}
> +
> +static const struct misc_ops caam_jr_ops = {
> + .ioctl = caam_jr_ioctl,
> +};
> +
> +static const struct udevice_id caam_jr_match[] = {
> + { .compatible = "fsl,sec-v4.0" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(caam_jr) = {
> + .name = "caam_jr",
> + .id = UCLASS_MISC,
> + .of_match = caam_jr_match,
> + .ops = &caam_jr_ops,
> + .bind = caam_jr_bind,
> + .probe = caam_jr_probe,
> + .priv_auto = sizeof(struct caam_regs),
> +};
> +#endif
> diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
> index 1047aa772c..3eb7be79da 100644
> --- a/drivers/crypto/fsl/jr.h
> +++ b/drivers/crypto/fsl/jr.h
> @@ -1,6 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
> * Copyright 2008-2014 Freescale Semiconductor, Inc.
> + * Copyright 2021 NXP
> *
> */
>
> @@ -8,7 +9,9 @@
> #define __JR_H
>
> #include <linux/compiler.h>
> +#include "fsl_sec.h"
> #include "type.h"
> +#include <misc.h>
>
> #define JR_SIZE 4
> /* Timeout currently defined as 10 sec */
> @@ -35,12 +38,21 @@
> #define JRSLIODN_SHIFT 0
> #define JRSLIODN_MASK 0x00000fff
>
> -#define JQ_DEQ_ERR -1
> -#define JQ_DEQ_TO_ERR -2
> -#define JQ_ENQ_ERR -3
> +#define JRDID_MS_PRIM_DID BIT(0)
> +#define JRDID_MS_PRIM_TZ BIT(4)
> +#define JRDID_MS_TZ_OWN BIT(15)
> +
> +#define JQ_DEQ_ERR (-1)
> +#define JQ_DEQ_TO_ERR (-2)
> +#define JQ_ENQ_ERR (-3)
>
> #define RNG4_MAX_HANDLES 2
>
> +enum {
> + /* Run caam jobring descriptor(in buf) */
> + CAAM_JR_RUN_DESC,
> +};
> +
> struct op_ring {
> caam_dma_addr_t desc;
> uint32_t status;
> @@ -102,6 +114,19 @@ struct result {
> uint32_t status;
> };
>
> +/*
> + * struct caam_regs - CAAM initialization register interface
> + *
> + * Interface to caam memory map, jobring register, jobring storage.
> + */
> +struct caam_regs {
> + ccsr_sec_t *sec; /*caam initialization registers*/
> + struct jr_regs *regs; /*jobring configuration registers*/
> + u8 jrid; /*id to identify a jobring*/
> + /*Private sub-storage for a single JobR*/
> + struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> +};
> +
> void caam_jr_strstatus(u32 status);
> int run_descriptor_jr(uint32_t *desc);
>
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-02-05 14:16 ` Stefano Babic
@ 2022-02-07 7:13 ` Gaurav Jain
2022-02-11 9:38 ` Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-02-07 7:13 UTC (permalink / raw)
To: Stefano Babic, u-boot, Marek Vasut
Cc: Fabio Estevam, Peng Fan, Simon Glass, Priyanka Jain, Ye Li,
Horia Geanta, Ji Luo, Franck Lenormand, Silvano Di Ninno,
Sahil Malhotra, Pankaj Gupta, Varun Sethi, dl-uboot-imx,
Shengzhou Liu, Mingkai Hu, Rajesh Bhagat, Meenakshi Aggarwal,
Wasim Khan, Alison Wang, Pramod Kumar, Andy Tang, Adrian Alonso,
Vladimir Oltean
Hello Marek
> -----Original Message-----
> From: Stefano Babic <sbabic@denx.de>
> Sent: Saturday, February 5, 2022 7:46 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>; u-boot@lists.denx.de
> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>;
> Peng Fan <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Priyanka
> Jain <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
> <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> <franck.lenormand@nxp.com>; Silvano Di Ninno <silvano.dininno@nxp.com>;
> Sahil Malhotra <sahil.malhotra@nxp.com>; Pankaj Gupta
> <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-uboot-imx
> <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>; Meenakshi
> Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean
> <olteanv@gmail.com>; Marek Vasut <marex@denx.de>
> Subject: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring
> driver model
>
> Caution: EXT Email
>
> Hi Gaurav,
>
> rather I still have issues to run CI with this applied. The reason is that this adds an
> overhead to SPL and it breaks the board imx6dl_mamoj because SPL exceeds the
> maximum size for a DL SOC.
>
> See
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsource.d
> enx.de%2Fu-boot%2Fcustodians%2Fu-boot-imx%2F-
> %2Fjobs%2F387370&data=04%7C01%7Cgaurav.jain%40nxp.com%7C3a273
> 1dd27fc4bebcad308d9e8b21464%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C
> 0%7C0%7C637796673834942697%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&am
> p;sdata=pI%2F%2FlNtrdrGCa8sSvcr6uNu4jze7pzDqZtI52FIDj50%3D&reserve
> d=0
>
> I do not know if it is possible to drop some features from SPL for this board
> (Added Marek as board maintainer).
CONFIG_IMX_HAB is enabled for imx6dl_mamoj. So CAAM is built for SPL, results in increased size.
However CAAM is not initialized in SPL. As Stefano suggested, Can you drop some features from SPL?
Regards
Gaurav Jain
>
> Best regards,
> Stefano
>
> On 10.01.22 13:27, Gaurav Jain wrote:
> > added device tree support for job ring driver.
> > sec is initialized based on job ring information processed from device
> > tree.
> >
> > Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> > Reviewed-by: Ye Li <ye.li@nxp.com>
> > ---
> > drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++++--------------
> > drivers/crypto/fsl/jr.h | 31 +++-
> > 2 files changed, 240 insertions(+), 114 deletions(-)
> >
> > diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index
> > 22b649219e..8103987425 100644
> > --- a/drivers/crypto/fsl/jr.c
> > +++ b/drivers/crypto/fsl/jr.c
> > @@ -1,7 +1,7 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> > * Copyright 2008-2014 Freescale Semiconductor, Inc.
> > - * Copyright 2018 NXP
> > + * Copyright 2018, 2021 NXP
> > *
> > * Based on CAAM driver in drivers/crypto/caam in Linux
> > */
> > @@ -11,7 +11,6 @@
> > #include <linux/kernel.h>
> > #include <log.h>
> > #include <malloc.h>
> > -#include "fsl_sec.h"
> > #include "jr.h"
> > #include "jobdesc.h"
> > #include "desc_constr.h"
> > @@ -21,7 +20,10 @@
> > #include <asm/cache.h>
> > #include <asm/fsl_pamu.h>
> > #endif
> > +#include <dm.h>
> > #include <dm/lists.h>
> > +#include <dm/root.h>
> > +#include <dm/device-internal.h>
> > #include <linux/delay.h>
> >
> > #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
> > @@ -35,20 +37,29 @@ uint32_t
> sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
> > #endif
> > };
> >
> > +#if CONFIG_IS_ENABLED(DM)
> > +struct udevice *caam_dev;
> > +#else
> > #define SEC_ADDR(idx) \
> > (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
> >
> > #define SEC_JR0_ADDR(idx) \
> > (ulong)(SEC_ADDR(idx) + \
> > (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
> > +struct caam_regs caam_st;
> > +#endif
> >
> > -struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> > +static inline u32 jr_start_reg(u8 jrid) {
> > + return (1 << jrid);
> > +}
> >
> > -static inline void start_jr0(uint8_t sec_idx)
> > +static inline void start_jr(struct caam_regs *caam)
> > {
> > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > + ccsr_sec_t *sec = caam->sec;
> > u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
> > u32 scfgr = sec_in32(&sec->scfgr);
> > + u32 jrstart = jr_start_reg(caam->jrid);
> >
> > if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
> > /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or @@ -56,23
> > +67,16 @@ static inline void start_jr0(uint8_t sec_idx)
> > */
> > if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
> > (scfgr & SEC_SCFGR_VIRT_EN))
> > - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
> > + sec_out32(&sec->jrstartr, jrstart);
> > } else {
> > /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
> > if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
> > - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
> > + sec_out32(&sec->jrstartr, jrstart);
> > }
> > }
> >
> > -static inline void jr_reset_liodn(uint8_t sec_idx)
> > +static inline void jr_disable_irq(struct jr_regs *regs)
> > {
> > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > - sec_out32(&sec->jrliodnr[0].ls, 0);
> > -}
> > -
> > -static inline void jr_disable_irq(uint8_t sec_idx) -{
> > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > uint32_t jrcfg = sec_in32(®s->jrcfg1);
> >
> > jrcfg = jrcfg | JR_INTMASK;
> > @@ -80,10 +84,10 @@ static inline void jr_disable_irq(uint8_t sec_idx)
> > sec_out32(®s->jrcfg1, jrcfg);
> > }
> >
> > -static void jr_initregs(uint8_t sec_idx)
> > +static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
> > {
> > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > - struct jobring *jr = &jr0[sec_idx];
> > + struct jr_regs *regs = caam->regs;
> > + struct jobring *jr = &caam->jr[sec_idx];
> > caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
> > caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
> >
> > @@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx)
> > sec_out32(®s->irs, JR_SIZE);
> >
> > if (!jr->irq)
> > - jr_disable_irq(sec_idx);
> > + jr_disable_irq(regs);
> > }
> >
> > -static int jr_init(uint8_t sec_idx)
> > +static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
> > {
> > - struct jobring *jr = &jr0[sec_idx];
> > + struct jobring *jr = &caam->jr[sec_idx];
> >
> > memset(jr, 0, sizeof(struct jobring));
> >
> > - jr->jq_id = DEFAULT_JR_ID;
> > + jr->jq_id = caam->jrid;
> > jr->irq = DEFAULT_IRQ;
> >
> > #ifdef CONFIG_FSL_CORENET
> > @@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx)
> > memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
> > memset(jr->output_ring, 0, jr->op_size);
> >
> > - start_jr0(sec_idx);
> > -
> > - jr_initregs(sec_idx);
> > -
> > - return 0;
> > -}
> > -
> > -static int jr_sw_cleanup(uint8_t sec_idx) -{
> > - struct jobring *jr = &jr0[sec_idx];
> > -
> > - jr->head = 0;
> > - jr->tail = 0;
> > - jr->read_idx = 0;
> > - jr->write_idx = 0;
> > - memset(jr->info, 0, sizeof(jr->info));
> > - memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
> > - memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
> > -
> > - return 0;
> > -}
> > -
> > -static int jr_hw_reset(uint8_t sec_idx) -{
> > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > - uint32_t timeout = 100000;
> > - uint32_t jrint, jrcr;
> > -
> > - sec_out32(®s->jrcr, JRCR_RESET);
> > - do {
> > - jrint = sec_in32(®s->jrint);
> > - } while (((jrint & JRINT_ERR_HALT_MASK) ==
> > - JRINT_ERR_HALT_INPROGRESS) && --timeout);
> > -
> > - jrint = sec_in32(®s->jrint);
> > - if (((jrint & JRINT_ERR_HALT_MASK) !=
> > - JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
> > - return -1;
> > -
> > - timeout = 100000;
> > - sec_out32(®s->jrcr, JRCR_RESET);
> > - do {
> > - jrcr = sec_in32(®s->jrcr);
> > - } while ((jrcr & JRCR_RESET) && --timeout);
> > -
> > - if (timeout == 0)
> > - return -1;
> > + start_jr(caam);
> > + jr_initregs(sec_idx, caam);
> >
> > return 0;
> > }
> > @@ -188,10 +147,10 @@ static int jr_hw_reset(uint8_t sec_idx)
> > /* -1 --- error, can't enqueue -- no space available */
> > static int jr_enqueue(uint32_t *desc_addr,
> > void (*callback)(uint32_t status, void *arg),
> > - void *arg, uint8_t sec_idx)
> > + void *arg, uint8_t sec_idx, struct caam_regs *caam)
> > {
> > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > - struct jobring *jr = &jr0[sec_idx];
> > + struct jr_regs *regs = caam->regs;
> > + struct jobring *jr = &caam->jr[sec_idx];
> > int head = jr->head;
> > uint32_t desc_word;
> > int length = desc_len(desc_addr); @@ -263,10 +222,10 @@ static
> > int jr_enqueue(uint32_t *desc_addr,
> > return 0;
> > }
> >
> > -static int jr_dequeue(int sec_idx)
> > +static int jr_dequeue(int sec_idx, struct caam_regs *caam)
> > {
> > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > - struct jobring *jr = &jr0[sec_idx];
> > + struct jr_regs *regs = caam->regs;
> > + struct jobring *jr = &caam->jr[sec_idx];
> > int head = jr->head;
> > int tail = jr->tail;
> > int idx, i, found;
> > @@ -349,14 +308,18 @@ static void desc_done(uint32_t status, void *arg)
> > {
> > struct result *x = arg;
> > x->status = status;
> > -#ifndef CONFIG_SPL_BUILD
> > caam_jr_strstatus(status);
> > -#endif
> > x->done = 1;
> > }
> >
> > static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
> > {
> > + struct caam_regs *caam;
> > +#if CONFIG_IS_ENABLED(DM)
> > + caam = dev_get_priv(caam_dev);
> > +#else
> > + caam = &caam_st;
> > +#endif
> > unsigned long long timeval = 0;
> > unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
> > struct result op;
> > @@ -364,7 +327,7 @@ static inline int run_descriptor_jr_idx(uint32_t
> > *desc, uint8_t sec_idx)
> >
> > memset(&op, 0, sizeof(op));
> >
> > - ret = jr_enqueue(desc, desc_done, &op, sec_idx);
> > + ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
> > if (ret) {
> > debug("Error in SEC enq\n");
> > ret = JQ_ENQ_ERR;
> > @@ -375,7 +338,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc,
> uint8_t sec_idx)
> > udelay(1);
> > timeval += 1;
> >
> > - ret = jr_dequeue(sec_idx);
> > + ret = jr_dequeue(sec_idx, caam);
> > if (ret) {
> > debug("Error in SEC deq\n");
> > ret = JQ_DEQ_ERR; @@ -402,13 +365,62 @@ int
> > run_descriptor_jr(uint32_t *desc)
> > return run_descriptor_jr_idx(desc, 0);
> > }
> >
> > +static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam) {
> > + struct jobring *jr = &caam->jr[sec_idx];
> > +
> > + jr->head = 0;
> > + jr->tail = 0;
> > + jr->read_idx = 0;
> > + jr->write_idx = 0;
> > + memset(jr->info, 0, sizeof(jr->info));
> > + memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
> > + memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
> > +
> > + return 0;
> > +}
> > +
> > +static int jr_hw_reset(struct jr_regs *regs) {
> > + uint32_t timeout = 100000;
> > + uint32_t jrint, jrcr;
> > +
> > + sec_out32(®s->jrcr, JRCR_RESET);
> > + do {
> > + jrint = sec_in32(®s->jrint);
> > + } while (((jrint & JRINT_ERR_HALT_MASK) ==
> > + JRINT_ERR_HALT_INPROGRESS) && --timeout);
> > +
> > + jrint = sec_in32(®s->jrint);
> > + if (((jrint & JRINT_ERR_HALT_MASK) !=
> > + JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
> > + return -1;
> > +
> > + timeout = 100000;
> > + sec_out32(®s->jrcr, JRCR_RESET);
> > + do {
> > + jrcr = sec_in32(®s->jrcr);
> > + } while ((jrcr & JRCR_RESET) && --timeout);
> > +
> > + if (timeout == 0)
> > + return -1;
> > +
> > + return 0;
> > +}
> > +
> > static inline int jr_reset_sec(uint8_t sec_idx)
> > {
> > - if (jr_hw_reset(sec_idx) < 0)
> > + struct caam_regs *caam;
> > +#if CONFIG_IS_ENABLED(DM)
> > + caam = dev_get_priv(caam_dev);
> > +#else
> > + caam = &caam_st;
> > +#endif
> > + if (jr_hw_reset(caam->regs) < 0)
> > return -1;
> >
> > /* Clean up the jobring structure maintained by software */
> > - jr_sw_cleanup(sec_idx);
> > + jr_sw_cleanup(sec_idx, caam);
> >
> > return 0;
> > }
> > @@ -418,9 +430,15 @@ int jr_reset(void)
> > return jr_reset_sec(0);
> > }
> >
> > -static inline int sec_reset_idx(uint8_t sec_idx)
> > +int sec_reset(void)
> > {
> > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > + struct caam_regs *caam;
> > +#if CONFIG_IS_ENABLED(DM)
> > + caam = dev_get_priv(caam_dev);
> > +#else
> > + caam = &caam_st;
> > +#endif
> > + ccsr_sec_t *sec = caam->sec;
> > uint32_t mcfgr = sec_in32(&sec->mcfgr);
> > uint32_t timeout = 100000;
> >
> > @@ -446,11 +464,7 @@ static inline int sec_reset_idx(uint8_t sec_idx)
> >
> > return 0;
> > }
> > -int sec_reset(void)
> > -{
> > - return sec_reset_idx(0);
> > -}
> > -#ifndef CONFIG_SPL_BUILD
> > +
> > static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
> > {
> > u32 *desc;
> > @@ -496,12 +510,11 @@ static int deinstantiate_rng(u8 sec_idx, int
> state_handle_mask)
> > return ret;
> > }
> >
> > -static int instantiate_rng(u8 sec_idx, int gen_sk)
> > +static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int
> > +gen_sk)
> > {
> > u32 *desc;
> > u32 rdsta_val;
> > int ret = 0, sh_idx, size;
> > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
> > struct rng4tst __iomem *rng =
> > (struct rng4tst __iomem *)&sec->rng;
> >
> > @@ -554,9 +567,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk)
> > return ret;
> > }
> >
> > -static u8 get_rng_vid(uint8_t sec_idx)
> > +static u8 get_rng_vid(ccsr_sec_t *sec)
> > {
> > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > u8 vid;
> >
> > if (caam_get_era() < 10) {
> > @@ -574,9 +586,8 @@ static u8 get_rng_vid(uint8_t sec_idx)
> > * By default, the TRNG runs for 200 clocks per sample;
> > * 1200 clocks per sample generates better entropy.
> > */
> > -static void kick_trng(int ent_delay, uint8_t sec_idx)
> > +static void kick_trng(int ent_delay, ccsr_sec_t *sec)
> > {
> > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
> > struct rng4tst __iomem *rng =
> > (struct rng4tst __iomem *)&sec->rng;
> > u32 val;
> > @@ -603,10 +614,9 @@ static void kick_trng(int ent_delay, uint8_t sec_idx)
> > sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
> > }
> >
> > -static int rng_init(uint8_t sec_idx)
> > +static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
> > {
> > int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
> > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
> > struct rng4tst __iomem *rng =
> > (struct rng4tst __iomem *)&sec->rng;
> > u32 inst_handles;
> > @@ -624,7 +634,7 @@ static int rng_init(uint8_t sec_idx)
> > * the TRNG parameters.
> > */
> > if (!inst_handles) {
> > - kick_trng(ent_delay, sec_idx);
> > + kick_trng(ent_delay, sec);
> > ent_delay += 400;
> > }
> > /*
> > @@ -634,7 +644,7 @@ static int rng_init(uint8_t sec_idx)
> > * interval, leading to a sucessful initialization of
> > * the RNG.
> > */
> > - ret = instantiate_rng(sec_idx, gen_sk);
> > + ret = instantiate_rng(sec_idx, sec, gen_sk);
> > } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
> > if (ret) {
> > printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
> > @@ -646,13 +656,28 @@ static int rng_init(uint8_t sec_idx)
> >
> > return ret;
> > }
> > -#endif
> > +
> > int sec_init_idx(uint8_t sec_idx)
> > {
> > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > - uint32_t mcr = sec_in32(&sec->mcfgr);
> > int ret = 0;
> > -
> > + struct caam_regs *caam;
> > +#if CONFIG_IS_ENABLED(DM)
> > + if (!caam_dev) {
> > + printf("caam_jr: caam not found\n");
> > + return -1;
> > + }
> > + caam = dev_get_priv(caam_dev);
> > +#else
> > + caam_st.sec = (void *)SEC_ADDR(sec_idx);
> > + caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > + caam_st.jrid = 0;
> > + caam = &caam_st;
> > +#endif
> > + ccsr_sec_t *sec = caam->sec;
> > + uint32_t mcr = sec_in32(&sec->mcfgr); #if
> > +defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> > + uint32_t jrdid_ms = 0;
> > +#endif
> > #ifdef CONFIG_FSL_CORENET
> > uint32_t liodnr;
> > uint32_t liodn_ns;
> > @@ -682,6 +707,11 @@ int sec_init_idx(uint8_t sec_idx)
> > mcr |= (1 << MCFGR_PS_SHIFT);
> > #endif
> > sec_out32(&sec->mcfgr, mcr);
> > +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> > + jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ |
> JRDID_MS_PRIM_DID;
> > + sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms); #endif
> > + jr_reset();
> >
> > #ifdef CONFIG_FSL_CORENET
> > #ifdef CONFIG_SPL_BUILD
> > @@ -693,20 +723,19 @@ int sec_init_idx(uint8_t sec_idx)
> > liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
> > liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
> >
> > - liodnr = sec_in32(&sec->jrliodnr[0].ls) &
> > + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
> > ~(JRNSLIODN_MASK | JRSLIODN_MASK);
> > liodnr = liodnr |
> > (liodn_ns << JRNSLIODN_SHIFT) |
> > (liodn_s << JRSLIODN_SHIFT);
> > - sec_out32(&sec->jrliodnr[0].ls, liodnr);
> > + sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
> > #else
> > - liodnr = sec_in32(&sec->jrliodnr[0].ls);
> > + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
> > liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
> > liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
> > #endif
> > #endif
> > -
> > - ret = jr_init(sec_idx);
> > + ret = jr_init(sec_idx, caam);
> > if (ret < 0) {
> > printf("SEC%u: initialization failed\n", sec_idx);
> > return -1;
> > @@ -719,9 +748,9 @@ int sec_init_idx(uint8_t sec_idx)
> >
> > pamu_enable();
> > #endif
> > -#ifndef CONFIG_SPL_BUILD
> > - if (get_rng_vid(sec_idx) >= 4) {
> > - if (rng_init(sec_idx) < 0) {
> > +
> > + if (get_rng_vid(caam->sec) >= 4) {
> > + if (rng_init(sec_idx, caam->sec) < 0) {
> > printf("SEC%u: RNG instantiation failed\n", sec_idx);
> > return -1;
> > }
> > @@ -735,7 +764,6 @@ int sec_init_idx(uint8_t sec_idx)
> >
> > printf("SEC%u: RNG instantiated\n", sec_idx);
> > }
> > -#endif
> > return ret;
> > }
> >
> > @@ -743,3 +771,76 @@ int sec_init(void)
> > {
> > return sec_init_idx(0);
> > }
> > +
> > +#if CONFIG_IS_ENABLED(DM)
> > +static int caam_jr_ioctl(struct udevice *dev, unsigned long request,
> > +void *buf) {
> > + if (request != CAAM_JR_RUN_DESC)
> > + return -ENOSYS;
> > +
> > + return run_descriptor_jr(buf);
> > +}
> > +
> > +static int caam_jr_probe(struct udevice *dev) {
> > + struct caam_regs *caam = dev_get_priv(dev);
> > + fdt_addr_t addr;
> > + ofnode node;
> > + unsigned int jr_node = 0;
> > +
> > + caam_dev = dev;
> > +
> > + addr = dev_read_addr(dev);
> > + if (addr == FDT_ADDR_T_NONE) {
> > + printf("caam_jr: crypto not found\n");
> > + return -EINVAL;
> > + }
> > + caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
> > + caam->regs = (struct jr_regs *)caam->sec;
> > +
> > + /* Check for enabled job ring node */
> > + ofnode_for_each_subnode(node, dev_ofnode(dev)) {
> > + if (!ofnode_is_available(node))
> > + continue;
> > +
> > + jr_node = ofnode_read_u32_default(node, "reg", -1);
> > + if (jr_node > 0) {
> > + caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
> > + while (!(jr_node & 0x0F))
> > + jr_node = jr_node >> 4;
> > +
> > + caam->jrid = jr_node - 1;
> > + break;
> > + }
> > + }
> > +
> > + if (sec_init())
> > + printf("\nsec_init failed!\n");
> > +
> > + return 0;
> > +}
> > +
> > +static int caam_jr_bind(struct udevice *dev) {
> > + return 0;
> > +}
> > +
> > +static const struct misc_ops caam_jr_ops = {
> > + .ioctl = caam_jr_ioctl,
> > +};
> > +
> > +static const struct udevice_id caam_jr_match[] = {
> > + { .compatible = "fsl,sec-v4.0" },
> > + { }
> > +};
> > +
> > +U_BOOT_DRIVER(caam_jr) = {
> > + .name = "caam_jr",
> > + .id = UCLASS_MISC,
> > + .of_match = caam_jr_match,
> > + .ops = &caam_jr_ops,
> > + .bind = caam_jr_bind,
> > + .probe = caam_jr_probe,
> > + .priv_auto = sizeof(struct caam_regs),
> > +};
> > +#endif
> > diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index
> > 1047aa772c..3eb7be79da 100644
> > --- a/drivers/crypto/fsl/jr.h
> > +++ b/drivers/crypto/fsl/jr.h
> > @@ -1,6 +1,7 @@
> > /* SPDX-License-Identifier: GPL-2.0+ */
> > /*
> > * Copyright 2008-2014 Freescale Semiconductor, Inc.
> > + * Copyright 2021 NXP
> > *
> > */
> >
> > @@ -8,7 +9,9 @@
> > #define __JR_H
> >
> > #include <linux/compiler.h>
> > +#include "fsl_sec.h"
> > #include "type.h"
> > +#include <misc.h>
> >
> > #define JR_SIZE 4
> > /* Timeout currently defined as 10 sec */ @@ -35,12 +38,21 @@
> > #define JRSLIODN_SHIFT 0
> > #define JRSLIODN_MASK 0x00000fff
> >
> > -#define JQ_DEQ_ERR -1
> > -#define JQ_DEQ_TO_ERR -2
> > -#define JQ_ENQ_ERR -3
> > +#define JRDID_MS_PRIM_DID BIT(0)
> > +#define JRDID_MS_PRIM_TZ BIT(4)
> > +#define JRDID_MS_TZ_OWN BIT(15)
> > +
> > +#define JQ_DEQ_ERR (-1)
> > +#define JQ_DEQ_TO_ERR (-2)
> > +#define JQ_ENQ_ERR (-3)
> >
> > #define RNG4_MAX_HANDLES 2
> >
> > +enum {
> > + /* Run caam jobring descriptor(in buf) */
> > + CAAM_JR_RUN_DESC,
> > +};
> > +
> > struct op_ring {
> > caam_dma_addr_t desc;
> > uint32_t status;
> > @@ -102,6 +114,19 @@ struct result {
> > uint32_t status;
> > };
> >
> > +/*
> > + * struct caam_regs - CAAM initialization register interface
> > + *
> > + * Interface to caam memory map, jobring register, jobring storage.
> > + */
> > +struct caam_regs {
> > + ccsr_sec_t *sec; /*caam initialization registers*/
> > + struct jr_regs *regs; /*jobring configuration registers*/
> > + u8 jrid; /*id to identify a jobring*/
> > + /*Private sub-storage for a single JobR*/
> > + struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> > +};
> > +
> > void caam_jr_strstatus(u32 status);
> > int run_descriptor_jr(uint32_t *desc);
> >
>
> --
> =================================================================
> ====
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
> =================================================================
> ====
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-02-07 7:13 ` [EXT] " Gaurav Jain
@ 2022-02-11 9:38 ` Gaurav Jain
2022-02-25 7:03 ` Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-02-11 9:38 UTC (permalink / raw)
To: Stefano Babic, u-boot, Marek Vasut
Cc: Fabio Estevam, Peng Fan, Simon Glass, Priyanka Jain, Ye Li,
Horia Geanta, Ji Luo, Franck Lenormand, Silvano Di Ninno,
Sahil Malhotra, Pankaj Gupta, Varun Sethi, dl-uboot-imx,
Shengzhou Liu, Mingkai Hu, Rajesh Bhagat, Meenakshi Aggarwal,
Wasim Khan, Alison Wang, Pramod Kumar, Andy Tang, Adrian Alonso,
Vladimir Oltean
Hello Marek
A gentle reminder!!
Please help to check if some feature can be dropped in SPL from imx6dl_mamoj board so that CAAM driver model patches can be accepted.
Regards
Gaurav Jain
> -----Original Message-----
> From: Gaurav Jain
> Sent: Monday, February 7, 2022 12:43 PM
> To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek Vasut
> <marex@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> Simon Glass <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye
> Li <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> Hello Marek
>
> > -----Original Message-----
> > From: Stefano Babic <sbabic@denx.de>
> > Sent: Saturday, February 5, 2022 7:46 PM
> > To: Gaurav Jain <gaurav.jain@nxp.com>; u-boot@lists.denx.de
> > Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
> > <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> > <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> > <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> > <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano
> > Di Ninno <silvano.dininno@nxp.com>; Sahil Malhotra
> > <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun
> > Sethi <V.Sethi@nxp.com>; dl-uboot-imx <uboot-imx@nxp.com>; Shengzhou
> > Liu <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> > Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> > <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> Alison
> > Wang <alison.wang@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>;
> > Andy Tang <andy.tang@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
> > Vladimir Oltean <olteanv@gmail.com>; Marek Vasut <marex@denx.de>
> > Subject: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM
> > Job ring driver model
> >
> > Caution: EXT Email
> >
> > Hi Gaurav,
> >
> > rather I still have issues to run CI with this applied. The reason is
> > that this adds an overhead to SPL and it breaks the board imx6dl_mamoj
> > because SPL exceeds the maximum size for a DL SOC.
> >
> > See
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsour
> > ce.d
> > enx.de%2Fu-boot%2Fcustodians%2Fu-boot-imx%2F-
> > %2Fjobs%2F387370&data=04%7C01%7Cgaurav.jain%40nxp.com%7C3a2
> 73
> >
> 1dd27fc4bebcad308d9e8b21464%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C
> >
> 0%7C0%7C637796673834942697%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> >
> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&am
> >
> p;sdata=pI%2F%2FlNtrdrGCa8sSvcr6uNu4jze7pzDqZtI52FIDj50%3D&reserve
> > d=0
> >
> > I do not know if it is possible to drop some features from SPL for
> > this board (Added Marek as board maintainer).
>
> CONFIG_IMX_HAB is enabled for imx6dl_mamoj. So CAAM is built for SPL,
> results in increased size.
> However CAAM is not initialized in SPL. As Stefano suggested, Can you drop
> some features from SPL?
>
> Regards
> Gaurav Jain
> >
> > Best regards,
> > Stefano
> >
> > On 10.01.22 13:27, Gaurav Jain wrote:
> > > added device tree support for job ring driver.
> > > sec is initialized based on job ring information processed from
> > > device tree.
> > >
> > > Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> > > Reviewed-by: Ye Li <ye.li@nxp.com>
> > > ---
> > > drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++++--------------
> > > drivers/crypto/fsl/jr.h | 31 +++-
> > > 2 files changed, 240 insertions(+), 114 deletions(-)
> > >
> > > diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index
> > > 22b649219e..8103987425 100644
> > > --- a/drivers/crypto/fsl/jr.c
> > > +++ b/drivers/crypto/fsl/jr.c
> > > @@ -1,7 +1,7 @@
> > > // SPDX-License-Identifier: GPL-2.0+
> > > /*
> > > * Copyright 2008-2014 Freescale Semiconductor, Inc.
> > > - * Copyright 2018 NXP
> > > + * Copyright 2018, 2021 NXP
> > > *
> > > * Based on CAAM driver in drivers/crypto/caam in Linux
> > > */
> > > @@ -11,7 +11,6 @@
> > > #include <linux/kernel.h>
> > > #include <log.h>
> > > #include <malloc.h>
> > > -#include "fsl_sec.h"
> > > #include "jr.h"
> > > #include "jobdesc.h"
> > > #include "desc_constr.h"
> > > @@ -21,7 +20,10 @@
> > > #include <asm/cache.h>
> > > #include <asm/fsl_pamu.h>
> > > #endif
> > > +#include <dm.h>
> > > #include <dm/lists.h>
> > > +#include <dm/root.h>
> > > +#include <dm/device-internal.h>
> > > #include <linux/delay.h>
> > >
> > > #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size -
> > > 1)) @@ -35,20 +37,29 @@ uint32_t
> > sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
> > > #endif
> > > };
> > >
> > > +#if CONFIG_IS_ENABLED(DM)
> > > +struct udevice *caam_dev;
> > > +#else
> > > #define SEC_ADDR(idx) \
> > > (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
> > >
> > > #define SEC_JR0_ADDR(idx) \
> > > (ulong)(SEC_ADDR(idx) + \
> > > (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
> > > +struct caam_regs caam_st;
> > > +#endif
> > >
> > > -struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> > > +static inline u32 jr_start_reg(u8 jrid) {
> > > + return (1 << jrid);
> > > +}
> > >
> > > -static inline void start_jr0(uint8_t sec_idx)
> > > +static inline void start_jr(struct caam_regs *caam)
> > > {
> > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > + ccsr_sec_t *sec = caam->sec;
> > > u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
> > > u32 scfgr = sec_in32(&sec->scfgr);
> > > + u32 jrstart = jr_start_reg(caam->jrid);
> > >
> > > if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
> > > /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or @@ -56,23
> > > +67,16 @@ static inline void start_jr0(uint8_t sec_idx)
> > > */
> > > if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
> > > (scfgr & SEC_SCFGR_VIRT_EN))
> > > - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
> > > + sec_out32(&sec->jrstartr, jrstart);
> > > } else {
> > > /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
> > > if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
> > > - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
> > > + sec_out32(&sec->jrstartr, jrstart);
> > > }
> > > }
> > >
> > > -static inline void jr_reset_liodn(uint8_t sec_idx)
> > > +static inline void jr_disable_irq(struct jr_regs *regs)
> > > {
> > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > - sec_out32(&sec->jrliodnr[0].ls, 0);
> > > -}
> > > -
> > > -static inline void jr_disable_irq(uint8_t sec_idx) -{
> > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > uint32_t jrcfg = sec_in32(®s->jrcfg1);
> > >
> > > jrcfg = jrcfg | JR_INTMASK;
> > > @@ -80,10 +84,10 @@ static inline void jr_disable_irq(uint8_t sec_idx)
> > > sec_out32(®s->jrcfg1, jrcfg);
> > > }
> > >
> > > -static void jr_initregs(uint8_t sec_idx)
> > > +static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
> > > {
> > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > - struct jobring *jr = &jr0[sec_idx];
> > > + struct jr_regs *regs = caam->regs;
> > > + struct jobring *jr = &caam->jr[sec_idx];
> > > caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
> > > caam_dma_addr_t op_base = virt_to_phys((void
> > > *)jr->output_ring);
> > >
> > > @@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx)
> > > sec_out32(®s->irs, JR_SIZE);
> > >
> > > if (!jr->irq)
> > > - jr_disable_irq(sec_idx);
> > > + jr_disable_irq(regs);
> > > }
> > >
> > > -static int jr_init(uint8_t sec_idx)
> > > +static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
> > > {
> > > - struct jobring *jr = &jr0[sec_idx];
> > > + struct jobring *jr = &caam->jr[sec_idx];
> > >
> > > memset(jr, 0, sizeof(struct jobring));
> > >
> > > - jr->jq_id = DEFAULT_JR_ID;
> > > + jr->jq_id = caam->jrid;
> > > jr->irq = DEFAULT_IRQ;
> > >
> > > #ifdef CONFIG_FSL_CORENET
> > > @@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx)
> > > memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
> > > memset(jr->output_ring, 0, jr->op_size);
> > >
> > > - start_jr0(sec_idx);
> > > -
> > > - jr_initregs(sec_idx);
> > > -
> > > - return 0;
> > > -}
> > > -
> > > -static int jr_sw_cleanup(uint8_t sec_idx) -{
> > > - struct jobring *jr = &jr0[sec_idx];
> > > -
> > > - jr->head = 0;
> > > - jr->tail = 0;
> > > - jr->read_idx = 0;
> > > - jr->write_idx = 0;
> > > - memset(jr->info, 0, sizeof(jr->info));
> > > - memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
> > > - memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
> > > -
> > > - return 0;
> > > -}
> > > -
> > > -static int jr_hw_reset(uint8_t sec_idx) -{
> > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > - uint32_t timeout = 100000;
> > > - uint32_t jrint, jrcr;
> > > -
> > > - sec_out32(®s->jrcr, JRCR_RESET);
> > > - do {
> > > - jrint = sec_in32(®s->jrint);
> > > - } while (((jrint & JRINT_ERR_HALT_MASK) ==
> > > - JRINT_ERR_HALT_INPROGRESS) && --timeout);
> > > -
> > > - jrint = sec_in32(®s->jrint);
> > > - if (((jrint & JRINT_ERR_HALT_MASK) !=
> > > - JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
> > > - return -1;
> > > -
> > > - timeout = 100000;
> > > - sec_out32(®s->jrcr, JRCR_RESET);
> > > - do {
> > > - jrcr = sec_in32(®s->jrcr);
> > > - } while ((jrcr & JRCR_RESET) && --timeout);
> > > -
> > > - if (timeout == 0)
> > > - return -1;
> > > + start_jr(caam);
> > > + jr_initregs(sec_idx, caam);
> > >
> > > return 0;
> > > }
> > > @@ -188,10 +147,10 @@ static int jr_hw_reset(uint8_t sec_idx)
> > > /* -1 --- error, can't enqueue -- no space available */
> > > static int jr_enqueue(uint32_t *desc_addr,
> > > void (*callback)(uint32_t status, void *arg),
> > > - void *arg, uint8_t sec_idx)
> > > + void *arg, uint8_t sec_idx, struct caam_regs *caam)
> > > {
> > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > - struct jobring *jr = &jr0[sec_idx];
> > > + struct jr_regs *regs = caam->regs;
> > > + struct jobring *jr = &caam->jr[sec_idx];
> > > int head = jr->head;
> > > uint32_t desc_word;
> > > int length = desc_len(desc_addr); @@ -263,10 +222,10 @@ static
> > > int jr_enqueue(uint32_t *desc_addr,
> > > return 0;
> > > }
> > >
> > > -static int jr_dequeue(int sec_idx)
> > > +static int jr_dequeue(int sec_idx, struct caam_regs *caam)
> > > {
> > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > - struct jobring *jr = &jr0[sec_idx];
> > > + struct jr_regs *regs = caam->regs;
> > > + struct jobring *jr = &caam->jr[sec_idx];
> > > int head = jr->head;
> > > int tail = jr->tail;
> > > int idx, i, found;
> > > @@ -349,14 +308,18 @@ static void desc_done(uint32_t status, void *arg)
> > > {
> > > struct result *x = arg;
> > > x->status = status;
> > > -#ifndef CONFIG_SPL_BUILD
> > > caam_jr_strstatus(status);
> > > -#endif
> > > x->done = 1;
> > > }
> > >
> > > static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
> > > {
> > > + struct caam_regs *caam;
> > > +#if CONFIG_IS_ENABLED(DM)
> > > + caam = dev_get_priv(caam_dev); #else
> > > + caam = &caam_st;
> > > +#endif
> > > unsigned long long timeval = 0;
> > > unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
> > > struct result op;
> > > @@ -364,7 +327,7 @@ static inline int run_descriptor_jr_idx(uint32_t
> > > *desc, uint8_t sec_idx)
> > >
> > > memset(&op, 0, sizeof(op));
> > >
> > > - ret = jr_enqueue(desc, desc_done, &op, sec_idx);
> > > + ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
> > > if (ret) {
> > > debug("Error in SEC enq\n");
> > > ret = JQ_ENQ_ERR;
> > > @@ -375,7 +338,7 @@ static inline int run_descriptor_jr_idx(uint32_t
> > > *desc,
> > uint8_t sec_idx)
> > > udelay(1);
> > > timeval += 1;
> > >
> > > - ret = jr_dequeue(sec_idx);
> > > + ret = jr_dequeue(sec_idx, caam);
> > > if (ret) {
> > > debug("Error in SEC deq\n");
> > > ret = JQ_DEQ_ERR; @@ -402,13 +365,62 @@ int
> > > run_descriptor_jr(uint32_t *desc)
> > > return run_descriptor_jr_idx(desc, 0);
> > > }
> > >
> > > +static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam) {
> > > + struct jobring *jr = &caam->jr[sec_idx];
> > > +
> > > + jr->head = 0;
> > > + jr->tail = 0;
> > > + jr->read_idx = 0;
> > > + jr->write_idx = 0;
> > > + memset(jr->info, 0, sizeof(jr->info));
> > > + memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
> > > + memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int jr_hw_reset(struct jr_regs *regs) {
> > > + uint32_t timeout = 100000;
> > > + uint32_t jrint, jrcr;
> > > +
> > > + sec_out32(®s->jrcr, JRCR_RESET);
> > > + do {
> > > + jrint = sec_in32(®s->jrint);
> > > + } while (((jrint & JRINT_ERR_HALT_MASK) ==
> > > + JRINT_ERR_HALT_INPROGRESS) && --timeout);
> > > +
> > > + jrint = sec_in32(®s->jrint);
> > > + if (((jrint & JRINT_ERR_HALT_MASK) !=
> > > + JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
> > > + return -1;
> > > +
> > > + timeout = 100000;
> > > + sec_out32(®s->jrcr, JRCR_RESET);
> > > + do {
> > > + jrcr = sec_in32(®s->jrcr);
> > > + } while ((jrcr & JRCR_RESET) && --timeout);
> > > +
> > > + if (timeout == 0)
> > > + return -1;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static inline int jr_reset_sec(uint8_t sec_idx)
> > > {
> > > - if (jr_hw_reset(sec_idx) < 0)
> > > + struct caam_regs *caam;
> > > +#if CONFIG_IS_ENABLED(DM)
> > > + caam = dev_get_priv(caam_dev); #else
> > > + caam = &caam_st;
> > > +#endif
> > > + if (jr_hw_reset(caam->regs) < 0)
> > > return -1;
> > >
> > > /* Clean up the jobring structure maintained by software */
> > > - jr_sw_cleanup(sec_idx);
> > > + jr_sw_cleanup(sec_idx, caam);
> > >
> > > return 0;
> > > }
> > > @@ -418,9 +430,15 @@ int jr_reset(void)
> > > return jr_reset_sec(0);
> > > }
> > >
> > > -static inline int sec_reset_idx(uint8_t sec_idx)
> > > +int sec_reset(void)
> > > {
> > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > + struct caam_regs *caam;
> > > +#if CONFIG_IS_ENABLED(DM)
> > > + caam = dev_get_priv(caam_dev); #else
> > > + caam = &caam_st;
> > > +#endif
> > > + ccsr_sec_t *sec = caam->sec;
> > > uint32_t mcfgr = sec_in32(&sec->mcfgr);
> > > uint32_t timeout = 100000;
> > >
> > > @@ -446,11 +464,7 @@ static inline int sec_reset_idx(uint8_t
> > > sec_idx)
> > >
> > > return 0;
> > > }
> > > -int sec_reset(void)
> > > -{
> > > - return sec_reset_idx(0);
> > > -}
> > > -#ifndef CONFIG_SPL_BUILD
> > > +
> > > static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
> > > {
> > > u32 *desc;
> > > @@ -496,12 +510,11 @@ static int deinstantiate_rng(u8 sec_idx, int
> > state_handle_mask)
> > > return ret;
> > > }
> > >
> > > -static int instantiate_rng(u8 sec_idx, int gen_sk)
> > > +static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int
> > > +gen_sk)
> > > {
> > > u32 *desc;
> > > u32 rdsta_val;
> > > int ret = 0, sh_idx, size;
> > > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
> > > struct rng4tst __iomem *rng =
> > > (struct rng4tst __iomem *)&sec->rng;
> > >
> > > @@ -554,9 +567,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk)
> > > return ret;
> > > }
> > >
> > > -static u8 get_rng_vid(uint8_t sec_idx)
> > > +static u8 get_rng_vid(ccsr_sec_t *sec)
> > > {
> > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > u8 vid;
> > >
> > > if (caam_get_era() < 10) {
> > > @@ -574,9 +586,8 @@ static u8 get_rng_vid(uint8_t sec_idx)
> > > * By default, the TRNG runs for 200 clocks per sample;
> > > * 1200 clocks per sample generates better entropy.
> > > */
> > > -static void kick_trng(int ent_delay, uint8_t sec_idx)
> > > +static void kick_trng(int ent_delay, ccsr_sec_t *sec)
> > > {
> > > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
> > > struct rng4tst __iomem *rng =
> > > (struct rng4tst __iomem *)&sec->rng;
> > > u32 val;
> > > @@ -603,10 +614,9 @@ static void kick_trng(int ent_delay, uint8_t sec_idx)
> > > sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
> > > }
> > >
> > > -static int rng_init(uint8_t sec_idx)
> > > +static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
> > > {
> > > int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
> > > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
> > > struct rng4tst __iomem *rng =
> > > (struct rng4tst __iomem *)&sec->rng;
> > > u32 inst_handles;
> > > @@ -624,7 +634,7 @@ static int rng_init(uint8_t sec_idx)
> > > * the TRNG parameters.
> > > */
> > > if (!inst_handles) {
> > > - kick_trng(ent_delay, sec_idx);
> > > + kick_trng(ent_delay, sec);
> > > ent_delay += 400;
> > > }
> > > /*
> > > @@ -634,7 +644,7 @@ static int rng_init(uint8_t sec_idx)
> > > * interval, leading to a sucessful initialization of
> > > * the RNG.
> > > */
> > > - ret = instantiate_rng(sec_idx, gen_sk);
> > > + ret = instantiate_rng(sec_idx, sec, gen_sk);
> > > } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
> > > if (ret) {
> > > printf("SEC%u: Failed to instantiate RNG\n",
> > > sec_idx); @@ -646,13 +656,28 @@ static int rng_init(uint8_t sec_idx)
> > >
> > > return ret;
> > > }
> > > -#endif
> > > +
> > > int sec_init_idx(uint8_t sec_idx)
> > > {
> > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > - uint32_t mcr = sec_in32(&sec->mcfgr);
> > > int ret = 0;
> > > -
> > > + struct caam_regs *caam;
> > > +#if CONFIG_IS_ENABLED(DM)
> > > + if (!caam_dev) {
> > > + printf("caam_jr: caam not found\n");
> > > + return -1;
> > > + }
> > > + caam = dev_get_priv(caam_dev); #else
> > > + caam_st.sec = (void *)SEC_ADDR(sec_idx);
> > > + caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > + caam_st.jrid = 0;
> > > + caam = &caam_st;
> > > +#endif
> > > + ccsr_sec_t *sec = caam->sec;
> > > + uint32_t mcr = sec_in32(&sec->mcfgr); #if
> > > +defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> > > + uint32_t jrdid_ms = 0;
> > > +#endif
> > > #ifdef CONFIG_FSL_CORENET
> > > uint32_t liodnr;
> > > uint32_t liodn_ns;
> > > @@ -682,6 +707,11 @@ int sec_init_idx(uint8_t sec_idx)
> > > mcr |= (1 << MCFGR_PS_SHIFT);
> > > #endif
> > > sec_out32(&sec->mcfgr, mcr);
> > > +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> > > + jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ |
> > JRDID_MS_PRIM_DID;
> > > + sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms); #endif
> > > + jr_reset();
> > >
> > > #ifdef CONFIG_FSL_CORENET
> > > #ifdef CONFIG_SPL_BUILD
> > > @@ -693,20 +723,19 @@ int sec_init_idx(uint8_t sec_idx)
> > > liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
> > > liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
> > >
> > > - liodnr = sec_in32(&sec->jrliodnr[0].ls) &
> > > + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
> > > ~(JRNSLIODN_MASK | JRSLIODN_MASK);
> > > liodnr = liodnr |
> > > (liodn_ns << JRNSLIODN_SHIFT) |
> > > (liodn_s << JRSLIODN_SHIFT);
> > > - sec_out32(&sec->jrliodnr[0].ls, liodnr);
> > > + sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
> > > #else
> > > - liodnr = sec_in32(&sec->jrliodnr[0].ls);
> > > + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
> > > liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
> > > liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
> > > #endif
> > > #endif
> > > -
> > > - ret = jr_init(sec_idx);
> > > + ret = jr_init(sec_idx, caam);
> > > if (ret < 0) {
> > > printf("SEC%u: initialization failed\n", sec_idx);
> > > return -1;
> > > @@ -719,9 +748,9 @@ int sec_init_idx(uint8_t sec_idx)
> > >
> > > pamu_enable();
> > > #endif
> > > -#ifndef CONFIG_SPL_BUILD
> > > - if (get_rng_vid(sec_idx) >= 4) {
> > > - if (rng_init(sec_idx) < 0) {
> > > +
> > > + if (get_rng_vid(caam->sec) >= 4) {
> > > + if (rng_init(sec_idx, caam->sec) < 0) {
> > > printf("SEC%u: RNG instantiation failed\n", sec_idx);
> > > return -1;
> > > }
> > > @@ -735,7 +764,6 @@ int sec_init_idx(uint8_t sec_idx)
> > >
> > > printf("SEC%u: RNG instantiated\n", sec_idx);
> > > }
> > > -#endif
> > > return ret;
> > > }
> > >
> > > @@ -743,3 +771,76 @@ int sec_init(void)
> > > {
> > > return sec_init_idx(0);
> > > }
> > > +
> > > +#if CONFIG_IS_ENABLED(DM)
> > > +static int caam_jr_ioctl(struct udevice *dev, unsigned long
> > > +request, void *buf) {
> > > + if (request != CAAM_JR_RUN_DESC)
> > > + return -ENOSYS;
> > > +
> > > + return run_descriptor_jr(buf); }
> > > +
> > > +static int caam_jr_probe(struct udevice *dev) {
> > > + struct caam_regs *caam = dev_get_priv(dev);
> > > + fdt_addr_t addr;
> > > + ofnode node;
> > > + unsigned int jr_node = 0;
> > > +
> > > + caam_dev = dev;
> > > +
> > > + addr = dev_read_addr(dev);
> > > + if (addr == FDT_ADDR_T_NONE) {
> > > + printf("caam_jr: crypto not found\n");
> > > + return -EINVAL;
> > > + }
> > > + caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
> > > + caam->regs = (struct jr_regs *)caam->sec;
> > > +
> > > + /* Check for enabled job ring node */
> > > + ofnode_for_each_subnode(node, dev_ofnode(dev)) {
> > > + if (!ofnode_is_available(node))
> > > + continue;
> > > +
> > > + jr_node = ofnode_read_u32_default(node, "reg", -1);
> > > + if (jr_node > 0) {
> > > + caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
> > > + while (!(jr_node & 0x0F))
> > > + jr_node = jr_node >> 4;
> > > +
> > > + caam->jrid = jr_node - 1;
> > > + break;
> > > + }
> > > + }
> > > +
> > > + if (sec_init())
> > > + printf("\nsec_init failed!\n");
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int caam_jr_bind(struct udevice *dev) {
> > > + return 0;
> > > +}
> > > +
> > > +static const struct misc_ops caam_jr_ops = {
> > > + .ioctl = caam_jr_ioctl,
> > > +};
> > > +
> > > +static const struct udevice_id caam_jr_match[] = {
> > > + { .compatible = "fsl,sec-v4.0" },
> > > + { }
> > > +};
> > > +
> > > +U_BOOT_DRIVER(caam_jr) = {
> > > + .name = "caam_jr",
> > > + .id = UCLASS_MISC,
> > > + .of_match = caam_jr_match,
> > > + .ops = &caam_jr_ops,
> > > + .bind = caam_jr_bind,
> > > + .probe = caam_jr_probe,
> > > + .priv_auto = sizeof(struct caam_regs),
> > > +};
> > > +#endif
> > > diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index
> > > 1047aa772c..3eb7be79da 100644
> > > --- a/drivers/crypto/fsl/jr.h
> > > +++ b/drivers/crypto/fsl/jr.h
> > > @@ -1,6 +1,7 @@
> > > /* SPDX-License-Identifier: GPL-2.0+ */
> > > /*
> > > * Copyright 2008-2014 Freescale Semiconductor, Inc.
> > > + * Copyright 2021 NXP
> > > *
> > > */
> > >
> > > @@ -8,7 +9,9 @@
> > > #define __JR_H
> > >
> > > #include <linux/compiler.h>
> > > +#include "fsl_sec.h"
> > > #include "type.h"
> > > +#include <misc.h>
> > >
> > > #define JR_SIZE 4
> > > /* Timeout currently defined as 10 sec */ @@ -35,12 +38,21 @@
> > > #define JRSLIODN_SHIFT 0
> > > #define JRSLIODN_MASK 0x00000fff
> > >
> > > -#define JQ_DEQ_ERR -1
> > > -#define JQ_DEQ_TO_ERR -2
> > > -#define JQ_ENQ_ERR -3
> > > +#define JRDID_MS_PRIM_DID BIT(0)
> > > +#define JRDID_MS_PRIM_TZ BIT(4)
> > > +#define JRDID_MS_TZ_OWN BIT(15)
> > > +
> > > +#define JQ_DEQ_ERR (-1)
> > > +#define JQ_DEQ_TO_ERR (-2)
> > > +#define JQ_ENQ_ERR (-3)
> > >
> > > #define RNG4_MAX_HANDLES 2
> > >
> > > +enum {
> > > + /* Run caam jobring descriptor(in buf) */
> > > + CAAM_JR_RUN_DESC,
> > > +};
> > > +
> > > struct op_ring {
> > > caam_dma_addr_t desc;
> > > uint32_t status;
> > > @@ -102,6 +114,19 @@ struct result {
> > > uint32_t status;
> > > };
> > >
> > > +/*
> > > + * struct caam_regs - CAAM initialization register interface
> > > + *
> > > + * Interface to caam memory map, jobring register, jobring storage.
> > > + */
> > > +struct caam_regs {
> > > + ccsr_sec_t *sec; /*caam initialization registers*/
> > > + struct jr_regs *regs; /*jobring configuration registers*/
> > > + u8 jrid; /*id to identify a jobring*/
> > > + /*Private sub-storage for a single JobR*/
> > > + struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> > > +};
> > > +
> > > void caam_jr_strstatus(u32 status);
> > > int run_descriptor_jr(uint32_t *desc);
> > >
> >
> > --
> >
> =================================================================
> > ====
> > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
> >
> =================================================================
> > ====
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-02-11 9:38 ` Gaurav Jain
@ 2022-02-25 7:03 ` Gaurav Jain
2022-03-03 12:44 ` Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-02-25 7:03 UTC (permalink / raw)
To: Stefano Babic, u-boot, Marek Vasut
Cc: Fabio Estevam, Peng Fan, Simon Glass, Priyanka Jain, Ye Li,
Horia Geanta, Ji Luo, Franck Lenormand, Silvano Di Ninno,
Sahil Malhotra, Pankaj Gupta, Varun Sethi, dl-uboot-imx,
Shengzhou Liu, Mingkai Hu, Rajesh Bhagat, Meenakshi Aggarwal,
Wasim Khan, Alison Wang, Pramod Kumar, Andy Tang, Adrian Alonso,
Vladimir Oltean
Hello Stefano
> -----Original Message-----
> From: Gaurav Jain
> Sent: Friday, February 11, 2022 3:09 PM
> To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek Vasut
> <marex@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> Simon Glass <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye
> Li <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> Hello Marek
>
> A gentle reminder!!
> Please help to check if some feature can be dropped in SPL from imx6dl_mamoj
> board so that CAAM driver model patches can be accepted.
>
> Regards
> Gaurav Jain
>
> > -----Original Message-----
> > From: Gaurav Jain
> > Sent: Monday, February 7, 2022 12:43 PM
> > To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek Vasut
> > <marex@denx.de>
> > Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> > Simon Glass <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>;
> > Ye Li <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> > <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano
> > Di Ninno <silvano.dininno@nxp.com>; Sahil Malhotra
> > <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun
> > Sethi <V.Sethi@nxp.com>; dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou
> > Liu <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> > Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> > <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> Alison
> > Wang <alison.wang@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>;
> > Andy Tang <andy.tang@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
> > Vladimir Oltean <olteanv@gmail.com>
> > Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> > CAAM Job ring driver model
> >
> > Hello Marek
> >
> > > -----Original Message-----
> > > From: Stefano Babic <sbabic@denx.de>
> > > Sent: Saturday, February 5, 2022 7:46 PM
> > > To: Gaurav Jain <gaurav.jain@nxp.com>; u-boot@lists.denx.de
> > > Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
> > > <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> > > <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> > > <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> > > <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>;
> > > Silvano Di Ninno <silvano.dininno@nxp.com>; Sahil Malhotra
> > > <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun
> > > Sethi <V.Sethi@nxp.com>; dl-uboot-imx <uboot-imx@nxp.com>; Shengzhou
> > > Liu <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> > > Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> > > <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> > Alison
> > > Wang <alison.wang@nxp.com>; Pramod Kumar
> > <pramod.kumar_1@nxp.com>;
> > > Andy Tang <andy.tang@nxp.com>; Adrian Alonso
> > > <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>; Marek
> > > Vasut <marex@denx.de>
> > > Subject: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM
> > > Job ring driver model
> > >
> > > Caution: EXT Email
> > >
> > > Hi Gaurav,
> > >
> > > rather I still have issues to run CI with this applied. The reason
> > > is that this adds an overhead to SPL and it breaks the board
> > > imx6dl_mamoj because SPL exceeds the maximum size for a DL SOC.
> > >
> > > See
> > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fso
> > > ur
> > > ce.d
> > > enx.de%2Fu-boot%2Fcustodians%2Fu-boot-imx%2F-
> > > %2Fjobs%2F387370&data=04%7C01%7Cgaurav.jain%40nxp.com%7C3a
> 2
> > 73
> > >
> >
> 1dd27fc4bebcad308d9e8b21464%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C
> > >
> >
> 0%7C0%7C637796673834942697%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> > >
> >
> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&am
> > >
> >
> p;sdata=pI%2F%2FlNtrdrGCa8sSvcr6uNu4jze7pzDqZtI52FIDj50%3D&reserve
> > > d=0
> > >
> > > I do not know if it is possible to drop some features from SPL for
> > > this board (Added Marek as board maintainer).
As we have not received any response from imx6dl_mamoj board maintainer.
I propose the below solution
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN
config IMX_HAB
- select FSL_CAAM if HAS_CAAM
- imply CMD_DEKBLOB if HAS_CAAM
+ imply FSL_CAAM if HAS_CAAM
+ imply CMD_DEKBLOB if FSL_CAAM
Help
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -59,3 +59,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_FSL_CAAM=n
Need your help to review this or suggest any other solution.
Regards
Gaurav Jain
> >
> > CONFIG_IMX_HAB is enabled for imx6dl_mamoj. So CAAM is built for SPL,
> > results in increased size.
> > However CAAM is not initialized in SPL. As Stefano suggested, Can you
> > drop some features from SPL?
> >
> > Regards
> > Gaurav Jain
> > >
> > > Best regards,
> > > Stefano
> > >
> > > On 10.01.22 13:27, Gaurav Jain wrote:
> > > > added device tree support for job ring driver.
> > > > sec is initialized based on job ring information processed from
> > > > device tree.
> > > >
> > > > Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> > > > Reviewed-by: Ye Li <ye.li@nxp.com>
> > > > ---
> > > > drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++++--------------
> > > > drivers/crypto/fsl/jr.h | 31 +++-
> > > > 2 files changed, 240 insertions(+), 114 deletions(-)
> > > >
> > > > diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
> > > > index
> > > > 22b649219e..8103987425 100644
> > > > --- a/drivers/crypto/fsl/jr.c
> > > > +++ b/drivers/crypto/fsl/jr.c
> > > > @@ -1,7 +1,7 @@
> > > > // SPDX-License-Identifier: GPL-2.0+
> > > > /*
> > > > * Copyright 2008-2014 Freescale Semiconductor, Inc.
> > > > - * Copyright 2018 NXP
> > > > + * Copyright 2018, 2021 NXP
> > > > *
> > > > * Based on CAAM driver in drivers/crypto/caam in Linux
> > > > */
> > > > @@ -11,7 +11,6 @@
> > > > #include <linux/kernel.h>
> > > > #include <log.h>
> > > > #include <malloc.h>
> > > > -#include "fsl_sec.h"
> > > > #include "jr.h"
> > > > #include "jobdesc.h"
> > > > #include "desc_constr.h"
> > > > @@ -21,7 +20,10 @@
> > > > #include <asm/cache.h>
> > > > #include <asm/fsl_pamu.h>
> > > > #endif
> > > > +#include <dm.h>
> > > > #include <dm/lists.h>
> > > > +#include <dm/root.h>
> > > > +#include <dm/device-internal.h>
> > > > #include <linux/delay.h>
> > > >
> > > > #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size -
> > > > 1)) @@ -35,20 +37,29 @@ uint32_t
> > > sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
> > > > #endif
> > > > };
> > > >
> > > > +#if CONFIG_IS_ENABLED(DM)
> > > > +struct udevice *caam_dev;
> > > > +#else
> > > > #define SEC_ADDR(idx) \
> > > > (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
> > > >
> > > > #define SEC_JR0_ADDR(idx) \
> > > > (ulong)(SEC_ADDR(idx) + \
> > > > (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
> > > > +struct caam_regs caam_st;
> > > > +#endif
> > > >
> > > > -struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> > > > +static inline u32 jr_start_reg(u8 jrid) {
> > > > + return (1 << jrid);
> > > > +}
> > > >
> > > > -static inline void start_jr0(uint8_t sec_idx)
> > > > +static inline void start_jr(struct caam_regs *caam)
> > > > {
> > > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > > + ccsr_sec_t *sec = caam->sec;
> > > > u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
> > > > u32 scfgr = sec_in32(&sec->scfgr);
> > > > + u32 jrstart = jr_start_reg(caam->jrid);
> > > >
> > > > if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
> > > > /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or @@ -56,23
> > > > +67,16 @@ static inline void start_jr0(uint8_t sec_idx)
> > > > */
> > > > if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
> > > > (scfgr & SEC_SCFGR_VIRT_EN))
> > > > - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
> > > > + sec_out32(&sec->jrstartr, jrstart);
> > > > } else {
> > > > /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
> > > > if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
> > > > - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
> > > > + sec_out32(&sec->jrstartr, jrstart);
> > > > }
> > > > }
> > > >
> > > > -static inline void jr_reset_liodn(uint8_t sec_idx)
> > > > +static inline void jr_disable_irq(struct jr_regs *regs)
> > > > {
> > > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > > - sec_out32(&sec->jrliodnr[0].ls, 0);
> > > > -}
> > > > -
> > > > -static inline void jr_disable_irq(uint8_t sec_idx) -{
> > > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > > uint32_t jrcfg = sec_in32(®s->jrcfg1);
> > > >
> > > > jrcfg = jrcfg | JR_INTMASK;
> > > > @@ -80,10 +84,10 @@ static inline void jr_disable_irq(uint8_t sec_idx)
> > > > sec_out32(®s->jrcfg1, jrcfg);
> > > > }
> > > >
> > > > -static void jr_initregs(uint8_t sec_idx)
> > > > +static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
> > > > {
> > > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > > - struct jobring *jr = &jr0[sec_idx];
> > > > + struct jr_regs *regs = caam->regs;
> > > > + struct jobring *jr = &caam->jr[sec_idx];
> > > > caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
> > > > caam_dma_addr_t op_base = virt_to_phys((void
> > > > *)jr->output_ring);
> > > >
> > > > @@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx)
> > > > sec_out32(®s->irs, JR_SIZE);
> > > >
> > > > if (!jr->irq)
> > > > - jr_disable_irq(sec_idx);
> > > > + jr_disable_irq(regs);
> > > > }
> > > >
> > > > -static int jr_init(uint8_t sec_idx)
> > > > +static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
> > > > {
> > > > - struct jobring *jr = &jr0[sec_idx];
> > > > + struct jobring *jr = &caam->jr[sec_idx];
> > > >
> > > > memset(jr, 0, sizeof(struct jobring));
> > > >
> > > > - jr->jq_id = DEFAULT_JR_ID;
> > > > + jr->jq_id = caam->jrid;
> > > > jr->irq = DEFAULT_IRQ;
> > > >
> > > > #ifdef CONFIG_FSL_CORENET
> > > > @@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx)
> > > > memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
> > > > memset(jr->output_ring, 0, jr->op_size);
> > > >
> > > > - start_jr0(sec_idx);
> > > > -
> > > > - jr_initregs(sec_idx);
> > > > -
> > > > - return 0;
> > > > -}
> > > > -
> > > > -static int jr_sw_cleanup(uint8_t sec_idx) -{
> > > > - struct jobring *jr = &jr0[sec_idx];
> > > > -
> > > > - jr->head = 0;
> > > > - jr->tail = 0;
> > > > - jr->read_idx = 0;
> > > > - jr->write_idx = 0;
> > > > - memset(jr->info, 0, sizeof(jr->info));
> > > > - memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
> > > > - memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
> > > > -
> > > > - return 0;
> > > > -}
> > > > -
> > > > -static int jr_hw_reset(uint8_t sec_idx) -{
> > > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > > - uint32_t timeout = 100000;
> > > > - uint32_t jrint, jrcr;
> > > > -
> > > > - sec_out32(®s->jrcr, JRCR_RESET);
> > > > - do {
> > > > - jrint = sec_in32(®s->jrint);
> > > > - } while (((jrint & JRINT_ERR_HALT_MASK) ==
> > > > - JRINT_ERR_HALT_INPROGRESS) && --timeout);
> > > > -
> > > > - jrint = sec_in32(®s->jrint);
> > > > - if (((jrint & JRINT_ERR_HALT_MASK) !=
> > > > - JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
> > > > - return -1;
> > > > -
> > > > - timeout = 100000;
> > > > - sec_out32(®s->jrcr, JRCR_RESET);
> > > > - do {
> > > > - jrcr = sec_in32(®s->jrcr);
> > > > - } while ((jrcr & JRCR_RESET) && --timeout);
> > > > -
> > > > - if (timeout == 0)
> > > > - return -1;
> > > > + start_jr(caam);
> > > > + jr_initregs(sec_idx, caam);
> > > >
> > > > return 0;
> > > > }
> > > > @@ -188,10 +147,10 @@ static int jr_hw_reset(uint8_t sec_idx)
> > > > /* -1 --- error, can't enqueue -- no space available */
> > > > static int jr_enqueue(uint32_t *desc_addr,
> > > > void (*callback)(uint32_t status, void *arg),
> > > > - void *arg, uint8_t sec_idx)
> > > > + void *arg, uint8_t sec_idx, struct caam_regs *caam)
> > > > {
> > > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > > - struct jobring *jr = &jr0[sec_idx];
> > > > + struct jr_regs *regs = caam->regs;
> > > > + struct jobring *jr = &caam->jr[sec_idx];
> > > > int head = jr->head;
> > > > uint32_t desc_word;
> > > > int length = desc_len(desc_addr); @@ -263,10 +222,10 @@
> > > > static int jr_enqueue(uint32_t *desc_addr,
> > > > return 0;
> > > > }
> > > >
> > > > -static int jr_dequeue(int sec_idx)
> > > > +static int jr_dequeue(int sec_idx, struct caam_regs *caam)
> > > > {
> > > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > > - struct jobring *jr = &jr0[sec_idx];
> > > > + struct jr_regs *regs = caam->regs;
> > > > + struct jobring *jr = &caam->jr[sec_idx];
> > > > int head = jr->head;
> > > > int tail = jr->tail;
> > > > int idx, i, found;
> > > > @@ -349,14 +308,18 @@ static void desc_done(uint32_t status, void *arg)
> > > > {
> > > > struct result *x = arg;
> > > > x->status = status;
> > > > -#ifndef CONFIG_SPL_BUILD
> > > > caam_jr_strstatus(status);
> > > > -#endif
> > > > x->done = 1;
> > > > }
> > > >
> > > > static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
> > > > {
> > > > + struct caam_regs *caam;
> > > > +#if CONFIG_IS_ENABLED(DM)
> > > > + caam = dev_get_priv(caam_dev); #else
> > > > + caam = &caam_st;
> > > > +#endif
> > > > unsigned long long timeval = 0;
> > > > unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
> > > > struct result op;
> > > > @@ -364,7 +327,7 @@ static inline int
> > > > run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
> > > >
> > > > memset(&op, 0, sizeof(op));
> > > >
> > > > - ret = jr_enqueue(desc, desc_done, &op, sec_idx);
> > > > + ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
> > > > if (ret) {
> > > > debug("Error in SEC enq\n");
> > > > ret = JQ_ENQ_ERR;
> > > > @@ -375,7 +338,7 @@ static inline int
> > > > run_descriptor_jr_idx(uint32_t *desc,
> > > uint8_t sec_idx)
> > > > udelay(1);
> > > > timeval += 1;
> > > >
> > > > - ret = jr_dequeue(sec_idx);
> > > > + ret = jr_dequeue(sec_idx, caam);
> > > > if (ret) {
> > > > debug("Error in SEC deq\n");
> > > > ret = JQ_DEQ_ERR; @@ -402,13 +365,62 @@ int
> > > > run_descriptor_jr(uint32_t *desc)
> > > > return run_descriptor_jr_idx(desc, 0);
> > > > }
> > > >
> > > > +static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam) {
> > > > + struct jobring *jr = &caam->jr[sec_idx];
> > > > +
> > > > + jr->head = 0;
> > > > + jr->tail = 0;
> > > > + jr->read_idx = 0;
> > > > + jr->write_idx = 0;
> > > > + memset(jr->info, 0, sizeof(jr->info));
> > > > + memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
> > > > + memset(jr->output_ring, 0, jr->size * sizeof(struct
> > > > + op_ring));
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int jr_hw_reset(struct jr_regs *regs) {
> > > > + uint32_t timeout = 100000;
> > > > + uint32_t jrint, jrcr;
> > > > +
> > > > + sec_out32(®s->jrcr, JRCR_RESET);
> > > > + do {
> > > > + jrint = sec_in32(®s->jrint);
> > > > + } while (((jrint & JRINT_ERR_HALT_MASK) ==
> > > > + JRINT_ERR_HALT_INPROGRESS) && --timeout);
> > > > +
> > > > + jrint = sec_in32(®s->jrint);
> > > > + if (((jrint & JRINT_ERR_HALT_MASK) !=
> > > > + JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
> > > > + return -1;
> > > > +
> > > > + timeout = 100000;
> > > > + sec_out32(®s->jrcr, JRCR_RESET);
> > > > + do {
> > > > + jrcr = sec_in32(®s->jrcr);
> > > > + } while ((jrcr & JRCR_RESET) && --timeout);
> > > > +
> > > > + if (timeout == 0)
> > > > + return -1;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > static inline int jr_reset_sec(uint8_t sec_idx)
> > > > {
> > > > - if (jr_hw_reset(sec_idx) < 0)
> > > > + struct caam_regs *caam;
> > > > +#if CONFIG_IS_ENABLED(DM)
> > > > + caam = dev_get_priv(caam_dev); #else
> > > > + caam = &caam_st;
> > > > +#endif
> > > > + if (jr_hw_reset(caam->regs) < 0)
> > > > return -1;
> > > >
> > > > /* Clean up the jobring structure maintained by software */
> > > > - jr_sw_cleanup(sec_idx);
> > > > + jr_sw_cleanup(sec_idx, caam);
> > > >
> > > > return 0;
> > > > }
> > > > @@ -418,9 +430,15 @@ int jr_reset(void)
> > > > return jr_reset_sec(0);
> > > > }
> > > >
> > > > -static inline int sec_reset_idx(uint8_t sec_idx)
> > > > +int sec_reset(void)
> > > > {
> > > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > > + struct caam_regs *caam;
> > > > +#if CONFIG_IS_ENABLED(DM)
> > > > + caam = dev_get_priv(caam_dev); #else
> > > > + caam = &caam_st;
> > > > +#endif
> > > > + ccsr_sec_t *sec = caam->sec;
> > > > uint32_t mcfgr = sec_in32(&sec->mcfgr);
> > > > uint32_t timeout = 100000;
> > > >
> > > > @@ -446,11 +464,7 @@ static inline int sec_reset_idx(uint8_t
> > > > sec_idx)
> > > >
> > > > return 0;
> > > > }
> > > > -int sec_reset(void)
> > > > -{
> > > > - return sec_reset_idx(0);
> > > > -}
> > > > -#ifndef CONFIG_SPL_BUILD
> > > > +
> > > > static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
> > > > {
> > > > u32 *desc;
> > > > @@ -496,12 +510,11 @@ static int deinstantiate_rng(u8 sec_idx, int
> > > state_handle_mask)
> > > > return ret;
> > > > }
> > > >
> > > > -static int instantiate_rng(u8 sec_idx, int gen_sk)
> > > > +static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int
> > > > +gen_sk)
> > > > {
> > > > u32 *desc;
> > > > u32 rdsta_val;
> > > > int ret = 0, sh_idx, size;
> > > > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
> > > > struct rng4tst __iomem *rng =
> > > > (struct rng4tst __iomem *)&sec->rng;
> > > >
> > > > @@ -554,9 +567,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk)
> > > > return ret;
> > > > }
> > > >
> > > > -static u8 get_rng_vid(uint8_t sec_idx)
> > > > +static u8 get_rng_vid(ccsr_sec_t *sec)
> > > > {
> > > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > > u8 vid;
> > > >
> > > > if (caam_get_era() < 10) {
> > > > @@ -574,9 +586,8 @@ static u8 get_rng_vid(uint8_t sec_idx)
> > > > * By default, the TRNG runs for 200 clocks per sample;
> > > > * 1200 clocks per sample generates better entropy.
> > > > */
> > > > -static void kick_trng(int ent_delay, uint8_t sec_idx)
> > > > +static void kick_trng(int ent_delay, ccsr_sec_t *sec)
> > > > {
> > > > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
> > > > struct rng4tst __iomem *rng =
> > > > (struct rng4tst __iomem *)&sec->rng;
> > > > u32 val;
> > > > @@ -603,10 +614,9 @@ static void kick_trng(int ent_delay, uint8_t
> sec_idx)
> > > > sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
> > > > }
> > > >
> > > > -static int rng_init(uint8_t sec_idx)
> > > > +static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
> > > > {
> > > > int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
> > > > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
> > > > struct rng4tst __iomem *rng =
> > > > (struct rng4tst __iomem *)&sec->rng;
> > > > u32 inst_handles;
> > > > @@ -624,7 +634,7 @@ static int rng_init(uint8_t sec_idx)
> > > > * the TRNG parameters.
> > > > */
> > > > if (!inst_handles) {
> > > > - kick_trng(ent_delay, sec_idx);
> > > > + kick_trng(ent_delay, sec);
> > > > ent_delay += 400;
> > > > }
> > > > /*
> > > > @@ -634,7 +644,7 @@ static int rng_init(uint8_t sec_idx)
> > > > * interval, leading to a sucessful initialization of
> > > > * the RNG.
> > > > */
> > > > - ret = instantiate_rng(sec_idx, gen_sk);
> > > > + ret = instantiate_rng(sec_idx, sec, gen_sk);
> > > > } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
> > > > if (ret) {
> > > > printf("SEC%u: Failed to instantiate RNG\n",
> > > > sec_idx); @@ -646,13 +656,28 @@ static int rng_init(uint8_t
> > > > sec_idx)
> > > >
> > > > return ret;
> > > > }
> > > > -#endif
> > > > +
> > > > int sec_init_idx(uint8_t sec_idx)
> > > > {
> > > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > > - uint32_t mcr = sec_in32(&sec->mcfgr);
> > > > int ret = 0;
> > > > -
> > > > + struct caam_regs *caam;
> > > > +#if CONFIG_IS_ENABLED(DM)
> > > > + if (!caam_dev) {
> > > > + printf("caam_jr: caam not found\n");
> > > > + return -1;
> > > > + }
> > > > + caam = dev_get_priv(caam_dev); #else
> > > > + caam_st.sec = (void *)SEC_ADDR(sec_idx);
> > > > + caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > > + caam_st.jrid = 0;
> > > > + caam = &caam_st;
> > > > +#endif
> > > > + ccsr_sec_t *sec = caam->sec;
> > > > + uint32_t mcr = sec_in32(&sec->mcfgr); #if
> > > > +defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> > > > + uint32_t jrdid_ms = 0;
> > > > +#endif
> > > > #ifdef CONFIG_FSL_CORENET
> > > > uint32_t liodnr;
> > > > uint32_t liodn_ns;
> > > > @@ -682,6 +707,11 @@ int sec_init_idx(uint8_t sec_idx)
> > > > mcr |= (1 << MCFGR_PS_SHIFT);
> > > > #endif
> > > > sec_out32(&sec->mcfgr, mcr);
> > > > +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> > > > + jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ |
> > > JRDID_MS_PRIM_DID;
> > > > + sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms); #endif
> > > > + jr_reset();
> > > >
> > > > #ifdef CONFIG_FSL_CORENET
> > > > #ifdef CONFIG_SPL_BUILD
> > > > @@ -693,20 +723,19 @@ int sec_init_idx(uint8_t sec_idx)
> > > > liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
> > > > liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
> > > >
> > > > - liodnr = sec_in32(&sec->jrliodnr[0].ls) &
> > > > + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
> > > > ~(JRNSLIODN_MASK | JRSLIODN_MASK);
> > > > liodnr = liodnr |
> > > > (liodn_ns << JRNSLIODN_SHIFT) |
> > > > (liodn_s << JRSLIODN_SHIFT);
> > > > - sec_out32(&sec->jrliodnr[0].ls, liodnr);
> > > > + sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
> > > > #else
> > > > - liodnr = sec_in32(&sec->jrliodnr[0].ls);
> > > > + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
> > > > liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
> > > > liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
> > > > #endif
> > > > #endif
> > > > -
> > > > - ret = jr_init(sec_idx);
> > > > + ret = jr_init(sec_idx, caam);
> > > > if (ret < 0) {
> > > > printf("SEC%u: initialization failed\n", sec_idx);
> > > > return -1;
> > > > @@ -719,9 +748,9 @@ int sec_init_idx(uint8_t sec_idx)
> > > >
> > > > pamu_enable();
> > > > #endif
> > > > -#ifndef CONFIG_SPL_BUILD
> > > > - if (get_rng_vid(sec_idx) >= 4) {
> > > > - if (rng_init(sec_idx) < 0) {
> > > > +
> > > > + if (get_rng_vid(caam->sec) >= 4) {
> > > > + if (rng_init(sec_idx, caam->sec) < 0) {
> > > > printf("SEC%u: RNG instantiation failed\n", sec_idx);
> > > > return -1;
> > > > }
> > > > @@ -735,7 +764,6 @@ int sec_init_idx(uint8_t sec_idx)
> > > >
> > > > printf("SEC%u: RNG instantiated\n", sec_idx);
> > > > }
> > > > -#endif
> > > > return ret;
> > > > }
> > > >
> > > > @@ -743,3 +771,76 @@ int sec_init(void)
> > > > {
> > > > return sec_init_idx(0);
> > > > }
> > > > +
> > > > +#if CONFIG_IS_ENABLED(DM)
> > > > +static int caam_jr_ioctl(struct udevice *dev, unsigned long
> > > > +request, void *buf) {
> > > > + if (request != CAAM_JR_RUN_DESC)
> > > > + return -ENOSYS;
> > > > +
> > > > + return run_descriptor_jr(buf); }
> > > > +
> > > > +static int caam_jr_probe(struct udevice *dev) {
> > > > + struct caam_regs *caam = dev_get_priv(dev);
> > > > + fdt_addr_t addr;
> > > > + ofnode node;
> > > > + unsigned int jr_node = 0;
> > > > +
> > > > + caam_dev = dev;
> > > > +
> > > > + addr = dev_read_addr(dev);
> > > > + if (addr == FDT_ADDR_T_NONE) {
> > > > + printf("caam_jr: crypto not found\n");
> > > > + return -EINVAL;
> > > > + }
> > > > + caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
> > > > + caam->regs = (struct jr_regs *)caam->sec;
> > > > +
> > > > + /* Check for enabled job ring node */
> > > > + ofnode_for_each_subnode(node, dev_ofnode(dev)) {
> > > > + if (!ofnode_is_available(node))
> > > > + continue;
> > > > +
> > > > + jr_node = ofnode_read_u32_default(node, "reg", -1);
> > > > + if (jr_node > 0) {
> > > > + caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
> > > > + while (!(jr_node & 0x0F))
> > > > + jr_node = jr_node >> 4;
> > > > +
> > > > + caam->jrid = jr_node - 1;
> > > > + break;
> > > > + }
> > > > + }
> > > > +
> > > > + if (sec_init())
> > > > + printf("\nsec_init failed!\n");
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int caam_jr_bind(struct udevice *dev) {
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static const struct misc_ops caam_jr_ops = {
> > > > + .ioctl = caam_jr_ioctl,
> > > > +};
> > > > +
> > > > +static const struct udevice_id caam_jr_match[] = {
> > > > + { .compatible = "fsl,sec-v4.0" },
> > > > + { }
> > > > +};
> > > > +
> > > > +U_BOOT_DRIVER(caam_jr) = {
> > > > + .name = "caam_jr",
> > > > + .id = UCLASS_MISC,
> > > > + .of_match = caam_jr_match,
> > > > + .ops = &caam_jr_ops,
> > > > + .bind = caam_jr_bind,
> > > > + .probe = caam_jr_probe,
> > > > + .priv_auto = sizeof(struct caam_regs),
> > > > +};
> > > > +#endif
> > > > diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
> > > > index 1047aa772c..3eb7be79da 100644
> > > > --- a/drivers/crypto/fsl/jr.h
> > > > +++ b/drivers/crypto/fsl/jr.h
> > > > @@ -1,6 +1,7 @@
> > > > /* SPDX-License-Identifier: GPL-2.0+ */
> > > > /*
> > > > * Copyright 2008-2014 Freescale Semiconductor, Inc.
> > > > + * Copyright 2021 NXP
> > > > *
> > > > */
> > > >
> > > > @@ -8,7 +9,9 @@
> > > > #define __JR_H
> > > >
> > > > #include <linux/compiler.h>
> > > > +#include "fsl_sec.h"
> > > > #include "type.h"
> > > > +#include <misc.h>
> > > >
> > > > #define JR_SIZE 4
> > > > /* Timeout currently defined as 10 sec */ @@ -35,12 +38,21 @@
> > > > #define JRSLIODN_SHIFT 0
> > > > #define JRSLIODN_MASK 0x00000fff
> > > >
> > > > -#define JQ_DEQ_ERR -1
> > > > -#define JQ_DEQ_TO_ERR -2
> > > > -#define JQ_ENQ_ERR -3
> > > > +#define JRDID_MS_PRIM_DID BIT(0)
> > > > +#define JRDID_MS_PRIM_TZ BIT(4)
> > > > +#define JRDID_MS_TZ_OWN BIT(15)
> > > > +
> > > > +#define JQ_DEQ_ERR (-1)
> > > > +#define JQ_DEQ_TO_ERR (-2)
> > > > +#define JQ_ENQ_ERR (-3)
> > > >
> > > > #define RNG4_MAX_HANDLES 2
> > > >
> > > > +enum {
> > > > + /* Run caam jobring descriptor(in buf) */
> > > > + CAAM_JR_RUN_DESC,
> > > > +};
> > > > +
> > > > struct op_ring {
> > > > caam_dma_addr_t desc;
> > > > uint32_t status;
> > > > @@ -102,6 +114,19 @@ struct result {
> > > > uint32_t status;
> > > > };
> > > >
> > > > +/*
> > > > + * struct caam_regs - CAAM initialization register interface
> > > > + *
> > > > + * Interface to caam memory map, jobring register, jobring storage.
> > > > + */
> > > > +struct caam_regs {
> > > > + ccsr_sec_t *sec; /*caam initialization registers*/
> > > > + struct jr_regs *regs; /*jobring configuration registers*/
> > > > + u8 jrid; /*id to identify a jobring*/
> > > > + /*Private sub-storage for a single JobR*/
> > > > + struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> > > > +};
> > > > +
> > > > void caam_jr_strstatus(u32 status);
> > > > int run_descriptor_jr(uint32_t *desc);
> > > >
> > >
> > > --
> > >
> >
> =================================================================
> > > ====
> > > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> > > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany
> > > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email:
> > > sbabic@denx.de
> > >
> >
> =================================================================
> > > ====
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-02-25 7:03 ` Gaurav Jain
@ 2022-03-03 12:44 ` Gaurav Jain
2022-03-03 13:02 ` Stefano Babic
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-03-03 12:44 UTC (permalink / raw)
To: Stefano Babic, u-boot, Marek Vasut
Cc: Fabio Estevam, Peng Fan, Simon Glass, Priyanka Jain, Ye Li,
Horia Geanta, Ji Luo, Franck Lenormand, Silvano Di Ninno,
Sahil Malhotra, Pankaj Gupta, Varun Sethi, dl-uboot-imx,
Shengzhou Liu, Mingkai Hu, Rajesh Bhagat, Meenakshi Aggarwal,
Wasim Khan, Alison Wang, Pramod Kumar, Andy Tang, Adrian Alonso,
Vladimir Oltean
Hello Stefano
A gentle reminder!!
Need your help to check the proposed solution to fix imx6dl_mamoj SPL size issue shared in last mail.
Regards
Gaurav Jain
> -----Original Message-----
> From: Gaurav Jain
> Sent: Friday, February 25, 2022 12:33 PM
> To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek Vasut
> <marex@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> Simon Glass <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye
> Li <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> Hello Stefano
>
> > -----Original Message-----
> > From: Gaurav Jain
> > Sent: Friday, February 11, 2022 3:09 PM
> > To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek Vasut
> > <marex@denx.de>
> > Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> > Simon Glass <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>;
> > Ye Li <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> > <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano
> > Di Ninno <silvano.dininno@nxp.com>; Sahil Malhotra
> > <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun
> > Sethi <V.Sethi@nxp.com>; dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou
> > Liu <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> > Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> > <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> Alison
> > Wang <alison.wang@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>;
> > Andy Tang <andy.tang@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
> > Vladimir Oltean <olteanv@gmail.com>
> > Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> > CAAM Job ring driver model
> >
> > Hello Marek
> >
> > A gentle reminder!!
> > Please help to check if some feature can be dropped in SPL from
> > imx6dl_mamoj board so that CAAM driver model patches can be accepted.
> >
> > Regards
> > Gaurav Jain
> >
> > > -----Original Message-----
> > > From: Gaurav Jain
> > > Sent: Monday, February 7, 2022 12:43 PM
> > > To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek
> > > Vasut <marex@denx.de>
> > > Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> > > Simon Glass <sjg@chromium.org>; Priyanka Jain
> > > <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
> > > <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> > > <franck.lenormand@nxp.com>; Silvano Di Ninno
> > > <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> > > Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> > > dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
> > > <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> > > Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> > > <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> > Alison
> > > Wang <alison.wang@nxp.com>; Pramod Kumar
> > <pramod.kumar_1@nxp.com>;
> > > Andy Tang <andy.tang@nxp.com>; Adrian Alonso
> > > <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> > > Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> > > CAAM Job ring driver model
> > >
> > > Hello Marek
> > >
> > > > -----Original Message-----
> > > > From: Stefano Babic <sbabic@denx.de>
> > > > Sent: Saturday, February 5, 2022 7:46 PM
> > > > To: Gaurav Jain <gaurav.jain@nxp.com>; u-boot@lists.denx.de
> > > > Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
> > > > <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> > > > <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> > > > <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> > > > <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>;
> > > > Silvano Di Ninno <silvano.dininno@nxp.com>; Sahil Malhotra
> > > > <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>;
> > > > Varun Sethi <V.Sethi@nxp.com>; dl-uboot-imx <uboot-imx@nxp.com>;
> > > > Shengzhou Liu <shengzhou.liu@nxp.com>; Mingkai Hu
> > > > <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> > > > Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> > > > <wasim.khan@nxp.com>;
> > > Alison
> > > > Wang <alison.wang@nxp.com>; Pramod Kumar
> > > <pramod.kumar_1@nxp.com>;
> > > > Andy Tang <andy.tang@nxp.com>; Adrian Alonso
> > > > <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>;
> > > > Marek Vasut <marex@denx.de>
> > > > Subject: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> > > > CAAM Job ring driver model
> > > >
> > > > Caution: EXT Email
> > > >
> > > > Hi Gaurav,
> > > >
> > > > rather I still have issues to run CI with this applied. The reason
> > > > is that this adds an overhead to SPL and it breaks the board
> > > > imx6dl_mamoj because SPL exceeds the maximum size for a DL SOC.
> > > >
> > > > See
> > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> > > > so
> > > > ur
> > > > ce.d
> > > > enx.de%2Fu-boot%2Fcustodians%2Fu-boot-imx%2F-
> > > > %2Fjobs%2F387370&data=04%7C01%7Cgaurav.jain%40nxp.com%7C
> 3a
> > 2
> > > 73
> > > >
> > >
> >
> 1dd27fc4bebcad308d9e8b21464%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C
> > > >
> > >
> >
> 0%7C0%7C637796673834942697%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> > > >
> > >
> >
> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&am
> > > >
> > >
> >
> p;sdata=pI%2F%2FlNtrdrGCa8sSvcr6uNu4jze7pzDqZtI52FIDj50%3D&reserve
> > > > d=0
> > > >
> > > > I do not know if it is possible to drop some features from SPL for
> > > > this board (Added Marek as board maintainer).
>
> As we have not received any response from imx6dl_mamoj board maintainer.
> I propose the below solution
>
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
> - select FSL_CAAM if HAS_CAAM
> - imply CMD_DEKBLOB if HAS_CAAM
> + imply FSL_CAAM if HAS_CAAM
> + imply CMD_DEKBLOB if FSL_CAAM
> Help
>
> --- a/configs/imx6dl_mamoj_defconfig
> +++ b/configs/imx6dl_mamoj_defconfig
> @@ -59,3 +59,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> +CONFIG_FSL_CAAM=n
>
> Need your help to review this or suggest any other solution.
>
> Regards
> Gaurav Jain
>
> > >
> > > CONFIG_IMX_HAB is enabled for imx6dl_mamoj. So CAAM is built for
> > > SPL, results in increased size.
> > > However CAAM is not initialized in SPL. As Stefano suggested, Can
> > > you drop some features from SPL?
> > >
> > > Regards
> > > Gaurav Jain
> > > >
> > > > Best regards,
> > > > Stefano
> > > >
> > > > On 10.01.22 13:27, Gaurav Jain wrote:
> > > > > added device tree support for job ring driver.
> > > > > sec is initialized based on job ring information processed from
> > > > > device tree.
> > > > >
> > > > > Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> > > > > Reviewed-by: Ye Li <ye.li@nxp.com>
> > > > > ---
> > > > > drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++++--------------
> > > > > drivers/crypto/fsl/jr.h | 31 +++-
> > > > > 2 files changed, 240 insertions(+), 114 deletions(-)
> > > > >
> > > > > diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
> > > > > index
> > > > > 22b649219e..8103987425 100644
> > > > > --- a/drivers/crypto/fsl/jr.c
> > > > > +++ b/drivers/crypto/fsl/jr.c
> > > > > @@ -1,7 +1,7 @@
> > > > > // SPDX-License-Identifier: GPL-2.0+
> > > > > /*
> > > > > * Copyright 2008-2014 Freescale Semiconductor, Inc.
> > > > > - * Copyright 2018 NXP
> > > > > + * Copyright 2018, 2021 NXP
> > > > > *
> > > > > * Based on CAAM driver in drivers/crypto/caam in Linux
> > > > > */
> > > > > @@ -11,7 +11,6 @@
> > > > > #include <linux/kernel.h>
> > > > > #include <log.h>
> > > > > #include <malloc.h>
> > > > > -#include "fsl_sec.h"
> > > > > #include "jr.h"
> > > > > #include "jobdesc.h"
> > > > > #include "desc_constr.h"
> > > > > @@ -21,7 +20,10 @@
> > > > > #include <asm/cache.h>
> > > > > #include <asm/fsl_pamu.h>
> > > > > #endif
> > > > > +#include <dm.h>
> > > > > #include <dm/lists.h>
> > > > > +#include <dm/root.h>
> > > > > +#include <dm/device-internal.h>
> > > > > #include <linux/delay.h>
> > > > >
> > > > > #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size
> > > > > -
> > > > > 1)) @@ -35,20 +37,29 @@ uint32_t
> > > > sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
> > > > > #endif
> > > > > };
> > > > >
> > > > > +#if CONFIG_IS_ENABLED(DM)
> > > > > +struct udevice *caam_dev;
> > > > > +#else
> > > > > #define SEC_ADDR(idx) \
> > > > > (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
> > > > >
> > > > > #define SEC_JR0_ADDR(idx) \
> > > > > (ulong)(SEC_ADDR(idx) + \
> > > > > (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
> > > > > +struct caam_regs caam_st;
> > > > > +#endif
> > > > >
> > > > > -struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> > > > > +static inline u32 jr_start_reg(u8 jrid) {
> > > > > + return (1 << jrid);
> > > > > +}
> > > > >
> > > > > -static inline void start_jr0(uint8_t sec_idx)
> > > > > +static inline void start_jr(struct caam_regs *caam)
> > > > > {
> > > > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > > > + ccsr_sec_t *sec = caam->sec;
> > > > > u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
> > > > > u32 scfgr = sec_in32(&sec->scfgr);
> > > > > + u32 jrstart = jr_start_reg(caam->jrid);
> > > > >
> > > > > if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
> > > > > /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or @@ -56,23
> > > > > +67,16 @@ static inline void start_jr0(uint8_t sec_idx)
> > > > > */
> > > > > if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
> > > > > (scfgr & SEC_SCFGR_VIRT_EN))
> > > > > - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
> > > > > + sec_out32(&sec->jrstartr, jrstart);
> > > > > } else {
> > > > > /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
> > > > > if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
> > > > > - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
> > > > > + sec_out32(&sec->jrstartr, jrstart);
> > > > > }
> > > > > }
> > > > >
> > > > > -static inline void jr_reset_liodn(uint8_t sec_idx)
> > > > > +static inline void jr_disable_irq(struct jr_regs *regs)
> > > > > {
> > > > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > > > - sec_out32(&sec->jrliodnr[0].ls, 0);
> > > > > -}
> > > > > -
> > > > > -static inline void jr_disable_irq(uint8_t sec_idx) -{
> > > > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > > > uint32_t jrcfg = sec_in32(®s->jrcfg1);
> > > > >
> > > > > jrcfg = jrcfg | JR_INTMASK; @@ -80,10 +84,10 @@ static
> > > > > inline void jr_disable_irq(uint8_t sec_idx)
> > > > > sec_out32(®s->jrcfg1, jrcfg);
> > > > > }
> > > > >
> > > > > -static void jr_initregs(uint8_t sec_idx)
> > > > > +static void jr_initregs(uint8_t sec_idx, struct caam_regs
> > > > > +*caam)
> > > > > {
> > > > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > > > - struct jobring *jr = &jr0[sec_idx];
> > > > > + struct jr_regs *regs = caam->regs;
> > > > > + struct jobring *jr = &caam->jr[sec_idx];
> > > > > caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
> > > > > caam_dma_addr_t op_base = virt_to_phys((void
> > > > > *)jr->output_ring);
> > > > >
> > > > > @@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx)
> > > > > sec_out32(®s->irs, JR_SIZE);
> > > > >
> > > > > if (!jr->irq)
> > > > > - jr_disable_irq(sec_idx);
> > > > > + jr_disable_irq(regs);
> > > > > }
> > > > >
> > > > > -static int jr_init(uint8_t sec_idx)
> > > > > +static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
> > > > > {
> > > > > - struct jobring *jr = &jr0[sec_idx];
> > > > > + struct jobring *jr = &caam->jr[sec_idx];
> > > > >
> > > > > memset(jr, 0, sizeof(struct jobring));
> > > > >
> > > > > - jr->jq_id = DEFAULT_JR_ID;
> > > > > + jr->jq_id = caam->jrid;
> > > > > jr->irq = DEFAULT_IRQ;
> > > > >
> > > > > #ifdef CONFIG_FSL_CORENET
> > > > > @@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx)
> > > > > memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
> > > > > memset(jr->output_ring, 0, jr->op_size);
> > > > >
> > > > > - start_jr0(sec_idx);
> > > > > -
> > > > > - jr_initregs(sec_idx);
> > > > > -
> > > > > - return 0;
> > > > > -}
> > > > > -
> > > > > -static int jr_sw_cleanup(uint8_t sec_idx) -{
> > > > > - struct jobring *jr = &jr0[sec_idx];
> > > > > -
> > > > > - jr->head = 0;
> > > > > - jr->tail = 0;
> > > > > - jr->read_idx = 0;
> > > > > - jr->write_idx = 0;
> > > > > - memset(jr->info, 0, sizeof(jr->info));
> > > > > - memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
> > > > > - memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
> > > > > -
> > > > > - return 0;
> > > > > -}
> > > > > -
> > > > > -static int jr_hw_reset(uint8_t sec_idx) -{
> > > > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > > > - uint32_t timeout = 100000;
> > > > > - uint32_t jrint, jrcr;
> > > > > -
> > > > > - sec_out32(®s->jrcr, JRCR_RESET);
> > > > > - do {
> > > > > - jrint = sec_in32(®s->jrint);
> > > > > - } while (((jrint & JRINT_ERR_HALT_MASK) ==
> > > > > - JRINT_ERR_HALT_INPROGRESS) && --timeout);
> > > > > -
> > > > > - jrint = sec_in32(®s->jrint);
> > > > > - if (((jrint & JRINT_ERR_HALT_MASK) !=
> > > > > - JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
> > > > > - return -1;
> > > > > -
> > > > > - timeout = 100000;
> > > > > - sec_out32(®s->jrcr, JRCR_RESET);
> > > > > - do {
> > > > > - jrcr = sec_in32(®s->jrcr);
> > > > > - } while ((jrcr & JRCR_RESET) && --timeout);
> > > > > -
> > > > > - if (timeout == 0)
> > > > > - return -1;
> > > > > + start_jr(caam);
> > > > > + jr_initregs(sec_idx, caam);
> > > > >
> > > > > return 0;
> > > > > }
> > > > > @@ -188,10 +147,10 @@ static int jr_hw_reset(uint8_t sec_idx)
> > > > > /* -1 --- error, can't enqueue -- no space available */
> > > > > static int jr_enqueue(uint32_t *desc_addr,
> > > > > void (*callback)(uint32_t status, void *arg),
> > > > > - void *arg, uint8_t sec_idx)
> > > > > + void *arg, uint8_t sec_idx, struct caam_regs *caam)
> > > > > {
> > > > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > > > - struct jobring *jr = &jr0[sec_idx];
> > > > > + struct jr_regs *regs = caam->regs;
> > > > > + struct jobring *jr = &caam->jr[sec_idx];
> > > > > int head = jr->head;
> > > > > uint32_t desc_word;
> > > > > int length = desc_len(desc_addr); @@ -263,10 +222,10 @@
> > > > > static int jr_enqueue(uint32_t *desc_addr,
> > > > > return 0;
> > > > > }
> > > > >
> > > > > -static int jr_dequeue(int sec_idx)
> > > > > +static int jr_dequeue(int sec_idx, struct caam_regs *caam)
> > > > > {
> > > > > - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > > > - struct jobring *jr = &jr0[sec_idx];
> > > > > + struct jr_regs *regs = caam->regs;
> > > > > + struct jobring *jr = &caam->jr[sec_idx];
> > > > > int head = jr->head;
> > > > > int tail = jr->tail;
> > > > > int idx, i, found;
> > > > > @@ -349,14 +308,18 @@ static void desc_done(uint32_t status, void
> *arg)
> > > > > {
> > > > > struct result *x = arg;
> > > > > x->status = status;
> > > > > -#ifndef CONFIG_SPL_BUILD
> > > > > caam_jr_strstatus(status); -#endif
> > > > > x->done = 1;
> > > > > }
> > > > >
> > > > > static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
> > > > > {
> > > > > + struct caam_regs *caam;
> > > > > +#if CONFIG_IS_ENABLED(DM)
> > > > > + caam = dev_get_priv(caam_dev); #else
> > > > > + caam = &caam_st;
> > > > > +#endif
> > > > > unsigned long long timeval = 0;
> > > > > unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
> > > > > struct result op;
> > > > > @@ -364,7 +327,7 @@ static inline int
> > > > > run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
> > > > >
> > > > > memset(&op, 0, sizeof(op));
> > > > >
> > > > > - ret = jr_enqueue(desc, desc_done, &op, sec_idx);
> > > > > + ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
> > > > > if (ret) {
> > > > > debug("Error in SEC enq\n");
> > > > > ret = JQ_ENQ_ERR;
> > > > > @@ -375,7 +338,7 @@ static inline int
> > > > > run_descriptor_jr_idx(uint32_t *desc,
> > > > uint8_t sec_idx)
> > > > > udelay(1);
> > > > > timeval += 1;
> > > > >
> > > > > - ret = jr_dequeue(sec_idx);
> > > > > + ret = jr_dequeue(sec_idx, caam);
> > > > > if (ret) {
> > > > > debug("Error in SEC deq\n");
> > > > > ret = JQ_DEQ_ERR; @@ -402,13 +365,62 @@
> > > > > int run_descriptor_jr(uint32_t *desc)
> > > > > return run_descriptor_jr_idx(desc, 0);
> > > > > }
> > > > >
> > > > > +static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam) {
> > > > > + struct jobring *jr = &caam->jr[sec_idx];
> > > > > +
> > > > > + jr->head = 0;
> > > > > + jr->tail = 0;
> > > > > + jr->read_idx = 0;
> > > > > + jr->write_idx = 0;
> > > > > + memset(jr->info, 0, sizeof(jr->info));
> > > > > + memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
> > > > > + memset(jr->output_ring, 0, jr->size * sizeof(struct
> > > > > + op_ring));
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +static int jr_hw_reset(struct jr_regs *regs) {
> > > > > + uint32_t timeout = 100000;
> > > > > + uint32_t jrint, jrcr;
> > > > > +
> > > > > + sec_out32(®s->jrcr, JRCR_RESET);
> > > > > + do {
> > > > > + jrint = sec_in32(®s->jrint);
> > > > > + } while (((jrint & JRINT_ERR_HALT_MASK) ==
> > > > > + JRINT_ERR_HALT_INPROGRESS) && --timeout);
> > > > > +
> > > > > + jrint = sec_in32(®s->jrint);
> > > > > + if (((jrint & JRINT_ERR_HALT_MASK) !=
> > > > > + JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
> > > > > + return -1;
> > > > > +
> > > > > + timeout = 100000;
> > > > > + sec_out32(®s->jrcr, JRCR_RESET);
> > > > > + do {
> > > > > + jrcr = sec_in32(®s->jrcr);
> > > > > + } while ((jrcr & JRCR_RESET) && --timeout);
> > > > > +
> > > > > + if (timeout == 0)
> > > > > + return -1;
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > static inline int jr_reset_sec(uint8_t sec_idx)
> > > > > {
> > > > > - if (jr_hw_reset(sec_idx) < 0)
> > > > > + struct caam_regs *caam;
> > > > > +#if CONFIG_IS_ENABLED(DM)
> > > > > + caam = dev_get_priv(caam_dev); #else
> > > > > + caam = &caam_st;
> > > > > +#endif
> > > > > + if (jr_hw_reset(caam->regs) < 0)
> > > > > return -1;
> > > > >
> > > > > /* Clean up the jobring structure maintained by software */
> > > > > - jr_sw_cleanup(sec_idx);
> > > > > + jr_sw_cleanup(sec_idx, caam);
> > > > >
> > > > > return 0;
> > > > > }
> > > > > @@ -418,9 +430,15 @@ int jr_reset(void)
> > > > > return jr_reset_sec(0);
> > > > > }
> > > > >
> > > > > -static inline int sec_reset_idx(uint8_t sec_idx)
> > > > > +int sec_reset(void)
> > > > > {
> > > > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > > > + struct caam_regs *caam;
> > > > > +#if CONFIG_IS_ENABLED(DM)
> > > > > + caam = dev_get_priv(caam_dev); #else
> > > > > + caam = &caam_st;
> > > > > +#endif
> > > > > + ccsr_sec_t *sec = caam->sec;
> > > > > uint32_t mcfgr = sec_in32(&sec->mcfgr);
> > > > > uint32_t timeout = 100000;
> > > > >
> > > > > @@ -446,11 +464,7 @@ static inline int sec_reset_idx(uint8_t
> > > > > sec_idx)
> > > > >
> > > > > return 0;
> > > > > }
> > > > > -int sec_reset(void)
> > > > > -{
> > > > > - return sec_reset_idx(0);
> > > > > -}
> > > > > -#ifndef CONFIG_SPL_BUILD
> > > > > +
> > > > > static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
> > > > > {
> > > > > u32 *desc;
> > > > > @@ -496,12 +510,11 @@ static int deinstantiate_rng(u8 sec_idx,
> > > > > int
> > > > state_handle_mask)
> > > > > return ret;
> > > > > }
> > > > >
> > > > > -static int instantiate_rng(u8 sec_idx, int gen_sk)
> > > > > +static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec,
> > > > > +int
> > > > > +gen_sk)
> > > > > {
> > > > > u32 *desc;
> > > > > u32 rdsta_val;
> > > > > int ret = 0, sh_idx, size;
> > > > > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
> *)SEC_ADDR(sec_idx);
> > > > > struct rng4tst __iomem *rng =
> > > > > (struct rng4tst __iomem *)&sec->rng;
> > > > >
> > > > > @@ -554,9 +567,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk)
> > > > > return ret;
> > > > > }
> > > > >
> > > > > -static u8 get_rng_vid(uint8_t sec_idx)
> > > > > +static u8 get_rng_vid(ccsr_sec_t *sec)
> > > > > {
> > > > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > > > u8 vid;
> > > > >
> > > > > if (caam_get_era() < 10) { @@ -574,9 +586,8 @@ static u8
> > > > > get_rng_vid(uint8_t sec_idx)
> > > > > * By default, the TRNG runs for 200 clocks per sample;
> > > > > * 1200 clocks per sample generates better entropy.
> > > > > */
> > > > > -static void kick_trng(int ent_delay, uint8_t sec_idx)
> > > > > +static void kick_trng(int ent_delay, ccsr_sec_t *sec)
> > > > > {
> > > > > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
> *)SEC_ADDR(sec_idx);
> > > > > struct rng4tst __iomem *rng =
> > > > > (struct rng4tst __iomem *)&sec->rng;
> > > > > u32 val;
> > > > > @@ -603,10 +614,9 @@ static void kick_trng(int ent_delay,
> > > > > uint8_t
> > sec_idx)
> > > > > sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
> > > > > }
> > > > >
> > > > > -static int rng_init(uint8_t sec_idx)
> > > > > +static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
> > > > > {
> > > > > int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
> > > > > - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
> *)SEC_ADDR(sec_idx);
> > > > > struct rng4tst __iomem *rng =
> > > > > (struct rng4tst __iomem *)&sec->rng;
> > > > > u32 inst_handles;
> > > > > @@ -624,7 +634,7 @@ static int rng_init(uint8_t sec_idx)
> > > > > * the TRNG parameters.
> > > > > */
> > > > > if (!inst_handles) {
> > > > > - kick_trng(ent_delay, sec_idx);
> > > > > + kick_trng(ent_delay, sec);
> > > > > ent_delay += 400;
> > > > > }
> > > > > /*
> > > > > @@ -634,7 +644,7 @@ static int rng_init(uint8_t sec_idx)
> > > > > * interval, leading to a sucessful initialization of
> > > > > * the RNG.
> > > > > */
> > > > > - ret = instantiate_rng(sec_idx, gen_sk);
> > > > > + ret = instantiate_rng(sec_idx, sec, gen_sk);
> > > > > } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
> > > > > if (ret) {
> > > > > printf("SEC%u: Failed to instantiate RNG\n",
> > > > > sec_idx); @@ -646,13 +656,28 @@ static int rng_init(uint8_t
> > > > > sec_idx)
> > > > >
> > > > > return ret;
> > > > > }
> > > > > -#endif
> > > > > +
> > > > > int sec_init_idx(uint8_t sec_idx)
> > > > > {
> > > > > - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> > > > > - uint32_t mcr = sec_in32(&sec->mcfgr);
> > > > > int ret = 0;
> > > > > -
> > > > > + struct caam_regs *caam;
> > > > > +#if CONFIG_IS_ENABLED(DM)
> > > > > + if (!caam_dev) {
> > > > > + printf("caam_jr: caam not found\n");
> > > > > + return -1;
> > > > > + }
> > > > > + caam = dev_get_priv(caam_dev); #else
> > > > > + caam_st.sec = (void *)SEC_ADDR(sec_idx);
> > > > > + caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> > > > > + caam_st.jrid = 0;
> > > > > + caam = &caam_st;
> > > > > +#endif
> > > > > + ccsr_sec_t *sec = caam->sec;
> > > > > + uint32_t mcr = sec_in32(&sec->mcfgr); #if
> > > > > +defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> > > > > + uint32_t jrdid_ms = 0;
> > > > > +#endif
> > > > > #ifdef CONFIG_FSL_CORENET
> > > > > uint32_t liodnr;
> > > > > uint32_t liodn_ns;
> > > > > @@ -682,6 +707,11 @@ int sec_init_idx(uint8_t sec_idx)
> > > > > mcr |= (1 << MCFGR_PS_SHIFT);
> > > > > #endif
> > > > > sec_out32(&sec->mcfgr, mcr);
> > > > > +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> > > > > + jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ |
> > > > JRDID_MS_PRIM_DID;
> > > > > + sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms); #endif
> > > > > + jr_reset();
> > > > >
> > > > > #ifdef CONFIG_FSL_CORENET
> > > > > #ifdef CONFIG_SPL_BUILD
> > > > > @@ -693,20 +723,19 @@ int sec_init_idx(uint8_t sec_idx)
> > > > > liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
> > > > > liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
> > > > >
> > > > > - liodnr = sec_in32(&sec->jrliodnr[0].ls) &
> > > > > + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
> > > > > ~(JRNSLIODN_MASK | JRSLIODN_MASK);
> > > > > liodnr = liodnr |
> > > > > (liodn_ns << JRNSLIODN_SHIFT) |
> > > > > (liodn_s << JRSLIODN_SHIFT);
> > > > > - sec_out32(&sec->jrliodnr[0].ls, liodnr);
> > > > > + sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
> > > > > #else
> > > > > - liodnr = sec_in32(&sec->jrliodnr[0].ls);
> > > > > + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
> > > > > liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
> > > > > liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
> > > > > #endif
> > > > > #endif
> > > > > -
> > > > > - ret = jr_init(sec_idx);
> > > > > + ret = jr_init(sec_idx, caam);
> > > > > if (ret < 0) {
> > > > > printf("SEC%u: initialization failed\n", sec_idx);
> > > > > return -1;
> > > > > @@ -719,9 +748,9 @@ int sec_init_idx(uint8_t sec_idx)
> > > > >
> > > > > pamu_enable();
> > > > > #endif
> > > > > -#ifndef CONFIG_SPL_BUILD
> > > > > - if (get_rng_vid(sec_idx) >= 4) {
> > > > > - if (rng_init(sec_idx) < 0) {
> > > > > +
> > > > > + if (get_rng_vid(caam->sec) >= 4) {
> > > > > + if (rng_init(sec_idx, caam->sec) < 0) {
> > > > > printf("SEC%u: RNG instantiation failed\n", sec_idx);
> > > > > return -1;
> > > > > }
> > > > > @@ -735,7 +764,6 @@ int sec_init_idx(uint8_t sec_idx)
> > > > >
> > > > > printf("SEC%u: RNG instantiated\n", sec_idx);
> > > > > }
> > > > > -#endif
> > > > > return ret;
> > > > > }
> > > > >
> > > > > @@ -743,3 +771,76 @@ int sec_init(void)
> > > > > {
> > > > > return sec_init_idx(0);
> > > > > }
> > > > > +
> > > > > +#if CONFIG_IS_ENABLED(DM)
> > > > > +static int caam_jr_ioctl(struct udevice *dev, unsigned long
> > > > > +request, void *buf) {
> > > > > + if (request != CAAM_JR_RUN_DESC)
> > > > > + return -ENOSYS;
> > > > > +
> > > > > + return run_descriptor_jr(buf); }
> > > > > +
> > > > > +static int caam_jr_probe(struct udevice *dev) {
> > > > > + struct caam_regs *caam = dev_get_priv(dev);
> > > > > + fdt_addr_t addr;
> > > > > + ofnode node;
> > > > > + unsigned int jr_node = 0;
> > > > > +
> > > > > + caam_dev = dev;
> > > > > +
> > > > > + addr = dev_read_addr(dev);
> > > > > + if (addr == FDT_ADDR_T_NONE) {
> > > > > + printf("caam_jr: crypto not found\n");
> > > > > + return -EINVAL;
> > > > > + }
> > > > > + caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
> > > > > + caam->regs = (struct jr_regs *)caam->sec;
> > > > > +
> > > > > + /* Check for enabled job ring node */
> > > > > + ofnode_for_each_subnode(node, dev_ofnode(dev)) {
> > > > > + if (!ofnode_is_available(node))
> > > > > + continue;
> > > > > +
> > > > > + jr_node = ofnode_read_u32_default(node, "reg", -1);
> > > > > + if (jr_node > 0) {
> > > > > + caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
> > > > > + while (!(jr_node & 0x0F))
> > > > > + jr_node = jr_node >> 4;
> > > > > +
> > > > > + caam->jrid = jr_node - 1;
> > > > > + break;
> > > > > + }
> > > > > + }
> > > > > +
> > > > > + if (sec_init())
> > > > > + printf("\nsec_init failed!\n");
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +static int caam_jr_bind(struct udevice *dev) {
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +static const struct misc_ops caam_jr_ops = {
> > > > > + .ioctl = caam_jr_ioctl,
> > > > > +};
> > > > > +
> > > > > +static const struct udevice_id caam_jr_match[] = {
> > > > > + { .compatible = "fsl,sec-v4.0" },
> > > > > + { }
> > > > > +};
> > > > > +
> > > > > +U_BOOT_DRIVER(caam_jr) = {
> > > > > + .name = "caam_jr",
> > > > > + .id = UCLASS_MISC,
> > > > > + .of_match = caam_jr_match,
> > > > > + .ops = &caam_jr_ops,
> > > > > + .bind = caam_jr_bind,
> > > > > + .probe = caam_jr_probe,
> > > > > + .priv_auto = sizeof(struct caam_regs),
> > > > > +};
> > > > > +#endif
> > > > > diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
> > > > > index 1047aa772c..3eb7be79da 100644
> > > > > --- a/drivers/crypto/fsl/jr.h
> > > > > +++ b/drivers/crypto/fsl/jr.h
> > > > > @@ -1,6 +1,7 @@
> > > > > /* SPDX-License-Identifier: GPL-2.0+ */
> > > > > /*
> > > > > * Copyright 2008-2014 Freescale Semiconductor, Inc.
> > > > > + * Copyright 2021 NXP
> > > > > *
> > > > > */
> > > > >
> > > > > @@ -8,7 +9,9 @@
> > > > > #define __JR_H
> > > > >
> > > > > #include <linux/compiler.h>
> > > > > +#include "fsl_sec.h"
> > > > > #include "type.h"
> > > > > +#include <misc.h>
> > > > >
> > > > > #define JR_SIZE 4
> > > > > /* Timeout currently defined as 10 sec */ @@ -35,12 +38,21 @@
> > > > > #define JRSLIODN_SHIFT 0
> > > > > #define JRSLIODN_MASK 0x00000fff
> > > > >
> > > > > -#define JQ_DEQ_ERR -1
> > > > > -#define JQ_DEQ_TO_ERR -2
> > > > > -#define JQ_ENQ_ERR -3
> > > > > +#define JRDID_MS_PRIM_DID BIT(0)
> > > > > +#define JRDID_MS_PRIM_TZ BIT(4)
> > > > > +#define JRDID_MS_TZ_OWN BIT(15)
> > > > > +
> > > > > +#define JQ_DEQ_ERR (-1)
> > > > > +#define JQ_DEQ_TO_ERR (-2)
> > > > > +#define JQ_ENQ_ERR (-3)
> > > > >
> > > > > #define RNG4_MAX_HANDLES 2
> > > > >
> > > > > +enum {
> > > > > + /* Run caam jobring descriptor(in buf) */
> > > > > + CAAM_JR_RUN_DESC,
> > > > > +};
> > > > > +
> > > > > struct op_ring {
> > > > > caam_dma_addr_t desc;
> > > > > uint32_t status;
> > > > > @@ -102,6 +114,19 @@ struct result {
> > > > > uint32_t status;
> > > > > };
> > > > >
> > > > > +/*
> > > > > + * struct caam_regs - CAAM initialization register interface
> > > > > + *
> > > > > + * Interface to caam memory map, jobring register, jobring storage.
> > > > > + */
> > > > > +struct caam_regs {
> > > > > + ccsr_sec_t *sec; /*caam initialization registers*/
> > > > > + struct jr_regs *regs; /*jobring configuration registers*/
> > > > > + u8 jrid; /*id to identify a jobring*/
> > > > > + /*Private sub-storage for a single JobR*/
> > > > > + struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> > > > > +};
> > > > > +
> > > > > void caam_jr_strstatus(u32 status);
> > > > > int run_descriptor_jr(uint32_t *desc);
> > > > >
> > > >
> > > > --
> > > >
> > >
> >
> =================================================================
> > > > ====
> > > > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> > > > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > > Germany
> > > > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email:
> > > > sbabic@denx.de
> > > >
> > >
> >
> =================================================================
> > > > ====
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-03 12:44 ` Gaurav Jain
@ 2022-03-03 13:02 ` Stefano Babic
2022-03-03 13:41 ` Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: Stefano Babic @ 2022-03-03 13:02 UTC (permalink / raw)
To: Gaurav Jain, Stefano Babic, u-boot, Marek Vasut
Cc: Fabio Estevam, Peng Fan, Simon Glass, Priyanka Jain, Ye Li,
Horia Geanta, Ji Luo, Franck Lenormand, Silvano Di Ninno,
Sahil Malhotra, Pankaj Gupta, Varun Sethi, dl-uboot-imx,
Shengzhou Liu, Mingkai Hu, Rajesh Bhagat, Meenakshi Aggarwal,
Wasim Khan, Alison Wang, Pramod Kumar, Andy Tang, Adrian Alonso,
Vladimir Oltean
On 03.03.22 13:44, Gaurav Jain wrote:
> Hello Stefano
>
> A gentle reminder!!
> Need your help to check the proposed solution to fix imx6dl_mamoj SPL size issue shared in last mail.
Ouch...is there a solution ? I confess I have not seen, is there an
answer by Marek ?
Regards,
Stefano
>
> Regards
> Gaurav Jain
>
>> -----Original Message-----
>> From: Gaurav Jain
>> Sent: Friday, February 25, 2022 12:33 PM
>> To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek Vasut
>> <marex@denx.de>
>> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
>> Simon Glass <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye
>> Li <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
>> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
>> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
>> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
>> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
>> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
>> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
>> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
>> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
>> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
>> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
>> ring driver model
>>
>> Hello Stefano
>>
>>> -----Original Message-----
>>> From: Gaurav Jain
>>> Sent: Friday, February 11, 2022 3:09 PM
>>> To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek Vasut
>>> <marex@denx.de>
>>> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
>>> Simon Glass <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>;
>>> Ye Li <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
>>> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano
>>> Di Ninno <silvano.dininno@nxp.com>; Sahil Malhotra
>>> <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun
>>> Sethi <V.Sethi@nxp.com>; dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou
>>> Liu <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
>>> Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
>>> <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
>> Alison
>>> Wang <alison.wang@nxp.com>; Pramod Kumar
>> <pramod.kumar_1@nxp.com>;
>>> Andy Tang <andy.tang@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
>>> Vladimir Oltean <olteanv@gmail.com>
>>> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
>>> CAAM Job ring driver model
>>>
>>> Hello Marek
>>>
>>> A gentle reminder!!
>>> Please help to check if some feature can be dropped in SPL from
>>> imx6dl_mamoj board so that CAAM driver model patches can be accepted.
>>>
>>> Regards
>>> Gaurav Jain
>>>
>>>> -----Original Message-----
>>>> From: Gaurav Jain
>>>> Sent: Monday, February 7, 2022 12:43 PM
>>>> To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek
>>>> Vasut <marex@denx.de>
>>>> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
>>>> Simon Glass <sjg@chromium.org>; Priyanka Jain
>>>> <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
>>>> <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
>>>> <franck.lenormand@nxp.com>; Silvano Di Ninno
>>>> <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
>>>> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
>>>> dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
>>>> <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
>>>> Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
>>>> <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
>>> Alison
>>>> Wang <alison.wang@nxp.com>; Pramod Kumar
>>> <pramod.kumar_1@nxp.com>;
>>>> Andy Tang <andy.tang@nxp.com>; Adrian Alonso
>>>> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
>>>> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
>>>> CAAM Job ring driver model
>>>>
>>>> Hello Marek
>>>>
>>>>> -----Original Message-----
>>>>> From: Stefano Babic <sbabic@denx.de>
>>>>> Sent: Saturday, February 5, 2022 7:46 PM
>>>>> To: Gaurav Jain <gaurav.jain@nxp.com>; u-boot@lists.denx.de
>>>>> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
>>>>> <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
>>>>> <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
>>>>> <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
>>>>> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>;
>>>>> Silvano Di Ninno <silvano.dininno@nxp.com>; Sahil Malhotra
>>>>> <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>;
>>>>> Varun Sethi <V.Sethi@nxp.com>; dl-uboot-imx <uboot-imx@nxp.com>;
>>>>> Shengzhou Liu <shengzhou.liu@nxp.com>; Mingkai Hu
>>>>> <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
>>>>> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
>>>>> <wasim.khan@nxp.com>;
>>>> Alison
>>>>> Wang <alison.wang@nxp.com>; Pramod Kumar
>>>> <pramod.kumar_1@nxp.com>;
>>>>> Andy Tang <andy.tang@nxp.com>; Adrian Alonso
>>>>> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>;
>>>>> Marek Vasut <marex@denx.de>
>>>>> Subject: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
>>>>> CAAM Job ring driver model
>>>>>
>>>>> Caution: EXT Email
>>>>>
>>>>> Hi Gaurav,
>>>>>
>>>>> rather I still have issues to run CI with this applied. The reason
>>>>> is that this adds an overhead to SPL and it breaks the board
>>>>> imx6dl_mamoj because SPL exceeds the maximum size for a DL SOC.
>>>>>
>>>>> See
>>>>> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
>>>>> so
>>>>> ur
>>>>> ce.d
>>>>> enx.de%2Fu-boot%2Fcustodians%2Fu-boot-imx%2F-
>>>>> %2Fjobs%2F387370&data=04%7C01%7Cgaurav.jain%40nxp.com%7C
>> 3a
>>> 2
>>>> 73
>>>>>
>>>>
>>>
>> 1dd27fc4bebcad308d9e8b21464%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C
>>>>>
>>>>
>>>
>> 0%7C0%7C637796673834942697%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
>>>>>
>>>>
>>>
>> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&am
>>>>>
>>>>
>>>
>> p;sdata=pI%2F%2FlNtrdrGCa8sSvcr6uNu4jze7pzDqZtI52FIDj50%3D&reserve
>>>>> d=0
>>>>>
>>>>> I do not know if it is possible to drop some features from SPL for
>>>>> this board (Added Marek as board maintainer).
>>
>> As we have not received any response from imx6dl_mamoj board maintainer.
>> I propose the below solution
>>
>> --- a/arch/arm/mach-imx/Kconfig
>> +++ b/arch/arm/mach-imx/Kconfig
>> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
>> - select FSL_CAAM if HAS_CAAM
>> - imply CMD_DEKBLOB if HAS_CAAM
>> + imply FSL_CAAM if HAS_CAAM
>> + imply CMD_DEKBLOB if FSL_CAAM
>> Help
>>
>> --- a/configs/imx6dl_mamoj_defconfig
>> +++ b/configs/imx6dl_mamoj_defconfig
>> @@ -59,3 +59,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
>> +CONFIG_FSL_CAAM=n
>>
>> Need your help to review this or suggest any other solution.
>>
>> Regards
>> Gaurav Jain
>>
>>>>
>>>> CONFIG_IMX_HAB is enabled for imx6dl_mamoj. So CAAM is built for
>>>> SPL, results in increased size.
>>>> However CAAM is not initialized in SPL. As Stefano suggested, Can
>>>> you drop some features from SPL?
>>>>
>>>> Regards
>>>> Gaurav Jain
>>>>>
>>>>> Best regards,
>>>>> Stefano
>>>>>
>>>>> On 10.01.22 13:27, Gaurav Jain wrote:
>>>>>> added device tree support for job ring driver.
>>>>>> sec is initialized based on job ring information processed from
>>>>>> device tree.
>>>>>>
>>>>>> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
>>>>>> Reviewed-by: Ye Li <ye.li@nxp.com>
>>>>>> ---
>>>>>> drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++++--------------
>>>>>> drivers/crypto/fsl/jr.h | 31 +++-
>>>>>> 2 files changed, 240 insertions(+), 114 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
>>>>>> index
>>>>>> 22b649219e..8103987425 100644
>>>>>> --- a/drivers/crypto/fsl/jr.c
>>>>>> +++ b/drivers/crypto/fsl/jr.c
>>>>>> @@ -1,7 +1,7 @@
>>>>>> // SPDX-License-Identifier: GPL-2.0+
>>>>>> /*
>>>>>> * Copyright 2008-2014 Freescale Semiconductor, Inc.
>>>>>> - * Copyright 2018 NXP
>>>>>> + * Copyright 2018, 2021 NXP
>>>>>> *
>>>>>> * Based on CAAM driver in drivers/crypto/caam in Linux
>>>>>> */
>>>>>> @@ -11,7 +11,6 @@
>>>>>> #include <linux/kernel.h>
>>>>>> #include <log.h>
>>>>>> #include <malloc.h>
>>>>>> -#include "fsl_sec.h"
>>>>>> #include "jr.h"
>>>>>> #include "jobdesc.h"
>>>>>> #include "desc_constr.h"
>>>>>> @@ -21,7 +20,10 @@
>>>>>> #include <asm/cache.h>
>>>>>> #include <asm/fsl_pamu.h>
>>>>>> #endif
>>>>>> +#include <dm.h>
>>>>>> #include <dm/lists.h>
>>>>>> +#include <dm/root.h>
>>>>>> +#include <dm/device-internal.h>
>>>>>> #include <linux/delay.h>
>>>>>>
>>>>>> #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size
>>>>>> -
>>>>>> 1)) @@ -35,20 +37,29 @@ uint32_t
>>>>> sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
>>>>>> #endif
>>>>>> };
>>>>>>
>>>>>> +#if CONFIG_IS_ENABLED(DM)
>>>>>> +struct udevice *caam_dev;
>>>>>> +#else
>>>>>> #define SEC_ADDR(idx) \
>>>>>> (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
>>>>>>
>>>>>> #define SEC_JR0_ADDR(idx) \
>>>>>> (ulong)(SEC_ADDR(idx) + \
>>>>>> (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
>>>>>> +struct caam_regs caam_st;
>>>>>> +#endif
>>>>>>
>>>>>> -struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
>>>>>> +static inline u32 jr_start_reg(u8 jrid) {
>>>>>> + return (1 << jrid);
>>>>>> +}
>>>>>>
>>>>>> -static inline void start_jr0(uint8_t sec_idx)
>>>>>> +static inline void start_jr(struct caam_regs *caam)
>>>>>> {
>>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
>>>>>> + ccsr_sec_t *sec = caam->sec;
>>>>>> u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
>>>>>> u32 scfgr = sec_in32(&sec->scfgr);
>>>>>> + u32 jrstart = jr_start_reg(caam->jrid);
>>>>>>
>>>>>> if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
>>>>>> /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or @@ -56,23
>>>>>> +67,16 @@ static inline void start_jr0(uint8_t sec_idx)
>>>>>> */
>>>>>> if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
>>>>>> (scfgr & SEC_SCFGR_VIRT_EN))
>>>>>> - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
>>>>>> + sec_out32(&sec->jrstartr, jrstart);
>>>>>> } else {
>>>>>> /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
>>>>>> if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
>>>>>> - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
>>>>>> + sec_out32(&sec->jrstartr, jrstart);
>>>>>> }
>>>>>> }
>>>>>>
>>>>>> -static inline void jr_reset_liodn(uint8_t sec_idx)
>>>>>> +static inline void jr_disable_irq(struct jr_regs *regs)
>>>>>> {
>>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
>>>>>> - sec_out32(&sec->jrliodnr[0].ls, 0);
>>>>>> -}
>>>>>> -
>>>>>> -static inline void jr_disable_irq(uint8_t sec_idx) -{
>>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
>>>>>> uint32_t jrcfg = sec_in32(®s->jrcfg1);
>>>>>>
>>>>>> jrcfg = jrcfg | JR_INTMASK; @@ -80,10 +84,10 @@ static
>>>>>> inline void jr_disable_irq(uint8_t sec_idx)
>>>>>> sec_out32(®s->jrcfg1, jrcfg);
>>>>>> }
>>>>>>
>>>>>> -static void jr_initregs(uint8_t sec_idx)
>>>>>> +static void jr_initregs(uint8_t sec_idx, struct caam_regs
>>>>>> +*caam)
>>>>>> {
>>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
>>>>>> - struct jobring *jr = &jr0[sec_idx];
>>>>>> + struct jr_regs *regs = caam->regs;
>>>>>> + struct jobring *jr = &caam->jr[sec_idx];
>>>>>> caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
>>>>>> caam_dma_addr_t op_base = virt_to_phys((void
>>>>>> *)jr->output_ring);
>>>>>>
>>>>>> @@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx)
>>>>>> sec_out32(®s->irs, JR_SIZE);
>>>>>>
>>>>>> if (!jr->irq)
>>>>>> - jr_disable_irq(sec_idx);
>>>>>> + jr_disable_irq(regs);
>>>>>> }
>>>>>>
>>>>>> -static int jr_init(uint8_t sec_idx)
>>>>>> +static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
>>>>>> {
>>>>>> - struct jobring *jr = &jr0[sec_idx];
>>>>>> + struct jobring *jr = &caam->jr[sec_idx];
>>>>>>
>>>>>> memset(jr, 0, sizeof(struct jobring));
>>>>>>
>>>>>> - jr->jq_id = DEFAULT_JR_ID;
>>>>>> + jr->jq_id = caam->jrid;
>>>>>> jr->irq = DEFAULT_IRQ;
>>>>>>
>>>>>> #ifdef CONFIG_FSL_CORENET
>>>>>> @@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx)
>>>>>> memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
>>>>>> memset(jr->output_ring, 0, jr->op_size);
>>>>>>
>>>>>> - start_jr0(sec_idx);
>>>>>> -
>>>>>> - jr_initregs(sec_idx);
>>>>>> -
>>>>>> - return 0;
>>>>>> -}
>>>>>> -
>>>>>> -static int jr_sw_cleanup(uint8_t sec_idx) -{
>>>>>> - struct jobring *jr = &jr0[sec_idx];
>>>>>> -
>>>>>> - jr->head = 0;
>>>>>> - jr->tail = 0;
>>>>>> - jr->read_idx = 0;
>>>>>> - jr->write_idx = 0;
>>>>>> - memset(jr->info, 0, sizeof(jr->info));
>>>>>> - memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
>>>>>> - memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
>>>>>> -
>>>>>> - return 0;
>>>>>> -}
>>>>>> -
>>>>>> -static int jr_hw_reset(uint8_t sec_idx) -{
>>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
>>>>>> - uint32_t timeout = 100000;
>>>>>> - uint32_t jrint, jrcr;
>>>>>> -
>>>>>> - sec_out32(®s->jrcr, JRCR_RESET);
>>>>>> - do {
>>>>>> - jrint = sec_in32(®s->jrint);
>>>>>> - } while (((jrint & JRINT_ERR_HALT_MASK) ==
>>>>>> - JRINT_ERR_HALT_INPROGRESS) && --timeout);
>>>>>> -
>>>>>> - jrint = sec_in32(®s->jrint);
>>>>>> - if (((jrint & JRINT_ERR_HALT_MASK) !=
>>>>>> - JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
>>>>>> - return -1;
>>>>>> -
>>>>>> - timeout = 100000;
>>>>>> - sec_out32(®s->jrcr, JRCR_RESET);
>>>>>> - do {
>>>>>> - jrcr = sec_in32(®s->jrcr);
>>>>>> - } while ((jrcr & JRCR_RESET) && --timeout);
>>>>>> -
>>>>>> - if (timeout == 0)
>>>>>> - return -1;
>>>>>> + start_jr(caam);
>>>>>> + jr_initregs(sec_idx, caam);
>>>>>>
>>>>>> return 0;
>>>>>> }
>>>>>> @@ -188,10 +147,10 @@ static int jr_hw_reset(uint8_t sec_idx)
>>>>>> /* -1 --- error, can't enqueue -- no space available */
>>>>>> static int jr_enqueue(uint32_t *desc_addr,
>>>>>> void (*callback)(uint32_t status, void *arg),
>>>>>> - void *arg, uint8_t sec_idx)
>>>>>> + void *arg, uint8_t sec_idx, struct caam_regs *caam)
>>>>>> {
>>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
>>>>>> - struct jobring *jr = &jr0[sec_idx];
>>>>>> + struct jr_regs *regs = caam->regs;
>>>>>> + struct jobring *jr = &caam->jr[sec_idx];
>>>>>> int head = jr->head;
>>>>>> uint32_t desc_word;
>>>>>> int length = desc_len(desc_addr); @@ -263,10 +222,10 @@
>>>>>> static int jr_enqueue(uint32_t *desc_addr,
>>>>>> return 0;
>>>>>> }
>>>>>>
>>>>>> -static int jr_dequeue(int sec_idx)
>>>>>> +static int jr_dequeue(int sec_idx, struct caam_regs *caam)
>>>>>> {
>>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
>>>>>> - struct jobring *jr = &jr0[sec_idx];
>>>>>> + struct jr_regs *regs = caam->regs;
>>>>>> + struct jobring *jr = &caam->jr[sec_idx];
>>>>>> int head = jr->head;
>>>>>> int tail = jr->tail;
>>>>>> int idx, i, found;
>>>>>> @@ -349,14 +308,18 @@ static void desc_done(uint32_t status, void
>> *arg)
>>>>>> {
>>>>>> struct result *x = arg;
>>>>>> x->status = status;
>>>>>> -#ifndef CONFIG_SPL_BUILD
>>>>>> caam_jr_strstatus(status); -#endif
>>>>>> x->done = 1;
>>>>>> }
>>>>>>
>>>>>> static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
>>>>>> {
>>>>>> + struct caam_regs *caam;
>>>>>> +#if CONFIG_IS_ENABLED(DM)
>>>>>> + caam = dev_get_priv(caam_dev); #else
>>>>>> + caam = &caam_st;
>>>>>> +#endif
>>>>>> unsigned long long timeval = 0;
>>>>>> unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
>>>>>> struct result op;
>>>>>> @@ -364,7 +327,7 @@ static inline int
>>>>>> run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
>>>>>>
>>>>>> memset(&op, 0, sizeof(op));
>>>>>>
>>>>>> - ret = jr_enqueue(desc, desc_done, &op, sec_idx);
>>>>>> + ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
>>>>>> if (ret) {
>>>>>> debug("Error in SEC enq\n");
>>>>>> ret = JQ_ENQ_ERR;
>>>>>> @@ -375,7 +338,7 @@ static inline int
>>>>>> run_descriptor_jr_idx(uint32_t *desc,
>>>>> uint8_t sec_idx)
>>>>>> udelay(1);
>>>>>> timeval += 1;
>>>>>>
>>>>>> - ret = jr_dequeue(sec_idx);
>>>>>> + ret = jr_dequeue(sec_idx, caam);
>>>>>> if (ret) {
>>>>>> debug("Error in SEC deq\n");
>>>>>> ret = JQ_DEQ_ERR; @@ -402,13 +365,62 @@
>>>>>> int run_descriptor_jr(uint32_t *desc)
>>>>>> return run_descriptor_jr_idx(desc, 0);
>>>>>> }
>>>>>>
>>>>>> +static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam) {
>>>>>> + struct jobring *jr = &caam->jr[sec_idx];
>>>>>> +
>>>>>> + jr->head = 0;
>>>>>> + jr->tail = 0;
>>>>>> + jr->read_idx = 0;
>>>>>> + jr->write_idx = 0;
>>>>>> + memset(jr->info, 0, sizeof(jr->info));
>>>>>> + memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
>>>>>> + memset(jr->output_ring, 0, jr->size * sizeof(struct
>>>>>> + op_ring));
>>>>>> +
>>>>>> + return 0;
>>>>>> +}
>>>>>> +
>>>>>> +static int jr_hw_reset(struct jr_regs *regs) {
>>>>>> + uint32_t timeout = 100000;
>>>>>> + uint32_t jrint, jrcr;
>>>>>> +
>>>>>> + sec_out32(®s->jrcr, JRCR_RESET);
>>>>>> + do {
>>>>>> + jrint = sec_in32(®s->jrint);
>>>>>> + } while (((jrint & JRINT_ERR_HALT_MASK) ==
>>>>>> + JRINT_ERR_HALT_INPROGRESS) && --timeout);
>>>>>> +
>>>>>> + jrint = sec_in32(®s->jrint);
>>>>>> + if (((jrint & JRINT_ERR_HALT_MASK) !=
>>>>>> + JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
>>>>>> + return -1;
>>>>>> +
>>>>>> + timeout = 100000;
>>>>>> + sec_out32(®s->jrcr, JRCR_RESET);
>>>>>> + do {
>>>>>> + jrcr = sec_in32(®s->jrcr);
>>>>>> + } while ((jrcr & JRCR_RESET) && --timeout);
>>>>>> +
>>>>>> + if (timeout == 0)
>>>>>> + return -1;
>>>>>> +
>>>>>> + return 0;
>>>>>> +}
>>>>>> +
>>>>>> static inline int jr_reset_sec(uint8_t sec_idx)
>>>>>> {
>>>>>> - if (jr_hw_reset(sec_idx) < 0)
>>>>>> + struct caam_regs *caam;
>>>>>> +#if CONFIG_IS_ENABLED(DM)
>>>>>> + caam = dev_get_priv(caam_dev); #else
>>>>>> + caam = &caam_st;
>>>>>> +#endif
>>>>>> + if (jr_hw_reset(caam->regs) < 0)
>>>>>> return -1;
>>>>>>
>>>>>> /* Clean up the jobring structure maintained by software */
>>>>>> - jr_sw_cleanup(sec_idx);
>>>>>> + jr_sw_cleanup(sec_idx, caam);
>>>>>>
>>>>>> return 0;
>>>>>> }
>>>>>> @@ -418,9 +430,15 @@ int jr_reset(void)
>>>>>> return jr_reset_sec(0);
>>>>>> }
>>>>>>
>>>>>> -static inline int sec_reset_idx(uint8_t sec_idx)
>>>>>> +int sec_reset(void)
>>>>>> {
>>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
>>>>>> + struct caam_regs *caam;
>>>>>> +#if CONFIG_IS_ENABLED(DM)
>>>>>> + caam = dev_get_priv(caam_dev); #else
>>>>>> + caam = &caam_st;
>>>>>> +#endif
>>>>>> + ccsr_sec_t *sec = caam->sec;
>>>>>> uint32_t mcfgr = sec_in32(&sec->mcfgr);
>>>>>> uint32_t timeout = 100000;
>>>>>>
>>>>>> @@ -446,11 +464,7 @@ static inline int sec_reset_idx(uint8_t
>>>>>> sec_idx)
>>>>>>
>>>>>> return 0;
>>>>>> }
>>>>>> -int sec_reset(void)
>>>>>> -{
>>>>>> - return sec_reset_idx(0);
>>>>>> -}
>>>>>> -#ifndef CONFIG_SPL_BUILD
>>>>>> +
>>>>>> static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
>>>>>> {
>>>>>> u32 *desc;
>>>>>> @@ -496,12 +510,11 @@ static int deinstantiate_rng(u8 sec_idx,
>>>>>> int
>>>>> state_handle_mask)
>>>>>> return ret;
>>>>>> }
>>>>>>
>>>>>> -static int instantiate_rng(u8 sec_idx, int gen_sk)
>>>>>> +static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec,
>>>>>> +int
>>>>>> +gen_sk)
>>>>>> {
>>>>>> u32 *desc;
>>>>>> u32 rdsta_val;
>>>>>> int ret = 0, sh_idx, size;
>>>>>> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
>> *)SEC_ADDR(sec_idx);
>>>>>> struct rng4tst __iomem *rng =
>>>>>> (struct rng4tst __iomem *)&sec->rng;
>>>>>>
>>>>>> @@ -554,9 +567,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk)
>>>>>> return ret;
>>>>>> }
>>>>>>
>>>>>> -static u8 get_rng_vid(uint8_t sec_idx)
>>>>>> +static u8 get_rng_vid(ccsr_sec_t *sec)
>>>>>> {
>>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
>>>>>> u8 vid;
>>>>>>
>>>>>> if (caam_get_era() < 10) { @@ -574,9 +586,8 @@ static u8
>>>>>> get_rng_vid(uint8_t sec_idx)
>>>>>> * By default, the TRNG runs for 200 clocks per sample;
>>>>>> * 1200 clocks per sample generates better entropy.
>>>>>> */
>>>>>> -static void kick_trng(int ent_delay, uint8_t sec_idx)
>>>>>> +static void kick_trng(int ent_delay, ccsr_sec_t *sec)
>>>>>> {
>>>>>> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
>> *)SEC_ADDR(sec_idx);
>>>>>> struct rng4tst __iomem *rng =
>>>>>> (struct rng4tst __iomem *)&sec->rng;
>>>>>> u32 val;
>>>>>> @@ -603,10 +614,9 @@ static void kick_trng(int ent_delay,
>>>>>> uint8_t
>>> sec_idx)
>>>>>> sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
>>>>>> }
>>>>>>
>>>>>> -static int rng_init(uint8_t sec_idx)
>>>>>> +static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
>>>>>> {
>>>>>> int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
>>>>>> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
>> *)SEC_ADDR(sec_idx);
>>>>>> struct rng4tst __iomem *rng =
>>>>>> (struct rng4tst __iomem *)&sec->rng;
>>>>>> u32 inst_handles;
>>>>>> @@ -624,7 +634,7 @@ static int rng_init(uint8_t sec_idx)
>>>>>> * the TRNG parameters.
>>>>>> */
>>>>>> if (!inst_handles) {
>>>>>> - kick_trng(ent_delay, sec_idx);
>>>>>> + kick_trng(ent_delay, sec);
>>>>>> ent_delay += 400;
>>>>>> }
>>>>>> /*
>>>>>> @@ -634,7 +644,7 @@ static int rng_init(uint8_t sec_idx)
>>>>>> * interval, leading to a sucessful initialization of
>>>>>> * the RNG.
>>>>>> */
>>>>>> - ret = instantiate_rng(sec_idx, gen_sk);
>>>>>> + ret = instantiate_rng(sec_idx, sec, gen_sk);
>>>>>> } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
>>>>>> if (ret) {
>>>>>> printf("SEC%u: Failed to instantiate RNG\n",
>>>>>> sec_idx); @@ -646,13 +656,28 @@ static int rng_init(uint8_t
>>>>>> sec_idx)
>>>>>>
>>>>>> return ret;
>>>>>> }
>>>>>> -#endif
>>>>>> +
>>>>>> int sec_init_idx(uint8_t sec_idx)
>>>>>> {
>>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
>>>>>> - uint32_t mcr = sec_in32(&sec->mcfgr);
>>>>>> int ret = 0;
>>>>>> -
>>>>>> + struct caam_regs *caam;
>>>>>> +#if CONFIG_IS_ENABLED(DM)
>>>>>> + if (!caam_dev) {
>>>>>> + printf("caam_jr: caam not found\n");
>>>>>> + return -1;
>>>>>> + }
>>>>>> + caam = dev_get_priv(caam_dev); #else
>>>>>> + caam_st.sec = (void *)SEC_ADDR(sec_idx);
>>>>>> + caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
>>>>>> + caam_st.jrid = 0;
>>>>>> + caam = &caam_st;
>>>>>> +#endif
>>>>>> + ccsr_sec_t *sec = caam->sec;
>>>>>> + uint32_t mcr = sec_in32(&sec->mcfgr); #if
>>>>>> +defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
>>>>>> + uint32_t jrdid_ms = 0;
>>>>>> +#endif
>>>>>> #ifdef CONFIG_FSL_CORENET
>>>>>> uint32_t liodnr;
>>>>>> uint32_t liodn_ns;
>>>>>> @@ -682,6 +707,11 @@ int sec_init_idx(uint8_t sec_idx)
>>>>>> mcr |= (1 << MCFGR_PS_SHIFT);
>>>>>> #endif
>>>>>> sec_out32(&sec->mcfgr, mcr);
>>>>>> +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
>>>>>> + jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ |
>>>>> JRDID_MS_PRIM_DID;
>>>>>> + sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms); #endif
>>>>>> + jr_reset();
>>>>>>
>>>>>> #ifdef CONFIG_FSL_CORENET
>>>>>> #ifdef CONFIG_SPL_BUILD
>>>>>> @@ -693,20 +723,19 @@ int sec_init_idx(uint8_t sec_idx)
>>>>>> liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
>>>>>> liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
>>>>>>
>>>>>> - liodnr = sec_in32(&sec->jrliodnr[0].ls) &
>>>>>> + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
>>>>>> ~(JRNSLIODN_MASK | JRSLIODN_MASK);
>>>>>> liodnr = liodnr |
>>>>>> (liodn_ns << JRNSLIODN_SHIFT) |
>>>>>> (liodn_s << JRSLIODN_SHIFT);
>>>>>> - sec_out32(&sec->jrliodnr[0].ls, liodnr);
>>>>>> + sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
>>>>>> #else
>>>>>> - liodnr = sec_in32(&sec->jrliodnr[0].ls);
>>>>>> + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
>>>>>> liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
>>>>>> liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
>>>>>> #endif
>>>>>> #endif
>>>>>> -
>>>>>> - ret = jr_init(sec_idx);
>>>>>> + ret = jr_init(sec_idx, caam);
>>>>>> if (ret < 0) {
>>>>>> printf("SEC%u: initialization failed\n", sec_idx);
>>>>>> return -1;
>>>>>> @@ -719,9 +748,9 @@ int sec_init_idx(uint8_t sec_idx)
>>>>>>
>>>>>> pamu_enable();
>>>>>> #endif
>>>>>> -#ifndef CONFIG_SPL_BUILD
>>>>>> - if (get_rng_vid(sec_idx) >= 4) {
>>>>>> - if (rng_init(sec_idx) < 0) {
>>>>>> +
>>>>>> + if (get_rng_vid(caam->sec) >= 4) {
>>>>>> + if (rng_init(sec_idx, caam->sec) < 0) {
>>>>>> printf("SEC%u: RNG instantiation failed\n", sec_idx);
>>>>>> return -1;
>>>>>> }
>>>>>> @@ -735,7 +764,6 @@ int sec_init_idx(uint8_t sec_idx)
>>>>>>
>>>>>> printf("SEC%u: RNG instantiated\n", sec_idx);
>>>>>> }
>>>>>> -#endif
>>>>>> return ret;
>>>>>> }
>>>>>>
>>>>>> @@ -743,3 +771,76 @@ int sec_init(void)
>>>>>> {
>>>>>> return sec_init_idx(0);
>>>>>> }
>>>>>> +
>>>>>> +#if CONFIG_IS_ENABLED(DM)
>>>>>> +static int caam_jr_ioctl(struct udevice *dev, unsigned long
>>>>>> +request, void *buf) {
>>>>>> + if (request != CAAM_JR_RUN_DESC)
>>>>>> + return -ENOSYS;
>>>>>> +
>>>>>> + return run_descriptor_jr(buf); }
>>>>>> +
>>>>>> +static int caam_jr_probe(struct udevice *dev) {
>>>>>> + struct caam_regs *caam = dev_get_priv(dev);
>>>>>> + fdt_addr_t addr;
>>>>>> + ofnode node;
>>>>>> + unsigned int jr_node = 0;
>>>>>> +
>>>>>> + caam_dev = dev;
>>>>>> +
>>>>>> + addr = dev_read_addr(dev);
>>>>>> + if (addr == FDT_ADDR_T_NONE) {
>>>>>> + printf("caam_jr: crypto not found\n");
>>>>>> + return -EINVAL;
>>>>>> + }
>>>>>> + caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
>>>>>> + caam->regs = (struct jr_regs *)caam->sec;
>>>>>> +
>>>>>> + /* Check for enabled job ring node */
>>>>>> + ofnode_for_each_subnode(node, dev_ofnode(dev)) {
>>>>>> + if (!ofnode_is_available(node))
>>>>>> + continue;
>>>>>> +
>>>>>> + jr_node = ofnode_read_u32_default(node, "reg", -1);
>>>>>> + if (jr_node > 0) {
>>>>>> + caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
>>>>>> + while (!(jr_node & 0x0F))
>>>>>> + jr_node = jr_node >> 4;
>>>>>> +
>>>>>> + caam->jrid = jr_node - 1;
>>>>>> + break;
>>>>>> + }
>>>>>> + }
>>>>>> +
>>>>>> + if (sec_init())
>>>>>> + printf("\nsec_init failed!\n");
>>>>>> +
>>>>>> + return 0;
>>>>>> +}
>>>>>> +
>>>>>> +static int caam_jr_bind(struct udevice *dev) {
>>>>>> + return 0;
>>>>>> +}
>>>>>> +
>>>>>> +static const struct misc_ops caam_jr_ops = {
>>>>>> + .ioctl = caam_jr_ioctl,
>>>>>> +};
>>>>>> +
>>>>>> +static const struct udevice_id caam_jr_match[] = {
>>>>>> + { .compatible = "fsl,sec-v4.0" },
>>>>>> + { }
>>>>>> +};
>>>>>> +
>>>>>> +U_BOOT_DRIVER(caam_jr) = {
>>>>>> + .name = "caam_jr",
>>>>>> + .id = UCLASS_MISC,
>>>>>> + .of_match = caam_jr_match,
>>>>>> + .ops = &caam_jr_ops,
>>>>>> + .bind = caam_jr_bind,
>>>>>> + .probe = caam_jr_probe,
>>>>>> + .priv_auto = sizeof(struct caam_regs),
>>>>>> +};
>>>>>> +#endif
>>>>>> diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
>>>>>> index 1047aa772c..3eb7be79da 100644
>>>>>> --- a/drivers/crypto/fsl/jr.h
>>>>>> +++ b/drivers/crypto/fsl/jr.h
>>>>>> @@ -1,6 +1,7 @@
>>>>>> /* SPDX-License-Identifier: GPL-2.0+ */
>>>>>> /*
>>>>>> * Copyright 2008-2014 Freescale Semiconductor, Inc.
>>>>>> + * Copyright 2021 NXP
>>>>>> *
>>>>>> */
>>>>>>
>>>>>> @@ -8,7 +9,9 @@
>>>>>> #define __JR_H
>>>>>>
>>>>>> #include <linux/compiler.h>
>>>>>> +#include "fsl_sec.h"
>>>>>> #include "type.h"
>>>>>> +#include <misc.h>
>>>>>>
>>>>>> #define JR_SIZE 4
>>>>>> /* Timeout currently defined as 10 sec */ @@ -35,12 +38,21 @@
>>>>>> #define JRSLIODN_SHIFT 0
>>>>>> #define JRSLIODN_MASK 0x00000fff
>>>>>>
>>>>>> -#define JQ_DEQ_ERR -1
>>>>>> -#define JQ_DEQ_TO_ERR -2
>>>>>> -#define JQ_ENQ_ERR -3
>>>>>> +#define JRDID_MS_PRIM_DID BIT(0)
>>>>>> +#define JRDID_MS_PRIM_TZ BIT(4)
>>>>>> +#define JRDID_MS_TZ_OWN BIT(15)
>>>>>> +
>>>>>> +#define JQ_DEQ_ERR (-1)
>>>>>> +#define JQ_DEQ_TO_ERR (-2)
>>>>>> +#define JQ_ENQ_ERR (-3)
>>>>>>
>>>>>> #define RNG4_MAX_HANDLES 2
>>>>>>
>>>>>> +enum {
>>>>>> + /* Run caam jobring descriptor(in buf) */
>>>>>> + CAAM_JR_RUN_DESC,
>>>>>> +};
>>>>>> +
>>>>>> struct op_ring {
>>>>>> caam_dma_addr_t desc;
>>>>>> uint32_t status;
>>>>>> @@ -102,6 +114,19 @@ struct result {
>>>>>> uint32_t status;
>>>>>> };
>>>>>>
>>>>>> +/*
>>>>>> + * struct caam_regs - CAAM initialization register interface
>>>>>> + *
>>>>>> + * Interface to caam memory map, jobring register, jobring storage.
>>>>>> + */
>>>>>> +struct caam_regs {
>>>>>> + ccsr_sec_t *sec; /*caam initialization registers*/
>>>>>> + struct jr_regs *regs; /*jobring configuration registers*/
>>>>>> + u8 jrid; /*id to identify a jobring*/
>>>>>> + /*Private sub-storage for a single JobR*/
>>>>>> + struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
>>>>>> +};
>>>>>> +
>>>>>> void caam_jr_strstatus(u32 status);
>>>>>> int run_descriptor_jr(uint32_t *desc);
>>>>>>
>>>>>
>>>>> --
>>>>>
>>>>
>>>
>> =================================================================
>>>>> ====
>>>>> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
>>>>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
>>>>> Germany
>>>>> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email:
>>>>> sbabic@denx.de
>>>>>
>>>>
>>>
>> =================================================================
>>>>> ====
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-03 13:02 ` Stefano Babic
@ 2022-03-03 13:41 ` Gaurav Jain
2022-03-03 15:30 ` Stefano Babic
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-03-03 13:41 UTC (permalink / raw)
To: Stefano Babic, u-boot, Marek Vasut
Cc: Fabio Estevam, Peng Fan, Simon Glass, Priyanka Jain, Ye Li,
Horia Geanta, Ji Luo, Franck Lenormand, Silvano Di Ninno,
Sahil Malhotra, Pankaj Gupta, Varun Sethi, dl-uboot-imx,
Shengzhou Liu, Mingkai Hu, Rajesh Bhagat, Meenakshi Aggarwal,
Wasim Khan, Alison Wang, Pramod Kumar, Andy Tang, Adrian Alonso,
Vladimir Oltean
Hi Stefano
As we have not received any response from imx6dl_mamoj board maintainer.
I propose the below solution
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
- select FSL_CAAM if HAS_CAAM
- imply CMD_DEKBLOB if HAS_CAAM
+ imply FSL_CAAM if HAS_CAAM
+ imply CMD_DEKBLOB if FSL_CAAM
Help
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -59,3 +59,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_FSL_CAAM=n
Need your help to review this or suggest any other solution.
Regards
Gaurav Jain
> -----Original Message-----
> From: Stefano Babic <sbabic@denx.de>
> Sent: Thursday, March 3, 2022 6:32 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>; Stefano Babic <sbabic@denx.de>; u-
> boot@lists.denx.de; Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> Simon Glass <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye
> Li <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> Caution: EXT Email
>
> On 03.03.22 13:44, Gaurav Jain wrote:
> > Hello Stefano
> >
> > A gentle reminder!!
> > Need your help to check the proposed solution to fix imx6dl_mamoj SPL size
> issue shared in last mail.
>
> Ouch...is there a solution ? I confess I have not seen, is there an answer by
> Marek ?
>
> Regards,
> Stefano
>
> >
> > Regards
> > Gaurav Jain
> >
> >> -----Original Message-----
> >> From: Gaurav Jain
> >> Sent: Friday, February 25, 2022 12:33 PM
> >> To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek Vasut
> >> <marex@denx.de>
> >> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> >> Simon Glass <sjg@chromium.org>; Priyanka Jain
> >> <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
> >> <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> >> <franck.lenormand@nxp.com>; Silvano Di Ninno
> >> <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> >> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> >> dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
> >> <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> >> Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> >> <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> Alison
> >> Wang <alison.wang@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>;
> >> Andy Tang <andy.tang@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
> >> Vladimir Oltean <olteanv@gmail.com>
> >> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> >> CAAM Job ring driver model
> >>
> >> Hello Stefano
> >>
> >>> -----Original Message-----
> >>> From: Gaurav Jain
> >>> Sent: Friday, February 11, 2022 3:09 PM
> >>> To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek
> >>> Vasut <marex@denx.de>
> >>> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> >>> Simon Glass <sjg@chromium.org>; Priyanka Jain
> >>> <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
> >>> <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> >>> <franck.lenormand@nxp.com>; Silvano Di Ninno
> >>> <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> >>> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> >>> dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
> >>> <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> >>> Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> >>> <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> >> Alison
> >>> Wang <alison.wang@nxp.com>; Pramod Kumar
> >> <pramod.kumar_1@nxp.com>;
> >>> Andy Tang <andy.tang@nxp.com>; Adrian Alonso
> >>> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> >>> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> >>> CAAM Job ring driver model
> >>>
> >>> Hello Marek
> >>>
> >>> A gentle reminder!!
> >>> Please help to check if some feature can be dropped in SPL from
> >>> imx6dl_mamoj board so that CAAM driver model patches can be accepted.
> >>>
> >>> Regards
> >>> Gaurav Jain
> >>>
> >>>> -----Original Message-----
> >>>> From: Gaurav Jain
> >>>> Sent: Monday, February 7, 2022 12:43 PM
> >>>> To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek
> >>>> Vasut <marex@denx.de>
> >>>> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan
> >>>> <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Priyanka Jain
> >>>> <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
> >>>> <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> >>>> <franck.lenormand@nxp.com>; Silvano Di Ninno
> >>>> <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> >>>> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> >>>> dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
> >>>> <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> >>>> Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> >>>> <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> >>> Alison
> >>>> Wang <alison.wang@nxp.com>; Pramod Kumar
> >>> <pramod.kumar_1@nxp.com>;
> >>>> Andy Tang <andy.tang@nxp.com>; Adrian Alonso
> >>>> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> >>>> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> >>>> CAAM Job ring driver model
> >>>>
> >>>> Hello Marek
> >>>>
> >>>>> -----Original Message-----
> >>>>> From: Stefano Babic <sbabic@denx.de>
> >>>>> Sent: Saturday, February 5, 2022 7:46 PM
> >>>>> To: Gaurav Jain <gaurav.jain@nxp.com>; u-boot@lists.denx.de
> >>>>> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
> >>>>> <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> >>>>> <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> >>>>> <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> >>>>> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>;
> >>>>> Silvano Di Ninno <silvano.dininno@nxp.com>; Sahil Malhotra
> >>>>> <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>;
> >>>>> Varun Sethi <V.Sethi@nxp.com>; dl-uboot-imx <uboot-imx@nxp.com>;
> >>>>> Shengzhou Liu <shengzhou.liu@nxp.com>; Mingkai Hu
> >>>>> <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> >>>>> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> >>>>> <wasim.khan@nxp.com>;
> >>>> Alison
> >>>>> Wang <alison.wang@nxp.com>; Pramod Kumar
> >>>> <pramod.kumar_1@nxp.com>;
> >>>>> Andy Tang <andy.tang@nxp.com>; Adrian Alonso
> >>>>> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>;
> >>>>> Marek Vasut <marex@denx.de>
> >>>>> Subject: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> >>>>> CAAM Job ring driver model
> >>>>>
> >>>>> Caution: EXT Email
> >>>>>
> >>>>> Hi Gaurav,
> >>>>>
> >>>>> rather I still have issues to run CI with this applied. The reason
> >>>>> is that this adds an overhead to SPL and it breaks the board
> >>>>> imx6dl_mamoj because SPL exceeds the maximum size for a DL SOC.
> >>>>>
> >>>>> See
> >>>>> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> >>>>> so
> >>>>> ur
> >>>>> ce.d
> >>>>> enx.de%2Fu-boot%2Fcustodians%2Fu-boot-imx%2F-
> >>>>> %2Fjobs%2F387370&data=04%7C01%7Cgaurav.jain%40nxp.com%7
> C
> >> 3a
> >>> 2
> >>>> 73
> >>>>>
> >>>>
> >>>
> >>
> 1dd27fc4bebcad308d9e8b21464%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C
> >>>>>
> >>>>
> >>>
> >>
> 0%7C0%7C637796673834942697%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> >>>>>
> >>>>
> >>>
> >>
> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&am
> >>>>>
> >>>>
> >>>
> >>
> p;sdata=pI%2F%2FlNtrdrGCa8sSvcr6uNu4jze7pzDqZtI52FIDj50%3D&reserv
> >> e
> >>>>> d=0
> >>>>>
> >>>>> I do not know if it is possible to drop some features from SPL for
> >>>>> this board (Added Marek as board maintainer).
> >>
> >> As we have not received any response from imx6dl_mamoj board maintainer.
> >> I propose the below solution
> >>
> >> --- a/arch/arm/mach-imx/Kconfig
> >> +++ b/arch/arm/mach-imx/Kconfig
> >> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
> >> - select FSL_CAAM if HAS_CAAM
> >> - imply CMD_DEKBLOB if HAS_CAAM
> >> + imply FSL_CAAM if HAS_CAAM
> >> + imply CMD_DEKBLOB if FSL_CAAM
> >> Help
> >>
> >> --- a/configs/imx6dl_mamoj_defconfig
> >> +++ b/configs/imx6dl_mamoj_defconfig
> >> @@ -59,3 +59,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> >> +CONFIG_FSL_CAAM=n
> >>
> >> Need your help to review this or suggest any other solution.
> >>
> >> Regards
> >> Gaurav Jain
> >>
> >>>>
> >>>> CONFIG_IMX_HAB is enabled for imx6dl_mamoj. So CAAM is built for
> >>>> SPL, results in increased size.
> >>>> However CAAM is not initialized in SPL. As Stefano suggested, Can
> >>>> you drop some features from SPL?
> >>>>
> >>>> Regards
> >>>> Gaurav Jain
> >>>>>
> >>>>> Best regards,
> >>>>> Stefano
> >>>>>
> >>>>> On 10.01.22 13:27, Gaurav Jain wrote:
> >>>>>> added device tree support for job ring driver.
> >>>>>> sec is initialized based on job ring information processed from
> >>>>>> device tree.
> >>>>>>
> >>>>>> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> >>>>>> Reviewed-by: Ye Li <ye.li@nxp.com>
> >>>>>> ---
> >>>>>> drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++++-------------
> -
> >>>>>> drivers/crypto/fsl/jr.h | 31 +++-
> >>>>>> 2 files changed, 240 insertions(+), 114 deletions(-)
> >>>>>>
> >>>>>> diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
> >>>>>> index
> >>>>>> 22b649219e..8103987425 100644
> >>>>>> --- a/drivers/crypto/fsl/jr.c
> >>>>>> +++ b/drivers/crypto/fsl/jr.c
> >>>>>> @@ -1,7 +1,7 @@
> >>>>>> // SPDX-License-Identifier: GPL-2.0+
> >>>>>> /*
> >>>>>> * Copyright 2008-2014 Freescale Semiconductor, Inc.
> >>>>>> - * Copyright 2018 NXP
> >>>>>> + * Copyright 2018, 2021 NXP
> >>>>>> *
> >>>>>> * Based on CAAM driver in drivers/crypto/caam in Linux
> >>>>>> */
> >>>>>> @@ -11,7 +11,6 @@
> >>>>>> #include <linux/kernel.h>
> >>>>>> #include <log.h>
> >>>>>> #include <malloc.h>
> >>>>>> -#include "fsl_sec.h"
> >>>>>> #include "jr.h"
> >>>>>> #include "jobdesc.h"
> >>>>>> #include "desc_constr.h"
> >>>>>> @@ -21,7 +20,10 @@
> >>>>>> #include <asm/cache.h>
> >>>>>> #include <asm/fsl_pamu.h>
> >>>>>> #endif
> >>>>>> +#include <dm.h>
> >>>>>> #include <dm/lists.h>
> >>>>>> +#include <dm/root.h>
> >>>>>> +#include <dm/device-internal.h>
> >>>>>> #include <linux/delay.h>
> >>>>>>
> >>>>>> #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size
> >>>>>> -
> >>>>>> 1)) @@ -35,20 +37,29 @@ uint32_t
> >>>>> sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
> >>>>>> #endif
> >>>>>> };
> >>>>>>
> >>>>>> +#if CONFIG_IS_ENABLED(DM)
> >>>>>> +struct udevice *caam_dev;
> >>>>>> +#else
> >>>>>> #define SEC_ADDR(idx) \
> >>>>>> (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
> >>>>>>
> >>>>>> #define SEC_JR0_ADDR(idx) \
> >>>>>> (ulong)(SEC_ADDR(idx) + \
> >>>>>> (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
> >>>>>> +struct caam_regs caam_st;
> >>>>>> +#endif
> >>>>>>
> >>>>>> -struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> >>>>>> +static inline u32 jr_start_reg(u8 jrid) {
> >>>>>> + return (1 << jrid);
> >>>>>> +}
> >>>>>>
> >>>>>> -static inline void start_jr0(uint8_t sec_idx)
> >>>>>> +static inline void start_jr(struct caam_regs *caam)
> >>>>>> {
> >>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> >>>>>> + ccsr_sec_t *sec = caam->sec;
> >>>>>> u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
> >>>>>> u32 scfgr = sec_in32(&sec->scfgr);
> >>>>>> + u32 jrstart = jr_start_reg(caam->jrid);
> >>>>>>
> >>>>>> if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
> >>>>>> /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or @@ -56,23
> >>>>>> +67,16 @@ static inline void start_jr0(uint8_t sec_idx)
> >>>>>> */
> >>>>>> if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
> >>>>>> (scfgr & SEC_SCFGR_VIRT_EN))
> >>>>>> - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
> >>>>>> + sec_out32(&sec->jrstartr, jrstart);
> >>>>>> } else {
> >>>>>> /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
> >>>>>> if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
> >>>>>> - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
> >>>>>> + sec_out32(&sec->jrstartr, jrstart);
> >>>>>> }
> >>>>>> }
> >>>>>>
> >>>>>> -static inline void jr_reset_liodn(uint8_t sec_idx)
> >>>>>> +static inline void jr_disable_irq(struct jr_regs *regs)
> >>>>>> {
> >>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> >>>>>> - sec_out32(&sec->jrliodnr[0].ls, 0);
> >>>>>> -}
> >>>>>> -
> >>>>>> -static inline void jr_disable_irq(uint8_t sec_idx) -{
> >>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> >>>>>> uint32_t jrcfg = sec_in32(®s->jrcfg1);
> >>>>>>
> >>>>>> jrcfg = jrcfg | JR_INTMASK; @@ -80,10 +84,10 @@ static
> >>>>>> inline void jr_disable_irq(uint8_t sec_idx)
> >>>>>> sec_out32(®s->jrcfg1, jrcfg);
> >>>>>> }
> >>>>>>
> >>>>>> -static void jr_initregs(uint8_t sec_idx)
> >>>>>> +static void jr_initregs(uint8_t sec_idx, struct caam_regs
> >>>>>> +*caam)
> >>>>>> {
> >>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> >>>>>> - struct jobring *jr = &jr0[sec_idx];
> >>>>>> + struct jr_regs *regs = caam->regs;
> >>>>>> + struct jobring *jr = &caam->jr[sec_idx];
> >>>>>> caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
> >>>>>> caam_dma_addr_t op_base = virt_to_phys((void
> >>>>>> *)jr->output_ring);
> >>>>>>
> >>>>>> @@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx)
> >>>>>> sec_out32(®s->irs, JR_SIZE);
> >>>>>>
> >>>>>> if (!jr->irq)
> >>>>>> - jr_disable_irq(sec_idx);
> >>>>>> + jr_disable_irq(regs);
> >>>>>> }
> >>>>>>
> >>>>>> -static int jr_init(uint8_t sec_idx)
> >>>>>> +static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
> >>>>>> {
> >>>>>> - struct jobring *jr = &jr0[sec_idx];
> >>>>>> + struct jobring *jr = &caam->jr[sec_idx];
> >>>>>>
> >>>>>> memset(jr, 0, sizeof(struct jobring));
> >>>>>>
> >>>>>> - jr->jq_id = DEFAULT_JR_ID;
> >>>>>> + jr->jq_id = caam->jrid;
> >>>>>> jr->irq = DEFAULT_IRQ;
> >>>>>>
> >>>>>> #ifdef CONFIG_FSL_CORENET
> >>>>>> @@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx)
> >>>>>> memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
> >>>>>> memset(jr->output_ring, 0, jr->op_size);
> >>>>>>
> >>>>>> - start_jr0(sec_idx);
> >>>>>> -
> >>>>>> - jr_initregs(sec_idx);
> >>>>>> -
> >>>>>> - return 0;
> >>>>>> -}
> >>>>>> -
> >>>>>> -static int jr_sw_cleanup(uint8_t sec_idx) -{
> >>>>>> - struct jobring *jr = &jr0[sec_idx];
> >>>>>> -
> >>>>>> - jr->head = 0;
> >>>>>> - jr->tail = 0;
> >>>>>> - jr->read_idx = 0;
> >>>>>> - jr->write_idx = 0;
> >>>>>> - memset(jr->info, 0, sizeof(jr->info));
> >>>>>> - memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
> >>>>>> - memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
> >>>>>> -
> >>>>>> - return 0;
> >>>>>> -}
> >>>>>> -
> >>>>>> -static int jr_hw_reset(uint8_t sec_idx) -{
> >>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> >>>>>> - uint32_t timeout = 100000;
> >>>>>> - uint32_t jrint, jrcr;
> >>>>>> -
> >>>>>> - sec_out32(®s->jrcr, JRCR_RESET);
> >>>>>> - do {
> >>>>>> - jrint = sec_in32(®s->jrint);
> >>>>>> - } while (((jrint & JRINT_ERR_HALT_MASK) ==
> >>>>>> - JRINT_ERR_HALT_INPROGRESS) && --timeout);
> >>>>>> -
> >>>>>> - jrint = sec_in32(®s->jrint);
> >>>>>> - if (((jrint & JRINT_ERR_HALT_MASK) !=
> >>>>>> - JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
> >>>>>> - return -1;
> >>>>>> -
> >>>>>> - timeout = 100000;
> >>>>>> - sec_out32(®s->jrcr, JRCR_RESET);
> >>>>>> - do {
> >>>>>> - jrcr = sec_in32(®s->jrcr);
> >>>>>> - } while ((jrcr & JRCR_RESET) && --timeout);
> >>>>>> -
> >>>>>> - if (timeout == 0)
> >>>>>> - return -1;
> >>>>>> + start_jr(caam);
> >>>>>> + jr_initregs(sec_idx, caam);
> >>>>>>
> >>>>>> return 0;
> >>>>>> }
> >>>>>> @@ -188,10 +147,10 @@ static int jr_hw_reset(uint8_t sec_idx)
> >>>>>> /* -1 --- error, can't enqueue -- no space available */
> >>>>>> static int jr_enqueue(uint32_t *desc_addr,
> >>>>>> void (*callback)(uint32_t status, void *arg),
> >>>>>> - void *arg, uint8_t sec_idx)
> >>>>>> + void *arg, uint8_t sec_idx, struct caam_regs *caam)
> >>>>>> {
> >>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> >>>>>> - struct jobring *jr = &jr0[sec_idx];
> >>>>>> + struct jr_regs *regs = caam->regs;
> >>>>>> + struct jobring *jr = &caam->jr[sec_idx];
> >>>>>> int head = jr->head;
> >>>>>> uint32_t desc_word;
> >>>>>> int length = desc_len(desc_addr); @@ -263,10 +222,10 @@
> >>>>>> static int jr_enqueue(uint32_t *desc_addr,
> >>>>>> return 0;
> >>>>>> }
> >>>>>>
> >>>>>> -static int jr_dequeue(int sec_idx)
> >>>>>> +static int jr_dequeue(int sec_idx, struct caam_regs *caam)
> >>>>>> {
> >>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> >>>>>> - struct jobring *jr = &jr0[sec_idx];
> >>>>>> + struct jr_regs *regs = caam->regs;
> >>>>>> + struct jobring *jr = &caam->jr[sec_idx];
> >>>>>> int head = jr->head;
> >>>>>> int tail = jr->tail;
> >>>>>> int idx, i, found;
> >>>>>> @@ -349,14 +308,18 @@ static void desc_done(uint32_t status, void
> >> *arg)
> >>>>>> {
> >>>>>> struct result *x = arg;
> >>>>>> x->status = status;
> >>>>>> -#ifndef CONFIG_SPL_BUILD
> >>>>>> caam_jr_strstatus(status); -#endif
> >>>>>> x->done = 1;
> >>>>>> }
> >>>>>>
> >>>>>> static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
> >>>>>> {
> >>>>>> + struct caam_regs *caam;
> >>>>>> +#if CONFIG_IS_ENABLED(DM)
> >>>>>> + caam = dev_get_priv(caam_dev); #else
> >>>>>> + caam = &caam_st;
> >>>>>> +#endif
> >>>>>> unsigned long long timeval = 0;
> >>>>>> unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
> >>>>>> struct result op;
> >>>>>> @@ -364,7 +327,7 @@ static inline int
> >>>>>> run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
> >>>>>>
> >>>>>> memset(&op, 0, sizeof(op));
> >>>>>>
> >>>>>> - ret = jr_enqueue(desc, desc_done, &op, sec_idx);
> >>>>>> + ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
> >>>>>> if (ret) {
> >>>>>> debug("Error in SEC enq\n");
> >>>>>> ret = JQ_ENQ_ERR;
> >>>>>> @@ -375,7 +338,7 @@ static inline int
> >>>>>> run_descriptor_jr_idx(uint32_t *desc,
> >>>>> uint8_t sec_idx)
> >>>>>> udelay(1);
> >>>>>> timeval += 1;
> >>>>>>
> >>>>>> - ret = jr_dequeue(sec_idx);
> >>>>>> + ret = jr_dequeue(sec_idx, caam);
> >>>>>> if (ret) {
> >>>>>> debug("Error in SEC deq\n");
> >>>>>> ret = JQ_DEQ_ERR; @@ -402,13 +365,62 @@
> >>>>>> int run_descriptor_jr(uint32_t *desc)
> >>>>>> return run_descriptor_jr_idx(desc, 0);
> >>>>>> }
> >>>>>>
> >>>>>> +static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam) {
> >>>>>> + struct jobring *jr = &caam->jr[sec_idx];
> >>>>>> +
> >>>>>> + jr->head = 0;
> >>>>>> + jr->tail = 0;
> >>>>>> + jr->read_idx = 0;
> >>>>>> + jr->write_idx = 0;
> >>>>>> + memset(jr->info, 0, sizeof(jr->info));
> >>>>>> + memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
> >>>>>> + memset(jr->output_ring, 0, jr->size * sizeof(struct
> >>>>>> + op_ring));
> >>>>>> +
> >>>>>> + return 0;
> >>>>>> +}
> >>>>>> +
> >>>>>> +static int jr_hw_reset(struct jr_regs *regs) {
> >>>>>> + uint32_t timeout = 100000;
> >>>>>> + uint32_t jrint, jrcr;
> >>>>>> +
> >>>>>> + sec_out32(®s->jrcr, JRCR_RESET);
> >>>>>> + do {
> >>>>>> + jrint = sec_in32(®s->jrint);
> >>>>>> + } while (((jrint & JRINT_ERR_HALT_MASK) ==
> >>>>>> + JRINT_ERR_HALT_INPROGRESS) && --timeout);
> >>>>>> +
> >>>>>> + jrint = sec_in32(®s->jrint);
> >>>>>> + if (((jrint & JRINT_ERR_HALT_MASK) !=
> >>>>>> + JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
> >>>>>> + return -1;
> >>>>>> +
> >>>>>> + timeout = 100000;
> >>>>>> + sec_out32(®s->jrcr, JRCR_RESET);
> >>>>>> + do {
> >>>>>> + jrcr = sec_in32(®s->jrcr);
> >>>>>> + } while ((jrcr & JRCR_RESET) && --timeout);
> >>>>>> +
> >>>>>> + if (timeout == 0)
> >>>>>> + return -1;
> >>>>>> +
> >>>>>> + return 0;
> >>>>>> +}
> >>>>>> +
> >>>>>> static inline int jr_reset_sec(uint8_t sec_idx)
> >>>>>> {
> >>>>>> - if (jr_hw_reset(sec_idx) < 0)
> >>>>>> + struct caam_regs *caam;
> >>>>>> +#if CONFIG_IS_ENABLED(DM)
> >>>>>> + caam = dev_get_priv(caam_dev); #else
> >>>>>> + caam = &caam_st;
> >>>>>> +#endif
> >>>>>> + if (jr_hw_reset(caam->regs) < 0)
> >>>>>> return -1;
> >>>>>>
> >>>>>> /* Clean up the jobring structure maintained by software */
> >>>>>> - jr_sw_cleanup(sec_idx);
> >>>>>> + jr_sw_cleanup(sec_idx, caam);
> >>>>>>
> >>>>>> return 0;
> >>>>>> }
> >>>>>> @@ -418,9 +430,15 @@ int jr_reset(void)
> >>>>>> return jr_reset_sec(0);
> >>>>>> }
> >>>>>>
> >>>>>> -static inline int sec_reset_idx(uint8_t sec_idx)
> >>>>>> +int sec_reset(void)
> >>>>>> {
> >>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> >>>>>> + struct caam_regs *caam;
> >>>>>> +#if CONFIG_IS_ENABLED(DM)
> >>>>>> + caam = dev_get_priv(caam_dev); #else
> >>>>>> + caam = &caam_st;
> >>>>>> +#endif
> >>>>>> + ccsr_sec_t *sec = caam->sec;
> >>>>>> uint32_t mcfgr = sec_in32(&sec->mcfgr);
> >>>>>> uint32_t timeout = 100000;
> >>>>>>
> >>>>>> @@ -446,11 +464,7 @@ static inline int sec_reset_idx(uint8_t
> >>>>>> sec_idx)
> >>>>>>
> >>>>>> return 0;
> >>>>>> }
> >>>>>> -int sec_reset(void)
> >>>>>> -{
> >>>>>> - return sec_reset_idx(0);
> >>>>>> -}
> >>>>>> -#ifndef CONFIG_SPL_BUILD
> >>>>>> +
> >>>>>> static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
> >>>>>> {
> >>>>>> u32 *desc;
> >>>>>> @@ -496,12 +510,11 @@ static int deinstantiate_rng(u8 sec_idx,
> >>>>>> int
> >>>>> state_handle_mask)
> >>>>>> return ret;
> >>>>>> }
> >>>>>>
> >>>>>> -static int instantiate_rng(u8 sec_idx, int gen_sk)
> >>>>>> +static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int
> >>>>>> +gen_sk)
> >>>>>> {
> >>>>>> u32 *desc;
> >>>>>> u32 rdsta_val;
> >>>>>> int ret = 0, sh_idx, size;
> >>>>>> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
> >> *)SEC_ADDR(sec_idx);
> >>>>>> struct rng4tst __iomem *rng =
> >>>>>> (struct rng4tst __iomem *)&sec->rng;
> >>>>>>
> >>>>>> @@ -554,9 +567,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk)
> >>>>>> return ret;
> >>>>>> }
> >>>>>>
> >>>>>> -static u8 get_rng_vid(uint8_t sec_idx)
> >>>>>> +static u8 get_rng_vid(ccsr_sec_t *sec)
> >>>>>> {
> >>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> >>>>>> u8 vid;
> >>>>>>
> >>>>>> if (caam_get_era() < 10) { @@ -574,9 +586,8 @@ static u8
> >>>>>> get_rng_vid(uint8_t sec_idx)
> >>>>>> * By default, the TRNG runs for 200 clocks per sample;
> >>>>>> * 1200 clocks per sample generates better entropy.
> >>>>>> */
> >>>>>> -static void kick_trng(int ent_delay, uint8_t sec_idx)
> >>>>>> +static void kick_trng(int ent_delay, ccsr_sec_t *sec)
> >>>>>> {
> >>>>>> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
> >> *)SEC_ADDR(sec_idx);
> >>>>>> struct rng4tst __iomem *rng =
> >>>>>> (struct rng4tst __iomem *)&sec->rng;
> >>>>>> u32 val;
> >>>>>> @@ -603,10 +614,9 @@ static void kick_trng(int ent_delay, uint8_t
> >>> sec_idx)
> >>>>>> sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
> >>>>>> }
> >>>>>>
> >>>>>> -static int rng_init(uint8_t sec_idx)
> >>>>>> +static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
> >>>>>> {
> >>>>>> int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
> >>>>>> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
> >> *)SEC_ADDR(sec_idx);
> >>>>>> struct rng4tst __iomem *rng =
> >>>>>> (struct rng4tst __iomem *)&sec->rng;
> >>>>>> u32 inst_handles;
> >>>>>> @@ -624,7 +634,7 @@ static int rng_init(uint8_t sec_idx)
> >>>>>> * the TRNG parameters.
> >>>>>> */
> >>>>>> if (!inst_handles) {
> >>>>>> - kick_trng(ent_delay, sec_idx);
> >>>>>> + kick_trng(ent_delay, sec);
> >>>>>> ent_delay += 400;
> >>>>>> }
> >>>>>> /*
> >>>>>> @@ -634,7 +644,7 @@ static int rng_init(uint8_t sec_idx)
> >>>>>> * interval, leading to a sucessful initialization of
> >>>>>> * the RNG.
> >>>>>> */
> >>>>>> - ret = instantiate_rng(sec_idx, gen_sk);
> >>>>>> + ret = instantiate_rng(sec_idx, sec, gen_sk);
> >>>>>> } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
> >>>>>> if (ret) {
> >>>>>> printf("SEC%u: Failed to instantiate RNG\n",
> >>>>>> sec_idx); @@ -646,13 +656,28 @@ static int rng_init(uint8_t
> >>>>>> sec_idx)
> >>>>>>
> >>>>>> return ret;
> >>>>>> }
> >>>>>> -#endif
> >>>>>> +
> >>>>>> int sec_init_idx(uint8_t sec_idx)
> >>>>>> {
> >>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
> >>>>>> - uint32_t mcr = sec_in32(&sec->mcfgr);
> >>>>>> int ret = 0;
> >>>>>> -
> >>>>>> + struct caam_regs *caam;
> >>>>>> +#if CONFIG_IS_ENABLED(DM)
> >>>>>> + if (!caam_dev) {
> >>>>>> + printf("caam_jr: caam not found\n");
> >>>>>> + return -1;
> >>>>>> + }
> >>>>>> + caam = dev_get_priv(caam_dev); #else
> >>>>>> + caam_st.sec = (void *)SEC_ADDR(sec_idx);
> >>>>>> + caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
> >>>>>> + caam_st.jrid = 0;
> >>>>>> + caam = &caam_st;
> >>>>>> +#endif
> >>>>>> + ccsr_sec_t *sec = caam->sec;
> >>>>>> + uint32_t mcr = sec_in32(&sec->mcfgr); #if
> >>>>>> +defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> >>>>>> + uint32_t jrdid_ms = 0;
> >>>>>> +#endif
> >>>>>> #ifdef CONFIG_FSL_CORENET
> >>>>>> uint32_t liodnr;
> >>>>>> uint32_t liodn_ns;
> >>>>>> @@ -682,6 +707,11 @@ int sec_init_idx(uint8_t sec_idx)
> >>>>>> mcr |= (1 << MCFGR_PS_SHIFT);
> >>>>>> #endif
> >>>>>> sec_out32(&sec->mcfgr, mcr);
> >>>>>> +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
> >>>>>> + jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ |
> >>>>> JRDID_MS_PRIM_DID;
> >>>>>> + sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms); #endif
> >>>>>> + jr_reset();
> >>>>>>
> >>>>>> #ifdef CONFIG_FSL_CORENET
> >>>>>> #ifdef CONFIG_SPL_BUILD
> >>>>>> @@ -693,20 +723,19 @@ int sec_init_idx(uint8_t sec_idx)
> >>>>>> liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
> >>>>>> liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
> >>>>>>
> >>>>>> - liodnr = sec_in32(&sec->jrliodnr[0].ls) &
> >>>>>> + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
> >>>>>> ~(JRNSLIODN_MASK | JRSLIODN_MASK);
> >>>>>> liodnr = liodnr |
> >>>>>> (liodn_ns << JRNSLIODN_SHIFT) |
> >>>>>> (liodn_s << JRSLIODN_SHIFT);
> >>>>>> - sec_out32(&sec->jrliodnr[0].ls, liodnr);
> >>>>>> + sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
> >>>>>> #else
> >>>>>> - liodnr = sec_in32(&sec->jrliodnr[0].ls);
> >>>>>> + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
> >>>>>> liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
> >>>>>> liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
> >>>>>> #endif
> >>>>>> #endif
> >>>>>> -
> >>>>>> - ret = jr_init(sec_idx);
> >>>>>> + ret = jr_init(sec_idx, caam);
> >>>>>> if (ret < 0) {
> >>>>>> printf("SEC%u: initialization failed\n", sec_idx);
> >>>>>> return -1;
> >>>>>> @@ -719,9 +748,9 @@ int sec_init_idx(uint8_t sec_idx)
> >>>>>>
> >>>>>> pamu_enable();
> >>>>>> #endif
> >>>>>> -#ifndef CONFIG_SPL_BUILD
> >>>>>> - if (get_rng_vid(sec_idx) >= 4) {
> >>>>>> - if (rng_init(sec_idx) < 0) {
> >>>>>> +
> >>>>>> + if (get_rng_vid(caam->sec) >= 4) {
> >>>>>> + if (rng_init(sec_idx, caam->sec) < 0) {
> >>>>>> printf("SEC%u: RNG instantiation failed\n", sec_idx);
> >>>>>> return -1;
> >>>>>> }
> >>>>>> @@ -735,7 +764,6 @@ int sec_init_idx(uint8_t sec_idx)
> >>>>>>
> >>>>>> printf("SEC%u: RNG instantiated\n", sec_idx);
> >>>>>> }
> >>>>>> -#endif
> >>>>>> return ret;
> >>>>>> }
> >>>>>>
> >>>>>> @@ -743,3 +771,76 @@ int sec_init(void)
> >>>>>> {
> >>>>>> return sec_init_idx(0);
> >>>>>> }
> >>>>>> +
> >>>>>> +#if CONFIG_IS_ENABLED(DM)
> >>>>>> +static int caam_jr_ioctl(struct udevice *dev, unsigned long
> >>>>>> +request, void *buf) {
> >>>>>> + if (request != CAAM_JR_RUN_DESC)
> >>>>>> + return -ENOSYS;
> >>>>>> +
> >>>>>> + return run_descriptor_jr(buf); }
> >>>>>> +
> >>>>>> +static int caam_jr_probe(struct udevice *dev) {
> >>>>>> + struct caam_regs *caam = dev_get_priv(dev);
> >>>>>> + fdt_addr_t addr;
> >>>>>> + ofnode node;
> >>>>>> + unsigned int jr_node = 0;
> >>>>>> +
> >>>>>> + caam_dev = dev;
> >>>>>> +
> >>>>>> + addr = dev_read_addr(dev);
> >>>>>> + if (addr == FDT_ADDR_T_NONE) {
> >>>>>> + printf("caam_jr: crypto not found\n");
> >>>>>> + return -EINVAL;
> >>>>>> + }
> >>>>>> + caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
> >>>>>> + caam->regs = (struct jr_regs *)caam->sec;
> >>>>>> +
> >>>>>> + /* Check for enabled job ring node */
> >>>>>> + ofnode_for_each_subnode(node, dev_ofnode(dev)) {
> >>>>>> + if (!ofnode_is_available(node))
> >>>>>> + continue;
> >>>>>> +
> >>>>>> + jr_node = ofnode_read_u32_default(node, "reg", -1);
> >>>>>> + if (jr_node > 0) {
> >>>>>> + caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
> >>>>>> + while (!(jr_node & 0x0F))
> >>>>>> + jr_node = jr_node >> 4;
> >>>>>> +
> >>>>>> + caam->jrid = jr_node - 1;
> >>>>>> + break;
> >>>>>> + }
> >>>>>> + }
> >>>>>> +
> >>>>>> + if (sec_init())
> >>>>>> + printf("\nsec_init failed!\n");
> >>>>>> +
> >>>>>> + return 0;
> >>>>>> +}
> >>>>>> +
> >>>>>> +static int caam_jr_bind(struct udevice *dev) {
> >>>>>> + return 0;
> >>>>>> +}
> >>>>>> +
> >>>>>> +static const struct misc_ops caam_jr_ops = {
> >>>>>> + .ioctl = caam_jr_ioctl,
> >>>>>> +};
> >>>>>> +
> >>>>>> +static const struct udevice_id caam_jr_match[] = {
> >>>>>> + { .compatible = "fsl,sec-v4.0" },
> >>>>>> + { }
> >>>>>> +};
> >>>>>> +
> >>>>>> +U_BOOT_DRIVER(caam_jr) = {
> >>>>>> + .name = "caam_jr",
> >>>>>> + .id = UCLASS_MISC,
> >>>>>> + .of_match = caam_jr_match,
> >>>>>> + .ops = &caam_jr_ops,
> >>>>>> + .bind = caam_jr_bind,
> >>>>>> + .probe = caam_jr_probe,
> >>>>>> + .priv_auto = sizeof(struct caam_regs),
> >>>>>> +};
> >>>>>> +#endif
> >>>>>> diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
> >>>>>> index 1047aa772c..3eb7be79da 100644
> >>>>>> --- a/drivers/crypto/fsl/jr.h
> >>>>>> +++ b/drivers/crypto/fsl/jr.h
> >>>>>> @@ -1,6 +1,7 @@
> >>>>>> /* SPDX-License-Identifier: GPL-2.0+ */
> >>>>>> /*
> >>>>>> * Copyright 2008-2014 Freescale Semiconductor, Inc.
> >>>>>> + * Copyright 2021 NXP
> >>>>>> *
> >>>>>> */
> >>>>>>
> >>>>>> @@ -8,7 +9,9 @@
> >>>>>> #define __JR_H
> >>>>>>
> >>>>>> #include <linux/compiler.h>
> >>>>>> +#include "fsl_sec.h"
> >>>>>> #include "type.h"
> >>>>>> +#include <misc.h>
> >>>>>>
> >>>>>> #define JR_SIZE 4
> >>>>>> /* Timeout currently defined as 10 sec */ @@ -35,12 +38,21 @@
> >>>>>> #define JRSLIODN_SHIFT 0
> >>>>>> #define JRSLIODN_MASK 0x00000fff
> >>>>>>
> >>>>>> -#define JQ_DEQ_ERR -1
> >>>>>> -#define JQ_DEQ_TO_ERR -2
> >>>>>> -#define JQ_ENQ_ERR -3
> >>>>>> +#define JRDID_MS_PRIM_DID BIT(0)
> >>>>>> +#define JRDID_MS_PRIM_TZ BIT(4)
> >>>>>> +#define JRDID_MS_TZ_OWN BIT(15)
> >>>>>> +
> >>>>>> +#define JQ_DEQ_ERR (-1)
> >>>>>> +#define JQ_DEQ_TO_ERR (-2)
> >>>>>> +#define JQ_ENQ_ERR (-3)
> >>>>>>
> >>>>>> #define RNG4_MAX_HANDLES 2
> >>>>>>
> >>>>>> +enum {
> >>>>>> + /* Run caam jobring descriptor(in buf) */
> >>>>>> + CAAM_JR_RUN_DESC,
> >>>>>> +};
> >>>>>> +
> >>>>>> struct op_ring {
> >>>>>> caam_dma_addr_t desc;
> >>>>>> uint32_t status;
> >>>>>> @@ -102,6 +114,19 @@ struct result {
> >>>>>> uint32_t status;
> >>>>>> };
> >>>>>>
> >>>>>> +/*
> >>>>>> + * struct caam_regs - CAAM initialization register interface
> >>>>>> + *
> >>>>>> + * Interface to caam memory map, jobring register, jobring storage.
> >>>>>> + */
> >>>>>> +struct caam_regs {
> >>>>>> + ccsr_sec_t *sec; /*caam initialization registers*/
> >>>>>> + struct jr_regs *regs; /*jobring configuration registers*/
> >>>>>> + u8 jrid; /*id to identify a jobring*/
> >>>>>> + /*Private sub-storage for a single JobR*/
> >>>>>> + struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> >>>>>> +};
> >>>>>> +
> >>>>>> void caam_jr_strstatus(u32 status);
> >>>>>> int run_descriptor_jr(uint32_t *desc);
> >>>>>>
> >>>>>
> >>>>> --
> >>>>>
> >>>>
> >>>
> >>
> =================================================================
> >>>>> ====
> >>>>> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> >>>>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> >>>>> Germany
> >>>>> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email:
> >>>>> sbabic@denx.de
> >>>>>
> >>>>
> >>>
> >>
> =================================================================
> >>>>> ====
>
>
> --
> =================================================================
> ====
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
> =================================================================
> ====
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-03 13:41 ` Gaurav Jain
@ 2022-03-03 15:30 ` Stefano Babic
2022-03-06 19:38 ` ZHIZHIKIN Andrey
2022-03-07 9:58 ` Michael Walle
0 siblings, 2 replies; 69+ messages in thread
From: Stefano Babic @ 2022-03-03 15:30 UTC (permalink / raw)
To: Gaurav Jain, Stefano Babic, u-boot, Marek Vasut
Cc: Fabio Estevam, Peng Fan, Simon Glass, Priyanka Jain, Ye Li,
Horia Geanta, Ji Luo, Franck Lenormand, Silvano Di Ninno,
Sahil Malhotra, Pankaj Gupta, Varun Sethi, dl-uboot-imx,
Shengzhou Liu, Mingkai Hu, Rajesh Bhagat, Meenakshi Aggarwal,
Wasim Khan, Alison Wang, Pramod Kumar, Andy Tang, Adrian Alonso,
Vladimir Oltean
Hi,
On 03.03.22 14:41, Gaurav Jain wrote:
> Hi Stefano
>
> As we have not received any response from imx6dl_mamoj board maintainer.
> I propose the below solution
>
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
> - select FSL_CAAM if HAS_CAAM
> - imply CMD_DEKBLOB if HAS_CAAM
> + imply FSL_CAAM if HAS_CAAM
> + imply CMD_DEKBLOB if FSL_CAAM
> Help
>
IMO this is ok, I was also wrong, Marek is not the maintainer of this
board. This was the only board with broken build - let's say, I will
still wait a couple of days, and if there is no comments, I will apply
your series (but then V10). I can apply this fix myself, no need to post
the series again (I have not seen any other comment or request to change).
Regards,
Stefano
> --- a/configs/imx6dl_mamoj_defconfig
> +++ b/configs/imx6dl_mamoj_defconfig
> @@ -59,3 +59,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> +CONFIG_FSL_CAAM=n
>
> Need your help to review this or suggest any other solution.
>
> Regards
> Gaurav Jain
>
>> -----Original Message-----
>> From: Stefano Babic <sbabic@denx.de>
>> Sent: Thursday, March 3, 2022 6:32 PM
>> To: Gaurav Jain <gaurav.jain@nxp.com>; Stefano Babic <sbabic@denx.de>; u-
>> boot@lists.denx.de; Marek Vasut <marex@denx.de>
>> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
>> Simon Glass <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye
>> Li <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
>> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
>> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
>> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
>> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
>> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
>> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
>> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
>> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
>> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
>> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
>> ring driver model
>>
>> Caution: EXT Email
>>
>> On 03.03.22 13:44, Gaurav Jain wrote:
>>> Hello Stefano
>>>
>>> A gentle reminder!!
>>> Need your help to check the proposed solution to fix imx6dl_mamoj SPL size
>> issue shared in last mail.
>>
>> Ouch...is there a solution ? I confess I have not seen, is there an answer by
>> Marek ?
>>
>> Regards,
>> Stefano
>>
>>>
>>> Regards
>>> Gaurav Jain
>>>
>>>> -----Original Message-----
>>>> From: Gaurav Jain
>>>> Sent: Friday, February 25, 2022 12:33 PM
>>>> To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek Vasut
>>>> <marex@denx.de>
>>>> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
>>>> Simon Glass <sjg@chromium.org>; Priyanka Jain
>>>> <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
>>>> <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
>>>> <franck.lenormand@nxp.com>; Silvano Di Ninno
>>>> <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
>>>> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
>>>> dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
>>>> <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
>>>> Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
>>>> <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
>> Alison
>>>> Wang <alison.wang@nxp.com>; Pramod Kumar
>> <pramod.kumar_1@nxp.com>;
>>>> Andy Tang <andy.tang@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
>>>> Vladimir Oltean <olteanv@gmail.com>
>>>> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
>>>> CAAM Job ring driver model
>>>>
>>>> Hello Stefano
>>>>
>>>>> -----Original Message-----
>>>>> From: Gaurav Jain
>>>>> Sent: Friday, February 11, 2022 3:09 PM
>>>>> To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek
>>>>> Vasut <marex@denx.de>
>>>>> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
>>>>> Simon Glass <sjg@chromium.org>; Priyanka Jain
>>>>> <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
>>>>> <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
>>>>> <franck.lenormand@nxp.com>; Silvano Di Ninno
>>>>> <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
>>>>> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
>>>>> dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
>>>>> <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
>>>>> Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
>>>>> <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
>>>> Alison
>>>>> Wang <alison.wang@nxp.com>; Pramod Kumar
>>>> <pramod.kumar_1@nxp.com>;
>>>>> Andy Tang <andy.tang@nxp.com>; Adrian Alonso
>>>>> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
>>>>> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
>>>>> CAAM Job ring driver model
>>>>>
>>>>> Hello Marek
>>>>>
>>>>> A gentle reminder!!
>>>>> Please help to check if some feature can be dropped in SPL from
>>>>> imx6dl_mamoj board so that CAAM driver model patches can be accepted.
>>>>>
>>>>> Regards
>>>>> Gaurav Jain
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: Gaurav Jain
>>>>>> Sent: Monday, February 7, 2022 12:43 PM
>>>>>> To: Stefano Babic <sbabic@denx.de>; u-boot@lists.denx.de; Marek
>>>>>> Vasut <marex@denx.de>
>>>>>> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan
>>>>>> <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Priyanka Jain
>>>>>> <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>; Horia Geanta
>>>>>> <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
>>>>>> <franck.lenormand@nxp.com>; Silvano Di Ninno
>>>>>> <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
>>>>>> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
>>>>>> dl- uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
>>>>>> <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
>>>>>> Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
>>>>>> <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
>>>>> Alison
>>>>>> Wang <alison.wang@nxp.com>; Pramod Kumar
>>>>> <pramod.kumar_1@nxp.com>;
>>>>>> Andy Tang <andy.tang@nxp.com>; Adrian Alonso
>>>>>> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
>>>>>> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
>>>>>> CAAM Job ring driver model
>>>>>>
>>>>>> Hello Marek
>>>>>>
>>>>>>> -----Original Message-----
>>>>>>> From: Stefano Babic <sbabic@denx.de>
>>>>>>> Sent: Saturday, February 5, 2022 7:46 PM
>>>>>>> To: Gaurav Jain <gaurav.jain@nxp.com>; u-boot@lists.denx.de
>>>>>>> Cc: Stefano Babic <sbabic@denx.de>; Fabio Estevam
>>>>>>> <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
>>>>>>> <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
>>>>>>> <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
>>>>>>> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>;
>>>>>>> Silvano Di Ninno <silvano.dininno@nxp.com>; Sahil Malhotra
>>>>>>> <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>;
>>>>>>> Varun Sethi <V.Sethi@nxp.com>; dl-uboot-imx <uboot-imx@nxp.com>;
>>>>>>> Shengzhou Liu <shengzhou.liu@nxp.com>; Mingkai Hu
>>>>>>> <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
>>>>>>> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
>>>>>>> <wasim.khan@nxp.com>;
>>>>>> Alison
>>>>>>> Wang <alison.wang@nxp.com>; Pramod Kumar
>>>>>> <pramod.kumar_1@nxp.com>;
>>>>>>> Andy Tang <andy.tang@nxp.com>; Adrian Alonso
>>>>>>> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>;
>>>>>>> Marek Vasut <marex@denx.de>
>>>>>>> Subject: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
>>>>>>> CAAM Job ring driver model
>>>>>>>
>>>>>>> Caution: EXT Email
>>>>>>>
>>>>>>> Hi Gaurav,
>>>>>>>
>>>>>>> rather I still have issues to run CI with this applied. The reason
>>>>>>> is that this adds an overhead to SPL and it breaks the board
>>>>>>> imx6dl_mamoj because SPL exceeds the maximum size for a DL SOC.
>>>>>>>
>>>>>>> See
>>>>>>> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
>>>>>>> so
>>>>>>> ur
>>>>>>> ce.d
>>>>>>> enx.de%2Fu-boot%2Fcustodians%2Fu-boot-imx%2F-
>>>>>>> %2Fjobs%2F387370&data=04%7C01%7Cgaurav.jain%40nxp.com%7
>> C
>>>> 3a
>>>>> 2
>>>>>> 73
>>>>>>>
>>>>>>
>>>>>
>>>>
>> 1dd27fc4bebcad308d9e8b21464%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C
>>>>>>>
>>>>>>
>>>>>
>>>>
>> 0%7C0%7C637796673834942697%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
>>>>>>>
>>>>>>
>>>>>
>>>>
>> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&am
>>>>>>>
>>>>>>
>>>>>
>>>>
>> p;sdata=pI%2F%2FlNtrdrGCa8sSvcr6uNu4jze7pzDqZtI52FIDj50%3D&reserv
>>>> e
>>>>>>> d=0
>>>>>>>
>>>>>>> I do not know if it is possible to drop some features from SPL for
>>>>>>> this board (Added Marek as board maintainer).
>>>>
>>>> As we have not received any response from imx6dl_mamoj board maintainer.
>>>> I propose the below solution
>>>>
>>>> --- a/arch/arm/mach-imx/Kconfig
>>>> +++ b/arch/arm/mach-imx/Kconfig
>>>> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
>>>> - select FSL_CAAM if HAS_CAAM
>>>> - imply CMD_DEKBLOB if HAS_CAAM
>>>> + imply FSL_CAAM if HAS_CAAM
>>>> + imply CMD_DEKBLOB if FSL_CAAM
>>>> Help
>>>>
>>>> --- a/configs/imx6dl_mamoj_defconfig
>>>> +++ b/configs/imx6dl_mamoj_defconfig
>>>> @@ -59,3 +59,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
>>>> +CONFIG_FSL_CAAM=n
>>>>
>>>> Need your help to review this or suggest any other solution.
>>>>
>>>> Regards
>>>> Gaurav Jain
>>>>
>>>>>>
>>>>>> CONFIG_IMX_HAB is enabled for imx6dl_mamoj. So CAAM is built for
>>>>>> SPL, results in increased size.
>>>>>> However CAAM is not initialized in SPL. As Stefano suggested, Can
>>>>>> you drop some features from SPL?
>>>>>>
>>>>>> Regards
>>>>>> Gaurav Jain
>>>>>>>
>>>>>>> Best regards,
>>>>>>> Stefano
>>>>>>>
>>>>>>> On 10.01.22 13:27, Gaurav Jain wrote:
>>>>>>>> added device tree support for job ring driver.
>>>>>>>> sec is initialized based on job ring information processed from
>>>>>>>> device tree.
>>>>>>>>
>>>>>>>> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
>>>>>>>> Reviewed-by: Ye Li <ye.li@nxp.com>
>>>>>>>> ---
>>>>>>>> drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++++-------------
>> -
>>>>>>>> drivers/crypto/fsl/jr.h | 31 +++-
>>>>>>>> 2 files changed, 240 insertions(+), 114 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
>>>>>>>> index
>>>>>>>> 22b649219e..8103987425 100644
>>>>>>>> --- a/drivers/crypto/fsl/jr.c
>>>>>>>> +++ b/drivers/crypto/fsl/jr.c
>>>>>>>> @@ -1,7 +1,7 @@
>>>>>>>> // SPDX-License-Identifier: GPL-2.0+
>>>>>>>> /*
>>>>>>>> * Copyright 2008-2014 Freescale Semiconductor, Inc.
>>>>>>>> - * Copyright 2018 NXP
>>>>>>>> + * Copyright 2018, 2021 NXP
>>>>>>>> *
>>>>>>>> * Based on CAAM driver in drivers/crypto/caam in Linux
>>>>>>>> */
>>>>>>>> @@ -11,7 +11,6 @@
>>>>>>>> #include <linux/kernel.h>
>>>>>>>> #include <log.h>
>>>>>>>> #include <malloc.h>
>>>>>>>> -#include "fsl_sec.h"
>>>>>>>> #include "jr.h"
>>>>>>>> #include "jobdesc.h"
>>>>>>>> #include "desc_constr.h"
>>>>>>>> @@ -21,7 +20,10 @@
>>>>>>>> #include <asm/cache.h>
>>>>>>>> #include <asm/fsl_pamu.h>
>>>>>>>> #endif
>>>>>>>> +#include <dm.h>
>>>>>>>> #include <dm/lists.h>
>>>>>>>> +#include <dm/root.h>
>>>>>>>> +#include <dm/device-internal.h>
>>>>>>>> #include <linux/delay.h>
>>>>>>>>
>>>>>>>> #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size
>>>>>>>> -
>>>>>>>> 1)) @@ -35,20 +37,29 @@ uint32_t
>>>>>>> sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
>>>>>>>> #endif
>>>>>>>> };
>>>>>>>>
>>>>>>>> +#if CONFIG_IS_ENABLED(DM)
>>>>>>>> +struct udevice *caam_dev;
>>>>>>>> +#else
>>>>>>>> #define SEC_ADDR(idx) \
>>>>>>>> (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
>>>>>>>>
>>>>>>>> #define SEC_JR0_ADDR(idx) \
>>>>>>>> (ulong)(SEC_ADDR(idx) + \
>>>>>>>> (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
>>>>>>>> +struct caam_regs caam_st;
>>>>>>>> +#endif
>>>>>>>>
>>>>>>>> -struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
>>>>>>>> +static inline u32 jr_start_reg(u8 jrid) {
>>>>>>>> + return (1 << jrid);
>>>>>>>> +}
>>>>>>>>
>>>>>>>> -static inline void start_jr0(uint8_t sec_idx)
>>>>>>>> +static inline void start_jr(struct caam_regs *caam)
>>>>>>>> {
>>>>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
>>>>>>>> + ccsr_sec_t *sec = caam->sec;
>>>>>>>> u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
>>>>>>>> u32 scfgr = sec_in32(&sec->scfgr);
>>>>>>>> + u32 jrstart = jr_start_reg(caam->jrid);
>>>>>>>>
>>>>>>>> if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
>>>>>>>> /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or @@ -56,23
>>>>>>>> +67,16 @@ static inline void start_jr0(uint8_t sec_idx)
>>>>>>>> */
>>>>>>>> if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
>>>>>>>> (scfgr & SEC_SCFGR_VIRT_EN))
>>>>>>>> - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
>>>>>>>> + sec_out32(&sec->jrstartr, jrstart);
>>>>>>>> } else {
>>>>>>>> /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
>>>>>>>> if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
>>>>>>>> - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
>>>>>>>> + sec_out32(&sec->jrstartr, jrstart);
>>>>>>>> }
>>>>>>>> }
>>>>>>>>
>>>>>>>> -static inline void jr_reset_liodn(uint8_t sec_idx)
>>>>>>>> +static inline void jr_disable_irq(struct jr_regs *regs)
>>>>>>>> {
>>>>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
>>>>>>>> - sec_out32(&sec->jrliodnr[0].ls, 0);
>>>>>>>> -}
>>>>>>>> -
>>>>>>>> -static inline void jr_disable_irq(uint8_t sec_idx) -{
>>>>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
>>>>>>>> uint32_t jrcfg = sec_in32(®s->jrcfg1);
>>>>>>>>
>>>>>>>> jrcfg = jrcfg | JR_INTMASK; @@ -80,10 +84,10 @@ static
>>>>>>>> inline void jr_disable_irq(uint8_t sec_idx)
>>>>>>>> sec_out32(®s->jrcfg1, jrcfg);
>>>>>>>> }
>>>>>>>>
>>>>>>>> -static void jr_initregs(uint8_t sec_idx)
>>>>>>>> +static void jr_initregs(uint8_t sec_idx, struct caam_regs
>>>>>>>> +*caam)
>>>>>>>> {
>>>>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
>>>>>>>> - struct jobring *jr = &jr0[sec_idx];
>>>>>>>> + struct jr_regs *regs = caam->regs;
>>>>>>>> + struct jobring *jr = &caam->jr[sec_idx];
>>>>>>>> caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
>>>>>>>> caam_dma_addr_t op_base = virt_to_phys((void
>>>>>>>> *)jr->output_ring);
>>>>>>>>
>>>>>>>> @@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx)
>>>>>>>> sec_out32(®s->irs, JR_SIZE);
>>>>>>>>
>>>>>>>> if (!jr->irq)
>>>>>>>> - jr_disable_irq(sec_idx);
>>>>>>>> + jr_disable_irq(regs);
>>>>>>>> }
>>>>>>>>
>>>>>>>> -static int jr_init(uint8_t sec_idx)
>>>>>>>> +static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
>>>>>>>> {
>>>>>>>> - struct jobring *jr = &jr0[sec_idx];
>>>>>>>> + struct jobring *jr = &caam->jr[sec_idx];
>>>>>>>>
>>>>>>>> memset(jr, 0, sizeof(struct jobring));
>>>>>>>>
>>>>>>>> - jr->jq_id = DEFAULT_JR_ID;
>>>>>>>> + jr->jq_id = caam->jrid;
>>>>>>>> jr->irq = DEFAULT_IRQ;
>>>>>>>>
>>>>>>>> #ifdef CONFIG_FSL_CORENET
>>>>>>>> @@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx)
>>>>>>>> memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
>>>>>>>> memset(jr->output_ring, 0, jr->op_size);
>>>>>>>>
>>>>>>>> - start_jr0(sec_idx);
>>>>>>>> -
>>>>>>>> - jr_initregs(sec_idx);
>>>>>>>> -
>>>>>>>> - return 0;
>>>>>>>> -}
>>>>>>>> -
>>>>>>>> -static int jr_sw_cleanup(uint8_t sec_idx) -{
>>>>>>>> - struct jobring *jr = &jr0[sec_idx];
>>>>>>>> -
>>>>>>>> - jr->head = 0;
>>>>>>>> - jr->tail = 0;
>>>>>>>> - jr->read_idx = 0;
>>>>>>>> - jr->write_idx = 0;
>>>>>>>> - memset(jr->info, 0, sizeof(jr->info));
>>>>>>>> - memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
>>>>>>>> - memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
>>>>>>>> -
>>>>>>>> - return 0;
>>>>>>>> -}
>>>>>>>> -
>>>>>>>> -static int jr_hw_reset(uint8_t sec_idx) -{
>>>>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
>>>>>>>> - uint32_t timeout = 100000;
>>>>>>>> - uint32_t jrint, jrcr;
>>>>>>>> -
>>>>>>>> - sec_out32(®s->jrcr, JRCR_RESET);
>>>>>>>> - do {
>>>>>>>> - jrint = sec_in32(®s->jrint);
>>>>>>>> - } while (((jrint & JRINT_ERR_HALT_MASK) ==
>>>>>>>> - JRINT_ERR_HALT_INPROGRESS) && --timeout);
>>>>>>>> -
>>>>>>>> - jrint = sec_in32(®s->jrint);
>>>>>>>> - if (((jrint & JRINT_ERR_HALT_MASK) !=
>>>>>>>> - JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
>>>>>>>> - return -1;
>>>>>>>> -
>>>>>>>> - timeout = 100000;
>>>>>>>> - sec_out32(®s->jrcr, JRCR_RESET);
>>>>>>>> - do {
>>>>>>>> - jrcr = sec_in32(®s->jrcr);
>>>>>>>> - } while ((jrcr & JRCR_RESET) && --timeout);
>>>>>>>> -
>>>>>>>> - if (timeout == 0)
>>>>>>>> - return -1;
>>>>>>>> + start_jr(caam);
>>>>>>>> + jr_initregs(sec_idx, caam);
>>>>>>>>
>>>>>>>> return 0;
>>>>>>>> }
>>>>>>>> @@ -188,10 +147,10 @@ static int jr_hw_reset(uint8_t sec_idx)
>>>>>>>> /* -1 --- error, can't enqueue -- no space available */
>>>>>>>> static int jr_enqueue(uint32_t *desc_addr,
>>>>>>>> void (*callback)(uint32_t status, void *arg),
>>>>>>>> - void *arg, uint8_t sec_idx)
>>>>>>>> + void *arg, uint8_t sec_idx, struct caam_regs *caam)
>>>>>>>> {
>>>>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
>>>>>>>> - struct jobring *jr = &jr0[sec_idx];
>>>>>>>> + struct jr_regs *regs = caam->regs;
>>>>>>>> + struct jobring *jr = &caam->jr[sec_idx];
>>>>>>>> int head = jr->head;
>>>>>>>> uint32_t desc_word;
>>>>>>>> int length = desc_len(desc_addr); @@ -263,10 +222,10 @@
>>>>>>>> static int jr_enqueue(uint32_t *desc_addr,
>>>>>>>> return 0;
>>>>>>>> }
>>>>>>>>
>>>>>>>> -static int jr_dequeue(int sec_idx)
>>>>>>>> +static int jr_dequeue(int sec_idx, struct caam_regs *caam)
>>>>>>>> {
>>>>>>>> - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
>>>>>>>> - struct jobring *jr = &jr0[sec_idx];
>>>>>>>> + struct jr_regs *regs = caam->regs;
>>>>>>>> + struct jobring *jr = &caam->jr[sec_idx];
>>>>>>>> int head = jr->head;
>>>>>>>> int tail = jr->tail;
>>>>>>>> int idx, i, found;
>>>>>>>> @@ -349,14 +308,18 @@ static void desc_done(uint32_t status, void
>>>> *arg)
>>>>>>>> {
>>>>>>>> struct result *x = arg;
>>>>>>>> x->status = status;
>>>>>>>> -#ifndef CONFIG_SPL_BUILD
>>>>>>>> caam_jr_strstatus(status); -#endif
>>>>>>>> x->done = 1;
>>>>>>>> }
>>>>>>>>
>>>>>>>> static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
>>>>>>>> {
>>>>>>>> + struct caam_regs *caam;
>>>>>>>> +#if CONFIG_IS_ENABLED(DM)
>>>>>>>> + caam = dev_get_priv(caam_dev); #else
>>>>>>>> + caam = &caam_st;
>>>>>>>> +#endif
>>>>>>>> unsigned long long timeval = 0;
>>>>>>>> unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
>>>>>>>> struct result op;
>>>>>>>> @@ -364,7 +327,7 @@ static inline int
>>>>>>>> run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
>>>>>>>>
>>>>>>>> memset(&op, 0, sizeof(op));
>>>>>>>>
>>>>>>>> - ret = jr_enqueue(desc, desc_done, &op, sec_idx);
>>>>>>>> + ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
>>>>>>>> if (ret) {
>>>>>>>> debug("Error in SEC enq\n");
>>>>>>>> ret = JQ_ENQ_ERR;
>>>>>>>> @@ -375,7 +338,7 @@ static inline int
>>>>>>>> run_descriptor_jr_idx(uint32_t *desc,
>>>>>>> uint8_t sec_idx)
>>>>>>>> udelay(1);
>>>>>>>> timeval += 1;
>>>>>>>>
>>>>>>>> - ret = jr_dequeue(sec_idx);
>>>>>>>> + ret = jr_dequeue(sec_idx, caam);
>>>>>>>> if (ret) {
>>>>>>>> debug("Error in SEC deq\n");
>>>>>>>> ret = JQ_DEQ_ERR; @@ -402,13 +365,62 @@
>>>>>>>> int run_descriptor_jr(uint32_t *desc)
>>>>>>>> return run_descriptor_jr_idx(desc, 0);
>>>>>>>> }
>>>>>>>>
>>>>>>>> +static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam) {
>>>>>>>> + struct jobring *jr = &caam->jr[sec_idx];
>>>>>>>> +
>>>>>>>> + jr->head = 0;
>>>>>>>> + jr->tail = 0;
>>>>>>>> + jr->read_idx = 0;
>>>>>>>> + jr->write_idx = 0;
>>>>>>>> + memset(jr->info, 0, sizeof(jr->info));
>>>>>>>> + memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
>>>>>>>> + memset(jr->output_ring, 0, jr->size * sizeof(struct
>>>>>>>> + op_ring));
>>>>>>>> +
>>>>>>>> + return 0;
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static int jr_hw_reset(struct jr_regs *regs) {
>>>>>>>> + uint32_t timeout = 100000;
>>>>>>>> + uint32_t jrint, jrcr;
>>>>>>>> +
>>>>>>>> + sec_out32(®s->jrcr, JRCR_RESET);
>>>>>>>> + do {
>>>>>>>> + jrint = sec_in32(®s->jrint);
>>>>>>>> + } while (((jrint & JRINT_ERR_HALT_MASK) ==
>>>>>>>> + JRINT_ERR_HALT_INPROGRESS) && --timeout);
>>>>>>>> +
>>>>>>>> + jrint = sec_in32(®s->jrint);
>>>>>>>> + if (((jrint & JRINT_ERR_HALT_MASK) !=
>>>>>>>> + JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
>>>>>>>> + return -1;
>>>>>>>> +
>>>>>>>> + timeout = 100000;
>>>>>>>> + sec_out32(®s->jrcr, JRCR_RESET);
>>>>>>>> + do {
>>>>>>>> + jrcr = sec_in32(®s->jrcr);
>>>>>>>> + } while ((jrcr & JRCR_RESET) && --timeout);
>>>>>>>> +
>>>>>>>> + if (timeout == 0)
>>>>>>>> + return -1;
>>>>>>>> +
>>>>>>>> + return 0;
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> static inline int jr_reset_sec(uint8_t sec_idx)
>>>>>>>> {
>>>>>>>> - if (jr_hw_reset(sec_idx) < 0)
>>>>>>>> + struct caam_regs *caam;
>>>>>>>> +#if CONFIG_IS_ENABLED(DM)
>>>>>>>> + caam = dev_get_priv(caam_dev); #else
>>>>>>>> + caam = &caam_st;
>>>>>>>> +#endif
>>>>>>>> + if (jr_hw_reset(caam->regs) < 0)
>>>>>>>> return -1;
>>>>>>>>
>>>>>>>> /* Clean up the jobring structure maintained by software */
>>>>>>>> - jr_sw_cleanup(sec_idx);
>>>>>>>> + jr_sw_cleanup(sec_idx, caam);
>>>>>>>>
>>>>>>>> return 0;
>>>>>>>> }
>>>>>>>> @@ -418,9 +430,15 @@ int jr_reset(void)
>>>>>>>> return jr_reset_sec(0);
>>>>>>>> }
>>>>>>>>
>>>>>>>> -static inline int sec_reset_idx(uint8_t sec_idx)
>>>>>>>> +int sec_reset(void)
>>>>>>>> {
>>>>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
>>>>>>>> + struct caam_regs *caam;
>>>>>>>> +#if CONFIG_IS_ENABLED(DM)
>>>>>>>> + caam = dev_get_priv(caam_dev); #else
>>>>>>>> + caam = &caam_st;
>>>>>>>> +#endif
>>>>>>>> + ccsr_sec_t *sec = caam->sec;
>>>>>>>> uint32_t mcfgr = sec_in32(&sec->mcfgr);
>>>>>>>> uint32_t timeout = 100000;
>>>>>>>>
>>>>>>>> @@ -446,11 +464,7 @@ static inline int sec_reset_idx(uint8_t
>>>>>>>> sec_idx)
>>>>>>>>
>>>>>>>> return 0;
>>>>>>>> }
>>>>>>>> -int sec_reset(void)
>>>>>>>> -{
>>>>>>>> - return sec_reset_idx(0);
>>>>>>>> -}
>>>>>>>> -#ifndef CONFIG_SPL_BUILD
>>>>>>>> +
>>>>>>>> static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
>>>>>>>> {
>>>>>>>> u32 *desc;
>>>>>>>> @@ -496,12 +510,11 @@ static int deinstantiate_rng(u8 sec_idx,
>>>>>>>> int
>>>>>>> state_handle_mask)
>>>>>>>> return ret;
>>>>>>>> }
>>>>>>>>
>>>>>>>> -static int instantiate_rng(u8 sec_idx, int gen_sk)
>>>>>>>> +static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int
>>>>>>>> +gen_sk)
>>>>>>>> {
>>>>>>>> u32 *desc;
>>>>>>>> u32 rdsta_val;
>>>>>>>> int ret = 0, sh_idx, size;
>>>>>>>> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
>>>> *)SEC_ADDR(sec_idx);
>>>>>>>> struct rng4tst __iomem *rng =
>>>>>>>> (struct rng4tst __iomem *)&sec->rng;
>>>>>>>>
>>>>>>>> @@ -554,9 +567,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk)
>>>>>>>> return ret;
>>>>>>>> }
>>>>>>>>
>>>>>>>> -static u8 get_rng_vid(uint8_t sec_idx)
>>>>>>>> +static u8 get_rng_vid(ccsr_sec_t *sec)
>>>>>>>> {
>>>>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
>>>>>>>> u8 vid;
>>>>>>>>
>>>>>>>> if (caam_get_era() < 10) { @@ -574,9 +586,8 @@ static u8
>>>>>>>> get_rng_vid(uint8_t sec_idx)
>>>>>>>> * By default, the TRNG runs for 200 clocks per sample;
>>>>>>>> * 1200 clocks per sample generates better entropy.
>>>>>>>> */
>>>>>>>> -static void kick_trng(int ent_delay, uint8_t sec_idx)
>>>>>>>> +static void kick_trng(int ent_delay, ccsr_sec_t *sec)
>>>>>>>> {
>>>>>>>> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
>>>> *)SEC_ADDR(sec_idx);
>>>>>>>> struct rng4tst __iomem *rng =
>>>>>>>> (struct rng4tst __iomem *)&sec->rng;
>>>>>>>> u32 val;
>>>>>>>> @@ -603,10 +614,9 @@ static void kick_trng(int ent_delay, uint8_t
>>>>> sec_idx)
>>>>>>>> sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
>>>>>>>> }
>>>>>>>>
>>>>>>>> -static int rng_init(uint8_t sec_idx)
>>>>>>>> +static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
>>>>>>>> {
>>>>>>>> int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
>>>>>>>> - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem
>>>> *)SEC_ADDR(sec_idx);
>>>>>>>> struct rng4tst __iomem *rng =
>>>>>>>> (struct rng4tst __iomem *)&sec->rng;
>>>>>>>> u32 inst_handles;
>>>>>>>> @@ -624,7 +634,7 @@ static int rng_init(uint8_t sec_idx)
>>>>>>>> * the TRNG parameters.
>>>>>>>> */
>>>>>>>> if (!inst_handles) {
>>>>>>>> - kick_trng(ent_delay, sec_idx);
>>>>>>>> + kick_trng(ent_delay, sec);
>>>>>>>> ent_delay += 400;
>>>>>>>> }
>>>>>>>> /*
>>>>>>>> @@ -634,7 +644,7 @@ static int rng_init(uint8_t sec_idx)
>>>>>>>> * interval, leading to a sucessful initialization of
>>>>>>>> * the RNG.
>>>>>>>> */
>>>>>>>> - ret = instantiate_rng(sec_idx, gen_sk);
>>>>>>>> + ret = instantiate_rng(sec_idx, sec, gen_sk);
>>>>>>>> } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
>>>>>>>> if (ret) {
>>>>>>>> printf("SEC%u: Failed to instantiate RNG\n",
>>>>>>>> sec_idx); @@ -646,13 +656,28 @@ static int rng_init(uint8_t
>>>>>>>> sec_idx)
>>>>>>>>
>>>>>>>> return ret;
>>>>>>>> }
>>>>>>>> -#endif
>>>>>>>> +
>>>>>>>> int sec_init_idx(uint8_t sec_idx)
>>>>>>>> {
>>>>>>>> - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
>>>>>>>> - uint32_t mcr = sec_in32(&sec->mcfgr);
>>>>>>>> int ret = 0;
>>>>>>>> -
>>>>>>>> + struct caam_regs *caam;
>>>>>>>> +#if CONFIG_IS_ENABLED(DM)
>>>>>>>> + if (!caam_dev) {
>>>>>>>> + printf("caam_jr: caam not found\n");
>>>>>>>> + return -1;
>>>>>>>> + }
>>>>>>>> + caam = dev_get_priv(caam_dev); #else
>>>>>>>> + caam_st.sec = (void *)SEC_ADDR(sec_idx);
>>>>>>>> + caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
>>>>>>>> + caam_st.jrid = 0;
>>>>>>>> + caam = &caam_st;
>>>>>>>> +#endif
>>>>>>>> + ccsr_sec_t *sec = caam->sec;
>>>>>>>> + uint32_t mcr = sec_in32(&sec->mcfgr); #if
>>>>>>>> +defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
>>>>>>>> + uint32_t jrdid_ms = 0;
>>>>>>>> +#endif
>>>>>>>> #ifdef CONFIG_FSL_CORENET
>>>>>>>> uint32_t liodnr;
>>>>>>>> uint32_t liodn_ns;
>>>>>>>> @@ -682,6 +707,11 @@ int sec_init_idx(uint8_t sec_idx)
>>>>>>>> mcr |= (1 << MCFGR_PS_SHIFT);
>>>>>>>> #endif
>>>>>>>> sec_out32(&sec->mcfgr, mcr);
>>>>>>>> +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
>>>>>>>> + jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ |
>>>>>>> JRDID_MS_PRIM_DID;
>>>>>>>> + sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms); #endif
>>>>>>>> + jr_reset();
>>>>>>>>
>>>>>>>> #ifdef CONFIG_FSL_CORENET
>>>>>>>> #ifdef CONFIG_SPL_BUILD
>>>>>>>> @@ -693,20 +723,19 @@ int sec_init_idx(uint8_t sec_idx)
>>>>>>>> liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
>>>>>>>> liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
>>>>>>>>
>>>>>>>> - liodnr = sec_in32(&sec->jrliodnr[0].ls) &
>>>>>>>> + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
>>>>>>>> ~(JRNSLIODN_MASK | JRSLIODN_MASK);
>>>>>>>> liodnr = liodnr |
>>>>>>>> (liodn_ns << JRNSLIODN_SHIFT) |
>>>>>>>> (liodn_s << JRSLIODN_SHIFT);
>>>>>>>> - sec_out32(&sec->jrliodnr[0].ls, liodnr);
>>>>>>>> + sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
>>>>>>>> #else
>>>>>>>> - liodnr = sec_in32(&sec->jrliodnr[0].ls);
>>>>>>>> + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
>>>>>>>> liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
>>>>>>>> liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
>>>>>>>> #endif
>>>>>>>> #endif
>>>>>>>> -
>>>>>>>> - ret = jr_init(sec_idx);
>>>>>>>> + ret = jr_init(sec_idx, caam);
>>>>>>>> if (ret < 0) {
>>>>>>>> printf("SEC%u: initialization failed\n", sec_idx);
>>>>>>>> return -1;
>>>>>>>> @@ -719,9 +748,9 @@ int sec_init_idx(uint8_t sec_idx)
>>>>>>>>
>>>>>>>> pamu_enable();
>>>>>>>> #endif
>>>>>>>> -#ifndef CONFIG_SPL_BUILD
>>>>>>>> - if (get_rng_vid(sec_idx) >= 4) {
>>>>>>>> - if (rng_init(sec_idx) < 0) {
>>>>>>>> +
>>>>>>>> + if (get_rng_vid(caam->sec) >= 4) {
>>>>>>>> + if (rng_init(sec_idx, caam->sec) < 0) {
>>>>>>>> printf("SEC%u: RNG instantiation failed\n", sec_idx);
>>>>>>>> return -1;
>>>>>>>> }
>>>>>>>> @@ -735,7 +764,6 @@ int sec_init_idx(uint8_t sec_idx)
>>>>>>>>
>>>>>>>> printf("SEC%u: RNG instantiated\n", sec_idx);
>>>>>>>> }
>>>>>>>> -#endif
>>>>>>>> return ret;
>>>>>>>> }
>>>>>>>>
>>>>>>>> @@ -743,3 +771,76 @@ int sec_init(void)
>>>>>>>> {
>>>>>>>> return sec_init_idx(0);
>>>>>>>> }
>>>>>>>> +
>>>>>>>> +#if CONFIG_IS_ENABLED(DM)
>>>>>>>> +static int caam_jr_ioctl(struct udevice *dev, unsigned long
>>>>>>>> +request, void *buf) {
>>>>>>>> + if (request != CAAM_JR_RUN_DESC)
>>>>>>>> + return -ENOSYS;
>>>>>>>> +
>>>>>>>> + return run_descriptor_jr(buf); }
>>>>>>>> +
>>>>>>>> +static int caam_jr_probe(struct udevice *dev) {
>>>>>>>> + struct caam_regs *caam = dev_get_priv(dev);
>>>>>>>> + fdt_addr_t addr;
>>>>>>>> + ofnode node;
>>>>>>>> + unsigned int jr_node = 0;
>>>>>>>> +
>>>>>>>> + caam_dev = dev;
>>>>>>>> +
>>>>>>>> + addr = dev_read_addr(dev);
>>>>>>>> + if (addr == FDT_ADDR_T_NONE) {
>>>>>>>> + printf("caam_jr: crypto not found\n");
>>>>>>>> + return -EINVAL;
>>>>>>>> + }
>>>>>>>> + caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
>>>>>>>> + caam->regs = (struct jr_regs *)caam->sec;
>>>>>>>> +
>>>>>>>> + /* Check for enabled job ring node */
>>>>>>>> + ofnode_for_each_subnode(node, dev_ofnode(dev)) {
>>>>>>>> + if (!ofnode_is_available(node))
>>>>>>>> + continue;
>>>>>>>> +
>>>>>>>> + jr_node = ofnode_read_u32_default(node, "reg", -1);
>>>>>>>> + if (jr_node > 0) {
>>>>>>>> + caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
>>>>>>>> + while (!(jr_node & 0x0F))
>>>>>>>> + jr_node = jr_node >> 4;
>>>>>>>> +
>>>>>>>> + caam->jrid = jr_node - 1;
>>>>>>>> + break;
>>>>>>>> + }
>>>>>>>> + }
>>>>>>>> +
>>>>>>>> + if (sec_init())
>>>>>>>> + printf("\nsec_init failed!\n");
>>>>>>>> +
>>>>>>>> + return 0;
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static int caam_jr_bind(struct udevice *dev) {
>>>>>>>> + return 0;
>>>>>>>> +}
>>>>>>>> +
>>>>>>>> +static const struct misc_ops caam_jr_ops = {
>>>>>>>> + .ioctl = caam_jr_ioctl,
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static const struct udevice_id caam_jr_match[] = {
>>>>>>>> + { .compatible = "fsl,sec-v4.0" },
>>>>>>>> + { }
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +U_BOOT_DRIVER(caam_jr) = {
>>>>>>>> + .name = "caam_jr",
>>>>>>>> + .id = UCLASS_MISC,
>>>>>>>> + .of_match = caam_jr_match,
>>>>>>>> + .ops = &caam_jr_ops,
>>>>>>>> + .bind = caam_jr_bind,
>>>>>>>> + .probe = caam_jr_probe,
>>>>>>>> + .priv_auto = sizeof(struct caam_regs),
>>>>>>>> +};
>>>>>>>> +#endif
>>>>>>>> diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
>>>>>>>> index 1047aa772c..3eb7be79da 100644
>>>>>>>> --- a/drivers/crypto/fsl/jr.h
>>>>>>>> +++ b/drivers/crypto/fsl/jr.h
>>>>>>>> @@ -1,6 +1,7 @@
>>>>>>>> /* SPDX-License-Identifier: GPL-2.0+ */
>>>>>>>> /*
>>>>>>>> * Copyright 2008-2014 Freescale Semiconductor, Inc.
>>>>>>>> + * Copyright 2021 NXP
>>>>>>>> *
>>>>>>>> */
>>>>>>>>
>>>>>>>> @@ -8,7 +9,9 @@
>>>>>>>> #define __JR_H
>>>>>>>>
>>>>>>>> #include <linux/compiler.h>
>>>>>>>> +#include "fsl_sec.h"
>>>>>>>> #include "type.h"
>>>>>>>> +#include <misc.h>
>>>>>>>>
>>>>>>>> #define JR_SIZE 4
>>>>>>>> /* Timeout currently defined as 10 sec */ @@ -35,12 +38,21 @@
>>>>>>>> #define JRSLIODN_SHIFT 0
>>>>>>>> #define JRSLIODN_MASK 0x00000fff
>>>>>>>>
>>>>>>>> -#define JQ_DEQ_ERR -1
>>>>>>>> -#define JQ_DEQ_TO_ERR -2
>>>>>>>> -#define JQ_ENQ_ERR -3
>>>>>>>> +#define JRDID_MS_PRIM_DID BIT(0)
>>>>>>>> +#define JRDID_MS_PRIM_TZ BIT(4)
>>>>>>>> +#define JRDID_MS_TZ_OWN BIT(15)
>>>>>>>> +
>>>>>>>> +#define JQ_DEQ_ERR (-1)
>>>>>>>> +#define JQ_DEQ_TO_ERR (-2)
>>>>>>>> +#define JQ_ENQ_ERR (-3)
>>>>>>>>
>>>>>>>> #define RNG4_MAX_HANDLES 2
>>>>>>>>
>>>>>>>> +enum {
>>>>>>>> + /* Run caam jobring descriptor(in buf) */
>>>>>>>> + CAAM_JR_RUN_DESC,
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> struct op_ring {
>>>>>>>> caam_dma_addr_t desc;
>>>>>>>> uint32_t status;
>>>>>>>> @@ -102,6 +114,19 @@ struct result {
>>>>>>>> uint32_t status;
>>>>>>>> };
>>>>>>>>
>>>>>>>> +/*
>>>>>>>> + * struct caam_regs - CAAM initialization register interface
>>>>>>>> + *
>>>>>>>> + * Interface to caam memory map, jobring register, jobring storage.
>>>>>>>> + */
>>>>>>>> +struct caam_regs {
>>>>>>>> + ccsr_sec_t *sec; /*caam initialization registers*/
>>>>>>>> + struct jr_regs *regs; /*jobring configuration registers*/
>>>>>>>> + u8 jrid; /*id to identify a jobring*/
>>>>>>>> + /*Private sub-storage for a single JobR*/
>>>>>>>> + struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> void caam_jr_strstatus(u32 status);
>>>>>>>> int run_descriptor_jr(uint32_t *desc);
>>>>>>>>
>>>>>>>
>>>>>>> --
>>>>>>>
>>>>>>
>>>>>
>>>>
>> =================================================================
>>>>>>> ====
>>>>>>> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
>>>>>>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
>>>>>>> Germany
>>>>>>> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email:
>>>>>>> sbabic@denx.de
>>>>>>>
>>>>>>
>>>>>
>>>>
>> =================================================================
>>>>>>> ====
>>
>>
>> --
>> =================================================================
>> ====
>> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
>> =================================================================
>> ====
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-03 15:30 ` Stefano Babic
@ 2022-03-06 19:38 ` ZHIZHIKIN Andrey
2022-03-07 14:10 ` Gaurav Jain
2022-03-07 9:58 ` Michael Walle
1 sibling, 1 reply; 69+ messages in thread
From: ZHIZHIKIN Andrey @ 2022-03-06 19:38 UTC (permalink / raw)
To: Stefano Babic, Gaurav Jain, u-boot, Marek Vasut
Cc: Fabio Estevam, Peng Fan, Simon Glass, Priyanka Jain, Ye Li,
Horia Geanta, Ji Luo, Franck Lenormand, Silvano Di Ninno,
Sahil Malhotra, Pankaj Gupta, Varun Sethi, dl-uboot-imx,
Shengzhou Liu, Mingkai Hu, Rajesh Bhagat, Meenakshi Aggarwal,
Wasim Khan, Alison Wang, Pramod Kumar, Andy Tang, Adrian Alonso,
Vladimir Oltean
Hello Stefano,
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Stefano Babic
> Sent: Thursday, March 3, 2022 4:30 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>; Stefano Babic <sbabic@denx.de>; u-
> boot@lists.denx.de; Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>;
> Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> <franck.lenormand@nxp.com>; Silvano Di Ninno <silvano.dininno@nxp.com>; Sahil
> Malhotra <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun
> Sethi <V.Sethi@nxp.com>; dl-uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
> <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat
> <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim
> Khan <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>; Adrian Alonso
> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring
> driver model
>
> Hi,
>
> On 03.03.22 14:41, Gaurav Jain wrote:
> > Hi Stefano
> >
> > As we have not received any response from imx6dl_mamoj board maintainer.
> > I propose the below solution
> >
> > --- a/arch/arm/mach-imx/Kconfig
> > +++ b/arch/arm/mach-imx/Kconfig
> > @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
> > - select FSL_CAAM if HAS_CAAM
> > - imply CMD_DEKBLOB if HAS_CAAM
> > + imply FSL_CAAM if HAS_CAAM
> > + imply CMD_DEKBLOB if FSL_CAAM
> > Help
> >
>
> IMO this is ok, I was also wrong, Marek is not the maintainer of this
> board. This was the only board with broken build - let's say, I will
> still wait a couple of days, and if there is no comments, I will apply
> your series (but then V10). I can apply this fix myself, no need to post
> the series again (I have not seen any other comment or request to change).
I had a couple of concerns which I raised in V10 without any follow-up.
Main thing is the JR reservation, which (if applied) would lead to
misconfiguration when upstream TF-A is used, see [1].
>
> Regards,
> Stefano
>
Link: [1]: https://lore.kernel.org/u-boot/AM6PR06MB4691178347827CB77F44F537A6309@AM6PR06MB4691.eurprd06.prod.outlook.com/
-- andrey
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-03 15:30 ` Stefano Babic
2022-03-06 19:38 ` ZHIZHIKIN Andrey
@ 2022-03-07 9:58 ` Michael Walle
2022-03-07 10:56 ` Gaurav Jain
1 sibling, 1 reply; 69+ messages in thread
From: Michael Walle @ 2022-03-07 9:58 UTC (permalink / raw)
To: sbabic
Cc: V.Sethi, adrian.alonso, alison.wang, andy.tang, festevam,
franck.lenormand, gaurav.jain, horia.geanta, ji.luo, marex,
meenakshi.aggarwal, mingkai.hu, olteanv, pankaj.gupta, peng.fan,
pramod.kumar_1, priyanka.jain, rajesh.bhagat, sahil.malhotra,
shengzhou.liu, silvano.dininno, sjg, u-boot, uboot-imx,
wasim.khan, ye.li, Michael Walle
> On 03.03.22 14:41, Gaurav Jain wrote:
>> As we have not received any response from imx6dl_mamoj board maintainer.
>> I propose the below solution
>>
>> --- a/arch/arm/mach-imx/Kconfig
>> +++ b/arch/arm/mach-imx/Kconfig
>> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
>> - select FSL_CAAM if HAS_CAAM
>> - imply CMD_DEKBLOB if HAS_CAAM
>> + imply FSL_CAAM if HAS_CAAM
>> + imply CMD_DEKBLOB if FSL_CAAM
>> Help
>>
>
> IMO this is ok, I was also wrong, Marek is not the maintainer of this
> board. This was the only board with broken build - let's say, I will
> still wait a couple of days, and if there is no comments, I will apply
> your series (but then V10). I can apply this fix myself, no need to post
> the series again (I have not seen any other comment or request to change).
I don't understand why the solution isn't the same one as for the
layerscape part in this series[1]: enable the config per board (that is
your boards) and leave all others the same as before?
-michael
[1] https://lore.kernel.org/u-boot/4068dc3f802dad82972c64123743fd08@walle.cc/
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-07 9:58 ` Michael Walle
@ 2022-03-07 10:56 ` Gaurav Jain
2022-03-07 11:08 ` Michael Walle
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-03-07 10:56 UTC (permalink / raw)
To: Michael Walle, sbabic
Cc: Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang, festevam,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li
> -----Original Message-----
> From: Michael Walle <michael@walle.cc>
> Sent: Monday, March 7, 2022 3:28 PM
> To: sbabic@denx.de
> Cc: Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
> Alison Wang <alison.wang@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> festevam@gmail.com; Franck Lenormand <franck.lenormand@nxp.com>;
> Gaurav Jain <gaurav.jain@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji
> Luo <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
> olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
> <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>; Priyanka
> Jain <priyanka.jain@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>; Sahil
> Malhotra <sahil.malhotra@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>; Michael Walle
> <michael@walle.cc>
> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> Caution: EXT Email
>
> > On 03.03.22 14:41, Gaurav Jain wrote:
> >> As we have not received any response from imx6dl_mamoj board maintainer.
> >> I propose the below solution
> >>
> >> --- a/arch/arm/mach-imx/Kconfig
> >> +++ b/arch/arm/mach-imx/Kconfig
> >> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
> >> - select FSL_CAAM if HAS_CAAM
> >> - imply CMD_DEKBLOB if HAS_CAAM
> >> + imply FSL_CAAM if HAS_CAAM
> >> + imply CMD_DEKBLOB if FSL_CAAM
> >> Help
> >>
> >
> > IMO this is ok, I was also wrong, Marek is not the maintainer of this
> > board. This was the only board with broken build - let's say, I will
> > still wait a couple of days, and if there is no comments, I will apply
> > your series (but then V10). I can apply this fix myself, no need to
> > post the series again (I have not seen any other comment or request to
> change).
>
> I don't understand why the solution isn't the same one as for the layerscape part
> in this series[1]: enable the config per board (that is your boards) and leave all
> others the same as before?
imx6dl_mamoj caam driver is not enabled by any of my changes.
This board is enabling IMX_HAB which select FSL_CAAM.
Proposed changes making it imply so that FSL_CAAM can be disabled in board defconfig.
Gaurav
>
> -michael
>
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kern
> el.org%2Fu-
> boot%2F4068dc3f802dad82972c64123743fd08%40walle.cc%2F&data=04%
> 7C01%7Cgaurav.jain%40nxp.com%7C998fc3ba1b384d75e58708da0021058b%7
> C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637822439101994232%7
> CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI
> 6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=u7fCKThNnSHG0ttLAzOxTo0
> SHC6kGAwDpJgUmdSDokw%3D&reserved=0
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-07 10:56 ` Gaurav Jain
@ 2022-03-07 11:08 ` Michael Walle
2022-03-07 11:33 ` Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: Michael Walle @ 2022-03-07 11:08 UTC (permalink / raw)
To: Gaurav Jain
Cc: sbabic, Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
festevam, Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li
Am 2022-03-07 11:56, schrieb Gaurav Jain:
>> -----Original Message-----
>> From: Michael Walle <michael@walle.cc>
>> Sent: Monday, March 7, 2022 3:28 PM
>> To: sbabic@denx.de
>> Cc: Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
>> <adrian.alonso@nxp.com>;
>> Alison Wang <alison.wang@nxp.com>; Andy Tang <andy.tang@nxp.com>;
>> festevam@gmail.com; Franck Lenormand <franck.lenormand@nxp.com>;
>> Gaurav Jain <gaurav.jain@nxp.com>; Horia Geanta
>> <horia.geanta@nxp.com>; Ji
>> Luo <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
>> <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
>> olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
>> <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>; Priyanka
>> Jain <priyanka.jain@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
>> Sahil
>> Malhotra <sahil.malhotra@nxp.com>; Shengzhou Liu
>> <shengzhou.liu@nxp.com>;
>> Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
>> boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
>> <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>; Michael Walle
>> <michael@walle.cc>
>> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
>> CAAM Job
>> ring driver model
>>
>> Caution: EXT Email
>>
>> > On 03.03.22 14:41, Gaurav Jain wrote:
>> >> As we have not received any response from imx6dl_mamoj board maintainer.
>> >> I propose the below solution
>> >>
>> >> --- a/arch/arm/mach-imx/Kconfig
>> >> +++ b/arch/arm/mach-imx/Kconfig
>> >> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
>> >> - select FSL_CAAM if HAS_CAAM
>> >> - imply CMD_DEKBLOB if HAS_CAAM
>> >> + imply FSL_CAAM if HAS_CAAM
>> >> + imply CMD_DEKBLOB if FSL_CAAM
>> >> Help
>> >>
>> >
>> > IMO this is ok, I was also wrong, Marek is not the maintainer of this
>> > board. This was the only board with broken build - let's say, I will
>> > still wait a couple of days, and if there is no comments, I will apply
>> > your series (but then V10). I can apply this fix myself, no need to
>> > post the series again (I have not seen any other comment or request to
>> change).
>>
>> I don't understand why the solution isn't the same one as for the
>> layerscape part
>> in this series[1]: enable the config per board (that is your boards)
>> and leave all
>> others the same as before?
>
> imx6dl_mamoj caam driver is not enabled by any of my changes.
> This board is enabling IMX_HAB which select FSL_CAAM.
> Proposed changes making it imply so that FSL_CAAM can be disabled in
> board defconfig.
Ahh it was already selected before. But mhh, does IMX_HAB even
makes sense without FSL_CAAM? Why was is a hard dependency
before?
-michael
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-07 11:08 ` Michael Walle
@ 2022-03-07 11:33 ` Gaurav Jain
2022-03-07 11:41 ` Michael Walle
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-03-07 11:33 UTC (permalink / raw)
To: Michael Walle
Cc: sbabic, Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
festevam, Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li
> -----Original Message-----
> From: Michael Walle <michael@walle.cc>
> Sent: Monday, March 7, 2022 4:39 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>
> Cc: sbabic@denx.de; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy Tang
> <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
> <franck.lenormand@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
> olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
> <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>; Priyanka
> Jain <priyanka.jain@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>; Sahil
> Malhotra <sahil.malhotra@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>
> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> Caution: EXT Email
>
> Am 2022-03-07 11:56, schrieb Gaurav Jain:
> >> -----Original Message-----
> >> From: Michael Walle <michael@walle.cc>
> >> Sent: Monday, March 7, 2022 3:28 PM
> >> To: sbabic@denx.de
> >> Cc: Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> >> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy
> Tang
> >> <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
> >> <franck.lenormand@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>; Horia
> >> Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>;
> >> marex@denx.de; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> >> Mingkai Hu <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> >> <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> >> <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>;
> >> Rajesh Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra
> >> <sahil.malhotra@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> >> Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> >> boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
> >> <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>; Michael Walle
> >> <michael@walle.cc>
> >> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> >> CAAM Job ring driver model
> >>
> >> Caution: EXT Email
> >>
> >> > On 03.03.22 14:41, Gaurav Jain wrote:
> >> >> As we have not received any response from imx6dl_mamoj board
> maintainer.
> >> >> I propose the below solution
> >> >>
> >> >> --- a/arch/arm/mach-imx/Kconfig
> >> >> +++ b/arch/arm/mach-imx/Kconfig
> >> >> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
> >> >> - select FSL_CAAM if HAS_CAAM
> >> >> - imply CMD_DEKBLOB if HAS_CAAM
> >> >> + imply FSL_CAAM if HAS_CAAM
> >> >> + imply CMD_DEKBLOB if FSL_CAAM
> >> >> Help
> >> >>
> >> >
> >> > IMO this is ok, I was also wrong, Marek is not the maintainer of
> >> > this board. This was the only board with broken build - let's say,
> >> > I will still wait a couple of days, and if there is no comments, I
> >> > will apply your series (but then V10). I can apply this fix myself,
> >> > no need to post the series again (I have not seen any other comment
> >> > or request to
> >> change).
> >>
> >> I don't understand why the solution isn't the same one as for the
> >> layerscape part in this series[1]: enable the config per board (that
> >> is your boards) and leave all others the same as before?
> >
> > imx6dl_mamoj caam driver is not enabled by any of my changes.
> > This board is enabling IMX_HAB which select FSL_CAAM.
> > Proposed changes making it imply so that FSL_CAAM can be disabled in
> > board defconfig.
>
> Ahh it was already selected before. But mhh, does IMX_HAB even makes sense
> without FSL_CAAM? Why was is a hard dependency before?
With imply, this will still enable FSL_CAAM unless it is explicitly disabled in defconfig. With select I do not have choice of disabling FSL_CAAM in defconfig. Now I have disabled FSL_CAAM only for imx6dl_mamoj_defconfig, as it is reporting spl size issues with caam driver model approach.
Gaurav
>
> -michael
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-07 11:33 ` Gaurav Jain
@ 2022-03-07 11:41 ` Michael Walle
2022-03-07 12:03 ` Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: Michael Walle @ 2022-03-07 11:41 UTC (permalink / raw)
To: Gaurav Jain
Cc: sbabic, Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
festevam, Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li
Am 2022-03-07 12:33, schrieb Gaurav Jain:
>> -----Original Message-----
>> From: Michael Walle <michael@walle.cc>
>> Sent: Monday, March 7, 2022 4:39 PM
>> To: Gaurav Jain <gaurav.jain@nxp.com>
>> Cc: sbabic@denx.de; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
>> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy Tang
>> <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
>> <franck.lenormand@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji
>> Luo
>> <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
>> <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
>> olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
>> <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>; Priyanka
>> Jain <priyanka.jain@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
>> Sahil
>> Malhotra <sahil.malhotra@nxp.com>; Shengzhou Liu
>> <shengzhou.liu@nxp.com>;
>> Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
>> boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
>> <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>
>> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
>> CAAM Job
>> ring driver model
>>
>> Caution: EXT Email
>>
>> Am 2022-03-07 11:56, schrieb Gaurav Jain:
>> >> -----Original Message-----
>> >> From: Michael Walle <michael@walle.cc>
>> >> Sent: Monday, March 7, 2022 3:28 PM
>> >> To: sbabic@denx.de
>> >> Cc: Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
>> >> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy
>> Tang
>> >> <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
>> >> <franck.lenormand@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>; Horia
>> >> Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>;
>> >> marex@denx.de; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
>> >> Mingkai Hu <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
>> >> <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
>> >> <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>;
>> >> Rajesh Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra
>> >> <sahil.malhotra@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
>> >> Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
>> >> boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
>> >> <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>; Michael Walle
>> >> <michael@walle.cc>
>> >> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
>> >> CAAM Job ring driver model
>> >>
>> >> Caution: EXT Email
>> >>
>> >> > On 03.03.22 14:41, Gaurav Jain wrote:
>> >> >> As we have not received any response from imx6dl_mamoj board
>> maintainer.
>> >> >> I propose the below solution
>> >> >>
>> >> >> --- a/arch/arm/mach-imx/Kconfig
>> >> >> +++ b/arch/arm/mach-imx/Kconfig
>> >> >> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
>> >> >> - select FSL_CAAM if HAS_CAAM
>> >> >> - imply CMD_DEKBLOB if HAS_CAAM
>> >> >> + imply FSL_CAAM if HAS_CAAM
>> >> >> + imply CMD_DEKBLOB if FSL_CAAM
>> >> >> Help
>> >> >>
>> >> >
>> >> > IMO this is ok, I was also wrong, Marek is not the maintainer of
>> >> > this board. This was the only board with broken build - let's say,
>> >> > I will still wait a couple of days, and if there is no comments, I
>> >> > will apply your series (but then V10). I can apply this fix myself,
>> >> > no need to post the series again (I have not seen any other comment
>> >> > or request to
>> >> change).
>> >>
>> >> I don't understand why the solution isn't the same one as for the
>> >> layerscape part in this series[1]: enable the config per board (that
>> >> is your boards) and leave all others the same as before?
>> >
>> > imx6dl_mamoj caam driver is not enabled by any of my changes.
>> > This board is enabling IMX_HAB which select FSL_CAAM.
>> > Proposed changes making it imply so that FSL_CAAM can be disabled in
>> > board defconfig.
>>
>> Ahh it was already selected before. But mhh, does IMX_HAB even makes
>> sense
>> without FSL_CAAM? Why was is a hard dependency before?
>
> With imply, this will still enable FSL_CAAM unless it is explicitly
> disabled in defconfig. With select I do not have choice of disabling
> FSL_CAAM in defconfig. Now I have disabled FSL_CAAM only for
> imx6dl_mamoj_defconfig, as it is reporting spl size issues with caam
> driver model approach.
I can see *what* you are doing, but that doesn't answer *why* it was
a hard dependency before and why now of a sudden can be a soft
dependency.
-michael
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-07 11:41 ` Michael Walle
@ 2022-03-07 12:03 ` Gaurav Jain
2022-03-07 15:15 ` Tom Rini
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-03-07 12:03 UTC (permalink / raw)
To: Michael Walle
Cc: sbabic, Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
festevam, Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li
> -----Original Message-----
> From: Michael Walle <michael@walle.cc>
> Sent: Monday, March 7, 2022 5:12 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>
> Cc: sbabic@denx.de; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy Tang
> <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
> <franck.lenormand@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
> olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
> <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>; Priyanka
> Jain <priyanka.jain@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>; Sahil
> Malhotra <sahil.malhotra@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>
> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> Caution: EXT Email
>
> Am 2022-03-07 12:33, schrieb Gaurav Jain:
> >> -----Original Message-----
> >> From: Michael Walle <michael@walle.cc>
> >> Sent: Monday, March 7, 2022 4:39 PM
> >> To: Gaurav Jain <gaurav.jain@nxp.com>
> >> Cc: sbabic@denx.de; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> >> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy
> Tang
> >> <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
> >> <franck.lenormand@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji
> >> Luo <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
> >> <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
> >> olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
> >> <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>;
> Priyanka
> >> Jain <priyanka.jain@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> >> Sahil Malhotra <sahil.malhotra@nxp.com>; Shengzhou Liu
> >> <shengzhou.liu@nxp.com>; Silvano Di Ninno <silvano.dininno@nxp.com>;
> >> sjg@chromium.org; u- boot@lists.denx.de; dl-uboot-imx
> >> <uboot-imx@nxp.com>; Wasim Khan <wasim.khan@nxp.com>; Ye Li
> >> <ye.li@nxp.com>
> >> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> >> CAAM Job ring driver model
> >>
> >> Caution: EXT Email
> >>
> >> Am 2022-03-07 11:56, schrieb Gaurav Jain:
> >> >> -----Original Message-----
> >> >> From: Michael Walle <michael@walle.cc>
> >> >> Sent: Monday, March 7, 2022 3:28 PM
> >> >> To: sbabic@denx.de
> >> >> Cc: Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> >> >> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy
> >> Tang
> >> >> <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
> >> >> <franck.lenormand@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>;
> >> >> Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>;
> >> >> marex@denx.de; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> >> >> Mingkai Hu <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> >> >> <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod
> Kumar
> >> >> <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>;
> >> >> Rajesh Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra
> >> >> <sahil.malhotra@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> >> >> Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> >> >> boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
> >> >> <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>; Michael Walle
> >> >> <michael@walle.cc>
> >> >> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support
> >> >> for CAAM Job ring driver model
> >> >>
> >> >> Caution: EXT Email
> >> >>
> >> >> > On 03.03.22 14:41, Gaurav Jain wrote:
> >> >> >> As we have not received any response from imx6dl_mamoj board
> >> maintainer.
> >> >> >> I propose the below solution
> >> >> >>
> >> >> >> --- a/arch/arm/mach-imx/Kconfig
> >> >> >> +++ b/arch/arm/mach-imx/Kconfig
> >> >> >> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
> >> >> >> - select FSL_CAAM if HAS_CAAM
> >> >> >> - imply CMD_DEKBLOB if HAS_CAAM
> >> >> >> + imply FSL_CAAM if HAS_CAAM
> >> >> >> + imply CMD_DEKBLOB if FSL_CAAM
> >> >> >> Help
> >> >> >>
> >> >> >
> >> >> > IMO this is ok, I was also wrong, Marek is not the maintainer of
> >> >> > this board. This was the only board with broken build - let's
> >> >> > say, I will still wait a couple of days, and if there is no
> >> >> > comments, I will apply your series (but then V10). I can apply
> >> >> > this fix myself, no need to post the series again (I have not
> >> >> > seen any other comment or request to
> >> >> change).
> >> >>
> >> >> I don't understand why the solution isn't the same one as for the
> >> >> layerscape part in this series[1]: enable the config per board
> >> >> (that is your boards) and leave all others the same as before?
> >> >
> >> > imx6dl_mamoj caam driver is not enabled by any of my changes.
> >> > This board is enabling IMX_HAB which select FSL_CAAM.
> >> > Proposed changes making it imply so that FSL_CAAM can be disabled
> >> > in board defconfig.
> >>
> >> Ahh it was already selected before. But mhh, does IMX_HAB even makes
> >> sense without FSL_CAAM? Why was is a hard dependency before?
> >
> > With imply, this will still enable FSL_CAAM unless it is explicitly
> > disabled in defconfig. With select I do not have choice of disabling
> > FSL_CAAM in defconfig. Now I have disabled FSL_CAAM only for
> > imx6dl_mamoj_defconfig, as it is reporting spl size issues with caam
> > driver model approach.
>
> I can see *what* you are doing, but that doesn't answer *why* it was a hard
> dependency before and why now of a sudden can be a soft dependency.
I am not sure of any other dependency, but from the code ./arch/arm/mach-imx/cmd_dek.c needs caam for blob_encap_dek operation for mx6, mx7, mx7ulp.
Making it soft dependency allows me to disable caam for imx6dl_mamoj.
Gaurav
>
> -michael
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-06 19:38 ` ZHIZHIKIN Andrey
@ 2022-03-07 14:10 ` Gaurav Jain
2022-03-07 15:42 ` ZHIZHIKIN Andrey
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-03-07 14:10 UTC (permalink / raw)
To: ZHIZHIKIN Andrey, Stefano Babic, u-boot, Marek Vasut
Cc: Fabio Estevam, Peng Fan, Simon Glass, Priyanka Jain, Ye Li,
Horia Geanta, Ji Luo, Franck Lenormand, Silvano Di Ninno,
Sahil Malhotra, Pankaj Gupta, Varun Sethi, dl-uboot-imx,
Shengzhou Liu, Mingkai Hu, Rajesh Bhagat, Meenakshi Aggarwal,
Wasim Khan, Alison Wang, Pramod Kumar, Andy Tang, Adrian Alonso,
Vladimir Oltean
Hello Andrey
> -----Original Message-----
> From: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>
> Sent: Monday, March 7, 2022 1:08 AM
> To: Stefano Babic <sbabic@denx.de>; Gaurav Jain <gaurav.jain@nxp.com>; u-
> boot@lists.denx.de; Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> Simon Glass <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye
> Li <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> Caution: EXT Email
>
> Hello Stefano,
>
> > -----Original Message-----
> > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Stefano Babic
> > Sent: Thursday, March 3, 2022 4:30 PM
> > To: Gaurav Jain <gaurav.jain@nxp.com>; Stefano Babic <sbabic@denx.de>;
> > u- boot@lists.denx.de; Marek Vasut <marex@denx.de>
> > Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> > Simon Glass <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>;
> > Ye Li <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> > <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano
> > Di Ninno <silvano.dininno@nxp.com>; Sahil Malhotra
> > <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun
> > Sethi <V.Sethi@nxp.com>; dl-uboot-imx <uboot-imx@nxp.com>; Shengzhou
> > Liu <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh
> > Bhagat <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal
> > <meenakshi.aggarwal@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> Alison
> > Wang <alison.wang@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>;
> > Andy Tang <andy.tang@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
> > Vladimir Oltean <olteanv@gmail.com>
> > Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> > CAAM Job ring driver model
> >
> > Hi,
> >
> > On 03.03.22 14:41, Gaurav Jain wrote:
> > > Hi Stefano
> > >
> > > As we have not received any response from imx6dl_mamoj board maintainer.
> > > I propose the below solution
> > >
> > > --- a/arch/arm/mach-imx/Kconfig
> > > +++ b/arch/arm/mach-imx/Kconfig
> > > @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
> > > - select FSL_CAAM if HAS_CAAM
> > > - imply CMD_DEKBLOB if HAS_CAAM
> > > + imply FSL_CAAM if HAS_CAAM
> > > + imply CMD_DEKBLOB if FSL_CAAM
> > > Help
> > >
> >
> > IMO this is ok, I was also wrong, Marek is not the maintainer of this
> > board. This was the only board with broken build - let's say, I will
> > still wait a couple of days, and if there is no comments, I will apply
> > your series (but then V10). I can apply this fix myself, no need to
> > post the series again (I have not seen any other comment or request to
> change).
>
> I had a couple of concerns which I raised in V10 without any follow-up.
>
> Main thing is the JR reservation, which (if applied) would lead to
> misconfiguration when upstream TF-A is used, see [1].
>
> >
> > Regards,
> > Stefano
> >
>
> Link: [1]:
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kern
> el.org%2Fu-
> boot%2FAM6PR06MB4691178347827CB77F44F537A6309%40AM6PR06MB4691
> .eurprd06.prod.outlook.com%2F&data=04%7C01%7Cgaurav.jain%40nxp.c
> om%7C87775d9291044d6aad3808d9ffa8db17%7C686ea1d3bc2b4c6fa92cd99c5
> c301635%7C0%7C0%7C637821922977072803%7CUnknown%7CTWFpbGZsb3d8
> eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> 7C3000&sdata=3Gng6vVpNKyV8xNLSEuwG%2F7DEVDjSnYh5iYi47wvyvc%3
> D&reserved=0
Ok, I will follow the approach suggested by you. First a patch will be submitted to ATF and then the one for uboot will follow.
Will send a V11 after removing the JR0 reservation code. Any other concern?
Gaurav
>
> -- andrey
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-07 12:03 ` Gaurav Jain
@ 2022-03-07 15:15 ` Tom Rini
2022-03-08 11:10 ` Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: Tom Rini @ 2022-03-07 15:15 UTC (permalink / raw)
To: Gaurav Jain
Cc: Michael Walle, sbabic, Varun Sethi, Adrian Alonso, Alison Wang,
Andy Tang, festevam, Franck Lenormand, Horia Geanta, Ji Luo,
marex, Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta,
Peng Fan, Pramod Kumar, Priyanka Jain, Rajesh Bhagat,
Sahil Malhotra, Shengzhou Liu, Silvano Di Ninno, sjg, u-boot,
dl-uboot-imx, Wasim Khan, Ye Li
[-- Attachment #1: Type: text/plain, Size: 6889 bytes --]
On Mon, Mar 07, 2022 at 12:03:42PM +0000, Gaurav Jain wrote:
>
>
> > -----Original Message-----
> > From: Michael Walle <michael@walle.cc>
> > Sent: Monday, March 7, 2022 5:12 PM
> > To: Gaurav Jain <gaurav.jain@nxp.com>
> > Cc: sbabic@denx.de; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> > <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy Tang
> > <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
> > <franck.lenormand@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> > <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
> > <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
> > olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
> > <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>; Priyanka
> > Jain <priyanka.jain@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>; Sahil
> > Malhotra <sahil.malhotra@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> > Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> > boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
> > <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>
> > Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> > ring driver model
> >
> > Caution: EXT Email
> >
> > Am 2022-03-07 12:33, schrieb Gaurav Jain:
> > >> -----Original Message-----
> > >> From: Michael Walle <michael@walle.cc>
> > >> Sent: Monday, March 7, 2022 4:39 PM
> > >> To: Gaurav Jain <gaurav.jain@nxp.com>
> > >> Cc: sbabic@denx.de; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> > >> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy
> > Tang
> > >> <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
> > >> <franck.lenormand@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji
> > >> Luo <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
> > >> <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
> > >> olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
> > >> <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>;
> > Priyanka
> > >> Jain <priyanka.jain@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> > >> Sahil Malhotra <sahil.malhotra@nxp.com>; Shengzhou Liu
> > >> <shengzhou.liu@nxp.com>; Silvano Di Ninno <silvano.dininno@nxp.com>;
> > >> sjg@chromium.org; u- boot@lists.denx.de; dl-uboot-imx
> > >> <uboot-imx@nxp.com>; Wasim Khan <wasim.khan@nxp.com>; Ye Li
> > >> <ye.li@nxp.com>
> > >> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> > >> CAAM Job ring driver model
> > >>
> > >> Caution: EXT Email
> > >>
> > >> Am 2022-03-07 11:56, schrieb Gaurav Jain:
> > >> >> -----Original Message-----
> > >> >> From: Michael Walle <michael@walle.cc>
> > >> >> Sent: Monday, March 7, 2022 3:28 PM
> > >> >> To: sbabic@denx.de
> > >> >> Cc: Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> > >> >> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy
> > >> Tang
> > >> >> <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
> > >> >> <franck.lenormand@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>;
> > >> >> Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>;
> > >> >> marex@denx.de; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > >> >> Mingkai Hu <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> > >> >> <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod
> > Kumar
> > >> >> <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>;
> > >> >> Rajesh Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra
> > >> >> <sahil.malhotra@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> > >> >> Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> > >> >> boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
> > >> >> <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>; Michael Walle
> > >> >> <michael@walle.cc>
> > >> >> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support
> > >> >> for CAAM Job ring driver model
> > >> >>
> > >> >> Caution: EXT Email
> > >> >>
> > >> >> > On 03.03.22 14:41, Gaurav Jain wrote:
> > >> >> >> As we have not received any response from imx6dl_mamoj board
> > >> maintainer.
> > >> >> >> I propose the below solution
> > >> >> >>
> > >> >> >> --- a/arch/arm/mach-imx/Kconfig
> > >> >> >> +++ b/arch/arm/mach-imx/Kconfig
> > >> >> >> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config IMX_HAB
> > >> >> >> - select FSL_CAAM if HAS_CAAM
> > >> >> >> - imply CMD_DEKBLOB if HAS_CAAM
> > >> >> >> + imply FSL_CAAM if HAS_CAAM
> > >> >> >> + imply CMD_DEKBLOB if FSL_CAAM
> > >> >> >> Help
> > >> >> >>
> > >> >> >
> > >> >> > IMO this is ok, I was also wrong, Marek is not the maintainer of
> > >> >> > this board. This was the only board with broken build - let's
> > >> >> > say, I will still wait a couple of days, and if there is no
> > >> >> > comments, I will apply your series (but then V10). I can apply
> > >> >> > this fix myself, no need to post the series again (I have not
> > >> >> > seen any other comment or request to
> > >> >> change).
> > >> >>
> > >> >> I don't understand why the solution isn't the same one as for the
> > >> >> layerscape part in this series[1]: enable the config per board
> > >> >> (that is your boards) and leave all others the same as before?
> > >> >
> > >> > imx6dl_mamoj caam driver is not enabled by any of my changes.
> > >> > This board is enabling IMX_HAB which select FSL_CAAM.
> > >> > Proposed changes making it imply so that FSL_CAAM can be disabled
> > >> > in board defconfig.
> > >>
> > >> Ahh it was already selected before. But mhh, does IMX_HAB even makes
> > >> sense without FSL_CAAM? Why was is a hard dependency before?
> > >
> > > With imply, this will still enable FSL_CAAM unless it is explicitly
> > > disabled in defconfig. With select I do not have choice of disabling
> > > FSL_CAAM in defconfig. Now I have disabled FSL_CAAM only for
> > > imx6dl_mamoj_defconfig, as it is reporting spl size issues with caam
> > > driver model approach.
> >
> > I can see *what* you are doing, but that doesn't answer *why* it was a hard
> > dependency before and why now of a sudden can be a soft dependency.
>
> I am not sure of any other dependency, but from the code ./arch/arm/mach-imx/cmd_dek.c needs caam for blob_encap_dek operation for mx6, mx7, mx7ulp.
> Making it soft dependency allows me to disable caam for imx6dl_mamoj.
Yes, but can you reasonably, functionally, do that? Or are you just
making things link but now the platform is non functional? Nothing
that's an actual shell cmd should be linked in / included in the SPL
binary (it should get discarded if built), but my recollection from
migrating the HAB/CAAM symbols to Kconfig is that functionally you can't
do what you're trying to do.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-07 14:10 ` Gaurav Jain
@ 2022-03-07 15:42 ` ZHIZHIKIN Andrey
0 siblings, 0 replies; 69+ messages in thread
From: ZHIZHIKIN Andrey @ 2022-03-07 15:42 UTC (permalink / raw)
To: Gaurav Jain, Stefano Babic, u-boot, Marek Vasut
Cc: Fabio Estevam, Peng Fan, Simon Glass, Priyanka Jain, Ye Li,
Horia Geanta, Ji Luo, Franck Lenormand, Silvano Di Ninno,
Sahil Malhotra, Pankaj Gupta, Varun Sethi, dl-uboot-imx,
Shengzhou Liu, Mingkai Hu, Rajesh Bhagat, Meenakshi Aggarwal,
Wasim Khan, Alison Wang, Pramod Kumar, Andy Tang, Adrian Alonso,
Vladimir Oltean
Hello Gaurav,
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Gaurav Jain
> Sent: Monday, March 7, 2022 3:10 PM
> To: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>; Stefano Babic
> <sbabic@denx.de>; u-boot@lists.denx.de; Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>; Simon Glass
> <sjg@chromium.org>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li <ye.li@nxp.com>;
> Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; Franck Lenormand
> <franck.lenormand@nxp.com>; Silvano Di Ninno <silvano.dininno@nxp.com>; Sahil
> Malhotra <sahil.malhotra@nxp.com>; Pankaj Gupta <pankaj.gupta@nxp.com>; Varun
> Sethi <V.Sethi@nxp.com>; dl-uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu
> <shengzhou.liu@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat
> <rajesh.bhagat@nxp.com>; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim
> Khan <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>; Adrian Alonso
> <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring
> driver model
>
> Hello Andrey
>
>
> Ok, I will follow the approach suggested by you. First a patch will be submitted
> to ATF and then the one for uboot will follow.
Perfect, thanks a lot for following it up here!
> Will send a V11 after removing the JR0 reservation code. Any other concern?
Besides the one above, I have no further concerns on the series.
>
> Gaurav
>
> >
-- andrey
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-07 15:15 ` Tom Rini
@ 2022-03-08 11:10 ` Gaurav Jain
2022-03-08 11:12 ` Fabio Estevam
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-03-08 11:10 UTC (permalink / raw)
To: Tom Rini
Cc: Michael Walle, sbabic, Varun Sethi, Adrian Alonso, Alison Wang,
Andy Tang, festevam, Franck Lenormand, Horia Geanta, Ji Luo,
marex, Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta,
Peng Fan, Pramod Kumar, Priyanka Jain, Rajesh Bhagat,
Sahil Malhotra, Shengzhou Liu, Silvano Di Ninno, sjg, u-boot,
dl-uboot-imx, Wasim Khan, Ye Li
Hi Tom
> -----Original Message-----
> From: Tom Rini <trini@konsulko.com>
> Sent: Monday, March 7, 2022 8:46 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>
> Cc: Michael Walle <michael@walle.cc>; sbabic@denx.de; Varun Sethi
> <V.Sethi@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>; Alison Wang
> <alison.wang@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> festevam@gmail.com; Franck Lenormand <franck.lenormand@nxp.com>; Horia
> Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; marex@denx.de;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Rajesh
> Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Shengzhou Liu <shengzhou.liu@nxp.com>; Silvano Di Ninno
> <silvano.dininno@nxp.com>; sjg@chromium.org; u-boot@lists.denx.de; dl-
> uboot-imx <uboot-imx@nxp.com>; Wasim Khan <wasim.khan@nxp.com>; Ye Li
> <ye.li@nxp.com>
> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> On Mon, Mar 07, 2022 at 12:03:42PM +0000, Gaurav Jain wrote:
> >
> >
> > > -----Original Message-----
> > > From: Michael Walle <michael@walle.cc>
> > > Sent: Monday, March 7, 2022 5:12 PM
> > > To: Gaurav Jain <gaurav.jain@nxp.com>
> > > Cc: sbabic@denx.de; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> > > <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy
> > > Tang <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
> > > <franck.lenormand@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji
> > > Luo <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
> > > <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
> > > olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
> > > <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>;
> Priyanka
> > > Jain <priyanka.jain@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> > > Sahil Malhotra <sahil.malhotra@nxp.com>; Shengzhou Liu
> > > <shengzhou.liu@nxp.com>; Silvano Di Ninno <silvano.dininno@nxp.com>;
> > > sjg@chromium.org; u- boot@lists.denx.de; dl-uboot-imx
> > > <uboot-imx@nxp.com>; Wasim Khan <wasim.khan@nxp.com>; Ye Li
> > > <ye.li@nxp.com>
> > > Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> > > CAAM Job ring driver model
> > >
> > > Caution: EXT Email
> > >
> > > Am 2022-03-07 12:33, schrieb Gaurav Jain:
> > > >> -----Original Message-----
> > > >> From: Michael Walle <michael@walle.cc>
> > > >> Sent: Monday, March 7, 2022 4:39 PM
> > > >> To: Gaurav Jain <gaurav.jain@nxp.com>
> > > >> Cc: sbabic@denx.de; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> > > >> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy
> > > Tang
> > > >> <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
> > > >> <franck.lenormand@nxp.com>; Horia Geanta <horia.geanta@nxp.com>;
> > > >> Ji Luo <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
> > > >> <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
> > > >> olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
> > > >> <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>;
> > > Priyanka
> > > >> Jain <priyanka.jain@nxp.com>; Rajesh Bhagat
> > > >> <rajesh.bhagat@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> > > >> Shengzhou Liu <shengzhou.liu@nxp.com>; Silvano Di Ninno
> > > >> <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> > > >> boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
> > > >> <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>
> > > >> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support
> > > >> for CAAM Job ring driver model
> > > >>
> > > >> Caution: EXT Email
> > > >>
> > > >> Am 2022-03-07 11:56, schrieb Gaurav Jain:
> > > >> >> -----Original Message-----
> > > >> >> From: Michael Walle <michael@walle.cc>
> > > >> >> Sent: Monday, March 7, 2022 3:28 PM
> > > >> >> To: sbabic@denx.de
> > > >> >> Cc: Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> > > >> >> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>;
> > > >> >> Andy
> > > >> Tang
> > > >> >> <andy.tang@nxp.com>; festevam@gmail.com; Franck Lenormand
> > > >> >> <franck.lenormand@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>;
> > > >> >> Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>;
> > > >> >> marex@denx.de; Meenakshi Aggarwal
> > > >> >> <meenakshi.aggarwal@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>;
> > > >> >> olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng
> > > >> >> Fan <peng.fan@nxp.com>; Pramod
> > > Kumar
> > > >> >> <pramod.kumar_1@nxp.com>; Priyanka Jain
> > > >> >> <priyanka.jain@nxp.com>; Rajesh Bhagat
> > > >> >> <rajesh.bhagat@nxp.com>; Sahil Malhotra
> > > >> >> <sahil.malhotra@nxp.com>; Shengzhou Liu
> > > >> >> <shengzhou.liu@nxp.com>; Silvano Di Ninno
> > > >> >> <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> > > >> >> boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim
> > > >> >> Khan <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>; Michael
> > > >> >> Walle <michael@walle.cc>
> > > >> >> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add
> > > >> >> support for CAAM Job ring driver model
> > > >> >>
> > > >> >> Caution: EXT Email
> > > >> >>
> > > >> >> > On 03.03.22 14:41, Gaurav Jain wrote:
> > > >> >> >> As we have not received any response from imx6dl_mamoj
> > > >> >> >> board
> > > >> maintainer.
> > > >> >> >> I propose the below solution
> > > >> >> >>
> > > >> >> >> --- a/arch/arm/mach-imx/Kconfig
> > > >> >> >> +++ b/arch/arm/mach-imx/Kconfig
> > > >> >> >> @@ -49,8 +49,8 @@ config USE_IMXIMG_PLUGIN config
> IMX_HAB
> > > >> >> >> - select FSL_CAAM if HAS_CAAM
> > > >> >> >> - imply CMD_DEKBLOB if HAS_CAAM
> > > >> >> >> + imply FSL_CAAM if HAS_CAAM
> > > >> >> >> + imply CMD_DEKBLOB if FSL_CAAM
> > > >> >> >> Help
> > > >> >> >>
> > > >> >> >
> > > >> >> > IMO this is ok, I was also wrong, Marek is not the
> > > >> >> > maintainer of this board. This was the only board with
> > > >> >> > broken build - let's say, I will still wait a couple of
> > > >> >> > days, and if there is no comments, I will apply your series
> > > >> >> > (but then V10). I can apply this fix myself, no need to post
> > > >> >> > the series again (I have not seen any other comment or
> > > >> >> > request to
> > > >> >> change).
> > > >> >>
> > > >> >> I don't understand why the solution isn't the same one as for
> > > >> >> the layerscape part in this series[1]: enable the config per
> > > >> >> board (that is your boards) and leave all others the same as before?
> > > >> >
> > > >> > imx6dl_mamoj caam driver is not enabled by any of my changes.
> > > >> > This board is enabling IMX_HAB which select FSL_CAAM.
> > > >> > Proposed changes making it imply so that FSL_CAAM can be
> > > >> > disabled in board defconfig.
> > > >>
> > > >> Ahh it was already selected before. But mhh, does IMX_HAB even
> > > >> makes sense without FSL_CAAM? Why was is a hard dependency before?
> > > >
> > > > With imply, this will still enable FSL_CAAM unless it is
> > > > explicitly disabled in defconfig. With select I do not have choice
> > > > of disabling FSL_CAAM in defconfig. Now I have disabled FSL_CAAM
> > > > only for imx6dl_mamoj_defconfig, as it is reporting spl size
> > > > issues with caam driver model approach.
> > >
> > > I can see *what* you are doing, but that doesn't answer *why* it was
> > > a hard dependency before and why now of a sudden can be a soft
> dependency.
> >
> > I am not sure of any other dependency, but from the code ./arch/arm/mach-
> imx/cmd_dek.c needs caam for blob_encap_dek operation for mx6, mx7,
> mx7ulp.
> > Making it soft dependency allows me to disable caam for imx6dl_mamoj.
>
> Yes, but can you reasonably, functionally, do that? Or are you just making things
> link but now the platform is non functional? Nothing that's an actual shell cmd
> should be linked in / included in the SPL binary (it should get discarded if built),
> but my recollection from migrating the HAB/CAAM symbols to Kconfig is that
> functionally you can't do what you're trying to do.
>
I further checked on your concern and propose the below change to stop building caam driver in SPL for imx6dl_mamoj.
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -61,3 +61,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SPL_CRYPTO=n
Gaurav
> --
> Tom
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-08 11:10 ` Gaurav Jain
@ 2022-03-08 11:12 ` Fabio Estevam
2022-03-08 11:17 ` Gaurav Jain
2022-03-08 12:48 ` Tom Rini
0 siblings, 2 replies; 69+ messages in thread
From: Fabio Estevam @ 2022-03-08 11:12 UTC (permalink / raw)
To: Gaurav Jain
Cc: Tom Rini, Michael Walle, sbabic, Varun Sethi, Adrian Alonso,
Alison Wang, Andy Tang, Franck Lenormand, Horia Geanta, Ji Luo,
marex, Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta,
Peng Fan, Pramod Kumar, Priyanka Jain, Rajesh Bhagat,
Sahil Malhotra, Shengzhou Liu, Silvano Di Ninno, sjg, u-boot,
dl-uboot-imx, Wasim Khan, Ye Li
On Tue, Mar 8, 2022 at 8:10 AM Gaurav Jain <gaurav.jain@nxp.com> wrote:
> I further checked on your concern and propose the below change to stop building caam driver in SPL for imx6dl_mamoj.
>
> --- a/configs/imx6dl_mamoj_defconfig
> +++ b/configs/imx6dl_mamoj_defconfig
> @@ -61,3 +61,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> CONFIG_CI_UDC=y
> +CONFIG_SPL_CRYPTO=n
No, this is not how defconfig works.
You should set:
# CONFIG_SPL_CRYPTO is not set
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-08 11:12 ` Fabio Estevam
@ 2022-03-08 11:17 ` Gaurav Jain
2022-03-08 12:48 ` Tom Rini
1 sibling, 0 replies; 69+ messages in thread
From: Gaurav Jain @ 2022-03-08 11:17 UTC (permalink / raw)
To: Fabio Estevam
Cc: Tom Rini, Michael Walle, sbabic, Varun Sethi, Adrian Alonso,
Alison Wang, Andy Tang, Franck Lenormand, Horia Geanta, Ji Luo,
marex, Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta,
Peng Fan, Pramod Kumar, Priyanka Jain, Rajesh Bhagat,
Sahil Malhotra, Shengzhou Liu, Silvano Di Ninno, sjg, u-boot,
dl-uboot-imx, Wasim Khan, Ye Li
> -----Original Message-----
> From: Fabio Estevam <festevam@gmail.com>
> Sent: Tuesday, March 8, 2022 4:42 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>
> Cc: Tom Rini <trini@konsulko.com>; Michael Walle <michael@walle.cc>;
> sbabic@denx.de; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy Tang
> <andy.tang@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>;
> Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>;
> marex@denx.de; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Rajesh
> Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Shengzhou Liu <shengzhou.liu@nxp.com>; Silvano Di Ninno
> <silvano.dininno@nxp.com>; sjg@chromium.org; u-boot@lists.denx.de; dl-
> uboot-imx <uboot-imx@nxp.com>; Wasim Khan <wasim.khan@nxp.com>; Ye Li
> <ye.li@nxp.com>
> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> Caution: EXT Email
>
> On Tue, Mar 8, 2022 at 8:10 AM Gaurav Jain <gaurav.jain@nxp.com> wrote:
>
> > I further checked on your concern and propose the below change to stop
> building caam driver in SPL for imx6dl_mamoj.
> >
> > --- a/configs/imx6dl_mamoj_defconfig
> > +++ b/configs/imx6dl_mamoj_defconfig
> > @@ -61,3 +61,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> > CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> > CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> > CONFIG_CI_UDC=y
> > +CONFIG_SPL_CRYPTO=n
>
> No, this is not how defconfig works.
>
> You should set:
>
> # CONFIG_SPL_CRYPTO is not set
Ok. Noted.
Gaurav
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-08 11:12 ` Fabio Estevam
2022-03-08 11:17 ` Gaurav Jain
@ 2022-03-08 12:48 ` Tom Rini
2022-03-08 13:21 ` Gaurav Jain
2022-03-08 13:28 ` Stefano Babic
1 sibling, 2 replies; 69+ messages in thread
From: Tom Rini @ 2022-03-08 12:48 UTC (permalink / raw)
To: Fabio Estevam
Cc: Gaurav Jain, Michael Walle, sbabic, Varun Sethi, Adrian Alonso,
Alison Wang, Andy Tang, Franck Lenormand, Horia Geanta, Ji Luo,
marex, Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta,
Peng Fan, Pramod Kumar, Priyanka Jain, Rajesh Bhagat,
Sahil Malhotra, Shengzhou Liu, Silvano Di Ninno, sjg, u-boot,
dl-uboot-imx, Wasim Khan, Ye Li
[-- Attachment #1: Type: text/plain, Size: 957 bytes --]
On Tue, Mar 08, 2022 at 08:12:27AM -0300, Fabio Estevam wrote:
> On Tue, Mar 8, 2022 at 8:10 AM Gaurav Jain <gaurav.jain@nxp.com> wrote:
>
> > I further checked on your concern and propose the below change to stop building caam driver in SPL for imx6dl_mamoj.
> >
> > --- a/configs/imx6dl_mamoj_defconfig
> > +++ b/configs/imx6dl_mamoj_defconfig
> > @@ -61,3 +61,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> > CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> > CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> > CONFIG_CI_UDC=y
> > +CONFIG_SPL_CRYPTO=n
>
> No, this is not how defconfig works.
>
> You should set:
>
> # CONFIG_SPL_CRYPTO is not set
But more, WHY is this the right answer? You're disabling functionality
and the board maintainers aren't even on the CC list for this thread it
looks like. Why are you not fixing the board so it still links? What
makes this board a problem that other (I assume) imx6dl boards are not?
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-08 12:48 ` Tom Rini
@ 2022-03-08 13:21 ` Gaurav Jain
2022-03-08 13:29 ` Tom Rini
2022-03-08 13:28 ` Stefano Babic
1 sibling, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-03-08 13:21 UTC (permalink / raw)
To: Tom Rini, Fabio Estevam, jagan, Raffaele RECALCATI, Simone CIANNI
Cc: Michael Walle, sbabic, Varun Sethi, Adrian Alonso, Alison Wang,
Andy Tang, Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li
> -----Original Message-----
> From: Tom Rini <trini@konsulko.com>
> Sent: Tuesday, March 8, 2022 6:19 PM
> To: Fabio Estevam <festevam@gmail.com>
> Cc: Gaurav Jain <gaurav.jain@nxp.com>; Michael Walle <michael@walle.cc>;
> sbabic@denx.de; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy Tang
> <andy.tang@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>;
> Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>;
> marex@denx.de; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Rajesh
> Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Shengzhou Liu <shengzhou.liu@nxp.com>; Silvano Di Ninno
> <silvano.dininno@nxp.com>; sjg@chromium.org; u-boot@lists.denx.de; dl-
> uboot-imx <uboot-imx@nxp.com>; Wasim Khan <wasim.khan@nxp.com>; Ye Li
> <ye.li@nxp.com>
> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> On Tue, Mar 08, 2022 at 08:12:27AM -0300, Fabio Estevam wrote:
> > On Tue, Mar 8, 2022 at 8:10 AM Gaurav Jain <gaurav.jain@nxp.com> wrote:
> >
> > > I further checked on your concern and propose the below change to stop
> building caam driver in SPL for imx6dl_mamoj.
> > >
> > > --- a/configs/imx6dl_mamoj_defconfig
> > > +++ b/configs/imx6dl_mamoj_defconfig
> > > @@ -61,3 +61,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> > > CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> > > CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> > > CONFIG_CI_UDC=y
> > > +CONFIG_SPL_CRYPTO=n
> >
> > No, this is not how defconfig works.
> >
> > You should set:
> >
> > # CONFIG_SPL_CRYPTO is not set
>
> But more, WHY is this the right answer? You're disabling functionality and the
> board maintainers aren't even on the CC list for this thread it looks like. Why are
> you not fixing the board so it still links? What makes this board a problem that
> other (I assume) imx6dl boards are not?
>
SPL exceeds the maximum size for only imx6dl_mamoj.
spl/u-boot-spl.bin exceeds file size limit:
limit: 0xefa0 bytes
actual: 0x1004d bytes
excess: 0x10ad bytes
on further checking I see that caam is not initialized in SPL but only built.
So disabling the build for caam driver in SPL should not be a problem.
(Added Jagan, Raffaele, Simone as board maintainer.)
Gaurav
> --
> Tom
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-08 12:48 ` Tom Rini
2022-03-08 13:21 ` Gaurav Jain
@ 2022-03-08 13:28 ` Stefano Babic
2022-03-08 13:34 ` Michael Nazzareno Trimarchi
1 sibling, 1 reply; 69+ messages in thread
From: Stefano Babic @ 2022-03-08 13:28 UTC (permalink / raw)
To: Tom Rini, Fabio Estevam
Cc: Gaurav Jain, Michael Walle, sbabic, Varun Sethi, Adrian Alonso,
Alison Wang, Andy Tang, Franck Lenormand, Horia Geanta, Ji Luo,
marex, Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta,
Peng Fan, Pramod Kumar, Priyanka Jain, Rajesh Bhagat,
Sahil Malhotra, Shengzhou Liu, Silvano Di Ninno, sjg, u-boot,
dl-uboot-imx, Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
Hi Tom,
On 08.03.22 13:48, Tom Rini wrote:
> On Tue, Mar 08, 2022 at 08:12:27AM -0300, Fabio Estevam wrote:
>> On Tue, Mar 8, 2022 at 8:10 AM Gaurav Jain <gaurav.jain@nxp.com> wrote:
>>
>>> I further checked on your concern and propose the below change to stop building caam driver in SPL for imx6dl_mamoj.
>>>
>>> --- a/configs/imx6dl_mamoj_defconfig
>>> +++ b/configs/imx6dl_mamoj_defconfig
>>> @@ -61,3 +61,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
>>> CONFIG_USB_GADGET_VENDOR_NUM=0x0525
>>> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
>>> CONFIG_CI_UDC=y
>>> +CONFIG_SPL_CRYPTO=n
>>
>> No, this is not how defconfig works.
>>
>> You should set:
>>
>> # CONFIG_SPL_CRYPTO is not set
>
> But more, WHY is this the right answer? You're disabling functionality
> and the board maintainers aren't even on the CC list for this thread it
> looks like.
This was my blocking point, too, for this series. There is no answer
about the board.
I can just imagine (as for other MX6DL) that the required functionality
is secure boot, then CONFIG_IMX_HAB is enough. But well, just the board
maintainers can say. Added Raffaele and Jagan as reported maintainers
for this board.
> Why are you not fixing the board so it still links? What
> makes this board a problem that other (I assume) imx6dl boards are not?
Well, this board has, compared to other MX6DL, a lot of SPL_ option that
are bloating the SPL size. And then does not match anymore with the
internal RAm, while other MX6DL boards are not so affected by the
increased size because they have no SPL at all or SPL with less options
and then smaller. We do not need to fix the link, but reduce the size,
and nobody else than the maintainers can tell us if removing some
feature is ok.
Regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-08 13:21 ` Gaurav Jain
@ 2022-03-08 13:29 ` Tom Rini
0 siblings, 0 replies; 69+ messages in thread
From: Tom Rini @ 2022-03-08 13:29 UTC (permalink / raw)
To: Gaurav Jain
Cc: Fabio Estevam, jagan, Raffaele RECALCATI, Simone CIANNI,
Michael Walle, sbabic, Varun Sethi, Adrian Alonso, Alison Wang,
Andy Tang, Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li
[-- Attachment #1: Type: text/plain, Size: 2994 bytes --]
On Tue, Mar 08, 2022 at 01:21:41PM +0000, Gaurav Jain wrote:
>
>
> > -----Original Message-----
> > From: Tom Rini <trini@konsulko.com>
> > Sent: Tuesday, March 8, 2022 6:19 PM
> > To: Fabio Estevam <festevam@gmail.com>
> > Cc: Gaurav Jain <gaurav.jain@nxp.com>; Michael Walle <michael@walle.cc>;
> > sbabic@denx.de; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> > <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy Tang
> > <andy.tang@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>;
> > Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>;
> > marex@denx.de; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > Mingkai Hu <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> > <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> > <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Rajesh
> > Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> > Shengzhou Liu <shengzhou.liu@nxp.com>; Silvano Di Ninno
> > <silvano.dininno@nxp.com>; sjg@chromium.org; u-boot@lists.denx.de; dl-
> > uboot-imx <uboot-imx@nxp.com>; Wasim Khan <wasim.khan@nxp.com>; Ye Li
> > <ye.li@nxp.com>
> > Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> > ring driver model
> >
> > On Tue, Mar 08, 2022 at 08:12:27AM -0300, Fabio Estevam wrote:
> > > On Tue, Mar 8, 2022 at 8:10 AM Gaurav Jain <gaurav.jain@nxp.com> wrote:
> > >
> > > > I further checked on your concern and propose the below change to stop
> > building caam driver in SPL for imx6dl_mamoj.
> > > >
> > > > --- a/configs/imx6dl_mamoj_defconfig
> > > > +++ b/configs/imx6dl_mamoj_defconfig
> > > > @@ -61,3 +61,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> > > > CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> > > > CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> > > > CONFIG_CI_UDC=y
> > > > +CONFIG_SPL_CRYPTO=n
> > >
> > > No, this is not how defconfig works.
> > >
> > > You should set:
> > >
> > > # CONFIG_SPL_CRYPTO is not set
> >
> > But more, WHY is this the right answer? You're disabling functionality and the
> > board maintainers aren't even on the CC list for this thread it looks like. Why are
> > you not fixing the board so it still links? What makes this board a problem that
> > other (I assume) imx6dl boards are not?
> >
> SPL exceeds the maximum size for only imx6dl_mamoj.
> spl/u-boot-spl.bin exceeds file size limit:
> limit: 0xefa0 bytes
> actual: 0x1004d bytes
> excess: 0x10ad bytes
>
> on further checking I see that caam is not initialized in SPL but only built.
> So disabling the build for caam driver in SPL should not be a problem.
>
> (Added Jagan, Raffaele, Simone as board maintainer.)
That's a lot of growth, what's going on? And is the CAAM being built
but not initialized a generic issue with imx6 platforms? That seems
like something to further understand, and hopefully the board
maintainers can chime in here soon.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-08 13:28 ` Stefano Babic
@ 2022-03-08 13:34 ` Michael Nazzareno Trimarchi
2022-03-14 5:47 ` Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-03-08 13:34 UTC (permalink / raw)
To: Stefano Babic
Cc: Tom Rini, Fabio Estevam, Gaurav Jain, Michael Walle, Varun Sethi,
Adrian Alonso, Alison Wang, Andy Tang, Franck Lenormand,
Horia Geanta, Ji Luo, marex, Meenakshi Aggarwal, Mingkai Hu,
olteanv, Pankaj Gupta, Peng Fan, Pramod Kumar, Priyanka Jain,
Rajesh Bhagat, Sahil Malhotra, Shengzhou Liu, Silvano Di Ninno,
sjg, u-boot, dl-uboot-imx, Wasim Khan, Ye Li, Raffaele RECALCATI,
Jagan Teki
Hi
On Tue, Mar 8, 2022 at 2:28 PM Stefano Babic <sbabic@denx.de> wrote:
>
> Hi Tom,
>
> On 08.03.22 13:48, Tom Rini wrote:
> > On Tue, Mar 08, 2022 at 08:12:27AM -0300, Fabio Estevam wrote:
> >> On Tue, Mar 8, 2022 at 8:10 AM Gaurav Jain <gaurav.jain@nxp.com> wrote:
> >>
> >>> I further checked on your concern and propose the below change to stop building caam driver in SPL for imx6dl_mamoj.
> >>>
> >>> --- a/configs/imx6dl_mamoj_defconfig
> >>> +++ b/configs/imx6dl_mamoj_defconfig
> >>> @@ -61,3 +61,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> >>> CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> >>> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> >>> CONFIG_CI_UDC=y
> >>> +CONFIG_SPL_CRYPTO=n
> >>
> >> No, this is not how defconfig works.
> >>
> >> You should set:
> >>
> >> # CONFIG_SPL_CRYPTO is not set
> >
> > But more, WHY is this the right answer? You're disabling functionality
> > and the board maintainers aren't even on the CC list for this thread it
> > looks like.
>
> This was my blocking point, too, for this series. There is no answer
> about the board.
>
> I can just imagine (as for other MX6DL) that the required functionality
> is secure boot, then CONFIG_IMX_HAB is enough. But well, just the board
> maintainers can say. Added Raffaele and Jagan as reported maintainers
> for this board.
>
> > Why are you not fixing the board so it still links? What
> > makes this board a problem that other (I assume) imx6dl boards are not?
>
> Well, this board has, compared to other MX6DL, a lot of SPL_ option that
> are bloating the SPL size. And then does not match anymore with the
> internal RAm, while other MX6DL boards are not so affected by the
> increased size because they have no SPL at all or SPL with less options
> and then smaller. We do not need to fix the link, but reduce the size,
> and nobody else than the maintainers can tell us if removing some
> feature is ok.
>
I will test this week, and try to find a board here to test
* Jagan * Do you have a momoj?
Michael
> Regards,
> Stefano
>
> --
> =====================================================================
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
> =====================================================================
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-08 13:34 ` Michael Nazzareno Trimarchi
@ 2022-03-14 5:47 ` Gaurav Jain
2022-03-17 12:10 ` Gaurav Jain
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-03-14 5:47 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi, Stefano Babic
Cc: Tom Rini, Fabio Estevam, Michael Walle, Varun Sethi,
Adrian Alonso, Alison Wang, Andy Tang, Franck Lenormand,
Horia Geanta, Ji Luo, marex, Meenakshi Aggarwal, Mingkai Hu,
olteanv, Pankaj Gupta, Peng Fan, Pramod Kumar, Priyanka Jain,
Rajesh Bhagat, Sahil Malhotra, Shengzhou Liu, Silvano Di Ninno,
sjg, u-boot, dl-uboot-imx, Wasim Khan, Ye Li, Raffaele RECALCATI,
Jagan Teki
Hi Michael
> -----Original Message-----
> From: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
> Sent: Tuesday, March 8, 2022 7:05 PM
> To: Stefano Babic <sbabic@denx.de>
> Cc: Tom Rini <trini@konsulko.com>; Fabio Estevam <festevam@gmail.com>;
> Gaurav Jain <gaurav.jain@nxp.com>; Michael Walle <michael@walle.cc>;
> Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
> Alison Wang <alison.wang@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Franck Lenormand <franck.lenormand@nxp.com>; Horia Geanta
> <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; marex@denx.de;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>;
> Rajesh Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra
> <sahil.malhotra@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>; Raffaele RECALCATI
> <raffaele.recalcati@bticino.it>; Jagan Teki <jagan@amarulasolutions.com>
> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> Caution: EXT Email
>
> Hi
>
> On Tue, Mar 8, 2022 at 2:28 PM Stefano Babic <sbabic@denx.de> wrote:
> >
> > Hi Tom,
> >
> > On 08.03.22 13:48, Tom Rini wrote:
> > > On Tue, Mar 08, 2022 at 08:12:27AM -0300, Fabio Estevam wrote:
> > >> On Tue, Mar 8, 2022 at 8:10 AM Gaurav Jain <gaurav.jain@nxp.com>
> wrote:
> > >>
> > >>> I further checked on your concern and propose the below change to
> stop building caam driver in SPL for imx6dl_mamoj.
> > >>>
> > >>> --- a/configs/imx6dl_mamoj_defconfig
> > >>> +++ b/configs/imx6dl_mamoj_defconfig
> > >>> @@ -61,3 +61,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> > >>> CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> > >>> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> > >>> CONFIG_CI_UDC=y
> > >>> +CONFIG_SPL_CRYPTO=n
> > >>
> > >> No, this is not how defconfig works.
> > >>
> > >> You should set:
> > >>
> > >> # CONFIG_SPL_CRYPTO is not set
> > >
> > > But more, WHY is this the right answer? You're disabling
> > > functionality and the board maintainers aren't even on the CC list
> > > for this thread it looks like.
> >
> > This was my blocking point, too, for this series. There is no answer
> > about the board.
> >
> > I can just imagine (as for other MX6DL) that the required
> > functionality is secure boot, then CONFIG_IMX_HAB is enough. But well,
> > just the board maintainers can say. Added Raffaele and Jagan as
> > reported maintainers for this board.
> >
> > > Why are you not fixing the board so it still links? What makes
> > > this board a problem that other (I assume) imx6dl boards are not?
> >
> > Well, this board has, compared to other MX6DL, a lot of SPL_ option
> > that are bloating the SPL size. And then does not match anymore with
> > the internal RAm, while other MX6DL boards are not so affected by the
> > increased size because they have no SPL at all or SPL with less
> > options and then smaller. We do not need to fix the link, but reduce
> > the size, and nobody else than the maintainers can tell us if removing
> > some feature is ok.
> >
>
> I will test this week, and try to find a board here to test
>
> * Jagan * Do you have a momoj?
Have you tested mamoj board?
Regards
Gaurav
>
> Michael
>
> > Regards,
> > Stefano
> >
> > --
> >
> ================================================================
> =====
> > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
> >
> ================================================================
> =====
>
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> michael@amarulasolutions.com
> __________________________________
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172
> info@amarulasolutions.com
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.a
> marulasolutions.com%2F&data=04%7C01%7Cgaurav.jain%40nxp.com%
> 7C843e57f75346449f13ae08da010867b6%7C686ea1d3bc2b4c6fa92cd99c5c3
> 01635%7C0%7C0%7C637823432854617357%7CUnknown%7CTWFpbGZsb3d8
> eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> D%7C3000&sdata=f025HmlIM8FuTEYspDjwOevTT1k7JRZeIiS%2FpTH2hc
> Y%3D&reserved=0
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-14 5:47 ` Gaurav Jain
@ 2022-03-17 12:10 ` Gaurav Jain
2022-03-19 9:47 ` Michael Nazzareno Trimarchi
0 siblings, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-03-17 12:10 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi, Stefano Babic
Cc: Tom Rini, Fabio Estevam, Michael Walle, Varun Sethi,
Adrian Alonso, Alison Wang, Andy Tang, Franck Lenormand,
Horia Geanta, Ji Luo, marex, Meenakshi Aggarwal, Mingkai Hu,
olteanv, Pankaj Gupta, Peng Fan, Pramod Kumar, Priyanka Jain,
Rajesh Bhagat, Sahil Malhotra, Shengzhou Liu, Silvano Di Ninno,
sjg, u-boot, dl-uboot-imx, Wasim Khan, Ye Li, Raffaele RECALCATI,
Jagan Teki
Hello Michael
A gentle reminder!!
As you said earlier, can you test the mamoj board with proposed solution to fix SPL size issue.
Regards
Gaurav Jain
> -----Original Message-----
> From: Gaurav Jain
> Sent: Monday, March 14, 2022 11:18 AM
> To: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>; Stefano
> Babic <sbabic@denx.de>
> Cc: Tom Rini <trini@konsulko.com>; Fabio Estevam <festevam@gmail.com>;
> Michael Walle <michael@walle.cc>; Varun Sethi <V.Sethi@nxp.com>; Adrian
> Alonso <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>;
> Andy Tang <andy.tang@nxp.com>; Franck Lenormand
> <franck.lenormand@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji
> Luo <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
> olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
> <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>;
> Priyanka Jain <priyanka.jain@nxp.com>; Rajesh Bhagat
> <rajesh.bhagat@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Shengzhou Liu <shengzhou.liu@nxp.com>; Silvano Di Ninno
> <silvano.dininno@nxp.com>; sjg@chromium.org; u-boot@lists.denx.de; dl-
> uboot-imx <uboot-imx@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> Ye Li <ye.li@nxp.com>; Raffaele RECALCATI <raffaele.recalcati@bticino.it>;
> Jagan Teki <jagan@amarulasolutions.com>
> Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> Hi Michael
>
> > -----Original Message-----
> > From: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
> > Sent: Tuesday, March 8, 2022 7:05 PM
> > To: Stefano Babic <sbabic@denx.de>
> > Cc: Tom Rini <trini@konsulko.com>; Fabio Estevam
> <festevam@gmail.com>;
> > Gaurav Jain <gaurav.jain@nxp.com>; Michael Walle <michael@walle.cc>;
> > Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
> > Alison Wang <alison.wang@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> > Franck Lenormand <franck.lenormand@nxp.com>; Horia Geanta
> > <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; marex@denx.de;
> > Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Mingkai Hu
> > <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> > <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> > <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>;
> > Rajesh Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra
> > <sahil.malhotra@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> > Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> > boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
> > <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>; Raffaele RECALCATI
> > <raffaele.recalcati@bticino.it>; Jagan Teki
> > <jagan@amarulasolutions.com>
> > Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> > CAAM Job ring driver model
> >
> > Caution: EXT Email
> >
> > Hi
> >
> > On Tue, Mar 8, 2022 at 2:28 PM Stefano Babic <sbabic@denx.de> wrote:
> > >
> > > Hi Tom,
> > >
> > > On 08.03.22 13:48, Tom Rini wrote:
> > > > On Tue, Mar 08, 2022 at 08:12:27AM -0300, Fabio Estevam wrote:
> > > >> On Tue, Mar 8, 2022 at 8:10 AM Gaurav Jain <gaurav.jain@nxp.com>
> > wrote:
> > > >>
> > > >>> I further checked on your concern and propose the below change
> > > >>> to
> > stop building caam driver in SPL for imx6dl_mamoj.
> > > >>>
> > > >>> --- a/configs/imx6dl_mamoj_defconfig
> > > >>> +++ b/configs/imx6dl_mamoj_defconfig
> > > >>> @@ -61,3 +61,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> > > >>> CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> > > >>> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> > > >>> CONFIG_CI_UDC=y
> > > >>> +CONFIG_SPL_CRYPTO=n
> > > >>
> > > >> No, this is not how defconfig works.
> > > >>
> > > >> You should set:
> > > >>
> > > >> # CONFIG_SPL_CRYPTO is not set
> > > >
> > > > But more, WHY is this the right answer? You're disabling
> > > > functionality and the board maintainers aren't even on the CC list
> > > > for this thread it looks like.
> > >
> > > This was my blocking point, too, for this series. There is no answer
> > > about the board.
> > >
> > > I can just imagine (as for other MX6DL) that the required
> > > functionality is secure boot, then CONFIG_IMX_HAB is enough. But
> > > well, just the board maintainers can say. Added Raffaele and Jagan
> > > as reported maintainers for this board.
> > >
> > > > Why are you not fixing the board so it still links? What makes
> > > > this board a problem that other (I assume) imx6dl boards are not?
> > >
> > > Well, this board has, compared to other MX6DL, a lot of SPL_ option
> > > that are bloating the SPL size. And then does not match anymore with
> > > the internal RAm, while other MX6DL boards are not so affected by
> > > the increased size because they have no SPL at all or SPL with less
> > > options and then smaller. We do not need to fix the link, but reduce
> > > the size, and nobody else than the maintainers can tell us if
> > > removing some feature is ok.
> > >
> >
> > I will test this week, and try to find a board here to test
> >
> > * Jagan * Do you have a momoj?
>
> Have you tested mamoj board?
>
> Regards
> Gaurav
> >
> > Michael
> >
> > > Regards,
> > > Stefano
> > >
> > > --
> > >
> >
> ================================================================
> > =====
> > > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> > > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany
> > > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email:
> > > sbabic@denx.de
> > >
> >
> ================================================================
> > =====
> >
> >
> >
> > --
> > Michael Nazzareno Trimarchi
> > Co-Founder & Chief Executive Officer
> > M. +39 347 913 2170
> > michael@amarulasolutions.com
> > __________________________________
> >
> > Amarula Solutions BV
> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172
> > info@amarulasolutions.com
> >
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.a
> > marulasolutions.com%2F&data=04%7C01%7Cgaurav.jain%40nxp.com%
> >
> 7C843e57f75346449f13ae08da010867b6%7C686ea1d3bc2b4c6fa92cd99c5c3
> >
> 01635%7C0%7C0%7C637823432854617357%7CUnknown%7CTWFpbGZsb3d8
> >
> eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> >
> D%7C3000&sdata=f025HmlIM8FuTEYspDjwOevTT1k7JRZeIiS%2FpTH2hc
> > Y%3D&reserved=0
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-17 12:10 ` Gaurav Jain
@ 2022-03-19 9:47 ` Michael Nazzareno Trimarchi
2022-03-19 10:32 ` Michael Nazzareno Trimarchi
2022-03-19 13:24 ` Fabio Estevam
0 siblings, 2 replies; 69+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-03-19 9:47 UTC (permalink / raw)
To: Gaurav Jain
Cc: Stefano Babic, Tom Rini, Fabio Estevam, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
HI
Please send me a link to apply your series
Michael
On Thu, Mar 17, 2022 at 1:10 PM Gaurav Jain <gaurav.jain@nxp.com> wrote:
>
> Hello Michael
>
> A gentle reminder!!
> As you said earlier, can you test the mamoj board with proposed solution to fix SPL size issue.
>
> Regards
> Gaurav Jain
>
> > -----Original Message-----
> > From: Gaurav Jain
> > Sent: Monday, March 14, 2022 11:18 AM
> > To: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>; Stefano
> > Babic <sbabic@denx.de>
> > Cc: Tom Rini <trini@konsulko.com>; Fabio Estevam <festevam@gmail.com>;
> > Michael Walle <michael@walle.cc>; Varun Sethi <V.Sethi@nxp.com>; Adrian
> > Alonso <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>;
> > Andy Tang <andy.tang@nxp.com>; Franck Lenormand
> > <franck.lenormand@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji
> > Luo <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
> > <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
> > olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
> > <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>;
> > Priyanka Jain <priyanka.jain@nxp.com>; Rajesh Bhagat
> > <rajesh.bhagat@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> > Shengzhou Liu <shengzhou.liu@nxp.com>; Silvano Di Ninno
> > <silvano.dininno@nxp.com>; sjg@chromium.org; u-boot@lists.denx.de; dl-
> > uboot-imx <uboot-imx@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> > Ye Li <ye.li@nxp.com>; Raffaele RECALCATI <raffaele.recalcati@bticino.it>;
> > Jagan Teki <jagan@amarulasolutions.com>
> > Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> > ring driver model
> >
> > Hi Michael
> >
> > > -----Original Message-----
> > > From: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
> > > Sent: Tuesday, March 8, 2022 7:05 PM
> > > To: Stefano Babic <sbabic@denx.de>
> > > Cc: Tom Rini <trini@konsulko.com>; Fabio Estevam
> > <festevam@gmail.com>;
> > > Gaurav Jain <gaurav.jain@nxp.com>; Michael Walle <michael@walle.cc>;
> > > Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
> > > Alison Wang <alison.wang@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> > > Franck Lenormand <franck.lenormand@nxp.com>; Horia Geanta
> > > <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; marex@denx.de;
> > > Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Mingkai Hu
> > > <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> > > <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> > > <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>;
> > > Rajesh Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra
> > > <sahil.malhotra@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> > > Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> > > boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
> > > <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>; Raffaele RECALCATI
> > > <raffaele.recalcati@bticino.it>; Jagan Teki
> > > <jagan@amarulasolutions.com>
> > > Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> > > CAAM Job ring driver model
> > >
> > > Caution: EXT Email
> > >
> > > Hi
> > >
> > > On Tue, Mar 8, 2022 at 2:28 PM Stefano Babic <sbabic@denx.de> wrote:
> > > >
> > > > Hi Tom,
> > > >
> > > > On 08.03.22 13:48, Tom Rini wrote:
> > > > > On Tue, Mar 08, 2022 at 08:12:27AM -0300, Fabio Estevam wrote:
> > > > >> On Tue, Mar 8, 2022 at 8:10 AM Gaurav Jain <gaurav.jain@nxp.com>
> > > wrote:
> > > > >>
> > > > >>> I further checked on your concern and propose the below change
> > > > >>> to
> > > stop building caam driver in SPL for imx6dl_mamoj.
> > > > >>>
> > > > >>> --- a/configs/imx6dl_mamoj_defconfig
> > > > >>> +++ b/configs/imx6dl_mamoj_defconfig
> > > > >>> @@ -61,3 +61,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> > > > >>> CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> > > > >>> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> > > > >>> CONFIG_CI_UDC=y
> > > > >>> +CONFIG_SPL_CRYPTO=n
> > > > >>
> > > > >> No, this is not how defconfig works.
> > > > >>
> > > > >> You should set:
> > > > >>
> > > > >> # CONFIG_SPL_CRYPTO is not set
> > > > >
> > > > > But more, WHY is this the right answer? You're disabling
> > > > > functionality and the board maintainers aren't even on the CC list
> > > > > for this thread it looks like.
> > > >
> > > > This was my blocking point, too, for this series. There is no answer
> > > > about the board.
> > > >
> > > > I can just imagine (as for other MX6DL) that the required
> > > > functionality is secure boot, then CONFIG_IMX_HAB is enough. But
> > > > well, just the board maintainers can say. Added Raffaele and Jagan
> > > > as reported maintainers for this board.
> > > >
> > > > > Why are you not fixing the board so it still links? What makes
> > > > > this board a problem that other (I assume) imx6dl boards are not?
> > > >
> > > > Well, this board has, compared to other MX6DL, a lot of SPL_ option
> > > > that are bloating the SPL size. And then does not match anymore with
> > > > the internal RAm, while other MX6DL boards are not so affected by
> > > > the increased size because they have no SPL at all or SPL with less
> > > > options and then smaller. We do not need to fix the link, but reduce
> > > > the size, and nobody else than the maintainers can tell us if
> > > > removing some feature is ok.
> > > >
> > >
> > > I will test this week, and try to find a board here to test
> > >
> > > * Jagan * Do you have a momoj?
> >
> > Have you tested mamoj board?
> >
> > Regards
> > Gaurav
> > >
> > > Michael
> > >
> > > > Regards,
> > > > Stefano
> > > >
> > > > --
> > > >
> > >
> > ================================================================
> > > =====
> > > > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> > > > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > > Germany
> > > > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email:
> > > > sbabic@denx.de
> > > >
> > >
> > ================================================================
> > > =====
> > >
> > >
> > >
> > > --
> > > Michael Nazzareno Trimarchi
> > > Co-Founder & Chief Executive Officer
> > > M. +39 347 913 2170
> > > michael@amarulasolutions.com
> > > __________________________________
> > >
> > > Amarula Solutions BV
> > > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172
> > > info@amarulasolutions.com
> > >
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.a
> > > marulasolutions.com%2F&data=04%7C01%7Cgaurav.jain%40nxp.com%
> > >
> > 7C843e57f75346449f13ae08da010867b6%7C686ea1d3bc2b4c6fa92cd99c5c3
> > >
> > 01635%7C0%7C0%7C637823432854617357%7CUnknown%7CTWFpbGZsb3d8
> > >
> > eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> > >
> > D%7C3000&sdata=f025HmlIM8FuTEYspDjwOevTT1k7JRZeIiS%2FpTH2hc
> > > Y%3D&reserved=0
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 9:47 ` Michael Nazzareno Trimarchi
@ 2022-03-19 10:32 ` Michael Nazzareno Trimarchi
2022-03-19 13:24 ` Fabio Estevam
1 sibling, 0 replies; 69+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-03-19 10:32 UTC (permalink / raw)
To: Gaurav Jain
Cc: Stefano Babic, Tom Rini, Fabio Estevam, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
Hi Gaurav
On Sat, Mar 19, 2022 at 10:47 AM Michael Nazzareno Trimarchi
<michael@amarulasolutions.com> wrote:
>
> HI
>
> Please send me a link to apply your series
>
> Michael
>
> On Thu, Mar 17, 2022 at 1:10 PM Gaurav Jain <gaurav.jain@nxp.com> wrote:
> >
> > Hello Michael
> >
> > A gentle reminder!!
> > As you said earlier, can you test the mamoj board with proposed solution to fix SPL size issue.
> >
> > Regards
> > Gaurav Jain
> >
> > > -----Original Message-----
> > > From: Gaurav Jain
> > > Sent: Monday, March 14, 2022 11:18 AM
> > > To: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>; Stefano
> > > Babic <sbabic@denx.de>
> > > Cc: Tom Rini <trini@konsulko.com>; Fabio Estevam <festevam@gmail.com>;
> > > Michael Walle <michael@walle.cc>; Varun Sethi <V.Sethi@nxp.com>; Adrian
> > > Alonso <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>;
> > > Andy Tang <andy.tang@nxp.com>; Franck Lenormand
> > > <franck.lenormand@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji
> > > Luo <ji.luo@nxp.com>; marex@denx.de; Meenakshi Aggarwal
> > > <meenakshi.aggarwal@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;
> > > olteanv@gmail.com; Pankaj Gupta <pankaj.gupta@nxp.com>; Peng Fan
> > > <peng.fan@nxp.com>; Pramod Kumar <pramod.kumar_1@nxp.com>;
> > > Priyanka Jain <priyanka.jain@nxp.com>; Rajesh Bhagat
> > > <rajesh.bhagat@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> > > Shengzhou Liu <shengzhou.liu@nxp.com>; Silvano Di Ninno
> > > <silvano.dininno@nxp.com>; sjg@chromium.org; u-boot@lists.denx.de; dl-
> > > uboot-imx <uboot-imx@nxp.com>; Wasim Khan <wasim.khan@nxp.com>;
> > > Ye Li <ye.li@nxp.com>; Raffaele RECALCATI <raffaele.recalcati@bticino.it>;
> > > Jagan Teki <jagan@amarulasolutions.com>
> > > Subject: RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> > > ring driver model
> > >
> > > Hi Michael
> > >
> > > > -----Original Message-----
> > > > From: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
> > > > Sent: Tuesday, March 8, 2022 7:05 PM
> > > > To: Stefano Babic <sbabic@denx.de>
> > > > Cc: Tom Rini <trini@konsulko.com>; Fabio Estevam
> > > <festevam@gmail.com>;
> > > > Gaurav Jain <gaurav.jain@nxp.com>; Michael Walle <michael@walle.cc>;
> > > > Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso <adrian.alonso@nxp.com>;
> > > > Alison Wang <alison.wang@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> > > > Franck Lenormand <franck.lenormand@nxp.com>; Horia Geanta
> > > > <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>; marex@denx.de;
> > > > Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Mingkai Hu
> > > > <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> > > > <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> > > > <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>;
> > > > Rajesh Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra
> > > > <sahil.malhotra@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> > > > Silvano Di Ninno <silvano.dininno@nxp.com>; sjg@chromium.org; u-
> > > > boot@lists.denx.de; dl-uboot-imx <uboot-imx@nxp.com>; Wasim Khan
> > > > <wasim.khan@nxp.com>; Ye Li <ye.li@nxp.com>; Raffaele RECALCATI
> > > > <raffaele.recalcati@bticino.it>; Jagan Teki
> > > > <jagan@amarulasolutions.com>
> > > > Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for
> > > > CAAM Job ring driver model
> > > >
> > > > Caution: EXT Email
> > > >
> > > > Hi
> > > >
> > > > On Tue, Mar 8, 2022 at 2:28 PM Stefano Babic <sbabic@denx.de> wrote:
> > > > >
> > > > > Hi Tom,
> > > > >
> > > > > On 08.03.22 13:48, Tom Rini wrote:
> > > > > > On Tue, Mar 08, 2022 at 08:12:27AM -0300, Fabio Estevam wrote:
> > > > > >> On Tue, Mar 8, 2022 at 8:10 AM Gaurav Jain <gaurav.jain@nxp.com>
> > > > wrote:
> > > > > >>
> > > > > >>> I further checked on your concern and propose the below change
> > > > > >>> to
> > > > stop building caam driver in SPL for imx6dl_mamoj.
> > > > > >>>
> > > > > >>> --- a/configs/imx6dl_mamoj_defconfig
> > > > > >>> +++ b/configs/imx6dl_mamoj_defconfig
> > > > > >>> @@ -61,3 +61,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
> > > > > >>> CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> > > > > >>> CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> > > > > >>> CONFIG_CI_UDC=y
> > > > > >>> +CONFIG_SPL_CRYPTO=n
> > > > > >>
> > > > > >> No, this is not how defconfig works.
> > > > > >>
> > > > > >> You should set:
> > > > > >>
> > > > > >> # CONFIG_SPL_CRYPTO is not set
> > > > > >
> > > > > > But more, WHY is this the right answer? You're disabling
> > > > > > functionality and the board maintainers aren't even on the CC list
> > > > > > for this thread it looks like.
> > > > >
> > > > > This was my blocking point, too, for this series. There is no answer
> > > > > about the board.
> > > > >
> > > > > I can just imagine (as for other MX6DL) that the required
> > > > > functionality is secure boot, then CONFIG_IMX_HAB is enough. But
> > > > > well, just the board maintainers can say. Added Raffaele and Jagan
> > > > > as reported maintainers for this board.
> > > > >
> > > > > > Why are you not fixing the board so it still links? What makes
> > > > > > this board a problem that other (I assume) imx6dl boards are not?
> > > > >
> > > > > Well, this board has, compared to other MX6DL, a lot of SPL_ option
> > > > > that are bloating the SPL size. And then does not match anymore with
> > > > > the internal RAm, while other MX6DL boards are not so affected by
> > > > > the increased size because they have no SPL at all or SPL with less
> > > > > options and then smaller. We do not need to fix the link, but reduce
> > > > > the size, and nobody else than the maintainers can tell us if
> > > > > removing some feature is ok.
> > > > >
> > > >
> > > > I will test this week, and try to find a board here to test
> > > >
> > > > * Jagan * Do you have a momoj?
> > >
> > > Have you tested mamoj board?
> > >
git diff
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 98df4d4e42..b665ec887e 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -309,7 +309,6 @@ config TARGET_MX6DL_MAMOJ
select PINCTRL
select SPL
select SPL_DM if SPL
- select SPL_GPIO if SPL
select SPL_LIBCOMMON_SUPPORT if SPL
select SPL_LIBDISK_SUPPORT if SPL
select SPL_LIBGENERIC_SUPPORT if SPL
I strongly suggest to drop this and check again for now. I don't have
access to board and I have asked Jagan
Michael
> > > Regards
> > > Gaurav
> > > >
> > > > Michael
> > > >
> > > > > Regards,
> > > > > Stefano
> > > > >
> > > > > --
> > > > >
> > > >
> > > ================================================================
> > > > =====
> > > > > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> > > > > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > > > Germany
> > > > > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email:
> > > > > sbabic@denx.de
> > > > >
> > > >
> > > ================================================================
> > > > =====
> > > >
> > > >
> > > >
> > > > --
> > > > Michael Nazzareno Trimarchi
> > > > Co-Founder & Chief Executive Officer
> > > > M. +39 347 913 2170
> > > > michael@amarulasolutions.com
> > > > __________________________________
> > > >
> > > > Amarula Solutions BV
> > > > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172
> > > > info@amarulasolutions.com
> > > >
> > > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.a
> > > > marulasolutions.com%2F&data=04%7C01%7Cgaurav.jain%40nxp.com%
> > > >
> > > 7C843e57f75346449f13ae08da010867b6%7C686ea1d3bc2b4c6fa92cd99c5c3
> > > >
> > > 01635%7C0%7C0%7C637823432854617357%7CUnknown%7CTWFpbGZsb3d8
> > > >
> > > eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> > > >
> > > D%7C3000&sdata=f025HmlIM8FuTEYspDjwOevTT1k7JRZeIiS%2FpTH2hc
> > > > Y%3D&reserved=0
>
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> michael@amarulasolutions.com
> __________________________________
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> info@amarulasolutions.com
> www.amarulasolutions.com
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply related [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 9:47 ` Michael Nazzareno Trimarchi
2022-03-19 10:32 ` Michael Nazzareno Trimarchi
@ 2022-03-19 13:24 ` Fabio Estevam
2022-03-19 13:51 ` Michael Nazzareno Trimarchi
1 sibling, 1 reply; 69+ messages in thread
From: Fabio Estevam @ 2022-03-19 13:24 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: Gaurav Jain, Stefano Babic, Tom Rini, Michael Walle, Varun Sethi,
Adrian Alonso, Alison Wang, Andy Tang, Franck Lenormand,
Horia Geanta, Ji Luo, marex, Meenakshi Aggarwal, Mingkai Hu,
olteanv, Pankaj Gupta, Peng Fan, Pramod Kumar, Priyanka Jain,
Rajesh Bhagat, Sahil Malhotra, Shengzhou Liu, Silvano Di Ninno,
sjg, u-boot, dl-uboot-imx, Wasim Khan, Ye Li, Raffaele RECALCATI,
Jagan Teki
Hi Michael,
On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
<michael@amarulasolutions.com> wrote:
>
> HI
>
> Please send me a link to apply your series
You can get the series from patchwork (just click in the 'series' button)
https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 13:24 ` Fabio Estevam
@ 2022-03-19 13:51 ` Michael Nazzareno Trimarchi
2022-03-19 16:05 ` Tom Rini
0 siblings, 1 reply; 69+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-03-19 13:51 UTC (permalink / raw)
To: Fabio Estevam
Cc: Gaurav Jain, Stefano Babic, Tom Rini, Michael Walle, Varun Sethi,
Adrian Alonso, Alison Wang, Andy Tang, Franck Lenormand,
Horia Geanta, Ji Luo, marex, Meenakshi Aggarwal, Mingkai Hu,
olteanv, Pankaj Gupta, Peng Fan, Pramod Kumar, Priyanka Jain,
Rajesh Bhagat, Sahil Malhotra, Shengzhou Liu, Silvano Di Ninno,
sjg, u-boot, dl-uboot-imx, Wasim Khan, Ye Li, Raffaele RECALCATI,
Jagan Teki
Hi
On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Michael,
>
> On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> <michael@amarulasolutions.com> wrote:
> >
> > HI
> >
> > Please send me a link to apply your series
>
> You can get the series from patchwork (just click in the 'series' button)
> https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
remove a lot of features. I have tested LTO build but size
of SPL increase. Is that strange?
Michael
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 13:51 ` Michael Nazzareno Trimarchi
@ 2022-03-19 16:05 ` Tom Rini
2022-03-19 16:48 ` Michael Nazzareno Trimarchi
0 siblings, 1 reply; 69+ messages in thread
From: Tom Rini @ 2022-03-19 16:05 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
[-- Attachment #1: Type: text/plain, Size: 806 bytes --]
On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
> Hi
>
> On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> >
> > Hi Michael,
> >
> > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> > <michael@amarulasolutions.com> wrote:
> > >
> > > HI
> > >
> > > Please send me a link to apply your series
> >
> > You can get the series from patchwork (just click in the 'series' button)
> > https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
>
> Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
> remove a lot of features. I have tested LTO build but size
> of SPL increase. Is that strange?
That is very strange. Can you post your patches somewhere?
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 16:05 ` Tom Rini
@ 2022-03-19 16:48 ` Michael Nazzareno Trimarchi
2022-03-19 17:03 ` Tom Rini
0 siblings, 1 reply; 69+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-03-19 16:48 UTC (permalink / raw)
To: Tom Rini
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
Hi Tom
On Sat, Mar 19, 2022 at 5:05 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
> > Hi
> >
> > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> > >
> > > Hi Michael,
> > >
> > > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> > > <michael@amarulasolutions.com> wrote:
> > > >
> > > > HI
> > > >
> > > > Please send me a link to apply your series
> > >
> > > You can get the series from patchwork (just click in the 'series' button)
> > > https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
> >
> > Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
> > remove a lot of features. I have tested LTO build but size
> > of SPL increase. Is that strange?
>
> That is very strange. Can you post your patches somewhere?
>
> --
> Tom
Start from here 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
export ARCH=arm
export CROSS_COMPILE=arm-linux-gnueabihf-
make imx6dl_mamoj_defconfig
build it
Try then to enable LTO and build it again
spl/u-boot-spl.bin exceeds file size limit:
limit: 0xefa0 bytes
actual: 0xf071 bytes
excess: 0xd1 bytes
So LTO does not help even on beginning on this board. You don't need
to apply any patch for this test
Michael
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 16:48 ` Michael Nazzareno Trimarchi
@ 2022-03-19 17:03 ` Tom Rini
2022-03-19 17:08 ` Michael Nazzareno Trimarchi
0 siblings, 1 reply; 69+ messages in thread
From: Tom Rini @ 2022-03-19 17:03 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
[-- Attachment #1: Type: text/plain, Size: 1714 bytes --]
On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno Trimarchi wrote:
> Hi Tom
>
> On Sat, Mar 19, 2022 at 5:05 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
> > > Hi
> > >
> > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> > > >
> > > > Hi Michael,
> > > >
> > > > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> > > > <michael@amarulasolutions.com> wrote:
> > > > >
> > > > > HI
> > > > >
> > > > > Please send me a link to apply your series
> > > >
> > > > You can get the series from patchwork (just click in the 'series' button)
> > > > https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
> > >
> > > Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
> > > remove a lot of features. I have tested LTO build but size
> > > of SPL increase. Is that strange?
> >
> > That is very strange. Can you post your patches somewhere?
> >
> > --
> > Tom
>
> Start from here 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
> export ARCH=arm
> export CROSS_COMPILE=arm-linux-gnueabihf-
>
> make imx6dl_mamoj_defconfig
> build it
>
> Try then to enable LTO and build it again
>
> spl/u-boot-spl.bin exceeds file size limit:
> limit: 0xefa0 bytes
> actual: 0xf071 bytes
> excess: 0xd1 bytes
>
> So LTO does not help even on beginning on this board. You don't need
> to apply any patch for this test
I think that's some artifact of mixing LTO/non-LTO and the world not
getting rebuilt? Just enabling LTO after the defconfig works fine and
is smaller than before.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 17:03 ` Tom Rini
@ 2022-03-19 17:08 ` Michael Nazzareno Trimarchi
2022-03-19 17:25 ` Tom Rini
0 siblings, 1 reply; 69+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-03-19 17:08 UTC (permalink / raw)
To: Tom Rini
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
Hi Tom
On Sat, Mar 19, 2022 at 6:03 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno Trimarchi wrote:
> > Hi Tom
> >
> > On Sat, Mar 19, 2022 at 5:05 PM Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > Hi
> > > >
> > > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> > > > >
> > > > > Hi Michael,
> > > > >
> > > > > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> > > > > <michael@amarulasolutions.com> wrote:
> > > > > >
> > > > > > HI
> > > > > >
> > > > > > Please send me a link to apply your series
> > > > >
> > > > > You can get the series from patchwork (just click in the 'series' button)
> > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
> > > >
> > > > Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
> > > > remove a lot of features. I have tested LTO build but size
> > > > of SPL increase. Is that strange?
> > >
> > > That is very strange. Can you post your patches somewhere?
> > >
> > > --
> > > Tom
> >
> > Start from here 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
> > export ARCH=arm
> > export CROSS_COMPILE=arm-linux-gnueabihf-
> >
> > make imx6dl_mamoj_defconfig
> > build it
> >
> > Try then to enable LTO and build it again
> >
> > spl/u-boot-spl.bin exceeds file size limit:
> > limit: 0xefa0 bytes
> > actual: 0xf071 bytes
> > excess: 0xd1 bytes
> >
> > So LTO does not help even on beginning on this board. You don't need
> > to apply any patch for this test
>
> I think that's some artifact of mixing LTO/non-LTO and the world not
> getting rebuilt? Just enabling LTO after the defconfig works fine and
> is smaller than before.
>
In order to save space I did not change what we have. Every build starts from
a mrproper and new configuration. I can not mix LTO/non-LTO in this case. I'm
using upstream defconfig and upstream defconfig + LTO enabled and the result is
that spl increase in size for LTO building. I'm working to keep out
part that are not really needed but
I was hoping that LTO give me some help here
Michael
> --
> Tom
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 17:08 ` Michael Nazzareno Trimarchi
@ 2022-03-19 17:25 ` Tom Rini
2022-03-19 17:27 ` Michael Nazzareno Trimarchi
0 siblings, 1 reply; 69+ messages in thread
From: Tom Rini @ 2022-03-19 17:25 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
[-- Attachment #1: Type: text/plain, Size: 2646 bytes --]
On Sat, Mar 19, 2022 at 06:08:18PM +0100, Michael Nazzareno Trimarchi wrote:
> Hi Tom
>
> On Sat, Mar 19, 2022 at 6:03 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno Trimarchi wrote:
> > > Hi Tom
> > >
> > > On Sat, Mar 19, 2022 at 5:05 PM Tom Rini <trini@konsulko.com> wrote:
> > > >
> > > > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > Hi
> > > > >
> > > > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> > > > > >
> > > > > > Hi Michael,
> > > > > >
> > > > > > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> > > > > > <michael@amarulasolutions.com> wrote:
> > > > > > >
> > > > > > > HI
> > > > > > >
> > > > > > > Please send me a link to apply your series
> > > > > >
> > > > > > You can get the series from patchwork (just click in the 'series' button)
> > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
> > > > >
> > > > > Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
> > > > > remove a lot of features. I have tested LTO build but size
> > > > > of SPL increase. Is that strange?
> > > >
> > > > That is very strange. Can you post your patches somewhere?
> > > >
> > > > --
> > > > Tom
> > >
> > > Start from here 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
> > > export ARCH=arm
> > > export CROSS_COMPILE=arm-linux-gnueabihf-
> > >
> > > make imx6dl_mamoj_defconfig
> > > build it
> > >
> > > Try then to enable LTO and build it again
> > >
> > > spl/u-boot-spl.bin exceeds file size limit:
> > > limit: 0xefa0 bytes
> > > actual: 0xf071 bytes
> > > excess: 0xd1 bytes
> > >
> > > So LTO does not help even on beginning on this board. You don't need
> > > to apply any patch for this test
> >
> > I think that's some artifact of mixing LTO/non-LTO and the world not
> > getting rebuilt? Just enabling LTO after the defconfig works fine and
> > is smaller than before.
>
> In order to save space I did not change what we have. Every build starts from
> a mrproper and new configuration. I can not mix LTO/non-LTO in this case. I'm
> using upstream defconfig and upstream defconfig + LTO enabled and the result is
> that spl increase in size for LTO building. I'm working to keep out
> part that are not really needed but
> I was hoping that LTO give me some help here
Yes, LTO saves about 5KiB on the SPL binary. You just need to enable it
in the config before you start building, not after you've built
everything once.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 17:25 ` Tom Rini
@ 2022-03-19 17:27 ` Michael Nazzareno Trimarchi
2022-03-19 17:30 ` Tom Rini
0 siblings, 1 reply; 69+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-03-19 17:27 UTC (permalink / raw)
To: Tom Rini
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
Hi
On Sat, Mar 19, 2022 at 6:25 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Sat, Mar 19, 2022 at 06:08:18PM +0100, Michael Nazzareno Trimarchi wrote:
> > Hi Tom
> >
> > On Sat, Mar 19, 2022 at 6:03 PM Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > Hi Tom
> > > >
> > > > On Sat, Mar 19, 2022 at 5:05 PM Tom Rini <trini@konsulko.com> wrote:
> > > > >
> > > > > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > Hi
> > > > > >
> > > > > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> > > > > > >
> > > > > > > Hi Michael,
> > > > > > >
> > > > > > > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> > > > > > > <michael@amarulasolutions.com> wrote:
> > > > > > > >
> > > > > > > > HI
> > > > > > > >
> > > > > > > > Please send me a link to apply your series
> > > > > > >
> > > > > > > You can get the series from patchwork (just click in the 'series' button)
> > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
> > > > > >
> > > > > > Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
> > > > > > remove a lot of features. I have tested LTO build but size
> > > > > > of SPL increase. Is that strange?
> > > > >
> > > > > That is very strange. Can you post your patches somewhere?
> > > > >
> > > > > --
> > > > > Tom
> > > >
> > > > Start from here 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
> > > > export ARCH=arm
> > > > export CROSS_COMPILE=arm-linux-gnueabihf-
> > > >
> > > > make imx6dl_mamoj_defconfig
> > > > build it
> > > >
> > > > Try then to enable LTO and build it again
> > > >
> > > > spl/u-boot-spl.bin exceeds file size limit:
> > > > limit: 0xefa0 bytes
> > > > actual: 0xf071 bytes
> > > > excess: 0xd1 bytes
> > > >
> > > > So LTO does not help even on beginning on this board. You don't need
> > > > to apply any patch for this test
> > >
> > > I think that's some artifact of mixing LTO/non-LTO and the world not
> > > getting rebuilt? Just enabling LTO after the defconfig works fine and
> > > is smaller than before.
> >
> > In order to save space I did not change what we have. Every build starts from
> > a mrproper and new configuration. I can not mix LTO/non-LTO in this case. I'm
> > using upstream defconfig and upstream defconfig + LTO enabled and the result is
> > that spl increase in size for LTO building. I'm working to keep out
> > part that are not really needed but
> > I was hoping that LTO give me some help here
>
> Yes, LTO saves about 5KiB on the SPL binary. You just need to enable it
> in the config before you start building, not after you've built
> everything once.
Offcourse ;) but this not the case. I don't drink enough to think that
change a config, decrease the build size ;)
Michael
>
> --
> Tom
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 17:27 ` Michael Nazzareno Trimarchi
@ 2022-03-19 17:30 ` Tom Rini
2022-03-19 17:37 ` Michael Nazzareno Trimarchi
0 siblings, 1 reply; 69+ messages in thread
From: Tom Rini @ 2022-03-19 17:30 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
[-- Attachment #1: Type: text/plain, Size: 3354 bytes --]
On Sat, Mar 19, 2022 at 06:27:38PM +0100, Michael Nazzareno Trimarchi wrote:
> Hi
>
> On Sat, Mar 19, 2022 at 6:25 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Sat, Mar 19, 2022 at 06:08:18PM +0100, Michael Nazzareno Trimarchi wrote:
> > > Hi Tom
> > >
> > > On Sat, Mar 19, 2022 at 6:03 PM Tom Rini <trini@konsulko.com> wrote:
> > > >
> > > > On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > Hi Tom
> > > > >
> > > > > On Sat, Mar 19, 2022 at 5:05 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > >
> > > > > > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > > Hi
> > > > > > >
> > > > > > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> > > > > > > >
> > > > > > > > Hi Michael,
> > > > > > > >
> > > > > > > > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> > > > > > > > <michael@amarulasolutions.com> wrote:
> > > > > > > > >
> > > > > > > > > HI
> > > > > > > > >
> > > > > > > > > Please send me a link to apply your series
> > > > > > > >
> > > > > > > > You can get the series from patchwork (just click in the 'series' button)
> > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
> > > > > > >
> > > > > > > Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
> > > > > > > remove a lot of features. I have tested LTO build but size
> > > > > > > of SPL increase. Is that strange?
> > > > > >
> > > > > > That is very strange. Can you post your patches somewhere?
> > > > > >
> > > > > > --
> > > > > > Tom
> > > > >
> > > > > Start from here 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
> > > > > export ARCH=arm
> > > > > export CROSS_COMPILE=arm-linux-gnueabihf-
> > > > >
> > > > > make imx6dl_mamoj_defconfig
> > > > > build it
> > > > >
> > > > > Try then to enable LTO and build it again
> > > > >
> > > > > spl/u-boot-spl.bin exceeds file size limit:
> > > > > limit: 0xefa0 bytes
> > > > > actual: 0xf071 bytes
> > > > > excess: 0xd1 bytes
> > > > >
> > > > > So LTO does not help even on beginning on this board. You don't need
> > > > > to apply any patch for this test
> > > >
> > > > I think that's some artifact of mixing LTO/non-LTO and the world not
> > > > getting rebuilt? Just enabling LTO after the defconfig works fine and
> > > > is smaller than before.
> > >
> > > In order to save space I did not change what we have. Every build starts from
> > > a mrproper and new configuration. I can not mix LTO/non-LTO in this case. I'm
> > > using upstream defconfig and upstream defconfig + LTO enabled and the result is
> > > that spl increase in size for LTO building. I'm working to keep out
> > > part that are not really needed but
> > > I was hoping that LTO give me some help here
> >
> > Yes, LTO saves about 5KiB on the SPL binary. You just need to enable it
> > in the config before you start building, not after you've built
> > everything once.
>
> Offcourse ;) but this not the case. I don't drink enough to think that
> change a config, decrease the build size ;)
LTO is an entirely different way of the compiler / linker optimizing the
binary. So yes, in this case enabling a single option decreases the
size.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 17:30 ` Tom Rini
@ 2022-03-19 17:37 ` Michael Nazzareno Trimarchi
2022-03-19 17:43 ` Tom Rini
0 siblings, 1 reply; 69+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-03-19 17:37 UTC (permalink / raw)
To: Tom Rini
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
Hi Tom
On Sat, Mar 19, 2022 at 6:30 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Sat, Mar 19, 2022 at 06:27:38PM +0100, Michael Nazzareno Trimarchi wrote:
> > Hi
> >
> > On Sat, Mar 19, 2022 at 6:25 PM Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Sat, Mar 19, 2022 at 06:08:18PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > Hi Tom
> > > >
> > > > On Sat, Mar 19, 2022 at 6:03 PM Tom Rini <trini@konsulko.com> wrote:
> > > > >
> > > > > On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > Hi Tom
> > > > > >
> > > > > > On Sat, Mar 19, 2022 at 5:05 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > > >
> > > > > > > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > > > Hi
> > > > > > > >
> > > > > > > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> > > > > > > > >
> > > > > > > > > Hi Michael,
> > > > > > > > >
> > > > > > > > > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> > > > > > > > > <michael@amarulasolutions.com> wrote:
> > > > > > > > > >
> > > > > > > > > > HI
> > > > > > > > > >
> > > > > > > > > > Please send me a link to apply your series
> > > > > > > > >
> > > > > > > > > You can get the series from patchwork (just click in the 'series' button)
> > > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
> > > > > > > >
> > > > > > > > Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
> > > > > > > > remove a lot of features. I have tested LTO build but size
> > > > > > > > of SPL increase. Is that strange?
> > > > > > >
> > > > > > > That is very strange. Can you post your patches somewhere?
> > > > > > >
> > > > > > > --
> > > > > > > Tom
> > > > > >
> > > > > > Start from here 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
> > > > > > export ARCH=arm
> > > > > > export CROSS_COMPILE=arm-linux-gnueabihf-
> > > > > >
> > > > > > make imx6dl_mamoj_defconfig
> > > > > > build it
> > > > > >
> > > > > > Try then to enable LTO and build it again
> > > > > >
> > > > > > spl/u-boot-spl.bin exceeds file size limit:
> > > > > > limit: 0xefa0 bytes
> > > > > > actual: 0xf071 bytes
> > > > > > excess: 0xd1 bytes
> > > > > >
> > > > > > So LTO does not help even on beginning on this board. You don't need
> > > > > > to apply any patch for this test
> > > > >
> > > > > I think that's some artifact of mixing LTO/non-LTO and the world not
> > > > > getting rebuilt? Just enabling LTO after the defconfig works fine and
> > > > > is smaller than before.
> > > >
> > > > In order to save space I did not change what we have. Every build starts from
> > > > a mrproper and new configuration. I can not mix LTO/non-LTO in this case. I'm
> > > > using upstream defconfig and upstream defconfig + LTO enabled and the result is
> > > > that spl increase in size for LTO building. I'm working to keep out
> > > > part that are not really needed but
> > > > I was hoping that LTO give me some help here
> > >
> > > Yes, LTO saves about 5KiB on the SPL binary. You just need to enable it
> > > in the config before you start building, not after you've built
> > > everything once.
> >
> > Offcourse ;) but this not the case. I don't drink enough to think that
> > change a config, decrease the build size ;)
>
> LTO is an entirely different way of the compiler / linker optimizing the
> binary. So yes, in this case enabling a single option decreases the
> size.
I think we are in a circle. Let's have the result with LTO
spl/keep-syms-lto.c
( cd spl && arm-linux-gnueabihf-gcc -nostdlib -nostartfiles
-fuse-linker-plugin -flto=8 -Wall -Wstrict-prototypes
-Wno-format-security -fno-builtin -ffreestanding -std=gnu11
-fshort-wchar -fno-strict-aliasing -fno-PIE -Os -flto=8
-fno-stack-protector -fno-delete-null-pointer-checks -Wno-pointer-sign
-Wno-stringop-truncation -Wno-array-bounds -Wno-stringop-overflow
-Wno-maybe-uninitialized -fmacro-prefix-map=./= -g -fstack-usage
-Wno-format-nonliteral -Wno-address-of-packed-member
-Wno-unused-but-set-variable -Werror=date-time -Wno-packed-not-aligned
-ffunction-sections -fdata-sections -fno-stack-protector -D__KERNEL__
-D__UBOOT__ -DCONFIG_SPL_BUILD -D__ARM__ -Wa,-mimplicit-it=always
-mthumb -mthumb-interwork -mabi=aapcs-linux -mno-unaligned-access
-fno-common -ffixed-r9 -msoft-float -mgeneral-regs-only -pipe
-march=armv7-a -D__LINUX_ARM_ARCH__=7 -mtune=generic-armv7-a
-Ispl/include -Iinclude -I./arch/arm/include -include
./include/linux/kconfig.h -nostdinc -isystem
/usr/lib/gcc-cross/arm-linux-gnueabihf/9/include -Wl,-T
-Wl,u-boot-spl.lds -Wl,-Bstatic -Wl,--gc-sections
-Wl,--no-dynamic-linker -Wl,--build-id=none -Wl,-Ttext -Wl,0x00908000
arch/arm/cpu/armv7/start.o -Wl,--whole-archive
arch/arm/cpu/armv7/built-in.o arch/arm/cpu/built-in.o
arch/arm/lib/built-in.o arch/arm/mach-imx/built-in.o
board/bticino/mamoj/built-in.o common/spl/built-in.o
common/init/built-in.o boot/built-in.o common/built-in.o
cmd/built-in.o env/built-in.o lib/built-in.o disk/built-in.o
drivers/built-in.o drivers/usb/dwc3/built-in.o
drivers/usb/cdns3/built-in.o dts/built-in.o fs/built-in.o
keep-syms-lto.o arch/arm/lib/eabi_compat.o arch/arm/lib/lib.a
-Wl,--no-whole-archive -Wl,-Map,u-boot-spl.map -o u-boot-spl )
arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
.secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
.u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
.dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -O binary
spl/u-boot-spl spl/u-boot-spl-nodtb.bin
arm-linux-gnueabihf-objdump -t spl/u-boot-spl > spl/u-boot-spl.sym
cat spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb > spl/u-boot-spl-dtb.bin
cp spl/u-boot-spl-dtb.bin spl/u-boot-spl.bin
spl/u-boot-spl.bin exceeds file size limit:
limit: 0xefa0 bytes
actual: 0xf079 bytes
excess: 0xd9 bytes
make: *** [Makefile:2082: spl/u-boot-spl.bin] Error 1
make: *** Deleting file 'spl/u-boot-spl.bin'
and without
NUX_ARM_ARCH__=7 -mtune=generic-armv7-a -D__ASSEMBLY__ -x c -o
spl/u-boot-spl.cfgout arch/arm/mach-imx/spl_sd.cfg
./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e 0x00908000
-d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
Image Type: Freescale IMX Boot Image
Image Ver: 2 (i.MX53/6/7 compatible)
Mode: DCD
Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
Load Address: 00907420
Entry Point: 00908000
HAB Blocks: 0x00907400 0x00000000 0x0000fc00
DCD Blocks: 0x00910000 0x0000002c 0x00000004
make -f ./scripts/Makefile.build obj=arch/arm/mach-imx u-boot-with-spl.imx
mkdir -p spl/
./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e 0x00908000
-d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
Image Type: Freescale IMX Boot Image
Image Ver: 2 (i.MX53/6/7 compatible)
Mode: DCD
Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
Load Address: 00907420
Entry Point: 00908000
HAB Blocks: 0x00907400 0x00000000 0x0000fc00
DCD Blocks: 0x00910000 0x0000002c 0x00000004
arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
.secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
.u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
.dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -I binary -O
binary --pad-to=0x11000 SPL u-boot-with-spl.imx && cat u-boot.img >>
u-boot-with-spl.imx || rm -f u-boot-with-spl.imx
What I'm trying to say is that I have followed the correct steps and
this is the LTO change
git diff
diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
index ae27857e6f..4a535012b2 100644
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -14,6 +14,7 @@ CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_IMX_HAB=y
# CONFIG_CMD_BMODE is not set
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_OS_BOOT=y
Michael
>
> --
> Tom
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply related [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 17:37 ` Michael Nazzareno Trimarchi
@ 2022-03-19 17:43 ` Tom Rini
2022-03-19 17:49 ` Michael Nazzareno Trimarchi
0 siblings, 1 reply; 69+ messages in thread
From: Tom Rini @ 2022-03-19 17:43 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
[-- Attachment #1: Type: text/plain, Size: 10860 bytes --]
On Sat, Mar 19, 2022 at 06:37:18PM +0100, Michael Nazzareno Trimarchi wrote:
> Hi Tom
>
> On Sat, Mar 19, 2022 at 6:30 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Sat, Mar 19, 2022 at 06:27:38PM +0100, Michael Nazzareno Trimarchi wrote:
> > > Hi
> > >
> > > On Sat, Mar 19, 2022 at 6:25 PM Tom Rini <trini@konsulko.com> wrote:
> > > >
> > > > On Sat, Mar 19, 2022 at 06:08:18PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > Hi Tom
> > > > >
> > > > > On Sat, Mar 19, 2022 at 6:03 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > >
> > > > > > On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > > Hi Tom
> > > > > > >
> > > > > > > On Sat, Mar 19, 2022 at 5:05 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > > > >
> > > > > > > > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > > > > Hi
> > > > > > > > >
> > > > > > > > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> > > > > > > > > >
> > > > > > > > > > Hi Michael,
> > > > > > > > > >
> > > > > > > > > > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> > > > > > > > > > <michael@amarulasolutions.com> wrote:
> > > > > > > > > > >
> > > > > > > > > > > HI
> > > > > > > > > > >
> > > > > > > > > > > Please send me a link to apply your series
> > > > > > > > > >
> > > > > > > > > > You can get the series from patchwork (just click in the 'series' button)
> > > > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
> > > > > > > > >
> > > > > > > > > Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
> > > > > > > > > remove a lot of features. I have tested LTO build but size
> > > > > > > > > of SPL increase. Is that strange?
> > > > > > > >
> > > > > > > > That is very strange. Can you post your patches somewhere?
> > > > > > > >
> > > > > > > > --
> > > > > > > > Tom
> > > > > > >
> > > > > > > Start from here 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
> > > > > > > export ARCH=arm
> > > > > > > export CROSS_COMPILE=arm-linux-gnueabihf-
> > > > > > >
> > > > > > > make imx6dl_mamoj_defconfig
> > > > > > > build it
> > > > > > >
> > > > > > > Try then to enable LTO and build it again
> > > > > > >
> > > > > > > spl/u-boot-spl.bin exceeds file size limit:
> > > > > > > limit: 0xefa0 bytes
> > > > > > > actual: 0xf071 bytes
> > > > > > > excess: 0xd1 bytes
> > > > > > >
> > > > > > > So LTO does not help even on beginning on this board. You don't need
> > > > > > > to apply any patch for this test
> > > > > >
> > > > > > I think that's some artifact of mixing LTO/non-LTO and the world not
> > > > > > getting rebuilt? Just enabling LTO after the defconfig works fine and
> > > > > > is smaller than before.
> > > > >
> > > > > In order to save space I did not change what we have. Every build starts from
> > > > > a mrproper and new configuration. I can not mix LTO/non-LTO in this case. I'm
> > > > > using upstream defconfig and upstream defconfig + LTO enabled and the result is
> > > > > that spl increase in size for LTO building. I'm working to keep out
> > > > > part that are not really needed but
> > > > > I was hoping that LTO give me some help here
> > > >
> > > > Yes, LTO saves about 5KiB on the SPL binary. You just need to enable it
> > > > in the config before you start building, not after you've built
> > > > everything once.
> > >
> > > Offcourse ;) but this not the case. I don't drink enough to think that
> > > change a config, decrease the build size ;)
> >
> > LTO is an entirely different way of the compiler / linker optimizing the
> > binary. So yes, in this case enabling a single option decreases the
> > size.
>
>
> I think we are in a circle. Let's have the result with LTO
>
> spl/keep-syms-lto.c
> ( cd spl && arm-linux-gnueabihf-gcc -nostdlib -nostartfiles
> -fuse-linker-plugin -flto=8 -Wall -Wstrict-prototypes
> -Wno-format-security -fno-builtin -ffreestanding -std=gnu11
> -fshort-wchar -fno-strict-aliasing -fno-PIE -Os -flto=8
> -fno-stack-protector -fno-delete-null-pointer-checks -Wno-pointer-sign
> -Wno-stringop-truncation -Wno-array-bounds -Wno-stringop-overflow
> -Wno-maybe-uninitialized -fmacro-prefix-map=./= -g -fstack-usage
> -Wno-format-nonliteral -Wno-address-of-packed-member
> -Wno-unused-but-set-variable -Werror=date-time -Wno-packed-not-aligned
> -ffunction-sections -fdata-sections -fno-stack-protector -D__KERNEL__
> -D__UBOOT__ -DCONFIG_SPL_BUILD -D__ARM__ -Wa,-mimplicit-it=always
> -mthumb -mthumb-interwork -mabi=aapcs-linux -mno-unaligned-access
> -fno-common -ffixed-r9 -msoft-float -mgeneral-regs-only -pipe
> -march=armv7-a -D__LINUX_ARM_ARCH__=7 -mtune=generic-armv7-a
> -Ispl/include -Iinclude -I./arch/arm/include -include
> ./include/linux/kconfig.h -nostdinc -isystem
> /usr/lib/gcc-cross/arm-linux-gnueabihf/9/include -Wl,-T
> -Wl,u-boot-spl.lds -Wl,-Bstatic -Wl,--gc-sections
> -Wl,--no-dynamic-linker -Wl,--build-id=none -Wl,-Ttext -Wl,0x00908000
> arch/arm/cpu/armv7/start.o -Wl,--whole-archive
> arch/arm/cpu/armv7/built-in.o arch/arm/cpu/built-in.o
> arch/arm/lib/built-in.o arch/arm/mach-imx/built-in.o
> board/bticino/mamoj/built-in.o common/spl/built-in.o
> common/init/built-in.o boot/built-in.o common/built-in.o
> cmd/built-in.o env/built-in.o lib/built-in.o disk/built-in.o
> drivers/built-in.o drivers/usb/dwc3/built-in.o
> drivers/usb/cdns3/built-in.o dts/built-in.o fs/built-in.o
> keep-syms-lto.o arch/arm/lib/eabi_compat.o arch/arm/lib/lib.a
> -Wl,--no-whole-archive -Wl,-Map,u-boot-spl.map -o u-boot-spl )
> arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
> .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
> .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
> .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -O binary
> spl/u-boot-spl spl/u-boot-spl-nodtb.bin
> arm-linux-gnueabihf-objdump -t spl/u-boot-spl > spl/u-boot-spl.sym
> cat spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb > spl/u-boot-spl-dtb.bin
> cp spl/u-boot-spl-dtb.bin spl/u-boot-spl.bin
> spl/u-boot-spl.bin exceeds file size limit:
> limit: 0xefa0 bytes
> actual: 0xf079 bytes
> excess: 0xd9 bytes
> make: *** [Makefile:2082: spl/u-boot-spl.bin] Error 1
> make: *** Deleting file 'spl/u-boot-spl.bin'
>
> and without
>
> NUX_ARM_ARCH__=7 -mtune=generic-armv7-a -D__ASSEMBLY__ -x c -o
> spl/u-boot-spl.cfgout arch/arm/mach-imx/spl_sd.cfg
> ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e 0x00908000
> -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
> Image Type: Freescale IMX Boot Image
> Image Ver: 2 (i.MX53/6/7 compatible)
> Mode: DCD
> Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
> Load Address: 00907420
> Entry Point: 00908000
> HAB Blocks: 0x00907400 0x00000000 0x0000fc00
> DCD Blocks: 0x00910000 0x0000002c 0x00000004
> make -f ./scripts/Makefile.build obj=arch/arm/mach-imx u-boot-with-spl.imx
> mkdir -p spl/
> ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e 0x00908000
> -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
> Image Type: Freescale IMX Boot Image
> Image Ver: 2 (i.MX53/6/7 compatible)
> Mode: DCD
> Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
> Load Address: 00907420
> Entry Point: 00908000
> HAB Blocks: 0x00907400 0x00000000 0x0000fc00
> DCD Blocks: 0x00910000 0x0000002c 0x00000004
> arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
> .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
> .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
> .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -I binary -O
> binary --pad-to=0x11000 SPL u-boot-with-spl.imx && cat u-boot.img >>
> u-boot-with-spl.imx || rm -f u-boot-with-spl.imx
>
>
> What I'm trying to say is that I have followed the correct steps and
> this is the LTO change
>
> git diff
> diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
> index ae27857e6f..4a535012b2 100644
> --- a/configs/imx6dl_mamoj_defconfig
> +++ b/configs/imx6dl_mamoj_defconfig
> @@ -14,6 +14,7 @@ CONFIG_SPL_TEXT_BASE=0x00908000
> CONFIG_SPL_DRIVERS_MISC=y
> CONFIG_IMX_HAB=y
> # CONFIG_CMD_BMODE is not set
> +CONFIG_LTO=y
> CONFIG_DISTRO_DEFAULTS=y
> CONFIG_BOOTDELAY=3
> CONFIG_SPL_OS_BOOT=y
Here's what I see:
$ git describe HEAD
v2022.04-rc4-50-g9776c4e9d00a
$ make imx6dl_mamoj_defconfig
HOSTCC scripts/basic/fixdep
HOSTCC scripts/kconfig/conf.o
YACC scripts/kconfig/zconf.tab.c
LEX scripts/kconfig/zconf.lex.c
HOSTCC scripts/kconfig/zconf.tab.o
HOSTLD scripts/kconfig/conf
#
# configuration written to .config
#
$ sed -i -e 's/# CONFIG_LTO is not set/CONFIG_LTO=y/' .config
$ grep LTO .config
CONFIG_ARCH_SUPPORTS_LTO=y
CONFIG_LTO=y
$ make CROSS_COMPILE=~/.buildman-toolchains/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi- -sj12
===================== WARNING ======================
This board does not use CONFIG_DM_SERIAL (Driver Model
for Serial drivers). Please update the board to use
CONFIG_DM_SERIAL before the v2023.04 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl:pwms: cell 3 is not a phandle reference
arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl: Missing property '#pwm-cells' in node /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from pwms[3])
arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl:pwms: cell 3 is not a phandle reference
arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl: Missing property '#pwm-cells' in node /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from pwms[3])
$ ls -lh spl/u-boot-spl*
-rwxrwxr-x 1 trini trini 944K Mar 19 13:40 spl/u-boot-spl
-rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl.bin
-rw-rw-r-- 1 trini trini 1.6K Mar 19 13:40 spl/u-boot-spl.cfgout
-rw-rw-r-- 1 trini trini 2.2K Mar 19 13:40 spl/u-boot-spl.dtb
-rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl-dtb.bin
-rw-rw-r-- 1 trini trini 728 Mar 19 13:40 spl/u-boot-spl.lds
-rw-rw-r-- 1 trini trini 5.9K Mar 19 13:40 spl/u-boot-spl.ltrans0.ltrans.su
-rw-rw-r-- 1 trini trini 7.2K Mar 19 13:40 spl/u-boot-spl.ltrans1.ltrans.su
-rw-rw-r-- 1 trini trini 182K Mar 19 13:40 spl/u-boot-spl.map
-rwxrwxr-x 1 trini trini 51K Mar 19 13:40 spl/u-boot-spl-nodtb.bin
-rw-rw-r-- 1 trini trini 135K Mar 19 13:40 spl/u-boot-spl.sym
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 17:43 ` Tom Rini
@ 2022-03-19 17:49 ` Michael Nazzareno Trimarchi
2022-03-19 17:51 ` Tom Rini
0 siblings, 1 reply; 69+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-03-19 17:49 UTC (permalink / raw)
To: Tom Rini
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
HI Tom
On Sat, Mar 19, 2022 at 6:44 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Sat, Mar 19, 2022 at 06:37:18PM +0100, Michael Nazzareno Trimarchi wrote:
> > Hi Tom
> >
> > On Sat, Mar 19, 2022 at 6:30 PM Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Sat, Mar 19, 2022 at 06:27:38PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > Hi
> > > >
> > > > On Sat, Mar 19, 2022 at 6:25 PM Tom Rini <trini@konsulko.com> wrote:
> > > > >
> > > > > On Sat, Mar 19, 2022 at 06:08:18PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > Hi Tom
> > > > > >
> > > > > > On Sat, Mar 19, 2022 at 6:03 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > > >
> > > > > > > On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > > > Hi Tom
> > > > > > > >
> > > > > > > > On Sat, Mar 19, 2022 at 5:05 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > > > > >
> > > > > > > > > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > > > > > Hi
> > > > > > > > > >
> > > > > > > > > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> > > > > > > > > > >
> > > > > > > > > > > Hi Michael,
> > > > > > > > > > >
> > > > > > > > > > > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> > > > > > > > > > > <michael@amarulasolutions.com> wrote:
> > > > > > > > > > > >
> > > > > > > > > > > > HI
> > > > > > > > > > > >
> > > > > > > > > > > > Please send me a link to apply your series
> > > > > > > > > > >
> > > > > > > > > > > You can get the series from patchwork (just click in the 'series' button)
> > > > > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
> > > > > > > > > >
> > > > > > > > > > Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
> > > > > > > > > > remove a lot of features. I have tested LTO build but size
> > > > > > > > > > of SPL increase. Is that strange?
> > > > > > > > >
> > > > > > > > > That is very strange. Can you post your patches somewhere?
> > > > > > > > >
> > > > > > > > > --
> > > > > > > > > Tom
> > > > > > > >
> > > > > > > > Start from here 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
> > > > > > > > export ARCH=arm
> > > > > > > > export CROSS_COMPILE=arm-linux-gnueabihf-
> > > > > > > >
> > > > > > > > make imx6dl_mamoj_defconfig
> > > > > > > > build it
> > > > > > > >
> > > > > > > > Try then to enable LTO and build it again
> > > > > > > >
> > > > > > > > spl/u-boot-spl.bin exceeds file size limit:
> > > > > > > > limit: 0xefa0 bytes
> > > > > > > > actual: 0xf071 bytes
> > > > > > > > excess: 0xd1 bytes
> > > > > > > >
> > > > > > > > So LTO does not help even on beginning on this board. You don't need
> > > > > > > > to apply any patch for this test
> > > > > > >
> > > > > > > I think that's some artifact of mixing LTO/non-LTO and the world not
> > > > > > > getting rebuilt? Just enabling LTO after the defconfig works fine and
> > > > > > > is smaller than before.
> > > > > >
> > > > > > In order to save space I did not change what we have. Every build starts from
> > > > > > a mrproper and new configuration. I can not mix LTO/non-LTO in this case. I'm
> > > > > > using upstream defconfig and upstream defconfig + LTO enabled and the result is
> > > > > > that spl increase in size for LTO building. I'm working to keep out
> > > > > > part that are not really needed but
> > > > > > I was hoping that LTO give me some help here
> > > > >
> > > > > Yes, LTO saves about 5KiB on the SPL binary. You just need to enable it
> > > > > in the config before you start building, not after you've built
> > > > > everything once.
> > > >
> > > > Offcourse ;) but this not the case. I don't drink enough to think that
> > > > change a config, decrease the build size ;)
> > >
> > > LTO is an entirely different way of the compiler / linker optimizing the
> > > binary. So yes, in this case enabling a single option decreases the
> > > size.
> >
> >
> > I think we are in a circle. Let's have the result with LTO
> >
> > spl/keep-syms-lto.c
> > ( cd spl && arm-linux-gnueabihf-gcc -nostdlib -nostartfiles
> > -fuse-linker-plugin -flto=8 -Wall -Wstrict-prototypes
> > -Wno-format-security -fno-builtin -ffreestanding -std=gnu11
> > -fshort-wchar -fno-strict-aliasing -fno-PIE -Os -flto=8
> > -fno-stack-protector -fno-delete-null-pointer-checks -Wno-pointer-sign
> > -Wno-stringop-truncation -Wno-array-bounds -Wno-stringop-overflow
> > -Wno-maybe-uninitialized -fmacro-prefix-map=./= -g -fstack-usage
> > -Wno-format-nonliteral -Wno-address-of-packed-member
> > -Wno-unused-but-set-variable -Werror=date-time -Wno-packed-not-aligned
> > -ffunction-sections -fdata-sections -fno-stack-protector -D__KERNEL__
> > -D__UBOOT__ -DCONFIG_SPL_BUILD -D__ARM__ -Wa,-mimplicit-it=always
> > -mthumb -mthumb-interwork -mabi=aapcs-linux -mno-unaligned-access
> > -fno-common -ffixed-r9 -msoft-float -mgeneral-regs-only -pipe
> > -march=armv7-a -D__LINUX_ARM_ARCH__=7 -mtune=generic-armv7-a
> > -Ispl/include -Iinclude -I./arch/arm/include -include
> > ./include/linux/kconfig.h -nostdinc -isystem
> > /usr/lib/gcc-cross/arm-linux-gnueabihf/9/include -Wl,-T
> > -Wl,u-boot-spl.lds -Wl,-Bstatic -Wl,--gc-sections
> > -Wl,--no-dynamic-linker -Wl,--build-id=none -Wl,-Ttext -Wl,0x00908000
> > arch/arm/cpu/armv7/start.o -Wl,--whole-archive
> > arch/arm/cpu/armv7/built-in.o arch/arm/cpu/built-in.o
> > arch/arm/lib/built-in.o arch/arm/mach-imx/built-in.o
> > board/bticino/mamoj/built-in.o common/spl/built-in.o
> > common/init/built-in.o boot/built-in.o common/built-in.o
> > cmd/built-in.o env/built-in.o lib/built-in.o disk/built-in.o
> > drivers/built-in.o drivers/usb/dwc3/built-in.o
> > drivers/usb/cdns3/built-in.o dts/built-in.o fs/built-in.o
> > keep-syms-lto.o arch/arm/lib/eabi_compat.o arch/arm/lib/lib.a
> > -Wl,--no-whole-archive -Wl,-Map,u-boot-spl.map -o u-boot-spl )
> > arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
> > .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
> > .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
> > .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -O binary
> > spl/u-boot-spl spl/u-boot-spl-nodtb.bin
> > arm-linux-gnueabihf-objdump -t spl/u-boot-spl > spl/u-boot-spl.sym
> > cat spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb > spl/u-boot-spl-dtb.bin
> > cp spl/u-boot-spl-dtb.bin spl/u-boot-spl.bin
> > spl/u-boot-spl.bin exceeds file size limit:
> > limit: 0xefa0 bytes
> > actual: 0xf079 bytes
> > excess: 0xd9 bytes
> > make: *** [Makefile:2082: spl/u-boot-spl.bin] Error 1
> > make: *** Deleting file 'spl/u-boot-spl.bin'
> >
> > and without
> >
> > NUX_ARM_ARCH__=7 -mtune=generic-armv7-a -D__ASSEMBLY__ -x c -o
> > spl/u-boot-spl.cfgout arch/arm/mach-imx/spl_sd.cfg
> > ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e 0x00908000
> > -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
> > Image Type: Freescale IMX Boot Image
> > Image Ver: 2 (i.MX53/6/7 compatible)
> > Mode: DCD
> > Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
> > Load Address: 00907420
> > Entry Point: 00908000
> > HAB Blocks: 0x00907400 0x00000000 0x0000fc00
> > DCD Blocks: 0x00910000 0x0000002c 0x00000004
> > make -f ./scripts/Makefile.build obj=arch/arm/mach-imx u-boot-with-spl.imx
> > mkdir -p spl/
> > ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e 0x00908000
> > -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
> > Image Type: Freescale IMX Boot Image
> > Image Ver: 2 (i.MX53/6/7 compatible)
> > Mode: DCD
> > Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
> > Load Address: 00907420
> > Entry Point: 00908000
> > HAB Blocks: 0x00907400 0x00000000 0x0000fc00
> > DCD Blocks: 0x00910000 0x0000002c 0x00000004
> > arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
> > .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
> > .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
> > .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -I binary -O
> > binary --pad-to=0x11000 SPL u-boot-with-spl.imx && cat u-boot.img >>
> > u-boot-with-spl.imx || rm -f u-boot-with-spl.imx
> >
> >
> > What I'm trying to say is that I have followed the correct steps and
> > this is the LTO change
> >
> > git diff
> > diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
> > index ae27857e6f..4a535012b2 100644
> > --- a/configs/imx6dl_mamoj_defconfig
> > +++ b/configs/imx6dl_mamoj_defconfig
> > @@ -14,6 +14,7 @@ CONFIG_SPL_TEXT_BASE=0x00908000
> > CONFIG_SPL_DRIVERS_MISC=y
> > CONFIG_IMX_HAB=y
> > # CONFIG_CMD_BMODE is not set
> > +CONFIG_LTO=y
> > CONFIG_DISTRO_DEFAULTS=y
> > CONFIG_BOOTDELAY=3
> > CONFIG_SPL_OS_BOOT=y
>
> Here's what I see:
> $ git describe HEAD
> v2022.04-rc4-50-g9776c4e9d00a
> $ make imx6dl_mamoj_defconfig
> HOSTCC scripts/basic/fixdep
> HOSTCC scripts/kconfig/conf.o
> YACC scripts/kconfig/zconf.tab.c
> LEX scripts/kconfig/zconf.lex.c
> HOSTCC scripts/kconfig/zconf.tab.o
> HOSTLD scripts/kconfig/conf
> #
> # configuration written to .config
> #
> $ sed -i -e 's/# CONFIG_LTO is not set/CONFIG_LTO=y/' .config
> $ grep LTO .config
> CONFIG_ARCH_SUPPORTS_LTO=y
> CONFIG_LTO=y
> $ make CROSS_COMPILE=~/.buildman-toolchains/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi- -sj12
> ===================== WARNING ======================
> This board does not use CONFIG_DM_SERIAL (Driver Model
> for Serial drivers). Please update the board to use
> CONFIG_DM_SERIAL before the v2023.04 release. Failure to
> update by the deadline may result in board removal.
> See doc/driver-model/migration.rst for more info.
> ====================================================
> arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl:pwms: cell 3 is not a phandle reference
> arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl: Missing property '#pwm-cells' in node /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from pwms[3])
> arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl:pwms: cell 3 is not a phandle reference
> arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl: Missing property '#pwm-cells' in node /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from pwms[3])
> $ ls -lh spl/u-boot-spl*
> -rwxrwxr-x 1 trini trini 944K Mar 19 13:40 spl/u-boot-spl
> -rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl.bin
> -rw-rw-r-- 1 trini trini 1.6K Mar 19 13:40 spl/u-boot-spl.cfgout
> -rw-rw-r-- 1 trini trini 2.2K Mar 19 13:40 spl/u-boot-spl.dtb
> -rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl-dtb.bin
> -rw-rw-r-- 1 trini trini 728 Mar 19 13:40 spl/u-boot-spl.lds
> -rw-rw-r-- 1 trini trini 5.9K Mar 19 13:40 spl/u-boot-spl.ltrans0.ltrans.su
> -rw-rw-r-- 1 trini trini 7.2K Mar 19 13:40 spl/u-boot-spl.ltrans1.ltrans.su
> -rw-rw-r-- 1 trini trini 182K Mar 19 13:40 spl/u-boot-spl.map
> -rwxrwxr-x 1 trini trini 51K Mar 19 13:40 spl/u-boot-spl-nodtb.bin
> -rw-rw-r-- 1 trini trini 135K Mar 19 13:40 spl/u-boot-spl.sym
>
The only difference is the toolchain gcc version 9.4.0 (Ubuntu
9.4.0-1ubuntu1~20.04) and for the result you get I'm agree with you.
Michael
> --
> Tom
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 17:49 ` Michael Nazzareno Trimarchi
@ 2022-03-19 17:51 ` Tom Rini
2022-03-19 18:00 ` Michael Nazzareno Trimarchi
0 siblings, 1 reply; 69+ messages in thread
From: Tom Rini @ 2022-03-19 17:51 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
[-- Attachment #1: Type: text/plain, Size: 12190 bytes --]
On Sat, Mar 19, 2022 at 06:49:25PM +0100, Michael Nazzareno Trimarchi wrote:
> HI Tom
>
> On Sat, Mar 19, 2022 at 6:44 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Sat, Mar 19, 2022 at 06:37:18PM +0100, Michael Nazzareno Trimarchi wrote:
> > > Hi Tom
> > >
> > > On Sat, Mar 19, 2022 at 6:30 PM Tom Rini <trini@konsulko.com> wrote:
> > > >
> > > > On Sat, Mar 19, 2022 at 06:27:38PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > Hi
> > > > >
> > > > > On Sat, Mar 19, 2022 at 6:25 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > >
> > > > > > On Sat, Mar 19, 2022 at 06:08:18PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > > Hi Tom
> > > > > > >
> > > > > > > On Sat, Mar 19, 2022 at 6:03 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > > > >
> > > > > > > > On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > > > > Hi Tom
> > > > > > > > >
> > > > > > > > > On Sat, Mar 19, 2022 at 5:05 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > > > > > >
> > > > > > > > > > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > > > > > > Hi
> > > > > > > > > > >
> > > > > > > > > > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> > > > > > > > > > > >
> > > > > > > > > > > > Hi Michael,
> > > > > > > > > > > >
> > > > > > > > > > > > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> > > > > > > > > > > > <michael@amarulasolutions.com> wrote:
> > > > > > > > > > > > >
> > > > > > > > > > > > > HI
> > > > > > > > > > > > >
> > > > > > > > > > > > > Please send me a link to apply your series
> > > > > > > > > > > >
> > > > > > > > > > > > You can get the series from patchwork (just click in the 'series' button)
> > > > > > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
> > > > > > > > > > >
> > > > > > > > > > > Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
> > > > > > > > > > > remove a lot of features. I have tested LTO build but size
> > > > > > > > > > > of SPL increase. Is that strange?
> > > > > > > > > >
> > > > > > > > > > That is very strange. Can you post your patches somewhere?
> > > > > > > > > >
> > > > > > > > > > --
> > > > > > > > > > Tom
> > > > > > > > >
> > > > > > > > > Start from here 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
> > > > > > > > > export ARCH=arm
> > > > > > > > > export CROSS_COMPILE=arm-linux-gnueabihf-
> > > > > > > > >
> > > > > > > > > make imx6dl_mamoj_defconfig
> > > > > > > > > build it
> > > > > > > > >
> > > > > > > > > Try then to enable LTO and build it again
> > > > > > > > >
> > > > > > > > > spl/u-boot-spl.bin exceeds file size limit:
> > > > > > > > > limit: 0xefa0 bytes
> > > > > > > > > actual: 0xf071 bytes
> > > > > > > > > excess: 0xd1 bytes
> > > > > > > > >
> > > > > > > > > So LTO does not help even on beginning on this board. You don't need
> > > > > > > > > to apply any patch for this test
> > > > > > > >
> > > > > > > > I think that's some artifact of mixing LTO/non-LTO and the world not
> > > > > > > > getting rebuilt? Just enabling LTO after the defconfig works fine and
> > > > > > > > is smaller than before.
> > > > > > >
> > > > > > > In order to save space I did not change what we have. Every build starts from
> > > > > > > a mrproper and new configuration. I can not mix LTO/non-LTO in this case. I'm
> > > > > > > using upstream defconfig and upstream defconfig + LTO enabled and the result is
> > > > > > > that spl increase in size for LTO building. I'm working to keep out
> > > > > > > part that are not really needed but
> > > > > > > I was hoping that LTO give me some help here
> > > > > >
> > > > > > Yes, LTO saves about 5KiB on the SPL binary. You just need to enable it
> > > > > > in the config before you start building, not after you've built
> > > > > > everything once.
> > > > >
> > > > > Offcourse ;) but this not the case. I don't drink enough to think that
> > > > > change a config, decrease the build size ;)
> > > >
> > > > LTO is an entirely different way of the compiler / linker optimizing the
> > > > binary. So yes, in this case enabling a single option decreases the
> > > > size.
> > >
> > >
> > > I think we are in a circle. Let's have the result with LTO
> > >
> > > spl/keep-syms-lto.c
> > > ( cd spl && arm-linux-gnueabihf-gcc -nostdlib -nostartfiles
> > > -fuse-linker-plugin -flto=8 -Wall -Wstrict-prototypes
> > > -Wno-format-security -fno-builtin -ffreestanding -std=gnu11
> > > -fshort-wchar -fno-strict-aliasing -fno-PIE -Os -flto=8
> > > -fno-stack-protector -fno-delete-null-pointer-checks -Wno-pointer-sign
> > > -Wno-stringop-truncation -Wno-array-bounds -Wno-stringop-overflow
> > > -Wno-maybe-uninitialized -fmacro-prefix-map=./= -g -fstack-usage
> > > -Wno-format-nonliteral -Wno-address-of-packed-member
> > > -Wno-unused-but-set-variable -Werror=date-time -Wno-packed-not-aligned
> > > -ffunction-sections -fdata-sections -fno-stack-protector -D__KERNEL__
> > > -D__UBOOT__ -DCONFIG_SPL_BUILD -D__ARM__ -Wa,-mimplicit-it=always
> > > -mthumb -mthumb-interwork -mabi=aapcs-linux -mno-unaligned-access
> > > -fno-common -ffixed-r9 -msoft-float -mgeneral-regs-only -pipe
> > > -march=armv7-a -D__LINUX_ARM_ARCH__=7 -mtune=generic-armv7-a
> > > -Ispl/include -Iinclude -I./arch/arm/include -include
> > > ./include/linux/kconfig.h -nostdinc -isystem
> > > /usr/lib/gcc-cross/arm-linux-gnueabihf/9/include -Wl,-T
> > > -Wl,u-boot-spl.lds -Wl,-Bstatic -Wl,--gc-sections
> > > -Wl,--no-dynamic-linker -Wl,--build-id=none -Wl,-Ttext -Wl,0x00908000
> > > arch/arm/cpu/armv7/start.o -Wl,--whole-archive
> > > arch/arm/cpu/armv7/built-in.o arch/arm/cpu/built-in.o
> > > arch/arm/lib/built-in.o arch/arm/mach-imx/built-in.o
> > > board/bticino/mamoj/built-in.o common/spl/built-in.o
> > > common/init/built-in.o boot/built-in.o common/built-in.o
> > > cmd/built-in.o env/built-in.o lib/built-in.o disk/built-in.o
> > > drivers/built-in.o drivers/usb/dwc3/built-in.o
> > > drivers/usb/cdns3/built-in.o dts/built-in.o fs/built-in.o
> > > keep-syms-lto.o arch/arm/lib/eabi_compat.o arch/arm/lib/lib.a
> > > -Wl,--no-whole-archive -Wl,-Map,u-boot-spl.map -o u-boot-spl )
> > > arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
> > > .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
> > > .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
> > > .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -O binary
> > > spl/u-boot-spl spl/u-boot-spl-nodtb.bin
> > > arm-linux-gnueabihf-objdump -t spl/u-boot-spl > spl/u-boot-spl.sym
> > > cat spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb > spl/u-boot-spl-dtb.bin
> > > cp spl/u-boot-spl-dtb.bin spl/u-boot-spl.bin
> > > spl/u-boot-spl.bin exceeds file size limit:
> > > limit: 0xefa0 bytes
> > > actual: 0xf079 bytes
> > > excess: 0xd9 bytes
> > > make: *** [Makefile:2082: spl/u-boot-spl.bin] Error 1
> > > make: *** Deleting file 'spl/u-boot-spl.bin'
> > >
> > > and without
> > >
> > > NUX_ARM_ARCH__=7 -mtune=generic-armv7-a -D__ASSEMBLY__ -x c -o
> > > spl/u-boot-spl.cfgout arch/arm/mach-imx/spl_sd.cfg
> > > ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e 0x00908000
> > > -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
> > > Image Type: Freescale IMX Boot Image
> > > Image Ver: 2 (i.MX53/6/7 compatible)
> > > Mode: DCD
> > > Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
> > > Load Address: 00907420
> > > Entry Point: 00908000
> > > HAB Blocks: 0x00907400 0x00000000 0x0000fc00
> > > DCD Blocks: 0x00910000 0x0000002c 0x00000004
> > > make -f ./scripts/Makefile.build obj=arch/arm/mach-imx u-boot-with-spl.imx
> > > mkdir -p spl/
> > > ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e 0x00908000
> > > -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
> > > Image Type: Freescale IMX Boot Image
> > > Image Ver: 2 (i.MX53/6/7 compatible)
> > > Mode: DCD
> > > Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
> > > Load Address: 00907420
> > > Entry Point: 00908000
> > > HAB Blocks: 0x00907400 0x00000000 0x0000fc00
> > > DCD Blocks: 0x00910000 0x0000002c 0x00000004
> > > arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
> > > .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
> > > .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
> > > .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -I binary -O
> > > binary --pad-to=0x11000 SPL u-boot-with-spl.imx && cat u-boot.img >>
> > > u-boot-with-spl.imx || rm -f u-boot-with-spl.imx
> > >
> > >
> > > What I'm trying to say is that I have followed the correct steps and
> > > this is the LTO change
> > >
> > > git diff
> > > diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
> > > index ae27857e6f..4a535012b2 100644
> > > --- a/configs/imx6dl_mamoj_defconfig
> > > +++ b/configs/imx6dl_mamoj_defconfig
> > > @@ -14,6 +14,7 @@ CONFIG_SPL_TEXT_BASE=0x00908000
> > > CONFIG_SPL_DRIVERS_MISC=y
> > > CONFIG_IMX_HAB=y
> > > # CONFIG_CMD_BMODE is not set
> > > +CONFIG_LTO=y
> > > CONFIG_DISTRO_DEFAULTS=y
> > > CONFIG_BOOTDELAY=3
> > > CONFIG_SPL_OS_BOOT=y
> >
> > Here's what I see:
> > $ git describe HEAD
> > v2022.04-rc4-50-g9776c4e9d00a
> > $ make imx6dl_mamoj_defconfig
> > HOSTCC scripts/basic/fixdep
> > HOSTCC scripts/kconfig/conf.o
> > YACC scripts/kconfig/zconf.tab.c
> > LEX scripts/kconfig/zconf.lex.c
> > HOSTCC scripts/kconfig/zconf.tab.o
> > HOSTLD scripts/kconfig/conf
> > #
> > # configuration written to .config
> > #
> > $ sed -i -e 's/# CONFIG_LTO is not set/CONFIG_LTO=y/' .config
> > $ grep LTO .config
> > CONFIG_ARCH_SUPPORTS_LTO=y
> > CONFIG_LTO=y
> > $ make CROSS_COMPILE=~/.buildman-toolchains/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi- -sj12
> > ===================== WARNING ======================
> > This board does not use CONFIG_DM_SERIAL (Driver Model
> > for Serial drivers). Please update the board to use
> > CONFIG_DM_SERIAL before the v2023.04 release. Failure to
> > update by the deadline may result in board removal.
> > See doc/driver-model/migration.rst for more info.
> > ====================================================
> > arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl:pwms: cell 3 is not a phandle reference
> > arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl: Missing property '#pwm-cells' in node /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from pwms[3])
> > arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl:pwms: cell 3 is not a phandle reference
> > arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl: Missing property '#pwm-cells' in node /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from pwms[3])
> > $ ls -lh spl/u-boot-spl*
> > -rwxrwxr-x 1 trini trini 944K Mar 19 13:40 spl/u-boot-spl
> > -rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl.bin
> > -rw-rw-r-- 1 trini trini 1.6K Mar 19 13:40 spl/u-boot-spl.cfgout
> > -rw-rw-r-- 1 trini trini 2.2K Mar 19 13:40 spl/u-boot-spl.dtb
> > -rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl-dtb.bin
> > -rw-rw-r-- 1 trini trini 728 Mar 19 13:40 spl/u-boot-spl.lds
> > -rw-rw-r-- 1 trini trini 5.9K Mar 19 13:40 spl/u-boot-spl.ltrans0.ltrans.su
> > -rw-rw-r-- 1 trini trini 7.2K Mar 19 13:40 spl/u-boot-spl.ltrans1.ltrans.su
> > -rw-rw-r-- 1 trini trini 182K Mar 19 13:40 spl/u-boot-spl.map
> > -rwxrwxr-x 1 trini trini 51K Mar 19 13:40 spl/u-boot-spl-nodtb.bin
> > -rw-rw-r-- 1 trini trini 135K Mar 19 13:40 spl/u-boot-spl.sym
> >
>
> The only difference is the toolchain gcc version 9.4.0 (Ubuntu
> 9.4.0-1ubuntu1~20.04) and for the result you get I'm agree with you.
Yeah, that's too old of a toolchain for LTO to be usable. A patch to
catch and error out in that case would be good :)
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 17:51 ` Tom Rini
@ 2022-03-19 18:00 ` Michael Nazzareno Trimarchi
2022-03-19 18:33 ` R: " Raffaele RECALCATI
2022-03-23 12:06 ` Gaurav Jain
0 siblings, 2 replies; 69+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-03-19 18:00 UTC (permalink / raw)
To: Tom Rini
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
HI Tom
On Sat, Mar 19, 2022 at 6:51 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Sat, Mar 19, 2022 at 06:49:25PM +0100, Michael Nazzareno Trimarchi wrote:
> > HI Tom
> >
> > On Sat, Mar 19, 2022 at 6:44 PM Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Sat, Mar 19, 2022 at 06:37:18PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > Hi Tom
> > > >
> > > > On Sat, Mar 19, 2022 at 6:30 PM Tom Rini <trini@konsulko.com> wrote:
> > > > >
> > > > > On Sat, Mar 19, 2022 at 06:27:38PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > Hi
> > > > > >
> > > > > > On Sat, Mar 19, 2022 at 6:25 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > > >
> > > > > > > On Sat, Mar 19, 2022 at 06:08:18PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > > > Hi Tom
> > > > > > > >
> > > > > > > > On Sat, Mar 19, 2022 at 6:03 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > > > > >
> > > > > > > > > On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > > > > > Hi Tom
> > > > > > > > > >
> > > > > > > > > > On Sat, Mar 19, 2022 at 5:05 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > > > > > > >
> > > > > > > > > > > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
> > > > > > > > > > > > Hi
> > > > > > > > > > > >
> > > > > > > > > > > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> > > > > > > > > > > > >
> > > > > > > > > > > > > Hi Michael,
> > > > > > > > > > > > >
> > > > > > > > > > > > > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
> > > > > > > > > > > > > <michael@amarulasolutions.com> wrote:
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > HI
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > Please send me a link to apply your series
> > > > > > > > > > > > >
> > > > > > > > > > > > > You can get the series from patchwork (just click in the 'series' button)
> > > > > > > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220112133127.16880-2-gaurav.jain@nxp.com/
> > > > > > > > > > > >
> > > > > > > > > > > > Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
> > > > > > > > > > > > remove a lot of features. I have tested LTO build but size
> > > > > > > > > > > > of SPL increase. Is that strange?
> > > > > > > > > > >
> > > > > > > > > > > That is very strange. Can you post your patches somewhere?
> > > > > > > > > > >
> > > > > > > > > > > --
> > > > > > > > > > > Tom
> > > > > > > > > >
> > > > > > > > > > Start from here 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
> > > > > > > > > > export ARCH=arm
> > > > > > > > > > export CROSS_COMPILE=arm-linux-gnueabihf-
> > > > > > > > > >
> > > > > > > > > > make imx6dl_mamoj_defconfig
> > > > > > > > > > build it
> > > > > > > > > >
> > > > > > > > > > Try then to enable LTO and build it again
> > > > > > > > > >
> > > > > > > > > > spl/u-boot-spl.bin exceeds file size limit:
> > > > > > > > > > limit: 0xefa0 bytes
> > > > > > > > > > actual: 0xf071 bytes
> > > > > > > > > > excess: 0xd1 bytes
> > > > > > > > > >
> > > > > > > > > > So LTO does not help even on beginning on this board. You don't need
> > > > > > > > > > to apply any patch for this test
> > > > > > > > >
> > > > > > > > > I think that's some artifact of mixing LTO/non-LTO and the world not
> > > > > > > > > getting rebuilt? Just enabling LTO after the defconfig works fine and
> > > > > > > > > is smaller than before.
> > > > > > > >
> > > > > > > > In order to save space I did not change what we have. Every build starts from
> > > > > > > > a mrproper and new configuration. I can not mix LTO/non-LTO in this case. I'm
> > > > > > > > using upstream defconfig and upstream defconfig + LTO enabled and the result is
> > > > > > > > that spl increase in size for LTO building. I'm working to keep out
> > > > > > > > part that are not really needed but
> > > > > > > > I was hoping that LTO give me some help here
> > > > > > >
> > > > > > > Yes, LTO saves about 5KiB on the SPL binary. You just need to enable it
> > > > > > > in the config before you start building, not after you've built
> > > > > > > everything once.
> > > > > >
> > > > > > Offcourse ;) but this not the case. I don't drink enough to think that
> > > > > > change a config, decrease the build size ;)
> > > > >
> > > > > LTO is an entirely different way of the compiler / linker optimizing the
> > > > > binary. So yes, in this case enabling a single option decreases the
> > > > > size.
> > > >
> > > >
> > > > I think we are in a circle. Let's have the result with LTO
> > > >
> > > > spl/keep-syms-lto.c
> > > > ( cd spl && arm-linux-gnueabihf-gcc -nostdlib -nostartfiles
> > > > -fuse-linker-plugin -flto=8 -Wall -Wstrict-prototypes
> > > > -Wno-format-security -fno-builtin -ffreestanding -std=gnu11
> > > > -fshort-wchar -fno-strict-aliasing -fno-PIE -Os -flto=8
> > > > -fno-stack-protector -fno-delete-null-pointer-checks -Wno-pointer-sign
> > > > -Wno-stringop-truncation -Wno-array-bounds -Wno-stringop-overflow
> > > > -Wno-maybe-uninitialized -fmacro-prefix-map=./= -g -fstack-usage
> > > > -Wno-format-nonliteral -Wno-address-of-packed-member
> > > > -Wno-unused-but-set-variable -Werror=date-time -Wno-packed-not-aligned
> > > > -ffunction-sections -fdata-sections -fno-stack-protector -D__KERNEL__
> > > > -D__UBOOT__ -DCONFIG_SPL_BUILD -D__ARM__ -Wa,-mimplicit-it=always
> > > > -mthumb -mthumb-interwork -mabi=aapcs-linux -mno-unaligned-access
> > > > -fno-common -ffixed-r9 -msoft-float -mgeneral-regs-only -pipe
> > > > -march=armv7-a -D__LINUX_ARM_ARCH__=7 -mtune=generic-armv7-a
> > > > -Ispl/include -Iinclude -I./arch/arm/include -include
> > > > ./include/linux/kconfig.h -nostdinc -isystem
> > > > /usr/lib/gcc-cross/arm-linux-gnueabihf/9/include -Wl,-T
> > > > -Wl,u-boot-spl.lds -Wl,-Bstatic -Wl,--gc-sections
> > > > -Wl,--no-dynamic-linker -Wl,--build-id=none -Wl,-Ttext -Wl,0x00908000
> > > > arch/arm/cpu/armv7/start.o -Wl,--whole-archive
> > > > arch/arm/cpu/armv7/built-in.o arch/arm/cpu/built-in.o
> > > > arch/arm/lib/built-in.o arch/arm/mach-imx/built-in.o
> > > > board/bticino/mamoj/built-in.o common/spl/built-in.o
> > > > common/init/built-in.o boot/built-in.o common/built-in.o
> > > > cmd/built-in.o env/built-in.o lib/built-in.o disk/built-in.o
> > > > drivers/built-in.o drivers/usb/dwc3/built-in.o
> > > > drivers/usb/cdns3/built-in.o dts/built-in.o fs/built-in.o
> > > > keep-syms-lto.o arch/arm/lib/eabi_compat.o arch/arm/lib/lib.a
> > > > -Wl,--no-whole-archive -Wl,-Map,u-boot-spl.map -o u-boot-spl )
> > > > arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
> > > > .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
> > > > .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
> > > > .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -O binary
> > > > spl/u-boot-spl spl/u-boot-spl-nodtb.bin
> > > > arm-linux-gnueabihf-objdump -t spl/u-boot-spl > spl/u-boot-spl.sym
> > > > cat spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb > spl/u-boot-spl-dtb.bin
> > > > cp spl/u-boot-spl-dtb.bin spl/u-boot-spl.bin
> > > > spl/u-boot-spl.bin exceeds file size limit:
> > > > limit: 0xefa0 bytes
> > > > actual: 0xf079 bytes
> > > > excess: 0xd9 bytes
> > > > make: *** [Makefile:2082: spl/u-boot-spl.bin] Error 1
> > > > make: *** Deleting file 'spl/u-boot-spl.bin'
> > > >
> > > > and without
> > > >
> > > > NUX_ARM_ARCH__=7 -mtune=generic-armv7-a -D__ASSEMBLY__ -x c -o
> > > > spl/u-boot-spl.cfgout arch/arm/mach-imx/spl_sd.cfg
> > > > ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e 0x00908000
> > > > -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
> > > > Image Type: Freescale IMX Boot Image
> > > > Image Ver: 2 (i.MX53/6/7 compatible)
> > > > Mode: DCD
> > > > Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
> > > > Load Address: 00907420
> > > > Entry Point: 00908000
> > > > HAB Blocks: 0x00907400 0x00000000 0x0000fc00
> > > > DCD Blocks: 0x00910000 0x0000002c 0x00000004
> > > > make -f ./scripts/Makefile.build obj=arch/arm/mach-imx u-boot-with-spl.imx
> > > > mkdir -p spl/
> > > > ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e 0x00908000
> > > > -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
> > > > Image Type: Freescale IMX Boot Image
> > > > Image Ver: 2 (i.MX53/6/7 compatible)
> > > > Mode: DCD
> > > > Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
> > > > Load Address: 00907420
> > > > Entry Point: 00908000
> > > > HAB Blocks: 0x00907400 0x00000000 0x0000fc00
> > > > DCD Blocks: 0x00910000 0x0000002c 0x00000004
> > > > arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
> > > > .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
> > > > .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
> > > > .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -I binary -O
> > > > binary --pad-to=0x11000 SPL u-boot-with-spl.imx && cat u-boot.img >>
> > > > u-boot-with-spl.imx || rm -f u-boot-with-spl.imx
> > > >
> > > >
> > > > What I'm trying to say is that I have followed the correct steps and
> > > > this is the LTO change
> > > >
> > > > git diff
> > > > diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
> > > > index ae27857e6f..4a535012b2 100644
> > > > --- a/configs/imx6dl_mamoj_defconfig
> > > > +++ b/configs/imx6dl_mamoj_defconfig
> > > > @@ -14,6 +14,7 @@ CONFIG_SPL_TEXT_BASE=0x00908000
> > > > CONFIG_SPL_DRIVERS_MISC=y
> > > > CONFIG_IMX_HAB=y
> > > > # CONFIG_CMD_BMODE is not set
> > > > +CONFIG_LTO=y
> > > > CONFIG_DISTRO_DEFAULTS=y
> > > > CONFIG_BOOTDELAY=3
> > > > CONFIG_SPL_OS_BOOT=y
> > >
> > > Here's what I see:
> > > $ git describe HEAD
> > > v2022.04-rc4-50-g9776c4e9d00a
> > > $ make imx6dl_mamoj_defconfig
> > > HOSTCC scripts/basic/fixdep
> > > HOSTCC scripts/kconfig/conf.o
> > > YACC scripts/kconfig/zconf.tab.c
> > > LEX scripts/kconfig/zconf.lex.c
> > > HOSTCC scripts/kconfig/zconf.tab.o
> > > HOSTLD scripts/kconfig/conf
> > > #
> > > # configuration written to .config
> > > #
> > > $ sed -i -e 's/# CONFIG_LTO is not set/CONFIG_LTO=y/' .config
> > > $ grep LTO .config
> > > CONFIG_ARCH_SUPPORTS_LTO=y
> > > CONFIG_LTO=y
> > > $ make CROSS_COMPILE=~/.buildman-toolchains/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi- -sj12
> > > ===================== WARNING ======================
> > > This board does not use CONFIG_DM_SERIAL (Driver Model
> > > for Serial drivers). Please update the board to use
> > > CONFIG_DM_SERIAL before the v2023.04 release. Failure to
> > > update by the deadline may result in board removal.
> > > See doc/driver-model/migration.rst for more info.
> > > ====================================================
> > > arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl:pwms: cell 3 is not a phandle reference
> > > arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl: Missing property '#pwm-cells' in node /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from pwms[3])
> > > arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl:pwms: cell 3 is not a phandle reference
> > > arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl: Missing property '#pwm-cells' in node /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from pwms[3])
> > > $ ls -lh spl/u-boot-spl*
> > > -rwxrwxr-x 1 trini trini 944K Mar 19 13:40 spl/u-boot-spl
> > > -rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl.bin
> > > -rw-rw-r-- 1 trini trini 1.6K Mar 19 13:40 spl/u-boot-spl.cfgout
> > > -rw-rw-r-- 1 trini trini 2.2K Mar 19 13:40 spl/u-boot-spl.dtb
> > > -rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl-dtb.bin
> > > -rw-rw-r-- 1 trini trini 728 Mar 19 13:40 spl/u-boot-spl.lds
> > > -rw-rw-r-- 1 trini trini 5.9K Mar 19 13:40 spl/u-boot-spl.ltrans0.ltrans.su
> > > -rw-rw-r-- 1 trini trini 7.2K Mar 19 13:40 spl/u-boot-spl.ltrans1.ltrans.su
> > > -rw-rw-r-- 1 trini trini 182K Mar 19 13:40 spl/u-boot-spl.map
> > > -rwxrwxr-x 1 trini trini 51K Mar 19 13:40 spl/u-boot-spl-nodtb.bin
> > > -rw-rw-r-- 1 trini trini 135K Mar 19 13:40 spl/u-boot-spl.sym
> > >
> >
> > The only difference is the toolchain gcc version 9.4.0 (Ubuntu
> > 9.4.0-1ubuntu1~20.04) and for the result you get I'm agree with you.
>
> Yeah, that's too old of a toolchain for LTO to be usable. A patch to
> catch and error out in that case would be good :)
Let's do it this way. I will test with the newer gcc version and
decrease the size and send a patch.
This can be done on Monday, because I don't have access to it.
Michael
>
> --
> Tom
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 69+ messages in thread
* R: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 18:00 ` Michael Nazzareno Trimarchi
@ 2022-03-19 18:33 ` Raffaele RECALCATI
2022-03-23 12:06 ` Gaurav Jain
1 sibling, 0 replies; 69+ messages in thread
From: Raffaele RECALCATI @ 2022-03-19 18:33 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi, Tom Rini
Cc: Fabio Estevam, Gaurav Jain, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Jagan Teki
Hi Michael,
>HI Tom
>
>On Sat, Mar 19, 2022 at 6:51 PM Tom Rini <trini@konsulko.com> wrote:
>>
>> On Sat, Mar 19, 2022 at 06:49:25PM +0100, Michael Nazzareno Trimarchi wrote:
>> > HI Tom
>> >
>> > On Sat, Mar 19, 2022 at 6:44 PM Tom Rini <trini@konsulko.com> wrote:
>> > >
>> > > On Sat, Mar 19, 2022 at 06:37:18PM +0100, Michael Nazzareno Trimarchi wrote:
>> > > > Hi Tom
>> > > >
>> > > > On Sat, Mar 19, 2022 at 6:30 PM Tom Rini <trini@konsulko.com> wrote:
>> > > > >
>> > > > > On Sat, Mar 19, 2022 at 06:27:38PM +0100, Michael Nazzareno Trimarchi wrote:
>> > > > > > Hi
>> > > > > >
>> > > > > > On Sat, Mar 19, 2022 at 6:25 PM Tom Rini <trini@konsulko.com> wrote:
>> > > > > > >
>> > > > > > > On Sat, Mar 19, 2022 at 06:08:18PM +0100, Michael Nazzareno Trimarchi wrote:
>> > > > > > > > Hi Tom
>>> > > > > > > >
>>> > > > > > > > On Sat, Mar 19, 2022 at 6:03 PM Tom Rini <trini@konsulko.com> wrote:
>>> > > > > > > > >
>>>> > > > > > > > > On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno Trimarchi wrote:
>>>> > > > > > > > > > Hi Tom
>>> > > > > > > > > >
>>> > > > > > > > > > On Sat, Mar 19, 2022 at 5:05 PM Tom Rini <trini@konsulko.com> wrote:
>> > > > > > > > > > >
>> > > > > > > > > > > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael Nazzareno Trimarchi wrote:
>> > > > > > > > > > > > Hi
>> > > > > > > > > > > >
>> > > > > > > > > > > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam <festevam@gmail.com> wrote:
>> > > > > > > > > > > > >
>> > > > > > > > > > > > > Hi Michael,
>> > > > > > > > > > > > >
>> > > > > > > > > > > > > On Sat, Mar 19, 2022 at 6:47 AM Michael Nazzareno Trimarchi
>> > > > > > > > > > > > > <michael@amarulasolutions.com> wrote:
>> > > > > > > > > > > > > >
>> > > > > > > > > > > > > > HI
>> > > > > > > > > > > > > >
>> > > > > > > > > > > > > > Please send me a link to apply your series
>> > > > > > > > > > > > >
>> > > > > > > > > > > > > You can get the series from patchwork (just click in the 'series' button)
>> > > > > > > > > > > > > https://eur01.safelinks.protection.outlook.com/?>url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20220112133127.16880-2->gaurav.jain%40nxp.com%2F&data=04%7C01%7Craffaele.recalcati%40bticino.it%7Cd7b85983151448602>62808da09d260da%7C199686b5bef4496087867a6b1888fee3%7C1%7C0%7C637833096424290979%7CUnkn>own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C30>00&sdata=cLvLVUDGQzJ7VTyzBrTqOeobl0lgBOxJtmhV2RMjvB0%3D&reserved=0<https://eur01.safelinks.protection.outlook.com/?>url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F20220112133127.16880-2-gaurav.jain%40nxp.com%2F&data=04%7C01%7Craffaele.recalcati%40bticino.it%7Cd7b8598315144860262808da09d260da%7C199686b5bef4496087867a6b1888fee3%7C1%7C0%7C637833096424290979%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=cLvLVUDGQzJ7VTyzBrTqOeobl0lgBOxJtmhV2RMjvB0%3D&reserved=0>
>> > > > > > > > > > > >
>> > > > > > > > > > > > Done, well, I have tried remove DM_GPIO in SPL. Seems that I need to
>> > > > > > > > > > > > remove a lot of features. I have tested LTO build but size
>> > > > > > > > > > > > of SPL increase. Is that strange?
>> > > > > > > > > > >
>> > > > > > > > > > > That is very strange. Can you post your patches somewhere?
>> > > > > > > > > > >
>> > > > > > > > > > > --
>> > > > > > > > > > > Tom
>> > > > > > > > > >
>> > > > > > > > > > Start from here 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
>> > > > > > > > > > export ARCH=arm
>> > > > > > > > > > export CROSS_COMPILE=arm-linux-gnueabihf-
>> > > > > > > > > >
>> > > > > > > > > > make imx6dl_mamoj_defconfig
>> > > > > > > > > > build it
>> > > > > > > > > >
>> > > > > > > > > > Try then to enable LTO and build it again
>> > > > > > > > > >
>> > > > > > > > > > spl/u-boot-spl.bin exceeds file size limit:
>> > > > > > > > > > limit: 0xefa0 bytes
>> > > > > > > > > > actual: 0xf071 bytes
>> > > > > > > > > > excess: 0xd1 bytes
>> > > > > > > > > >
>> > > > > > > > > > So LTO does not help even on beginning on this board. You don't need
>> > > > > > > > > > to apply any patch for this test
>> > > > > > > > >
>> > > > > > > > > I think that's some artifact of mixing LTO/non-LTO and the world not
>> > > > > > > > > getting rebuilt? Just enabling LTO after the defconfig works fine and
>> > > > > > > > > is smaller than before.
>> > > > > > > >
>> > > > > > > > In order to save space I did not change what we have. Every build starts from
>> > > > > > > > a mrproper and new configuration. I can not mix LTO/non-LTO in this case. I'm
>> > > > > > > > using upstream defconfig and upstream defconfig + LTO enabled and the result is
>> > > > > > > > that spl increase in size for LTO building. I'm working to keep out
>> > > > > > > > part that are not really needed but
>> > > > > > > > I was hoping that LTO give me some help here
>> > > > > > >
>> > > > > > > Yes, LTO saves about 5KiB on the SPL binary. You just need to enable it
>> > > > > > > in the config before you start building, not after you've built
>> > > > > > > everything once.
>> > > > > >
>> > > > > > Offcourse ;) but this not the case. I don't drink enough to think that
>> > > > > > change a config, decrease the build size ;)
>> > > > >
>> > > > > LTO is an entirely different way of the compiler / linker optimizing the
>> > > > > binary. So yes, in this case enabling a single option decreases the
>> > > > > size.
>> > > >
>> > > >
>> > > > I think we are in a circle. Let's have the result with LTO
>> > > >
>> > > > spl/keep-syms-lto.c
>> > > > ( cd spl && arm-linux-gnueabihf-gcc -nostdlib -nostartfiles
>> > > > -fuse-linker-plugin -flto=8 -Wall -Wstrict-prototypes
>> > > > -Wno-format-security -fno-builtin -ffreestanding -std=gnu11
>> > > > -fshort-wchar -fno-strict-aliasing -fno-PIE -Os -flto=8
>> > > > -fno-stack-protector -fno-delete-null-pointer-checks -Wno-pointer-sign
>> > > > -Wno-stringop-truncation -Wno-array-bounds -Wno-stringop-overflow
>> > > > -Wno-maybe-uninitialized -fmacro-prefix-map=./= -g -fstack-usage
>> > > > -Wno-format-nonliteral -Wno-address-of-packed-member
>> > > > -Wno-unused-but-set-variable -Werror=date-time -Wno-packed-not-aligned
>> > > > -ffunction-sections -fdata-sections -fno-stack-protector -D__KERNEL__
>> > > > -D__UBOOT__ -DCONFIG_SPL_BUILD -D__ARM__ -Wa,-mimplicit-it=always
>> > > > -mthumb -mthumb-interwork -mabi=aapcs-linux -mno-unaligned-access
>> > > > -fno-common -ffixed-r9 -msoft-float -mgeneral-regs-only -pipe
>> > > > -march=armv7-a -D__LINUX_ARM_ARCH__=7 -mtune=generic-armv7-a
>> > > > -Ispl/include -Iinclude -I./arch/arm/include -include
>> > > > ./include/linux/kconfig.h -nostdinc -isystem
>> > > > /usr/lib/gcc-cross/arm-linux-gnueabihf/9/include -Wl,-T
>> > > > -Wl,u-boot-spl.lds -Wl,-Bstatic -Wl,--gc-sections
>> > > > -Wl,--no-dynamic-linker -Wl,--build-id=none -Wl,-Ttext -Wl,0x00908000
>> > > > arch/arm/cpu/armv7/start.o -Wl,--whole-archive
>> > > > arch/arm/cpu/armv7/built-in.o arch/arm/cpu/built-in.o
>> > > > arch/arm/lib/built-in.o arch/arm/mach-imx/built-in.o
>> > > > board/bticino/mamoj/built-in.o common/spl/built-in.o
>> > > > common/init/built-in.o boot/built-in.o common/built-in.o
>> > > > cmd/built-in.o env/built-in.o lib/built-in.o disk/built-in.o
>> > > > drivers/built-in.o drivers/usb/dwc3/built-in.o
>> > > > drivers/usb/cdns3/built-in.o dts/built-in.o fs/built-in.o
>> > > > keep-syms-lto.o arch/arm/lib/eabi_compat.o arch/arm/lib/lib.a
>> > > > -Wl,--no-whole-archive -Wl,-Map,u-boot-spl.map -o u-boot-spl )
>> > > > arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
>> > > > .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
>> > > > .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
>> > > > .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -O binary
>> > > > spl/u-boot-spl spl/u-boot-spl-nodtb.bin
>> > > > arm-linux-gnueabihf-objdump -t spl/u-boot-spl > spl/u-boot-spl.sym
>> > > > cat spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb > spl/u-boot-spl-dtb.bin
>> > > > cp spl/u-boot-spl-dtb.bin spl/u-boot-spl.bin
>> > > > spl/u-boot-spl.bin exceeds file size limit:
>> > > > limit: 0xefa0 bytes
>> > > > actual: 0xf079 bytes
>> > > > excess: 0xd9 bytes
>> > > > make: *** [Makefile:2082: spl/u-boot-spl.bin] Error 1
>> > > > make: *** Deleting file 'spl/u-boot-spl.bin'
>> > > >
>> > > > and without
>> > > >
>> > > > NUX_ARM_ARCH__=7 -mtune=generic-armv7-a -D__ASSEMBLY__ -x c -o
>> > > > spl/u-boot-spl.cfgout arch/arm/mach-imx/spl_sd.cfg
>> > > > ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e 0x00908000
>> > > > -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
>> > > > Image Type: Freescale IMX Boot Image
>> > > > Image Ver: 2 (i.MX53/6/7 compatible)
>> > > > Mode: DCD
>> > > > Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
>> > > > Load Address: 00907420
>> > > > Entry Point: 00908000
>> > > > HAB Blocks: 0x00907400 0x00000000 0x0000fc00
>> > > > DCD Blocks: 0x00910000 0x0000002c 0x00000004
>> > > > make -f ./scripts/Makefile.build obj=arch/arm/mach-imx u-boot-with-spl.imx
>> > > > mkdir -p spl/
>> > > > ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e 0x00908000
>> > > > -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
>> > > > Image Type: Freescale IMX Boot Image
>> > > > Image Ver: 2 (i.MX53/6/7 compatible)
>> > > > Mode: DCD
>> > > > Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
>> > > > Load Address: 00907420
>> > > > Entry Point: 00908000
>> > > > HAB Blocks: 0x00907400 0x00000000 0x0000fc00
>> > > > DCD Blocks: 0x00910000 0x0000002c 0x00000004
>> > > > arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
>> > > > .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
>> > > > .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
>> > > > .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -I binary -O
>> > > > binary --pad-to=0x11000 SPL u-boot-with-spl.imx && cat u-boot.img >>
>> > > > u-boot-with-spl.imx || rm -f u-boot-with-spl.imx
>> > > >
>> > > >
>> > > > What I'm trying to say is that I have followed the correct steps and
>> > > > this is the LTO change
>> > > >
>> > > > git diff
>> > > > diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
>> > > > index ae27857e6f..4a535012b2 100644
>> > > > --- a/configs/imx6dl_mamoj_defconfig
>> > > > +++ b/configs/imx6dl_mamoj_defconfig
>> > > > @@ -14,6 +14,7 @@ CONFIG_SPL_TEXT_BASE=0x00908000
>> > > > CONFIG_SPL_DRIVERS_MISC=y
>> > > > CONFIG_IMX_HAB=y
>> > > > # CONFIG_CMD_BMODE is not set
>> > > > +CONFIG_LTO=y
>> > > > CONFIG_DISTRO_DEFAULTS=y
>> > > > CONFIG_BOOTDELAY=3
>> > > > CONFIG_SPL_OS_BOOT=y
>> > >
>> > > Here's what I see:
>> > > $ git describe HEAD
>> > > v2022.04-rc4-50-g9776c4e9d00a
>> > > $ make imx6dl_mamoj_defconfig
>> > > HOSTCC scripts/basic/fixdep
>> > > HOSTCC scripts/kconfig/conf.o
>> > > YACC scripts/kconfig/zconf.tab.c
>> > > LEX scripts/kconfig/zconf.lex.c
>> > > HOSTCC scripts/kconfig/zconf.tab.o
>> > > HOSTLD scripts/kconfig/conf
>> > > #
>> > > # configuration written to .config
>> > > #
>> > > $ sed -i -e 's/# CONFIG_LTO is not set/CONFIG_LTO=y/' .config
>> > > $ grep LTO .config
>> > > CONFIG_ARCH_SUPPORTS_LTO=y
>> > > CONFIG_LTO=y
>> > > $ make CROSS_COMPILE=~/.buildman-toolchains/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-l>
>linux-gnueabi- -sj12
>> > > ===================== WARNING ======================
>> > > This board does not use CONFIG_DM_SERIAL (Driver Model
>> > > for Serial drivers). Please update the board to use
>> > > CONFIG_DM_SERIAL before the v2023.04 release. Failure to
>> > > update by the deadline may result in board removal.
>> > > See doc/driver-model/migration.rst for more info.
>> > > ====================================================
>> > > arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl:pwms: cell 3 is not a >phandle reference
>> > > arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl: Missing property '#pwm-cells' in node /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from pwms[3])
>> > > arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl:pwms: cell 3 is not a phandle reference
>> > > arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property): /display-bl: Missing property '>#pwm-cells' in node /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from pwms[3])
>> > > $ ls -lh spl/u-boot-spl*
> >> > -rwxrwxr-x 1 trini trini 944K Mar 19 13:40 spl/u-boot-spl
> >> > -rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl.bin
> >> > -rw-rw-r-- 1 trini trini 1.6K Mar 19 13:40 spl/u-boot-spl.cfgout
> >> > -rw-rw-r-- 1 trini trini 2.2K Mar 19 13:40 spl/u-boot-spl.dtb
> >> > -rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl-dtb.bin
> >> > -rw-rw-r-- 1 trini trini 728 Mar 19 13:40 spl/u-boot-spl.lds
> >> > -rw-rw-r-- 1 trini trini 5.9K Mar 19 13:40 spl/u-boot-spl.ltrans0.ltrans.su
> >> > -rw-rw-r-- 1 trini trini 7.2K Mar 19 13:40 spl/u-boot-spl.ltrans1.ltrans.su
> >> > -rw-rw-r-- 1 trini trini 182K Mar 19 13:40 spl/u-boot-spl.map
> >> > -rwxrwxr-x 1 trini trini 51K Mar 19 13:40 spl/u-boot-spl-nodtb.bin
>> > > -rw-rw-r-- 1 trini trini 135K Mar 19 13:40 spl/u-boot-spl.sym
>> > >
>> >
>> > The only difference is the toolchain gcc version 9.4.0 (Ubuntu
>> > 9.4.0-1ubuntu1~20.04) and for the result you get I'm agree with you.
>>
>> Yeah, that's too old of a toolchain for LTO to be usable. A patch to
>> catch and error out in that case would be good :)
>
>Let's do it this way. I will test with the newer gcc version and
>decrease the size and send a patch.
>This can be done on Monday, because I don't have access to it.
>
>Michael
I can test on the board if needed.
Let me know.
>
> --
> Tom
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.amarulasolutions.com%2F&data=04%7C01%7Craffaele.recalcati%40bticino.it%7Cd7b8598315144860262808da09d260da%7C199686b5bef4496087867a6b1888fee3%7C1%7C0%7C637833096424290979%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=6zWfMb%2Bt6h3CDq2Ktm4l3WRr24KqfP%2BaAMlNb%2F4xsxM%3D&reserved=0
________________________________
Ce message, ainsi que tous les fichiers joints à ce message, peuvent contenir des informations sensibles et/ ou confidentielles ne devant pas être divulguées. Si vous n'êtes pas le destinataire de ce message (ou que vous recevez ce message par erreur), nous vous remercions de le notifier immédiatement à son expéditeur, et de détruire ce message. Toute copie, divulgation, modification, utilisation ou diffusion, non autorisée, directe ou indirecte, de tout ou partie de ce message, est strictement interdite.
This e-mail, and any document attached hereby, may contain confidential and/or privileged information. If you are not the intended recipient (or have received this e-mail in error) please notify the sender immediately and destroy this e-mail. Any unauthorized, direct or indirect, copying, disclosure, distribution or other use of the material or parts thereof is strictly forbidden.
^ permalink raw reply [flat|nested] 69+ messages in thread
* RE: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-19 18:00 ` Michael Nazzareno Trimarchi
2022-03-19 18:33 ` R: " Raffaele RECALCATI
@ 2022-03-23 12:06 ` Gaurav Jain
2022-03-23 12:45 ` Michael Nazzareno Trimarchi
1 sibling, 1 reply; 69+ messages in thread
From: Gaurav Jain @ 2022-03-23 12:06 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi, Tom Rini
Cc: Fabio Estevam, Stefano Babic, Michael Walle, Varun Sethi,
Adrian Alonso, Alison Wang, Andy Tang, Franck Lenormand,
Horia Geanta, Ji Luo, marex, Meenakshi Aggarwal, Mingkai Hu,
olteanv, Pankaj Gupta, Peng Fan, Pramod Kumar, Priyanka Jain,
Rajesh Bhagat, Sahil Malhotra, Shengzhou Liu, Silvano Di Ninno,
sjg, u-boot, dl-uboot-imx, Wasim Khan, Ye Li, Raffaele RECALCATI,
Jagan Teki
Hi Michael
> -----Original Message-----
> From: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
> Sent: Saturday, March 19, 2022 11:30 PM
> To: Tom Rini <trini@konsulko.com>
> Cc: Fabio Estevam <festevam@gmail.com>; Gaurav Jain
> <gaurav.jain@nxp.com>; Stefano Babic <sbabic@denx.de>; Michael Walle
> <michael@walle.cc>; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy Tang
> <andy.tang@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>;
> Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>;
> marex@denx.de; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Rajesh
> Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Shengzhou Liu <shengzhou.liu@nxp.com>; Silvano Di Ninno
> <silvano.dininno@nxp.com>; sjg@chromium.org; u-boot@lists.denx.de; dl-
> uboot-imx <uboot-imx@nxp.com>; Wasim Khan <wasim.khan@nxp.com>; Ye Li
> <ye.li@nxp.com>; Raffaele RECALCATI <raffaele.recalcati@bticino.it>; Jagan
> Teki <jagan@amarulasolutions.com>
> Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> ring driver model
>
> Caution: EXT Email
>
> HI Tom
>
> On Sat, Mar 19, 2022 at 6:51 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Sat, Mar 19, 2022 at 06:49:25PM +0100, Michael Nazzareno Trimarchi
> wrote:
> > > HI Tom
> > >
> > > On Sat, Mar 19, 2022 at 6:44 PM Tom Rini <trini@konsulko.com> wrote:
> > > >
> > > > On Sat, Mar 19, 2022 at 06:37:18PM +0100, Michael Nazzareno Trimarchi
> wrote:
> > > > > Hi Tom
> > > > >
> > > > > On Sat, Mar 19, 2022 at 6:30 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > >
> > > > > > On Sat, Mar 19, 2022 at 06:27:38PM +0100, Michael Nazzareno
> Trimarchi wrote:
> > > > > > > Hi
> > > > > > >
> > > > > > > On Sat, Mar 19, 2022 at 6:25 PM Tom Rini <trini@konsulko.com>
> wrote:
> > > > > > > >
> > > > > > > > On Sat, Mar 19, 2022 at 06:08:18PM +0100, Michael Nazzareno
> Trimarchi wrote:
> > > > > > > > > Hi Tom
> > > > > > > > >
> > > > > > > > > On Sat, Mar 19, 2022 at 6:03 PM Tom Rini <trini@konsulko.com>
> wrote:
> > > > > > > > > >
> > > > > > > > > > On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno
> Trimarchi wrote:
> > > > > > > > > > > Hi Tom
> > > > > > > > > > >
> > > > > > > > > > > On Sat, Mar 19, 2022 at 5:05 PM Tom Rini
> <trini@konsulko.com> wrote:
> > > > > > > > > > > >
> > > > > > > > > > > > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael
> Nazzareno Trimarchi wrote:
> > > > > > > > > > > > > Hi
> > > > > > > > > > > > >
> > > > > > > > > > > > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam
> <festevam@gmail.com> wrote:
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > Hi Michael,
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > On Sat, Mar 19, 2022 at 6:47 AM Michael
> > > > > > > > > > > > > > Nazzareno Trimarchi <michael@amarulasolutions.com>
> wrote:
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > HI
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > Please send me a link to apply your series
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > You can get the series from patchwork (just
> > > > > > > > > > > > > > click in the 'series' button)
> > > > > > > > > > > > > > https://eur01.safelinks.protection.outlook.com
> > > > > > > > > > > > > > /?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpro
> > > > > > > > > > > > > > ject%2Fuboot%2Fpatch%2F20220112133127.16880-2-
> > > > > > > > > > > > > > gaurav.jain%40nxp.com%2F&data=04%7C01%7Cga
> > > > > > > > > > > > > > urav.jain%40nxp.com%7Cf2e5639efe9e491287e008da
> > > > > > > > > > > > > > 09d260f9%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C
> > > > > > > > > > > > > >
> 0%7C0%7C637833096989631395%7CUnknown%7CTWFpbGZ
> > > > > > > > > > > > > > sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBT
> > > > > > > > > > > > > > iI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=Sv5
> > > > > > > > > > > > > >
> W81K1CO1KdNO%2FW8v4cCrqK4gLC0IoChfHYmHSEZM%3D&
> > > > > > > > > > > > > > amp;reserved=0
> > > > > > > > > > > > >
> > > > > > > > > > > > > Done, well, I have tried remove DM_GPIO in SPL.
> > > > > > > > > > > > > Seems that I need to remove a lot of features. I
> > > > > > > > > > > > > have tested LTO build but size of SPL increase. Is that
> strange?
> > > > > > > > > > > >
> > > > > > > > > > > > That is very strange. Can you post your patches somewhere?
> > > > > > > > > > > >
> > > > > > > > > > > > --
> > > > > > > > > > > > Tom
> > > > > > > > > > >
> > > > > > > > > > > Start from here
> > > > > > > > > > > 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
> > > > > > > > > > > export ARCH=arm
> > > > > > > > > > > export CROSS_COMPILE=arm-linux-gnueabihf-
> > > > > > > > > > >
> > > > > > > > > > > make imx6dl_mamoj_defconfig build it
> > > > > > > > > > >
> > > > > > > > > > > Try then to enable LTO and build it again
> > > > > > > > > > >
> > > > > > > > > > > spl/u-boot-spl.bin exceeds file size limit:
> > > > > > > > > > > limit: 0xefa0 bytes
> > > > > > > > > > > actual: 0xf071 bytes
> > > > > > > > > > > excess: 0xd1 bytes
> > > > > > > > > > >
> > > > > > > > > > > So LTO does not help even on beginning on this
> > > > > > > > > > > board. You don't need to apply any patch for this
> > > > > > > > > > > test
> > > > > > > > > >
> > > > > > > > > > I think that's some artifact of mixing LTO/non-LTO and
> > > > > > > > > > the world not getting rebuilt? Just enabling LTO
> > > > > > > > > > after the defconfig works fine and is smaller than before.
> > > > > > > > >
> > > > > > > > > In order to save space I did not change what we have.
> > > > > > > > > Every build starts from a mrproper and new
> > > > > > > > > configuration. I can not mix LTO/non-LTO in this case.
> > > > > > > > > I'm using upstream defconfig and upstream defconfig +
> > > > > > > > > LTO enabled and the result is that spl increase in size
> > > > > > > > > for LTO building. I'm working to keep out part that are
> > > > > > > > > not really needed but I was hoping that LTO give me some
> > > > > > > > > help here
> > > > > > > >
> > > > > > > > Yes, LTO saves about 5KiB on the SPL binary. You just
> > > > > > > > need to enable it in the config before you start building,
> > > > > > > > not after you've built everything once.
> > > > > > >
> > > > > > > Offcourse ;) but this not the case. I don't drink enough to
> > > > > > > think that change a config, decrease the build size ;)
> > > > > >
> > > > > > LTO is an entirely different way of the compiler / linker
> > > > > > optimizing the binary. So yes, in this case enabling a single
> > > > > > option decreases the size.
> > > > >
> > > > >
> > > > > I think we are in a circle. Let's have the result with LTO
> > > > >
> > > > > spl/keep-syms-lto.c
> > > > > ( cd spl && arm-linux-gnueabihf-gcc -nostdlib -nostartfiles
> > > > > -fuse-linker-plugin -flto=8 -Wall -Wstrict-prototypes
> > > > > -Wno-format-security -fno-builtin -ffreestanding -std=gnu11
> > > > > -fshort-wchar -fno-strict-aliasing -fno-PIE -Os -flto=8
> > > > > -fno-stack-protector -fno-delete-null-pointer-checks
> > > > > -Wno-pointer-sign -Wno-stringop-truncation -Wno-array-bounds
> > > > > -Wno-stringop-overflow -Wno-maybe-uninitialized
> > > > > -fmacro-prefix-map=./= -g -fstack-usage -Wno-format-nonliteral
> > > > > -Wno-address-of-packed-member -Wno-unused-but-set-variable
> > > > > -Werror=date-time -Wno-packed-not-aligned -ffunction-sections
> > > > > -fdata-sections -fno-stack-protector -D__KERNEL__ -D__UBOOT__
> > > > > -DCONFIG_SPL_BUILD -D__ARM__ -Wa,-mimplicit-it=always -mthumb -
> mthumb-interwork -mabi=aapcs-linux -mno-unaligned-access
> > > > > -fno-common -ffixed-r9 -msoft-float -mgeneral-regs-only -pipe
> > > > > -march=armv7-a -D__LINUX_ARM_ARCH__=7 -mtune=generic-armv7-a
> > > > > -Ispl/include -Iinclude -I./arch/arm/include -include
> > > > > ./include/linux/kconfig.h -nostdinc -isystem
> > > > > /usr/lib/gcc-cross/arm-linux-gnueabihf/9/include -Wl,-T
> > > > > -Wl,u-boot-spl.lds -Wl,-Bstatic -Wl,--gc-sections
> > > > > -Wl,--no-dynamic-linker -Wl,--build-id=none -Wl,-Ttext
> > > > > -Wl,0x00908000 arch/arm/cpu/armv7/start.o -Wl,--whole-archive
> > > > > arch/arm/cpu/armv7/built-in.o arch/arm/cpu/built-in.o
> > > > > arch/arm/lib/built-in.o arch/arm/mach-imx/built-in.o
> > > > > board/bticino/mamoj/built-in.o common/spl/built-in.o
> > > > > common/init/built-in.o boot/built-in.o common/built-in.o
> > > > > cmd/built-in.o env/built-in.o lib/built-in.o disk/built-in.o
> > > > > drivers/built-in.o drivers/usb/dwc3/built-in.o
> > > > > drivers/usb/cdns3/built-in.o dts/built-in.o fs/built-in.o
> > > > > keep-syms-lto.o arch/arm/lib/eabi_compat.o arch/arm/lib/lib.a
> > > > > -Wl,--no-whole-archive -Wl,-Map,u-boot-spl.map -o u-boot-spl )
> > > > > arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
> > > > > .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
> > > > > .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
> > > > > .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -O binary
> > > > > spl/u-boot-spl spl/u-boot-spl-nodtb.bin
> > > > > arm-linux-gnueabihf-objdump -t spl/u-boot-spl > spl/u-boot-spl.sym
> > > > > cat spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb > spl/u-boot-spl-dtb.bin
> > > > > cp spl/u-boot-spl-dtb.bin spl/u-boot-spl.bin
> > > > > spl/u-boot-spl.bin exceeds file size limit:
> > > > > limit: 0xefa0 bytes
> > > > > actual: 0xf079 bytes
> > > > > excess: 0xd9 bytes
> > > > > make: *** [Makefile:2082: spl/u-boot-spl.bin] Error 1
> > > > > make: *** Deleting file 'spl/u-boot-spl.bin'
> > > > >
> > > > > and without
> > > > >
> > > > > NUX_ARM_ARCH__=7 -mtune=generic-armv7-a -D__ASSEMBLY__ -x c -
> o
> > > > > spl/u-boot-spl.cfgout arch/arm/mach-imx/spl_sd.cfg
> > > > > ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e
> > > > > 0x00908000 -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
> > > > > Image Type: Freescale IMX Boot Image
> > > > > Image Ver: 2 (i.MX53/6/7 compatible)
> > > > > Mode: DCD
> > > > > Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
> > > > > Load Address: 00907420
> > > > > Entry Point: 00908000
> > > > > HAB Blocks: 0x00907400 0x00000000 0x0000fc00
> > > > > DCD Blocks: 0x00910000 0x0000002c 0x00000004
> > > > > make -f ./scripts/Makefile.build obj=arch/arm/mach-imx
> > > > > u-boot-with-spl.imx mkdir -p spl/
> > > > > ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e
> > > > > 0x00908000 -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
> > > > > Image Type: Freescale IMX Boot Image
> > > > > Image Ver: 2 (i.MX53/6/7 compatible)
> > > > > Mode: DCD
> > > > > Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
> > > > > Load Address: 00907420
> > > > > Entry Point: 00908000
> > > > > HAB Blocks: 0x00907400 0x00000000 0x0000fc00
> > > > > DCD Blocks: 0x00910000 0x0000002c 0x00000004
> > > > > arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
> > > > > .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
> > > > > .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
> > > > > .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -I binary
> > > > > -O binary --pad-to=0x11000 SPL u-boot-with-spl.imx && cat
> > > > > u-boot.img >> u-boot-with-spl.imx || rm -f u-boot-with-spl.imx
> > > > >
> > > > >
> > > > > What I'm trying to say is that I have followed the correct steps
> > > > > and this is the LTO change
> > > > >
> > > > > git diff
> > > > > diff --git a/configs/imx6dl_mamoj_defconfig
> > > > > b/configs/imx6dl_mamoj_defconfig index ae27857e6f..4a535012b2
> > > > > 100644
> > > > > --- a/configs/imx6dl_mamoj_defconfig
> > > > > +++ b/configs/imx6dl_mamoj_defconfig
> > > > > @@ -14,6 +14,7 @@ CONFIG_SPL_TEXT_BASE=0x00908000
> > > > > CONFIG_SPL_DRIVERS_MISC=y CONFIG_IMX_HAB=y #
> CONFIG_CMD_BMODE
> > > > > is not set
> > > > > +CONFIG_LTO=y
> > > > > CONFIG_DISTRO_DEFAULTS=y
> > > > > CONFIG_BOOTDELAY=3
> > > > > CONFIG_SPL_OS_BOOT=y
> > > >
> > > > Here's what I see:
> > > > $ git describe HEAD
> > > > v2022.04-rc4-50-g9776c4e9d00a
> > > > $ make imx6dl_mamoj_defconfig
> > > > HOSTCC scripts/basic/fixdep
> > > > HOSTCC scripts/kconfig/conf.o
> > > > YACC scripts/kconfig/zconf.tab.c
> > > > LEX scripts/kconfig/zconf.lex.c
> > > > HOSTCC scripts/kconfig/zconf.tab.o
> > > > HOSTLD scripts/kconfig/conf
> > > > #
> > > > # configuration written to .config # $ sed -i -e 's/# CONFIG_LTO
> > > > is not set/CONFIG_LTO=y/' .config $ grep LTO .config
> > > > CONFIG_ARCH_SUPPORTS_LTO=y CONFIG_LTO=y $ make
> > > > CROSS_COMPILE=~/.buildman-toolchains/gcc-11.1.0-nolibc/arm-linux-g
> > > > nueabi/bin/arm-linux-gnueabi- -sj12 ===================== WARNING
> > > > ====================== This board does not use CONFIG_DM_SERIAL
> > > > (Driver Model for Serial drivers). Please update the board to use
> > > > CONFIG_DM_SERIAL before the v2023.04 release. Failure to update by
> > > > the deadline may result in board removal.
> > > > See doc/driver-model/migration.rst for more info.
> > > > ====================================================
> > > > arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property):
> > > > /display-bl:pwms: cell 3 is not a phandle reference
> > > > arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property):
> > > > /display-bl: Missing property '#pwm-cells' in node
> > > > /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from
> > > > pwms[3])
> > > > arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property):
> > > > /display-bl:pwms: cell 3 is not a phandle reference
> > > > arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property):
> > > > /display-bl: Missing property '#pwm-cells' in node
> > > > /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from
> > > > pwms[3]) $ ls -lh spl/u-boot-spl* -rwxrwxr-x 1 trini trini 944K
> > > > Mar 19 13:40 spl/u-boot-spl
> > > > -rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl.bin
> > > > -rw-rw-r-- 1 trini trini 1.6K Mar 19 13:40 spl/u-boot-spl.cfgout
> > > > -rw-rw-r-- 1 trini trini 2.2K Mar 19 13:40 spl/u-boot-spl.dtb
> > > > -rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl-dtb.bin
> > > > -rw-rw-r-- 1 trini trini 728 Mar 19 13:40 spl/u-boot-spl.lds
> > > > -rw-rw-r-- 1 trini trini 5.9K Mar 19 13:40
> > > > spl/u-boot-spl.ltrans0.ltrans.su
> > > > -rw-rw-r-- 1 trini trini 7.2K Mar 19 13:40
> > > > spl/u-boot-spl.ltrans1.ltrans.su
> > > > -rw-rw-r-- 1 trini trini 182K Mar 19 13:40 spl/u-boot-spl.map
> > > > -rwxrwxr-x 1 trini trini 51K Mar 19 13:40
> > > > spl/u-boot-spl-nodtb.bin
> > > > -rw-rw-r-- 1 trini trini 135K Mar 19 13:40 spl/u-boot-spl.sym
> > > >
> > >
> > > The only difference is the toolchain gcc version 9.4.0 (Ubuntu
> > > 9.4.0-1ubuntu1~20.04) and for the result you get I'm agree with you.
> >
> > Yeah, that's too old of a toolchain for LTO to be usable. A patch to
> > catch and error out in that case would be good :)
>
> Let's do it this way. I will test with the newer gcc version and decrease the size
> and send a patch.
> This can be done on Monday, because I don't have access to it.
Waiting for your patch to decrease the spl size as my patch series is dependent on your fix.
Gaurav
>
> Michael
> >
> > --
> > Tom
>
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> michael@amarulasolutions.com
> __________________________________
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172
> info@amarulasolutions.com
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.ama
> rulasolutions.com%2F&data=04%7C01%7Cgaurav.jain%40nxp.com%7Cf2e
> 5639efe9e491287e008da09d260f9%7C686ea1d3bc2b4c6fa92cd99c5c301635%
> 7C0%7C0%7C637833096989631395%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiM
> C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&a
> mp;sdata=pBaV4f5%2BrMJh7CsyEwpU0xOCQVQjWMkIyZ5%2BoPeey4k%3D&a
> mp;reserved=0
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
2022-03-23 12:06 ` Gaurav Jain
@ 2022-03-23 12:45 ` Michael Nazzareno Trimarchi
0 siblings, 0 replies; 69+ messages in thread
From: Michael Nazzareno Trimarchi @ 2022-03-23 12:45 UTC (permalink / raw)
To: Gaurav Jain
Cc: Tom Rini, Fabio Estevam, Stefano Babic, Michael Walle,
Varun Sethi, Adrian Alonso, Alison Wang, Andy Tang,
Franck Lenormand, Horia Geanta, Ji Luo, marex,
Meenakshi Aggarwal, Mingkai Hu, olteanv, Pankaj Gupta, Peng Fan,
Pramod Kumar, Priyanka Jain, Rajesh Bhagat, Sahil Malhotra,
Shengzhou Liu, Silvano Di Ninno, sjg, u-boot, dl-uboot-imx,
Wasim Khan, Ye Li, Raffaele RECALCATI, Jagan Teki
Hi
On Wed, Mar 23, 2022 at 1:06 PM Gaurav Jain <gaurav.jain@nxp.com> wrote:
>
> Hi Michael
>
> > -----Original Message-----
> > From: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
> > Sent: Saturday, March 19, 2022 11:30 PM
> > To: Tom Rini <trini@konsulko.com>
> > Cc: Fabio Estevam <festevam@gmail.com>; Gaurav Jain
> > <gaurav.jain@nxp.com>; Stefano Babic <sbabic@denx.de>; Michael Walle
> > <michael@walle.cc>; Varun Sethi <V.Sethi@nxp.com>; Adrian Alonso
> > <adrian.alonso@nxp.com>; Alison Wang <alison.wang@nxp.com>; Andy Tang
> > <andy.tang@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>;
> > Horia Geanta <horia.geanta@nxp.com>; Ji Luo <ji.luo@nxp.com>;
> > marex@denx.de; Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> > Mingkai Hu <mingkai.hu@nxp.com>; olteanv@gmail.com; Pankaj Gupta
> > <pankaj.gupta@nxp.com>; Peng Fan <peng.fan@nxp.com>; Pramod Kumar
> > <pramod.kumar_1@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Rajesh
> > Bhagat <rajesh.bhagat@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> > Shengzhou Liu <shengzhou.liu@nxp.com>; Silvano Di Ninno
> > <silvano.dininno@nxp.com>; sjg@chromium.org; u-boot@lists.denx.de; dl-
> > uboot-imx <uboot-imx@nxp.com>; Wasim Khan <wasim.khan@nxp.com>; Ye Li
> > <ye.li@nxp.com>; Raffaele RECALCATI <raffaele.recalcati@bticino.it>; Jagan
> > Teki <jagan@amarulasolutions.com>
> > Subject: Re: [EXT] Re: [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job
> > ring driver model
> >
> > Caution: EXT Email
> >
> > HI Tom
> >
> > On Sat, Mar 19, 2022 at 6:51 PM Tom Rini <trini@konsulko.com> wrote:
> > >
> > > On Sat, Mar 19, 2022 at 06:49:25PM +0100, Michael Nazzareno Trimarchi
> > wrote:
> > > > HI Tom
> > > >
> > > > On Sat, Mar 19, 2022 at 6:44 PM Tom Rini <trini@konsulko.com> wrote:
> > > > >
> > > > > On Sat, Mar 19, 2022 at 06:37:18PM +0100, Michael Nazzareno Trimarchi
> > wrote:
> > > > > > Hi Tom
> > > > > >
> > > > > > On Sat, Mar 19, 2022 at 6:30 PM Tom Rini <trini@konsulko.com> wrote:
> > > > > > >
> > > > > > > On Sat, Mar 19, 2022 at 06:27:38PM +0100, Michael Nazzareno
> > Trimarchi wrote:
> > > > > > > > Hi
> > > > > > > >
> > > > > > > > On Sat, Mar 19, 2022 at 6:25 PM Tom Rini <trini@konsulko.com>
> > wrote:
> > > > > > > > >
> > > > > > > > > On Sat, Mar 19, 2022 at 06:08:18PM +0100, Michael Nazzareno
> > Trimarchi wrote:
> > > > > > > > > > Hi Tom
> > > > > > > > > >
> > > > > > > > > > On Sat, Mar 19, 2022 at 6:03 PM Tom Rini <trini@konsulko.com>
> > wrote:
> > > > > > > > > > >
> > > > > > > > > > > On Sat, Mar 19, 2022 at 05:48:59PM +0100, Michael Nazzareno
> > Trimarchi wrote:
> > > > > > > > > > > > Hi Tom
> > > > > > > > > > > >
> > > > > > > > > > > > On Sat, Mar 19, 2022 at 5:05 PM Tom Rini
> > <trini@konsulko.com> wrote:
> > > > > > > > > > > > >
> > > > > > > > > > > > > On Sat, Mar 19, 2022 at 02:51:01PM +0100, Michael
> > Nazzareno Trimarchi wrote:
> > > > > > > > > > > > > > Hi
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > On Sat, Mar 19, 2022 at 2:25 PM Fabio Estevam
> > <festevam@gmail.com> wrote:
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > Hi Michael,
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > On Sat, Mar 19, 2022 at 6:47 AM Michael
> > > > > > > > > > > > > > > Nazzareno Trimarchi <michael@amarulasolutions.com>
> > wrote:
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > HI
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > Please send me a link to apply your series
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > You can get the series from patchwork (just
> > > > > > > > > > > > > > > click in the 'series' button)
> > > > > > > > > > > > > > > https://eur01.safelinks.protection.outlook.com
> > > > > > > > > > > > > > > /?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpro
> > > > > > > > > > > > > > > ject%2Fuboot%2Fpatch%2F20220112133127.16880-2-
> > > > > > > > > > > > > > > gaurav.jain%40nxp.com%2F&data=04%7C01%7Cga
> > > > > > > > > > > > > > > urav.jain%40nxp.com%7Cf2e5639efe9e491287e008da
> > > > > > > > > > > > > > > 09d260f9%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C
> > > > > > > > > > > > > > >
> > 0%7C0%7C637833096989631395%7CUnknown%7CTWFpbGZ
> > > > > > > > > > > > > > > sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBT
> > > > > > > > > > > > > > > iI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=Sv5
> > > > > > > > > > > > > > >
> > W81K1CO1KdNO%2FW8v4cCrqK4gLC0IoChfHYmHSEZM%3D&
> > > > > > > > > > > > > > > amp;reserved=0
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > Done, well, I have tried remove DM_GPIO in SPL.
> > > > > > > > > > > > > > Seems that I need to remove a lot of features. I
> > > > > > > > > > > > > > have tested LTO build but size of SPL increase. Is that
> > strange?
> > > > > > > > > > > > >
> > > > > > > > > > > > > That is very strange. Can you post your patches somewhere?
> > > > > > > > > > > > >
> > > > > > > > > > > > > --
> > > > > > > > > > > > > Tom
> > > > > > > > > > > >
> > > > > > > > > > > > Start from here
> > > > > > > > > > > > 9776c4e9d00ac49d6388ffe9e084ff03b37ae479
> > > > > > > > > > > > export ARCH=arm
> > > > > > > > > > > > export CROSS_COMPILE=arm-linux-gnueabihf-
> > > > > > > > > > > >
> > > > > > > > > > > > make imx6dl_mamoj_defconfig build it
> > > > > > > > > > > >
> > > > > > > > > > > > Try then to enable LTO and build it again
> > > > > > > > > > > >
> > > > > > > > > > > > spl/u-boot-spl.bin exceeds file size limit:
> > > > > > > > > > > > limit: 0xefa0 bytes
> > > > > > > > > > > > actual: 0xf071 bytes
> > > > > > > > > > > > excess: 0xd1 bytes
> > > > > > > > > > > >
> > > > > > > > > > > > So LTO does not help even on beginning on this
> > > > > > > > > > > > board. You don't need to apply any patch for this
> > > > > > > > > > > > test
> > > > > > > > > > >
> > > > > > > > > > > I think that's some artifact of mixing LTO/non-LTO and
> > > > > > > > > > > the world not getting rebuilt? Just enabling LTO
> > > > > > > > > > > after the defconfig works fine and is smaller than before.
> > > > > > > > > >
> > > > > > > > > > In order to save space I did not change what we have.
> > > > > > > > > > Every build starts from a mrproper and new
> > > > > > > > > > configuration. I can not mix LTO/non-LTO in this case.
> > > > > > > > > > I'm using upstream defconfig and upstream defconfig +
> > > > > > > > > > LTO enabled and the result is that spl increase in size
> > > > > > > > > > for LTO building. I'm working to keep out part that are
> > > > > > > > > > not really needed but I was hoping that LTO give me some
> > > > > > > > > > help here
> > > > > > > > >
> > > > > > > > > Yes, LTO saves about 5KiB on the SPL binary. You just
> > > > > > > > > need to enable it in the config before you start building,
> > > > > > > > > not after you've built everything once.
> > > > > > > >
> > > > > > > > Offcourse ;) but this not the case. I don't drink enough to
> > > > > > > > think that change a config, decrease the build size ;)
> > > > > > >
> > > > > > > LTO is an entirely different way of the compiler / linker
> > > > > > > optimizing the binary. So yes, in this case enabling a single
> > > > > > > option decreases the size.
> > > > > >
> > > > > >
> > > > > > I think we are in a circle. Let's have the result with LTO
> > > > > >
> > > > > > spl/keep-syms-lto.c
> > > > > > ( cd spl && arm-linux-gnueabihf-gcc -nostdlib -nostartfiles
> > > > > > -fuse-linker-plugin -flto=8 -Wall -Wstrict-prototypes
> > > > > > -Wno-format-security -fno-builtin -ffreestanding -std=gnu11
> > > > > > -fshort-wchar -fno-strict-aliasing -fno-PIE -Os -flto=8
> > > > > > -fno-stack-protector -fno-delete-null-pointer-checks
> > > > > > -Wno-pointer-sign -Wno-stringop-truncation -Wno-array-bounds
> > > > > > -Wno-stringop-overflow -Wno-maybe-uninitialized
> > > > > > -fmacro-prefix-map=./= -g -fstack-usage -Wno-format-nonliteral
> > > > > > -Wno-address-of-packed-member -Wno-unused-but-set-variable
> > > > > > -Werror=date-time -Wno-packed-not-aligned -ffunction-sections
> > > > > > -fdata-sections -fno-stack-protector -D__KERNEL__ -D__UBOOT__
> > > > > > -DCONFIG_SPL_BUILD -D__ARM__ -Wa,-mimplicit-it=always -mthumb -
> > mthumb-interwork -mabi=aapcs-linux -mno-unaligned-access
> > > > > > -fno-common -ffixed-r9 -msoft-float -mgeneral-regs-only -pipe
> > > > > > -march=armv7-a -D__LINUX_ARM_ARCH__=7 -mtune=generic-armv7-a
> > > > > > -Ispl/include -Iinclude -I./arch/arm/include -include
> > > > > > ./include/linux/kconfig.h -nostdinc -isystem
> > > > > > /usr/lib/gcc-cross/arm-linux-gnueabihf/9/include -Wl,-T
> > > > > > -Wl,u-boot-spl.lds -Wl,-Bstatic -Wl,--gc-sections
> > > > > > -Wl,--no-dynamic-linker -Wl,--build-id=none -Wl,-Ttext
> > > > > > -Wl,0x00908000 arch/arm/cpu/armv7/start.o -Wl,--whole-archive
> > > > > > arch/arm/cpu/armv7/built-in.o arch/arm/cpu/built-in.o
> > > > > > arch/arm/lib/built-in.o arch/arm/mach-imx/built-in.o
> > > > > > board/bticino/mamoj/built-in.o common/spl/built-in.o
> > > > > > common/init/built-in.o boot/built-in.o common/built-in.o
> > > > > > cmd/built-in.o env/built-in.o lib/built-in.o disk/built-in.o
> > > > > > drivers/built-in.o drivers/usb/dwc3/built-in.o
> > > > > > drivers/usb/cdns3/built-in.o dts/built-in.o fs/built-in.o
> > > > > > keep-syms-lto.o arch/arm/lib/eabi_compat.o arch/arm/lib/lib.a
> > > > > > -Wl,--no-whole-archive -Wl,-Map,u-boot-spl.map -o u-boot-spl )
> > > > > > arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
> > > > > > .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
> > > > > > .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
> > > > > > .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -O binary
> > > > > > spl/u-boot-spl spl/u-boot-spl-nodtb.bin
> > > > > > arm-linux-gnueabihf-objdump -t spl/u-boot-spl > spl/u-boot-spl.sym
> > > > > > cat spl/u-boot-spl-nodtb.bin spl/u-boot-spl.dtb > spl/u-boot-spl-dtb.bin
> > > > > > cp spl/u-boot-spl-dtb.bin spl/u-boot-spl.bin
> > > > > > spl/u-boot-spl.bin exceeds file size limit:
> > > > > > limit: 0xefa0 bytes
> > > > > > actual: 0xf079 bytes
> > > > > > excess: 0xd9 bytes
> > > > > > make: *** [Makefile:2082: spl/u-boot-spl.bin] Error 1
> > > > > > make: *** Deleting file 'spl/u-boot-spl.bin'
> > > > > >
> > > > > > and without
> > > > > >
> > > > > > NUX_ARM_ARCH__=7 -mtune=generic-armv7-a -D__ASSEMBLY__ -x c -
> > o
> > > > > > spl/u-boot-spl.cfgout arch/arm/mach-imx/spl_sd.cfg
> > > > > > ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e
> > > > > > 0x00908000 -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
> > > > > > Image Type: Freescale IMX Boot Image
> > > > > > Image Ver: 2 (i.MX53/6/7 compatible)
> > > > > > Mode: DCD
> > > > > > Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
> > > > > > Load Address: 00907420
> > > > > > Entry Point: 00908000
> > > > > > HAB Blocks: 0x00907400 0x00000000 0x0000fc00
> > > > > > DCD Blocks: 0x00910000 0x0000002c 0x00000004
> > > > > > make -f ./scripts/Makefile.build obj=arch/arm/mach-imx
> > > > > > u-boot-with-spl.imx mkdir -p spl/
> > > > > > ./tools/mkimage -n spl/u-boot-spl.cfgout -T imximage -e
> > > > > > 0x00908000 -d spl/u-boot-spl.bin SPL >SPL.log && cat SPL.log
> > > > > > Image Type: Freescale IMX Boot Image
> > > > > > Image Ver: 2 (i.MX53/6/7 compatible)
> > > > > > Mode: DCD
> > > > > > Data Size: 73824 Bytes = 72.09 KiB = 0.07 MiB
> > > > > > Load Address: 00907420
> > > > > > Entry Point: 00908000
> > > > > > HAB Blocks: 0x00907400 0x00000000 0x0000fc00
> > > > > > DCD Blocks: 0x00910000 0x0000002c 0x00000004
> > > > > > arm-linux-gnueabihf-objcopy -j .text -j .secure_text -j
> > > > > > .secure_data -j .rodata -j .hash -j .data -j .got -j .got.plt -j
> > > > > > .u_boot_list -j .rel.dyn -j .binman_sym_table -j .text_rest -j
> > > > > > .dtb.init.rodata -j .efi_runtime -j .efi_runtime_rel -I binary
> > > > > > -O binary --pad-to=0x11000 SPL u-boot-with-spl.imx && cat
> > > > > > u-boot.img >> u-boot-with-spl.imx || rm -f u-boot-with-spl.imx
> > > > > >
> > > > > >
> > > > > > What I'm trying to say is that I have followed the correct steps
> > > > > > and this is the LTO change
> > > > > >
> > > > > > git diff
> > > > > > diff --git a/configs/imx6dl_mamoj_defconfig
> > > > > > b/configs/imx6dl_mamoj_defconfig index ae27857e6f..4a535012b2
> > > > > > 100644
> > > > > > --- a/configs/imx6dl_mamoj_defconfig
> > > > > > +++ b/configs/imx6dl_mamoj_defconfig
> > > > > > @@ -14,6 +14,7 @@ CONFIG_SPL_TEXT_BASE=0x00908000
> > > > > > CONFIG_SPL_DRIVERS_MISC=y CONFIG_IMX_HAB=y #
> > CONFIG_CMD_BMODE
> > > > > > is not set
> > > > > > +CONFIG_LTO=y
> > > > > > CONFIG_DISTRO_DEFAULTS=y
> > > > > > CONFIG_BOOTDELAY=3
> > > > > > CONFIG_SPL_OS_BOOT=y
> > > > >
> > > > > Here's what I see:
> > > > > $ git describe HEAD
> > > > > v2022.04-rc4-50-g9776c4e9d00a
> > > > > $ make imx6dl_mamoj_defconfig
> > > > > HOSTCC scripts/basic/fixdep
> > > > > HOSTCC scripts/kconfig/conf.o
> > > > > YACC scripts/kconfig/zconf.tab.c
> > > > > LEX scripts/kconfig/zconf.lex.c
> > > > > HOSTCC scripts/kconfig/zconf.tab.o
> > > > > HOSTLD scripts/kconfig/conf
> > > > > #
> > > > > # configuration written to .config # $ sed -i -e 's/# CONFIG_LTO
> > > > > is not set/CONFIG_LTO=y/' .config $ grep LTO .config
> > > > > CONFIG_ARCH_SUPPORTS_LTO=y CONFIG_LTO=y $ make
> > > > > CROSS_COMPILE=~/.buildman-toolchains/gcc-11.1.0-nolibc/arm-linux-g
> > > > > nueabi/bin/arm-linux-gnueabi- -sj12 ===================== WARNING
> > > > > ====================== This board does not use CONFIG_DM_SERIAL
> > > > > (Driver Model for Serial drivers). Please update the board to use
> > > > > CONFIG_DM_SERIAL before the v2023.04 release. Failure to update by
> > > > > the deadline may result in board removal.
> > > > > See doc/driver-model/migration.rst for more info.
> > > > > ====================================================
> > > > > arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property):
> > > > > /display-bl:pwms: cell 3 is not a phandle reference
> > > > > arch/arm/dts/imx6dl-dhcom-pdk2.dtb: Warning (pwms_property):
> > > > > /display-bl: Missing property '#pwm-cells' in node
> > > > > /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from
> > > > > pwms[3])
> > > > > arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property):
> > > > > /display-bl:pwms: cell 3 is not a phandle reference
> > > > > arch/arm/dts/imx6q-dhcom-pdk2.dtb: Warning (pwms_property):
> > > > > /display-bl: Missing property '#pwm-cells' in node
> > > > > /soc/bus@2000000/gpc@20dc000 or bad phandle (referred from
> > > > > pwms[3]) $ ls -lh spl/u-boot-spl* -rwxrwxr-x 1 trini trini 944K
> > > > > Mar 19 13:40 spl/u-boot-spl
> > > > > -rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl.bin
> > > > > -rw-rw-r-- 1 trini trini 1.6K Mar 19 13:40 spl/u-boot-spl.cfgout
> > > > > -rw-rw-r-- 1 trini trini 2.2K Mar 19 13:40 spl/u-boot-spl.dtb
> > > > > -rw-rw-r-- 1 trini trini 54K Mar 19 13:40 spl/u-boot-spl-dtb.bin
> > > > > -rw-rw-r-- 1 trini trini 728 Mar 19 13:40 spl/u-boot-spl.lds
> > > > > -rw-rw-r-- 1 trini trini 5.9K Mar 19 13:40
> > > > > spl/u-boot-spl.ltrans0.ltrans.su
> > > > > -rw-rw-r-- 1 trini trini 7.2K Mar 19 13:40
> > > > > spl/u-boot-spl.ltrans1.ltrans.su
> > > > > -rw-rw-r-- 1 trini trini 182K Mar 19 13:40 spl/u-boot-spl.map
> > > > > -rwxrwxr-x 1 trini trini 51K Mar 19 13:40
> > > > > spl/u-boot-spl-nodtb.bin
> > > > > -rw-rw-r-- 1 trini trini 135K Mar 19 13:40 spl/u-boot-spl.sym
> > > > >
> > > >
> > > > The only difference is the toolchain gcc version 9.4.0 (Ubuntu
> > > > 9.4.0-1ubuntu1~20.04) and for the result you get I'm agree with you.
> > >
> > > Yeah, that's too old of a toolchain for LTO to be usable. A patch to
> > > catch and error out in that case would be good :)
> >
> > Let's do it this way. I will test with the newer gcc version and decrease the size
> > and send a patch.
> > This can be done on Monday, because I don't have access to it.
>
> Waiting for your patch to decrease the spl size as my patch series is dependent on your fix.
>
I will not let wait more. We had already gain using LTO enable and
remove DM_GPIO (around 8k)
Michael
> Gaurav
> >
> > Michael
> > >
> > > --
> > > Tom
> >
> >
> >
> > --
> > Michael Nazzareno Trimarchi
> > Co-Founder & Chief Executive Officer
> > M. +39 347 913 2170
> > michael@amarulasolutions.com
> > __________________________________
> >
> > Amarula Solutions BV
> > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172
> > info@amarulasolutions.com
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.ama
> > rulasolutions.com%2F&data=04%7C01%7Cgaurav.jain%40nxp.com%7Cf2e
> > 5639efe9e491287e008da09d260f9%7C686ea1d3bc2b4c6fa92cd99c5c301635%
> > 7C0%7C0%7C637833096989631395%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiM
> > C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&a
> > mp;sdata=pBaV4f5%2BrMJh7CsyEwpU0xOCQVQjWMkIyZ5%2BoPeey4k%3D&a
> > mp;reserved=0
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 69+ messages in thread
end of thread, other threads:[~2022-03-23 12:45 UTC | newest]
Thread overview: 69+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-10 12:26 [PATCH v8 00/15] Add CAAM driver model support Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model Gaurav Jain
2022-02-05 14:16 ` Stefano Babic
2022-02-07 7:13 ` [EXT] " Gaurav Jain
2022-02-11 9:38 ` Gaurav Jain
2022-02-25 7:03 ` Gaurav Jain
2022-03-03 12:44 ` Gaurav Jain
2022-03-03 13:02 ` Stefano Babic
2022-03-03 13:41 ` Gaurav Jain
2022-03-03 15:30 ` Stefano Babic
2022-03-06 19:38 ` ZHIZHIKIN Andrey
2022-03-07 14:10 ` Gaurav Jain
2022-03-07 15:42 ` ZHIZHIKIN Andrey
2022-03-07 9:58 ` Michael Walle
2022-03-07 10:56 ` Gaurav Jain
2022-03-07 11:08 ` Michael Walle
2022-03-07 11:33 ` Gaurav Jain
2022-03-07 11:41 ` Michael Walle
2022-03-07 12:03 ` Gaurav Jain
2022-03-07 15:15 ` Tom Rini
2022-03-08 11:10 ` Gaurav Jain
2022-03-08 11:12 ` Fabio Estevam
2022-03-08 11:17 ` Gaurav Jain
2022-03-08 12:48 ` Tom Rini
2022-03-08 13:21 ` Gaurav Jain
2022-03-08 13:29 ` Tom Rini
2022-03-08 13:28 ` Stefano Babic
2022-03-08 13:34 ` Michael Nazzareno Trimarchi
2022-03-14 5:47 ` Gaurav Jain
2022-03-17 12:10 ` Gaurav Jain
2022-03-19 9:47 ` Michael Nazzareno Trimarchi
2022-03-19 10:32 ` Michael Nazzareno Trimarchi
2022-03-19 13:24 ` Fabio Estevam
2022-03-19 13:51 ` Michael Nazzareno Trimarchi
2022-03-19 16:05 ` Tom Rini
2022-03-19 16:48 ` Michael Nazzareno Trimarchi
2022-03-19 17:03 ` Tom Rini
2022-03-19 17:08 ` Michael Nazzareno Trimarchi
2022-03-19 17:25 ` Tom Rini
2022-03-19 17:27 ` Michael Nazzareno Trimarchi
2022-03-19 17:30 ` Tom Rini
2022-03-19 17:37 ` Michael Nazzareno Trimarchi
2022-03-19 17:43 ` Tom Rini
2022-03-19 17:49 ` Michael Nazzareno Trimarchi
2022-03-19 17:51 ` Tom Rini
2022-03-19 18:00 ` Michael Nazzareno Trimarchi
2022-03-19 18:33 ` R: " Raffaele RECALCATI
2022-03-23 12:06 ` Gaurav Jain
2022-03-23 12:45 ` Michael Nazzareno Trimarchi
2022-01-10 12:27 ` [PATCH v8 02/15] i.MX8M: crypto: updated device tree for supporting DM in SPL Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 03/15] crypto/fsl: i.MX8M: Enable Job ring driver model Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 04/15] mx6sabre: Remove unnecessary SPL configs Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 05/15] i.MX6: Enable Job ring driver model Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 06/15] i.MX7: " Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 07/15] i.MX7ULP: " Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 08/15] i.MX8: Add crypto node in device tree Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 09/15] crypto/fsl: i.MX8: Enable Job ring driver model Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in kernel Gaurav Jain
2022-01-10 14:01 ` ZHIZHIKIN Andrey
2022-01-11 5:44 ` [EXT] " Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 11/15] Layerscape: Add crypto node in device tree Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 12/15] Layerscape: Enable Job ring driver model Gaurav Jain
2022-01-10 12:42 ` Michael Walle
2022-01-11 5:41 ` [EXT] " Gaurav Jain
2022-01-11 7:22 ` Michael Walle
2022-01-11 11:34 ` Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 13/15] PPC: Add crypto node in device tree Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 14/15] PPC: Enable Job ring driver model Gaurav Jain
2022-01-10 12:27 ` [PATCH v8 15/15] update CAAM MAINTAINER Gaurav Jain
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.