* [PATCH 1/7] arm64: dts: qcom: sm8250.dtsi: add display system nodes
@ 2020-11-27 9:55 Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 2/7] arm64: dts: qrb5165-rb5: add mdss/mdp/dsi nodes Dmitry Baryshkov
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2020-11-27 9:55 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring; +Cc: linux-arm-msm, devicetree
Add device tree nodes for mdss, mdp, dsi0/1.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 302 ++++++++++++++++++++++++++-
1 file changed, 295 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 65acd1f381eb..f4cae2b82e2a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4,10 +4,12 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
+#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -1254,14 +1256,8 @@ tcsr_mutex: hwlock@1f40000 {
};
gpu: gpu@3d00000 {
- /*
- * note: the amd,imageon compatible makes it possible
- * to use the drm/msm driver without the display node,
- * make sure to remove it when display node is added
- */
compatible = "qcom,adreno-650.2",
- "qcom,adreno",
- "amd,imageon";
+ "qcom,adreno";
#stream-id-cells = <16>;
reg = <0 0x03d00000 0 0x40000>;
@@ -1803,6 +1799,298 @@ usb_2_dwc3: dwc3@a800000 {
};
};
+ mdss: mdss@ae00000 {
+ compatible = "qcom,sdm845-mdss";
+ reg = <0 0x0ae00000 0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>,
+ <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
+ <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ assigned-clock-rates = <460000000>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x820 0x402>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: mdp@ae01000 {
+ compatible = "qcom,sdm845-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb0000 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <460000000>,
+ <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8250_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: mdp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM8250_MMCX>;
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi0_phy: dsi-phy@ae94400 {
+ compatible = "qcom,dsi-phy-7nm";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94900 0 0x260>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ dsi1: dsi@ae96000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae96000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SM8250_MMCX>;
+
+ phys = <&dsi1_phy>;
+ phy-names = "dsi";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi1_phy: dsi-phy@ae96400 {
+ compatible = "qcom,dsi-phy-7nm";
+ reg = <0 0x0ae96400 0 0x200>,
+ <0 0x0ae96600 0 0x280>,
+ <0 0x0ae96900 0 0x260>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+
+ dsi_opp_table: dsi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sm8250-dispcc";
+ reg = <0 0x0af00000 0 0x20000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&dsi0_phy 0>,
+ <&dsi0_phy 1>,
+ <&dsi1_phy 0>,
+ <&dsi1_phy 1>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <&sleep_clk>;
+ clock-names = "bi_tcxo",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_link_clk_divsel_ten",
+ "dp_vco_divided_clk_src_mux",
+ "dptx1_phy_pll_link_clk",
+ "dptx1_phy_pll_vco_div_clk",
+ "dptx2_phy_pll_link_clk",
+ "dptx2_phy_pll_vco_div_clk",
+ "edp_phy_pll_link_clk",
+ "edp_phy_pll_vco_div_clk",
+ "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8250-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
--
2.29.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/7] arm64: dts: qrb5165-rb5: add mdss/mdp/dsi nodes
2020-11-27 9:55 [PATCH 1/7] arm64: dts: qcom: sm8250.dtsi: add display system nodes Dmitry Baryshkov
@ 2020-11-27 9:55 ` Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 3/7] arm64: dts: qcom: qrb5165-rb5: add gpu/zap-shader node Dmitry Baryshkov
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2020-11-27 9:55 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring; +Cc: linux-arm-msm, devicetree
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 32 ++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index d9f52703ba2a..9c5135585ec9 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -399,6 +399,30 @@ vreg_s8c_1p3: smps8 {
};
};
+&dsi0 {
+ status = "okay";
+ vdda-supply = <&vreg_l9a_1p2>;
+
+#if 0
+ qcom,dual-dsi-mode;
+ qcom,master-dsi;
+#endif
+
+ ports {
+ port@1 {
+ endpoint {
+ //remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
+&dsi0_phy {
+ status = "okay";
+ vdds-supply = <&vreg_l5a_0p88>;
+};
+
/* LS-I2C0 */
&i2c4 {
status = "okay";
@@ -413,6 +437,14 @@ &i2c15 {
status = "okay";
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_mdp {
+ status = "okay";
+};
+
&pm8150_gpios {
gpio-reserved-ranges = <1 1>, <3 2>, <7 1>;
gpio-line-names =
--
2.29.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/7] arm64: dts: qcom: qrb5165-rb5: add gpu/zap-shader node
2020-11-27 9:55 [PATCH 1/7] arm64: dts: qcom: sm8250.dtsi: add display system nodes Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 2/7] arm64: dts: qrb5165-rb5: add mdss/mdp/dsi nodes Dmitry Baryshkov
@ 2020-11-27 9:55 ` Dmitry Baryshkov
2020-12-02 22:38 ` Bjorn Andersson
2020-11-27 9:55 ` [PATCH 4/7] arm64: dts: qcom: sm8250-mtp: " Dmitry Baryshkov
` (3 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Dmitry Baryshkov @ 2020-11-27 9:55 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring; +Cc: linux-arm-msm, devicetree
Add firmware configuration for Adreno zap shader on qrb5165-rb5.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index 9c5135585ec9..d1f6cadca35a 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -423,6 +423,13 @@ &dsi0_phy {
vdds-supply = <&vreg_l5a_0p88>;
};
+&gpu {
+ zap-shader {
+ memory-region = <&gpu_mem>;
+ firmware-name = "qcom/a650_zap.mdt";
+ };
+};
+
/* LS-I2C0 */
&i2c4 {
status = "okay";
--
2.29.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/7] arm64: dts: qcom: sm8250-mtp: add gpu/zap-shader node
2020-11-27 9:55 [PATCH 1/7] arm64: dts: qcom: sm8250.dtsi: add display system nodes Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 2/7] arm64: dts: qrb5165-rb5: add mdss/mdp/dsi nodes Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 3/7] arm64: dts: qcom: qrb5165-rb5: add gpu/zap-shader node Dmitry Baryshkov
@ 2020-11-27 9:55 ` Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 5/7] arm64: dts: qcom: qrb5165-rb5: correct vdc_3v3 regulator Dmitry Baryshkov
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2020-11-27 9:55 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring; +Cc: linux-arm-msm, devicetree
Add firmware configuration for Adreno zap shader on sm8250-mtp.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
index dea00f19711d..b5a474ee008e 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts
@@ -358,6 +358,13 @@ &cdsp {
firmware-name = "qcom/sm8250/cdsp.mbn";
};
+&gpu {
+ zap-shader {
+ memory-region = <&gpu_mem>;
+ firmware-name = "qcom/a650_zap.mdt";
+ };
+};
+
&i2c1 {
status = "okay";
clock-frequency = <1000000>;
--
2.29.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 5/7] arm64: dts: qcom: qrb5165-rb5: correct vdc_3v3 regulator
2020-11-27 9:55 [PATCH 1/7] arm64: dts: qcom: sm8250.dtsi: add display system nodes Dmitry Baryshkov
` (2 preceding siblings ...)
2020-11-27 9:55 ` [PATCH 4/7] arm64: dts: qcom: sm8250-mtp: " Dmitry Baryshkov
@ 2020-11-27 9:55 ` Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 6/7] arm64: dts: qcom: qrb5165-rb5: add lt9611 HDMI bridge Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 7/7] arm64: dts: qcom: sm8250: power up dispcc on sm8250 by MMCX regulator Dmitry Baryshkov
5 siblings, 0 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2020-11-27 9:55 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring; +Cc: linux-arm-msm, devicetree
vdc_3v3 regulator is sourced from 12V, but it is controlled by l11c
regulator, so set it as vin for vdc_3v3.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index d1f6cadca35a..70e11705e9f6 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -80,7 +80,7 @@ vbat_som: vbat-som-regulator {
vdc_3v3: vdc-3v3-regulator {
compatible = "regulator-fixed";
regulator-name = "VDC_3V3";
- vin-supply = <&dc12v>;
+ vin-supply = <&vreg_l11c_3p3>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
--
2.29.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 6/7] arm64: dts: qcom: qrb5165-rb5: add lt9611 HDMI bridge
2020-11-27 9:55 [PATCH 1/7] arm64: dts: qcom: sm8250.dtsi: add display system nodes Dmitry Baryshkov
` (3 preceding siblings ...)
2020-11-27 9:55 ` [PATCH 5/7] arm64: dts: qcom: qrb5165-rb5: correct vdc_3v3 regulator Dmitry Baryshkov
@ 2020-11-27 9:55 ` Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 7/7] arm64: dts: qcom: sm8250: power up dispcc on sm8250 by MMCX regulator Dmitry Baryshkov
5 siblings, 0 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2020-11-27 9:55 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring; +Cc: linux-arm-msm, devicetree
Add device tree node for the lontium lt9611ux DSI-HDMI bridge.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 97 +++++++++++++++++++++++-
1 file changed, 96 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index 70e11705e9f6..2c3eb3771ded 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -33,6 +33,17 @@ dc12v: dc12v-regulator {
regulator-always-on;
};
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -59,6 +70,26 @@ bt {
};
+ lt9611_1v2: lt9611-vdd12-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ vin-supply = <&vdc_3v3>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ lt9611_3v3: lt9611-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_3V3";
+
+ vin-supply = <&vdc_3v3>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
vbat: vbat-regulator {
compatible = "regulator-fixed";
regulator-name = "VBAT";
@@ -411,7 +442,7 @@ &dsi0 {
ports {
port@1 {
endpoint {
- //remote-endpoint = <<9611_a>;
+ remote-endpoint = <<9611_a>;
data-lanes = <0 1 2 3>;
};
};
@@ -437,6 +468,55 @@ &i2c4 {
&i2c5 {
status = "okay";
+ clock-frequency = <400000>;
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+ #sound-dai-cells = <1>;
+
+ interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&pm8150l_gpios 5 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+#if 0
+ port@1 {
+ reg = <1>;
+
+ lt9611_b: endpoint {
+ remote-endpoint = <&dsi1_out>;
+ };
+ };
+#endif
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+
+ };
+ };
};
/* LS-I2C1 */
@@ -497,6 +577,15 @@ &pm8150l_gpios {
"PM_GPIO-B",
"NC",
"PM3003A_MODE";
+
+ lt9611_rst_pin: lt9611-rst-pin {
+ pins = "gpio5";
+ function = "normal";
+
+ output-high;
+ input-disable;
+ power-source = <0>;
+ };
};
&pm8150_rtc {
@@ -718,6 +807,12 @@ &tlmm {
"HST_WLAN_UART_TX",
"HST_WLAN_UART_RX";
+ lt9611_irq_pin: lt9611-irq {
+ pins = "gpio63";
+ function = "gpio";
+ bias-disable;
+ };
+
sdc2_default_state: sdc2-default {
clk {
pins = "sdc2_clk";
--
2.29.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 7/7] arm64: dts: qcom: sm8250: power up dispcc on sm8250 by MMCX regulator
2020-11-27 9:55 [PATCH 1/7] arm64: dts: qcom: sm8250.dtsi: add display system nodes Dmitry Baryshkov
` (4 preceding siblings ...)
2020-11-27 9:55 ` [PATCH 6/7] arm64: dts: qcom: qrb5165-rb5: add lt9611 HDMI bridge Dmitry Baryshkov
@ 2020-11-27 9:55 ` Dmitry Baryshkov
5 siblings, 0 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2020-11-27 9:55 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring; +Cc: linux-arm-msm, devicetree
Add regulator controlling MMCX power domain to be used by display clock
controller on SM8250.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index f4cae2b82e2a..0c7986bf60d9 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -216,6 +216,13 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ mmcx_reg: mmcx-reg {
+ compatible = "regulator-fixed-domain";
+ power-domains = <&rpmhpd SM8250_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ regulator-name = "MMCX";
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -2058,6 +2065,7 @@ opp-358000000 {
dispcc: clock-controller@af00000 {
compatible = "qcom,sm8250-dispcc";
reg = <0 0x0af00000 0 0x20000>;
+ mmcx-supply = <&mmcx_reg>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
--
2.29.2
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/7] arm64: dts: qcom: qrb5165-rb5: add gpu/zap-shader node
2020-11-27 9:55 ` [PATCH 3/7] arm64: dts: qcom: qrb5165-rb5: add gpu/zap-shader node Dmitry Baryshkov
@ 2020-12-02 22:38 ` Bjorn Andersson
0 siblings, 0 replies; 8+ messages in thread
From: Bjorn Andersson @ 2020-12-02 22:38 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: Andy Gross, Rob Herring, linux-arm-msm, devicetree
On Fri 27 Nov 03:55 CST 2020, Dmitry Baryshkov wrote:
> Add firmware configuration for Adreno zap shader on qrb5165-rb5.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
> index 9c5135585ec9..d1f6cadca35a 100644
> --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
> +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
> @@ -423,6 +423,13 @@ &dsi0_phy {
> vdds-supply = <&vreg_l5a_0p88>;
> };
>
> +&gpu {
> + zap-shader {
> + memory-region = <&gpu_mem>;
> + firmware-name = "qcom/a650_zap.mdt";
The zap shader is unfortunately signed with a vendor specific key. So
can we please move the test signed file into qcom/sm8250/?
And to avoid pushing all these scattered files to linux-firmware, can
you please run pil-squasher [1] on it and use the a650_zap.mbn?
[1] https://github.com/andersson/pil-squasher
Regards,
Bjorn
> + };
> +};
> +
> /* LS-I2C0 */
> &i2c4 {
> status = "okay";
> --
> 2.29.2
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-12-02 22:48 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-27 9:55 [PATCH 1/7] arm64: dts: qcom: sm8250.dtsi: add display system nodes Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 2/7] arm64: dts: qrb5165-rb5: add mdss/mdp/dsi nodes Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 3/7] arm64: dts: qcom: qrb5165-rb5: add gpu/zap-shader node Dmitry Baryshkov
2020-12-02 22:38 ` Bjorn Andersson
2020-11-27 9:55 ` [PATCH 4/7] arm64: dts: qcom: sm8250-mtp: " Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 5/7] arm64: dts: qcom: qrb5165-rb5: correct vdc_3v3 regulator Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 6/7] arm64: dts: qcom: qrb5165-rb5: add lt9611 HDMI bridge Dmitry Baryshkov
2020-11-27 9:55 ` [PATCH 7/7] arm64: dts: qcom: sm8250: power up dispcc on sm8250 by MMCX regulator Dmitry Baryshkov
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