* [PATCH 0/2] clk: renesas: r8a779f0: Minor fixes
@ 2022-10-12 7:02 Geert Uytterhoeven
2022-10-12 7:02 ` [PATCH 1/2] clk: renesas: r8a779f0: Fix SD0H clock name Geert Uytterhoeven
2022-10-12 7:02 ` [PATCH 2/2] clk: renesas: r8a779f0: Add SASYNCPER internal clock Geert Uytterhoeven
0 siblings, 2 replies; 5+ messages in thread
From: Geert Uytterhoeven @ 2022-10-12 7:02 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Wolfram Sang, Yoshihiro Shimoda
Cc: linux-renesas-soc, linux-clk, Geert Uytterhoeven
Hi all,
This patch series contain two minor fixes for the R-Car S4-8 clock
driver.
I plan to queue these in renesas-clk for v6.2.
Thanks for your comments!
Geert Uytterhoeven (2):
clk: renesas: r8a779f0: Fix SD0H clock name
clk: renesas: r8a779f0: Add SASYNCPER internal clock
drivers/clk/renesas/r8a779f0-cpg-mssr.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
--
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] clk: renesas: r8a779f0: Fix SD0H clock name
2022-10-12 7:02 [PATCH 0/2] clk: renesas: r8a779f0: Minor fixes Geert Uytterhoeven
@ 2022-10-12 7:02 ` Geert Uytterhoeven
2022-10-12 18:48 ` Wolfram Sang
2022-10-12 7:02 ` [PATCH 2/2] clk: renesas: r8a779f0: Add SASYNCPER internal clock Geert Uytterhoeven
1 sibling, 1 reply; 5+ messages in thread
From: Geert Uytterhoeven @ 2022-10-12 7:02 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Wolfram Sang, Yoshihiro Shimoda
Cc: linux-renesas-soc, linux-clk, Geert Uytterhoeven
Correct the misspelled textual name of the SD0H clock.
Fixes: 9b5dd1ff705c6854 ("clk: renesas: r8a779f0: Add SDH0 clock")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r8a779f0-cpg-mssr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index 304435613723c0a3..8e7b9180ec67bbf6 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -113,7 +113,7 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
DEF_FIXED("sasyncperd2", R8A779F0_CLK_SASYNCPERD2, R8A779F0_CLK_SASYNCPERD1, 2, 1),
DEF_FIXED("sasyncperd4", R8A779F0_CLK_SASYNCPERD4, R8A779F0_CLK_SASYNCPERD1, 4, 1),
- DEF_GEN4_SDH("sdh0", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870),
+ DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870),
DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, 0x870),
DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] clk: renesas: r8a779f0: Add SASYNCPER internal clock
2022-10-12 7:02 [PATCH 0/2] clk: renesas: r8a779f0: Minor fixes Geert Uytterhoeven
2022-10-12 7:02 ` [PATCH 1/2] clk: renesas: r8a779f0: Fix SD0H clock name Geert Uytterhoeven
@ 2022-10-12 7:02 ` Geert Uytterhoeven
2022-10-12 18:50 ` Wolfram Sang
1 sibling, 1 reply; 5+ messages in thread
From: Geert Uytterhoeven @ 2022-10-12 7:02 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Wolfram Sang, Yoshihiro Shimoda
Cc: linux-renesas-soc, linux-clk, Geert Uytterhoeven
Add the SASYNCPER internal clock, which is the clock source of the
various SASYNCPERD[124] clocks, to match the clock tree diagram in the
documentation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r8a779f0-cpg-mssr.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index 8e7b9180ec67bbf6..e4f2bbbfeb2d2ae4 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -42,6 +42,7 @@ enum clk_ids {
CLK_PLL5_DIV4,
CLK_PLL6_DIV2,
CLK_S0,
+ CLK_SASYNCPER,
CLK_SDSRC,
CLK_RPCSRC,
CLK_OCO,
@@ -71,6 +72,7 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
DEF_RATE(".oco", CLK_OCO, 32768),
@@ -109,9 +111,9 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1),
DEF_FIXED("sasyncrt", R8A779F0_CLK_SASYNCRT, CLK_PLL5_DIV4, 48, 1),
- DEF_FIXED("sasyncperd1", R8A779F0_CLK_SASYNCPERD1, CLK_PLL5_DIV4, 3, 1),
- DEF_FIXED("sasyncperd2", R8A779F0_CLK_SASYNCPERD2, R8A779F0_CLK_SASYNCPERD1, 2, 1),
- DEF_FIXED("sasyncperd4", R8A779F0_CLK_SASYNCPERD4, R8A779F0_CLK_SASYNCPERD1, 4, 1),
+ DEF_FIXED("sasyncperd1",R8A779F0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
+ DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
+ DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870),
DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, 0x870),
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] clk: renesas: r8a779f0: Fix SD0H clock name
2022-10-12 7:02 ` [PATCH 1/2] clk: renesas: r8a779f0: Fix SD0H clock name Geert Uytterhoeven
@ 2022-10-12 18:48 ` Wolfram Sang
0 siblings, 0 replies; 5+ messages in thread
From: Wolfram Sang @ 2022-10-12 18:48 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Yoshihiro Shimoda,
linux-renesas-soc, linux-clk
[-- Attachment #1: Type: text/plain, Size: 366 bytes --]
On Wed, Oct 12, 2022 at 09:02:33AM +0200, Geert Uytterhoeven wrote:
> Correct the misspelled textual name of the SD0H clock.
>
> Fixes: 9b5dd1ff705c6854 ("clk: renesas: r8a779f0: Add SDH0 clock")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Oops, thank you for catching it.
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] clk: renesas: r8a779f0: Add SASYNCPER internal clock
2022-10-12 7:02 ` [PATCH 2/2] clk: renesas: r8a779f0: Add SASYNCPER internal clock Geert Uytterhoeven
@ 2022-10-12 18:50 ` Wolfram Sang
0 siblings, 0 replies; 5+ messages in thread
From: Wolfram Sang @ 2022-10-12 18:50 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Yoshihiro Shimoda,
linux-renesas-soc, linux-clk
[-- Attachment #1: Type: text/plain, Size: 576 bytes --]
On Wed, Oct 12, 2022 at 09:02:34AM +0200, Geert Uytterhoeven wrote:
> Add the SASYNCPER internal clock, which is the clock source of the
> various SASYNCPERD[124] clocks, to match the clock tree diagram in the
> documentation.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
As discussed, looks good!
Reported-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
For the record, I'd like to test as well, but that will need some more
days until the board shows up in a lab again.
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-10-12 18:51 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-12 7:02 [PATCH 0/2] clk: renesas: r8a779f0: Minor fixes Geert Uytterhoeven
2022-10-12 7:02 ` [PATCH 1/2] clk: renesas: r8a779f0: Fix SD0H clock name Geert Uytterhoeven
2022-10-12 18:48 ` Wolfram Sang
2022-10-12 7:02 ` [PATCH 2/2] clk: renesas: r8a779f0: Add SASYNCPER internal clock Geert Uytterhoeven
2022-10-12 18:50 ` Wolfram Sang
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