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From: Ira Weiny <ira.weiny@intel.com>
To: Davidlohr Bueso <dave@stgolabs.net>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
	<alison.schofield@intel.com>, <bwidawsk@kernel.org>,
	<vishal.l.verma@intel.com>, <a.manzanares@samsung.com>,
	<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] cxl/pci: Add generic MSI-X/MSI irq support
Date: Thu, 20 Oct 2022 21:18:58 -0700	[thread overview]
Message-ID: <Y1Idsv0Nuu+V9aMj@iweiny-desk3> (raw)
In-Reply-To: <20221020223125.hyrfpt2noiicisxa@offworld>

On Thu, Oct 20, 2022 at 03:31:25PM -0700, Davidlohr Bueso wrote:
> On Tue, 18 Oct 2022, Jonathan Cameron wrote:
> 
> > Reality is that it is cleaner to more or less ignore the infrastructure
> > proposed in this patch.
> > 
> > 1. Query how many CPMU devices there are. Whilst there stash the maximim
> >   cpmu vector number in the cxlds.
> > 2. Run a stub in this infrastructure that does max(irq, cxlds->irq_num);
> > 3. Carry on as before.
> > 
> > Thus destroying the point of this infrastructure for that usecase at least
> > and leaving an extra bit of state in the cxl_dev_state that is just
> > to squirt a value into the callback...
> 
> If it doesn't fit, then it doesn't fit.
> 
> However, while I was expecting pass one to be in the callback, I wasn't
> expecting that both pass 1 and 2 shared the cpmu_regs_array. If the array
> could be reconstructed during pass 2, then it would fit a bit better;
> albeit the extra allocation, cycles etc., but this is probing phase, so
> overhead isn't that important (and cpmu_count isn't big enough to matter).
> 
> But if we're going to go with a free-for-all approach, can we establish
> who goes for the initial pci_alloc_irq_vectors()? I think perhaps mbox
> since it's the most straightforward and with least requirements, I'm
> also unsure of the status yet to merge events and pmu, but regardless
> they are still larger patchsets. If folks agree I can send a new mbox-only
> patch.

I think there needs to be some mechanism for all of the sub-device-functions to
report their max required vectors.

I don't think that the mbox code is necessarily the code which should need to
know about all those other sub-device-thingys.  But it could certainly take
some 'max vectors' value that probe passed to it.

I'm still not sure how dropping this infrastructure makes Jonathan's code
cleaner.  I still think there will need to be 2 passes over the number of
CPMU's.

Ira

> 
> Thanks,
> Davidlohr

  reply	other threads:[~2022-10-21  4:19 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-18  3:00 [PATCH v3 0/2] cxl: Add general MSI-X/MSI irq support Davidlohr Bueso
2022-10-18  3:00 ` [PATCH 1/2] cxl/pci: Add generic " Davidlohr Bueso
2022-10-18  9:36   ` Jonathan Cameron
2022-10-18 10:52     ` Jonathan Cameron
2022-10-20 22:31       ` Davidlohr Bueso
2022-10-21  4:18         ` Ira Weiny [this message]
2022-10-21  8:49           ` Jonathan Cameron
2022-10-21 16:20             ` Davidlohr Bueso
2022-10-21 21:05               ` Ira Weiny
2022-10-21  4:14       ` Ira Weiny
2022-10-21  8:58         ` Jonathan Cameron
2022-10-21 15:58           ` Davidlohr Bueso
2022-10-22 22:17           ` Dan Williams
2022-10-18 11:17   ` Jonathan Cameron
2022-10-22 22:05   ` Dan Williams
2022-10-24  0:09     ` Ira Weiny
2022-10-24  2:08       ` Dan Williams
2022-10-24 12:36         ` Jonathan Cameron
2022-10-25 23:25           ` Bjorn Helgaas
2022-10-30  8:38             ` Christoph Hellwig
2022-11-02 17:15             ` Davidlohr Bueso
2022-11-02 22:54               ` Bjorn Helgaas
2022-11-02 23:42               ` Ira Weiny
2022-11-03  0:18                 ` Davidlohr Bueso
2022-11-03 18:09                   ` Jonathan Cameron
2022-11-10  3:30                     ` Ira Weiny
2022-11-11 21:18                       ` Davidlohr Bueso
2022-11-03 18:08               ` Jonathan Cameron
2022-10-18  3:00 ` [PATCH 2/2] cxl/mbox: Wire up " Davidlohr Bueso
2022-10-18  9:38   ` Jonathan Cameron
2022-10-21 17:23     ` Davidlohr Bueso
2022-10-22 22:14       ` Dan Williams
2022-10-22 22:06   ` Dan Williams

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