[PATCH 0/5] Introduce the GSC CS

[PATCH 0/5] Introduce the GSC CS

[Daniele Ceraolo Spurio]

Starting on MTL, the GSC microcontroller resides inside the media GT
and the driver can communicate with it via a new Command Streamer, the
GSC CS. As a first step in supporting the GSC integration within the
media GT, this series adds the required defines and basic support for
this CS. Note that, given that the only user of this CS is i915 itself,
we don't need to expose it to userspace.

The CS has been purposely not added to the engine mask for MTL yet,
because it is only used in conjunction with the GSC FW, so there is
nothing we can do with it until we add support for the FW, which will
come as a separate next step.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Daniele Ceraolo Spurio (5):
  drm/i915/mtl: add initial definitions for GSC CS
  drm/i915/mtl: pass the GSC CS info to the GuC
  drm/i915/mtl: add GSC CS interrupt support
  drm/i915/mtl: add GSC CS reset support
  drm/i915/mtl: don't expose GSC command streamer to the user

 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |  9 +++
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  1 +
 drivers/gpu/drm/i915/gt/intel_engine_user.c  |  5 ++
 drivers/gpu/drm/i915/gt/intel_gt_irq.c       | 78 +++++++++++---------
 drivers/gpu/drm/i915/gt/intel_gt_regs.h      |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c   | 11 ++-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h  |  7 +-
 drivers/gpu/drm/i915/i915_reg.h              |  1 +
 8 files changed, 70 insertions(+), 43 deletions(-)

-- 
2.37.3

[Intel-gfx] [PATCH 0/5] Introduce the GSC CS

[Daniele Ceraolo Spurio]

Starting on MTL, the GSC microcontroller resides inside the media GT
and the driver can communicate with it via a new Command Streamer, the
GSC CS. As a first step in supporting the GSC integration within the
media GT, this series adds the required defines and basic support for
this CS. Note that, given that the only user of this CS is i915 itself,
we don't need to expose it to userspace.

The CS has been purposely not added to the engine mask for MTL yet,
because it is only used in conjunction with the GSC FW, so there is
nothing we can do with it until we add support for the FW, which will
come as a separate next step.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Daniele Ceraolo Spurio (5):
  drm/i915/mtl: add initial definitions for GSC CS
  drm/i915/mtl: pass the GSC CS info to the GuC
  drm/i915/mtl: add GSC CS interrupt support
  drm/i915/mtl: add GSC CS reset support
  drm/i915/mtl: don't expose GSC command streamer to the user

 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |  9 +++
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  1 +
 drivers/gpu/drm/i915/gt/intel_engine_user.c  |  5 ++
 drivers/gpu/drm/i915/gt/intel_gt_irq.c       | 78 +++++++++++---------
 drivers/gpu/drm/i915/gt/intel_gt_regs.h      |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c   | 11 ++-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h  |  7 +-
 drivers/gpu/drm/i915/i915_reg.h              |  1 +
 8 files changed, 70 insertions(+), 43 deletions(-)

-- 
2.37.3

[PATCH 1/5] drm/i915/mtl: add initial definitions for GSC CS

[Daniele Ceraolo Spurio]

Starting on MTL, the GSC is no longer managed with direct MMIO access,
but we instead have a dedicated command streamer for it. As a first step
for adding support for this CS, add the required definitions.
Note that, although it is now a CS, the GSC retains its old
class:instance value (OTHER_CLASS instance 6)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
 drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
 drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
 drivers/gpu/drm/i915/i915_reg.h              | 1 +
 4 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3b7d750ad054..e0fbfac03979 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
 			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
 		}
 	},
+	[GSC0] = {
+		.class = OTHER_CLASS,
+		.instance = OTHER_GSC_INSTANCE,
+		.mmio_bases = {
+			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
+		}
+	},
 };
 
 /**
@@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
 	case VIDEO_DECODE_CLASS:
 	case VIDEO_ENHANCEMENT_CLASS:
 	case COPY_ENGINE_CLASS:
+	case OTHER_CLASS:
 		if (GRAPHICS_VER(gt->i915) < 8)
 			return 0;
 		return GEN8_LR_CONTEXT_OTHER_SIZE;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 6b5d4ea22b67..4fd54fb8810f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -136,6 +136,7 @@ enum intel_engine_id {
 	CCS2,
 	CCS3,
 #define _CCS(n) (CCS0 + (n))
+	GSC0,
 	I915_NUM_ENGINES
 #define INVALID_ENGINE ((enum intel_engine_id)-1)
 };
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 46a174f8aa00..79312b734690 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
 		[COPY_ENGINE_CLASS] = "bcs",
 		[VIDEO_DECODE_CLASS] = "vcs",
 		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
+		[OTHER_CLASS] = "other",
 		[COMPUTE_CLASS] = "ccs",
 	};
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c0da50c0dc7..d056c3117ef2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -970,6 +970,7 @@
 #define GEN11_VEBOX2_RING_BASE		0x1d8000
 #define XEHP_VEBOX3_RING_BASE		0x1e8000
 #define XEHP_VEBOX4_RING_BASE		0x1f8000
+#define MTL_GSC_RING_BASE		0x11a000
 #define GEN12_COMPUTE0_RING_BASE	0x1a000
 #define GEN12_COMPUTE1_RING_BASE	0x1c000
 #define GEN12_COMPUTE2_RING_BASE	0x1e000
-- 
2.37.3

[Intel-gfx] [PATCH 1/5] drm/i915/mtl: add initial definitions for GSC CS

[Daniele Ceraolo Spurio]

Starting on MTL, the GSC is no longer managed with direct MMIO access,
but we instead have a dedicated command streamer for it. As a first step
for adding support for this CS, add the required definitions.
Note that, although it is now a CS, the GSC retains its old
class:instance value (OTHER_CLASS instance 6)

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
 drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
 drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
 drivers/gpu/drm/i915/i915_reg.h              | 1 +
 4 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3b7d750ad054..e0fbfac03979 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
 			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
 		}
 	},
+	[GSC0] = {
+		.class = OTHER_CLASS,
+		.instance = OTHER_GSC_INSTANCE,
+		.mmio_bases = {
+			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
+		}
+	},
 };
 
 /**
@@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
 	case VIDEO_DECODE_CLASS:
 	case VIDEO_ENHANCEMENT_CLASS:
 	case COPY_ENGINE_CLASS:
+	case OTHER_CLASS:
 		if (GRAPHICS_VER(gt->i915) < 8)
 			return 0;
 		return GEN8_LR_CONTEXT_OTHER_SIZE;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 6b5d4ea22b67..4fd54fb8810f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -136,6 +136,7 @@ enum intel_engine_id {
 	CCS2,
 	CCS3,
 #define _CCS(n) (CCS0 + (n))
+	GSC0,
 	I915_NUM_ENGINES
 #define INVALID_ENGINE ((enum intel_engine_id)-1)
 };
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 46a174f8aa00..79312b734690 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
 		[COPY_ENGINE_CLASS] = "bcs",
 		[VIDEO_DECODE_CLASS] = "vcs",
 		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
+		[OTHER_CLASS] = "other",
 		[COMPUTE_CLASS] = "ccs",
 	};
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c0da50c0dc7..d056c3117ef2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -970,6 +970,7 @@
 #define GEN11_VEBOX2_RING_BASE		0x1d8000
 #define XEHP_VEBOX3_RING_BASE		0x1e8000
 #define XEHP_VEBOX4_RING_BASE		0x1f8000
+#define MTL_GSC_RING_BASE		0x11a000
 #define GEN12_COMPUTE0_RING_BASE	0x1a000
 #define GEN12_COMPUTE1_RING_BASE	0x1c000
 #define GEN12_COMPUTE2_RING_BASE	0x1e000
-- 
2.37.3

[PATCH 2/5] drm/i915/mtl: pass the GSC CS info to the GuC

[Daniele Ceraolo Spurio]

We need to tell the GuC that the GSC CS is there. The GuC interface
swaps COMPUTE and OTHER class, so we also need to handle that.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  | 11 +++++------
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h |  7 +++++--
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 34ef4f36e660..63e3d98788bd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -478,6 +478,11 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
 	info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], BCS_MASK(gt));
 	info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));
 	info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));
+
+	/* The GSC engine is an instance (6) of OTHER_CLASS */
+	if (gt->engine[GSC0])
+		info_map_write(info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],
+			       BIT(gt->engine[GSC0]->instance));
 }
 
 #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
@@ -519,9 +524,6 @@ static int guc_prep_golden_context(struct intel_guc *guc)
 	}
 
 	for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
-		if (engine_class == OTHER_CLASS)
-			continue;
-
 		guc_class = engine_class_to_guc_class(engine_class);
 
 		if (!info_map_read(&info_map, engine_enabled_masks[guc_class]))
@@ -599,9 +601,6 @@ static void guc_init_golden_context(struct intel_guc *guc)
 	addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
 
 	for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
-		if (engine_class == OTHER_CLASS)
-			continue;
-
 		guc_class = engine_class_to_guc_class(engine_class);
 		if (!ads_blob_read(guc, system_info.engine_enabled_masks[guc_class]))
 			continue;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 968ebd79dce7..4ae5fc2f6002 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -47,7 +47,8 @@
 #define GUC_VIDEOENHANCE_CLASS		2
 #define GUC_BLITTER_CLASS		3
 #define GUC_COMPUTE_CLASS		4
-#define GUC_LAST_ENGINE_CLASS		GUC_COMPUTE_CLASS
+#define GUC_GSC_OTHER_CLASS		5
+#define GUC_LAST_ENGINE_CLASS		GUC_GSC_OTHER_CLASS
 #define GUC_MAX_ENGINE_CLASSES		16
 #define GUC_MAX_INSTANCES_PER_CLASS	32
 
@@ -169,6 +170,7 @@ static u8 engine_class_guc_class_map[] = {
 	[COPY_ENGINE_CLASS]       = GUC_BLITTER_CLASS,
 	[VIDEO_DECODE_CLASS]      = GUC_VIDEO_CLASS,
 	[VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS,
+	[OTHER_CLASS]             = GUC_GSC_OTHER_CLASS,
 	[COMPUTE_CLASS]           = GUC_COMPUTE_CLASS,
 };
 
@@ -178,12 +180,13 @@ static u8 guc_class_engine_class_map[] = {
 	[GUC_VIDEO_CLASS]        = VIDEO_DECODE_CLASS,
 	[GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS,
 	[GUC_COMPUTE_CLASS]      = COMPUTE_CLASS,
+	[GUC_GSC_OTHER_CLASS]    = OTHER_CLASS,
 };
 
 static inline u8 engine_class_to_guc_class(u8 class)
 {
 	BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1);
-	GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
+	GEM_BUG_ON(class > MAX_ENGINE_CLASS);
 
 	return engine_class_guc_class_map[class];
 }
-- 
2.37.3

[Intel-gfx] [PATCH 2/5] drm/i915/mtl: pass the GSC CS info to the GuC

[Daniele Ceraolo Spurio]

We need to tell the GuC that the GSC CS is there. The GuC interface
swaps COMPUTE and OTHER class, so we also need to handle that.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  | 11 +++++------
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h |  7 +++++--
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 34ef4f36e660..63e3d98788bd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -478,6 +478,11 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
 	info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], BCS_MASK(gt));
 	info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));
 	info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));
+
+	/* The GSC engine is an instance (6) of OTHER_CLASS */
+	if (gt->engine[GSC0])
+		info_map_write(info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],
+			       BIT(gt->engine[GSC0]->instance));
 }
 
 #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
@@ -519,9 +524,6 @@ static int guc_prep_golden_context(struct intel_guc *guc)
 	}
 
 	for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
-		if (engine_class == OTHER_CLASS)
-			continue;
-
 		guc_class = engine_class_to_guc_class(engine_class);
 
 		if (!info_map_read(&info_map, engine_enabled_masks[guc_class]))
@@ -599,9 +601,6 @@ static void guc_init_golden_context(struct intel_guc *guc)
 	addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
 
 	for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
-		if (engine_class == OTHER_CLASS)
-			continue;
-
 		guc_class = engine_class_to_guc_class(engine_class);
 		if (!ads_blob_read(guc, system_info.engine_enabled_masks[guc_class]))
 			continue;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 968ebd79dce7..4ae5fc2f6002 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -47,7 +47,8 @@
 #define GUC_VIDEOENHANCE_CLASS		2
 #define GUC_BLITTER_CLASS		3
 #define GUC_COMPUTE_CLASS		4
-#define GUC_LAST_ENGINE_CLASS		GUC_COMPUTE_CLASS
+#define GUC_GSC_OTHER_CLASS		5
+#define GUC_LAST_ENGINE_CLASS		GUC_GSC_OTHER_CLASS
 #define GUC_MAX_ENGINE_CLASSES		16
 #define GUC_MAX_INSTANCES_PER_CLASS	32
 
@@ -169,6 +170,7 @@ static u8 engine_class_guc_class_map[] = {
 	[COPY_ENGINE_CLASS]       = GUC_BLITTER_CLASS,
 	[VIDEO_DECODE_CLASS]      = GUC_VIDEO_CLASS,
 	[VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS,
+	[OTHER_CLASS]             = GUC_GSC_OTHER_CLASS,
 	[COMPUTE_CLASS]           = GUC_COMPUTE_CLASS,
 };
 
@@ -178,12 +180,13 @@ static u8 guc_class_engine_class_map[] = {
 	[GUC_VIDEO_CLASS]        = VIDEO_DECODE_CLASS,
 	[GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS,
 	[GUC_COMPUTE_CLASS]      = COMPUTE_CLASS,
+	[GUC_GSC_OTHER_CLASS]    = OTHER_CLASS,
 };
 
 static inline u8 engine_class_to_guc_class(u8 class)
 {
 	BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1);
-	GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
+	GEM_BUG_ON(class > MAX_ENGINE_CLASS);
 
 	return engine_class_guc_class_map[class];
 }
-- 
2.37.3

[PATCH 3/5] drm/i915/mtl: add GSC CS interrupt support

[Daniele Ceraolo Spurio]

The GSC CS re-uses the same interrupt bits that the GSC used in older
platforms. This means that we can now have an engine interrupt coming
out of OTHER_CLASS, so we need to handle that appropriately.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_irq.c | 78 ++++++++++++++------------
 1 file changed, 43 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f26882fdc24c..34ff1ee7e931 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
 		  instance, iir);
 }
 
-static void
-gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
-			 const u8 instance, const u16 iir)
+static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)
 {
-	struct intel_engine_cs *engine;
-
-	/*
-	 * Platforms with standalone media have their media engines in another
-	 * GT.
-	 */
-	if (MEDIA_VER(gt->i915) >= 13 &&
-	    (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
-		if (!gt->i915->media_gt)
-			goto err;
+	struct intel_gt *media_gt = gt->i915->media_gt;
 
-		gt = gt->i915->media_gt;
+	/* we expect the non-media gt to be passed in */
+	GEM_BUG_ON(gt == media_gt);
+
+	if (!media_gt)
+		return gt;
+
+	switch (class) {
+	case VIDEO_DECODE_CLASS:
+	case VIDEO_ENHANCEMENT_CLASS:
+		return media_gt;
+	case OTHER_CLASS:
+		if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
+			return media_gt;
+		fallthrough;
+	default:
+		return gt;
 	}
-
-	if (instance <= MAX_ENGINE_INSTANCE)
-		engine = gt->engine_class[class][instance];
-	else
-		engine = NULL;
-
-	if (likely(engine))
-		return intel_engine_cs_irq(engine, iir);
-
-err:
-	WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
-		  class, instance);
 }
 
 static void
@@ -118,12 +110,24 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
 	const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
 	const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
 	const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
+	struct intel_engine_cs *engine;
 
 	if (unlikely(!intr))
 		return;
 
-	if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
-		return gen11_engine_irq_handler(gt, class, instance, intr);
+	/*
+	 * Platforms with standalone media have the media and GSC engines in
+	 * another GT.
+	 */
+	gt = pick_gt(gt, class, instance);
+
+	if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE)
+		engine = gt->engine_class[class][instance];
+	else
+		engine = NULL;
+
+	if (engine)
+		return intel_engine_cs_irq(engine, intr);
 
 	if (class == OTHER_CLASS)
 		return gen11_other_irq_handler(gt, instance, intr);
@@ -206,7 +210,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
 	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,	  0);
 	if (CCS_MASK(gt))
 		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
-	if (HAS_HECI_GSC(gt->i915))
+	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
 
 	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
@@ -233,7 +237,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
 		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
 	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
 		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
-	if (HAS_HECI_GSC(gt->i915))
+	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
 
 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
@@ -249,7 +253,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
 {
 	struct intel_uncore *uncore = gt->uncore;
 	u32 irqs = GT_RENDER_USER_INTERRUPT;
-	const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
+	u32 gsc_mask = 0;
 	u32 dmask;
 	u32 smask;
 
@@ -261,6 +265,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
 	dmask = irqs << 16 | irqs;
 	smask = irqs << 16;
 
+	if (HAS_ENGINE(gt, GSC0))
+		gsc_mask = irqs;
+	else if (HAS_HECI_GSC(gt->i915))
+		gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
+
 	BUILD_BUG_ON(irqs & 0xffff0000);
 
 	/* Enable RCS, BCS, VCS and VECS class interrupts. */
@@ -268,9 +277,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
 	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
 	if (CCS_MASK(gt))
 		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
-	if (HAS_HECI_GSC(gt->i915))
-		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
-				   gsc_mask);
+	if (gsc_mask)
+		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask);
 
 	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
 	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
@@ -296,7 +304,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
 		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
 	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
 		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
-	if (HAS_HECI_GSC(gt->i915))
+	if (gsc_mask)
 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
 
 	/*
-- 
2.37.3

[Intel-gfx] [PATCH 3/5] drm/i915/mtl: add GSC CS interrupt support

[Daniele Ceraolo Spurio]

The GSC CS re-uses the same interrupt bits that the GSC used in older
platforms. This means that we can now have an engine interrupt coming
out of OTHER_CLASS, so we need to handle that appropriately.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_irq.c | 78 ++++++++++++++------------
 1 file changed, 43 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f26882fdc24c..34ff1ee7e931 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
 		  instance, iir);
 }
 
-static void
-gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
-			 const u8 instance, const u16 iir)
+static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)
 {
-	struct intel_engine_cs *engine;
-
-	/*
-	 * Platforms with standalone media have their media engines in another
-	 * GT.
-	 */
-	if (MEDIA_VER(gt->i915) >= 13 &&
-	    (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
-		if (!gt->i915->media_gt)
-			goto err;
+	struct intel_gt *media_gt = gt->i915->media_gt;
 
-		gt = gt->i915->media_gt;
+	/* we expect the non-media gt to be passed in */
+	GEM_BUG_ON(gt == media_gt);
+
+	if (!media_gt)
+		return gt;
+
+	switch (class) {
+	case VIDEO_DECODE_CLASS:
+	case VIDEO_ENHANCEMENT_CLASS:
+		return media_gt;
+	case OTHER_CLASS:
+		if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
+			return media_gt;
+		fallthrough;
+	default:
+		return gt;
 	}
-
-	if (instance <= MAX_ENGINE_INSTANCE)
-		engine = gt->engine_class[class][instance];
-	else
-		engine = NULL;
-
-	if (likely(engine))
-		return intel_engine_cs_irq(engine, iir);
-
-err:
-	WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
-		  class, instance);
 }
 
 static void
@@ -118,12 +110,24 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
 	const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
 	const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
 	const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
+	struct intel_engine_cs *engine;
 
 	if (unlikely(!intr))
 		return;
 
-	if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
-		return gen11_engine_irq_handler(gt, class, instance, intr);
+	/*
+	 * Platforms with standalone media have the media and GSC engines in
+	 * another GT.
+	 */
+	gt = pick_gt(gt, class, instance);
+
+	if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE)
+		engine = gt->engine_class[class][instance];
+	else
+		engine = NULL;
+
+	if (engine)
+		return intel_engine_cs_irq(engine, intr);
 
 	if (class == OTHER_CLASS)
 		return gen11_other_irq_handler(gt, instance, intr);
@@ -206,7 +210,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
 	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,	  0);
 	if (CCS_MASK(gt))
 		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
-	if (HAS_HECI_GSC(gt->i915))
+	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
 
 	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
@@ -233,7 +237,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
 		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
 	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
 		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
-	if (HAS_HECI_GSC(gt->i915))
+	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
 
 	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
@@ -249,7 +253,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
 {
 	struct intel_uncore *uncore = gt->uncore;
 	u32 irqs = GT_RENDER_USER_INTERRUPT;
-	const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
+	u32 gsc_mask = 0;
 	u32 dmask;
 	u32 smask;
 
@@ -261,6 +265,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
 	dmask = irqs << 16 | irqs;
 	smask = irqs << 16;
 
+	if (HAS_ENGINE(gt, GSC0))
+		gsc_mask = irqs;
+	else if (HAS_HECI_GSC(gt->i915))
+		gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
+
 	BUILD_BUG_ON(irqs & 0xffff0000);
 
 	/* Enable RCS, BCS, VCS and VECS class interrupts. */
@@ -268,9 +277,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
 	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
 	if (CCS_MASK(gt))
 		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
-	if (HAS_HECI_GSC(gt->i915))
-		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
-				   gsc_mask);
+	if (gsc_mask)
+		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask);
 
 	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
 	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
@@ -296,7 +304,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
 		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
 	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
 		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
-	if (HAS_HECI_GSC(gt->i915))
+	if (gsc_mask)
 		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
 
 	/*
-- 
2.37.3

[Intel-gfx] [PATCH 4/5] drm/i915/mtl: add GSC CS reset support

[Daniele Ceraolo Spurio]

The GSC CS has its own dedicated bit in the GDRST register.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index e0fbfac03979..f63829abf66c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -423,6 +423,7 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
 			[CCS1]  = GEN11_GRDOM_RENDER,
 			[CCS2]  = GEN11_GRDOM_RENDER,
 			[CCS3]  = GEN11_GRDOM_RENDER,
+			[GSC0]  = GEN12_GRDOM_GSC,
 		};
 		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
 			   !engine_reset_domains[id]);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 23844ba7e824..16cf90306085 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -640,6 +640,7 @@
 #define   XEHPC_GRDOM_BLT3			REG_BIT(26)
 #define   XEHPC_GRDOM_BLT2			REG_BIT(25)
 #define   XEHPC_GRDOM_BLT1			REG_BIT(24)
+#define   GEN12_GRDOM_GSC			REG_BIT(21)
 #define   GEN11_GRDOM_SFC3			REG_BIT(20)
 #define   GEN11_GRDOM_SFC2			REG_BIT(19)
 #define   GEN11_GRDOM_SFC1			REG_BIT(18)
-- 
2.37.3

[PATCH 4/5] drm/i915/mtl: add GSC CS reset support

[Daniele Ceraolo Spurio]

The GSC CS has its own dedicated bit in the GDRST register.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index e0fbfac03979..f63829abf66c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -423,6 +423,7 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
 			[CCS1]  = GEN11_GRDOM_RENDER,
 			[CCS2]  = GEN11_GRDOM_RENDER,
 			[CCS3]  = GEN11_GRDOM_RENDER,
+			[GSC0]  = GEN12_GRDOM_GSC,
 		};
 		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
 			   !engine_reset_domains[id]);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 23844ba7e824..16cf90306085 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -640,6 +640,7 @@
 #define   XEHPC_GRDOM_BLT3			REG_BIT(26)
 #define   XEHPC_GRDOM_BLT2			REG_BIT(25)
 #define   XEHPC_GRDOM_BLT1			REG_BIT(24)
+#define   GEN12_GRDOM_GSC			REG_BIT(21)
 #define   GEN11_GRDOM_SFC3			REG_BIT(20)
 #define   GEN11_GRDOM_SFC2			REG_BIT(19)
 #define   GEN11_GRDOM_SFC1			REG_BIT(18)
-- 
2.37.3

[PATCH 5/5] drm/i915/mtl: don't expose GSC command streamer to the user

[Daniele Ceraolo Spurio]

There is no userspace user for this CS yet, we only need it for internal
kernel ops (e.g. HuC, PXP), so don't expose it.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 79312b734690..ca795daca116 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -211,6 +211,10 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
 		if (intel_gt_has_unrecoverable_error(engine->gt))
 			continue; /* ignore incomplete engines */
 
+		/* don't expose GSC engine to user */
+		if (engine->class == OTHER_CLASS)
+			continue;
+
 		GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
 		engine->uabi_class = uabi_classes[engine->class];
 
-- 
2.37.3

[Intel-gfx] [PATCH 5/5] drm/i915/mtl: don't expose GSC command streamer to the user

[Daniele Ceraolo Spurio]

There is no userspace user for this CS yet, we only need it for internal
kernel ops (e.g. HuC, PXP), so don't expose it.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 79312b734690..ca795daca116 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -211,6 +211,10 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
 		if (intel_gt_has_unrecoverable_error(engine->gt))
 			continue; /* ignore incomplete engines */
 
+		/* don't expose GSC engine to user */
+		if (engine->class == OTHER_CLASS)
+			continue;
+
 		GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
 		engine->uabi_class = uabi_classes[engine->class];
 
-- 
2.37.3

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce the GSC CS

[Patchwork]

== Series Details ==

Series: Introduce the GSC CS
URL   : https://patchwork.freedesktop.org/series/110237/
State : warning

== Summary ==

Error: dim checkpatch failed
9a055873a680 drm/i915/mtl: add initial definitions for GSC CS
ddb719782376 drm/i915/mtl: pass the GSC CS info to the GuC
-:81: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#81: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h:189:
+	GEM_BUG_ON(class > MAX_ENGINE_CLASS);

total: 0 errors, 1 warnings, 0 checks, 59 lines checked
e62d625db085 drm/i915/mtl: add GSC CS interrupt support
-:40: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#40: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq.c:89:
+	GEM_BUG_ON(gt == media_gt);

total: 0 errors, 1 warnings, 0 checks, 133 lines checked
4f9506c1fa4d drm/i915/mtl: add GSC CS reset support
237e5c9277d0 drm/i915/mtl: don't expose GSC command streamer to the user

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce the GSC CS

[Patchwork]

== Series Details ==

Series: Introduce the GSC CS
URL   : https://patchwork.freedesktop.org/series/110237/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [PATCH 1/5] drm/i915/mtl: add initial definitions for GSC CS

[Matt Roper]

On Thu, Oct 27, 2022 at 03:15:50PM -0700, Daniele Ceraolo Spurio wrote:
> Starting on MTL, the GSC is no longer managed with direct MMIO access,
> but we instead have a dedicated command streamer for it. As a first step
> for adding support for this CS, add the required definitions.
> Note that, although it is now a CS, the GSC retains its old
> class:instance value (OTHER_CLASS instance 6)
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Maybe add "Bspec: 65308, 45605" as a reference?

Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
>  drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
>  drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
>  drivers/gpu/drm/i915/i915_reg.h              | 1 +
>  4 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 3b7d750ad054..e0fbfac03979 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
>  			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
>  		}
>  	},
> +	[GSC0] = {
> +		.class = OTHER_CLASS,
> +		.instance = OTHER_GSC_INSTANCE,
> +		.mmio_bases = {
> +			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
> +		}
> +	},
>  };
>  
>  /**
> @@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
>  	case VIDEO_DECODE_CLASS:
>  	case VIDEO_ENHANCEMENT_CLASS:
>  	case COPY_ENGINE_CLASS:
> +	case OTHER_CLASS:
>  		if (GRAPHICS_VER(gt->i915) < 8)
>  			return 0;
>  		return GEN8_LR_CONTEXT_OTHER_SIZE;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 6b5d4ea22b67..4fd54fb8810f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -136,6 +136,7 @@ enum intel_engine_id {
>  	CCS2,
>  	CCS3,
>  #define _CCS(n) (CCS0 + (n))
> +	GSC0,
>  	I915_NUM_ENGINES
>  #define INVALID_ENGINE ((enum intel_engine_id)-1)
>  };
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 46a174f8aa00..79312b734690 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
>  		[COPY_ENGINE_CLASS] = "bcs",
>  		[VIDEO_DECODE_CLASS] = "vcs",
>  		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
> +		[OTHER_CLASS] = "other",
>  		[COMPUTE_CLASS] = "ccs",
>  	};
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1c0da50c0dc7..d056c3117ef2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -970,6 +970,7 @@
>  #define GEN11_VEBOX2_RING_BASE		0x1d8000
>  #define XEHP_VEBOX3_RING_BASE		0x1e8000
>  #define XEHP_VEBOX4_RING_BASE		0x1f8000
> +#define MTL_GSC_RING_BASE		0x11a000
>  #define GEN12_COMPUTE0_RING_BASE	0x1a000
>  #define GEN12_COMPUTE1_RING_BASE	0x1c000
>  #define GEN12_COMPUTE2_RING_BASE	0x1e000
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 1/5] drm/i915/mtl: add initial definitions for GSC CS

[Matt Roper]

On Thu, Oct 27, 2022 at 03:15:50PM -0700, Daniele Ceraolo Spurio wrote:
> Starting on MTL, the GSC is no longer managed with direct MMIO access,
> but we instead have a dedicated command streamer for it. As a first step
> for adding support for this CS, add the required definitions.
> Note that, although it is now a CS, the GSC retains its old
> class:instance value (OTHER_CLASS instance 6)
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Maybe add "Bspec: 65308, 45605" as a reference?

Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
>  drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
>  drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
>  drivers/gpu/drm/i915/i915_reg.h              | 1 +
>  4 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 3b7d750ad054..e0fbfac03979 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
>  			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
>  		}
>  	},
> +	[GSC0] = {
> +		.class = OTHER_CLASS,
> +		.instance = OTHER_GSC_INSTANCE,
> +		.mmio_bases = {
> +			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
> +		}
> +	},
>  };
>  
>  /**
> @@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
>  	case VIDEO_DECODE_CLASS:
>  	case VIDEO_ENHANCEMENT_CLASS:
>  	case COPY_ENGINE_CLASS:
> +	case OTHER_CLASS:
>  		if (GRAPHICS_VER(gt->i915) < 8)
>  			return 0;
>  		return GEN8_LR_CONTEXT_OTHER_SIZE;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 6b5d4ea22b67..4fd54fb8810f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -136,6 +136,7 @@ enum intel_engine_id {
>  	CCS2,
>  	CCS3,
>  #define _CCS(n) (CCS0 + (n))
> +	GSC0,
>  	I915_NUM_ENGINES
>  #define INVALID_ENGINE ((enum intel_engine_id)-1)
>  };
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 46a174f8aa00..79312b734690 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
>  		[COPY_ENGINE_CLASS] = "bcs",
>  		[VIDEO_DECODE_CLASS] = "vcs",
>  		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
> +		[OTHER_CLASS] = "other",
>  		[COMPUTE_CLASS] = "ccs",
>  	};
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1c0da50c0dc7..d056c3117ef2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -970,6 +970,7 @@
>  #define GEN11_VEBOX2_RING_BASE		0x1d8000
>  #define XEHP_VEBOX3_RING_BASE		0x1e8000
>  #define XEHP_VEBOX4_RING_BASE		0x1f8000
> +#define MTL_GSC_RING_BASE		0x11a000
>  #define GEN12_COMPUTE0_RING_BASE	0x1a000
>  #define GEN12_COMPUTE1_RING_BASE	0x1c000
>  #define GEN12_COMPUTE2_RING_BASE	0x1e000
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce the GSC CS

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 11189 bytes --]

== Series Details ==

Series: Introduce the GSC CS
URL   : https://patchwork.freedesktop.org/series/110237/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12313 -> Patchwork_110237v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/index.html

Participating hosts (37 -> 38)
------------------------------

  Additional (4): fi-blb-e6850 fi-rkl-11600 bat-adls-5 fi-apl-guc 
  Missing    (3): fi-ctg-p8600 fi-hsw-4770 bat-adlp-6 

Known issues
------------

  Here are the changes found in Patchwork_110237v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - fi-rkl-11600:       NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-apl-guc:         NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-apl-guc/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-rkl-11600:       NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
    - fi-rkl-11600:       NOTRUN -> [SKIP][4] ([i915#3282])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
    - fi-rkl-11600:       NOTRUN -> [SKIP][5] ([i915#3012])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_pm_rpm@module-reload:
    - fi-blb-e6850:       NOTRUN -> [SKIP][6] ([fdo#109271]) +43 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-blb-e6850/igt@i915_pm_rpm@module-reload.html

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-rkl-11600:       NOTRUN -> [INCOMPLETE][7] ([i915#4817])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-rkl-guc:         NOTRUN -> [SKIP][8] ([fdo#111827])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-guc/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-apl-guc:         NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-apl-guc/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-rkl-11600:       NOTRUN -> [SKIP][10] ([fdo#111827]) +7 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-11600/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
    - fi-rkl-11600:       NOTRUN -> [SKIP][11] ([i915#4103])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-connector-state:
    - fi-apl-guc:         NOTRUN -> [SKIP][12] ([fdo#109271]) +13 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-apl-guc/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-rkl-11600:       NOTRUN -> [SKIP][13] ([fdo#109285] / [i915#4098])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_psr@sprite_plane_onoff:
    - fi-rkl-11600:       NOTRUN -> [SKIP][14] ([i915#1072]) +3 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-11600/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-rkl-11600:       NOTRUN -> [SKIP][15] ([i915#3555] / [i915#4098])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-read:
    - fi-rkl-11600:       NOTRUN -> [SKIP][16] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-11600/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-userptr:
    - fi-rkl-11600:       NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3301] / [i915#3708])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-11600/igt@prime_vgem@basic-userptr.html

  
#### Possible fixes ####

  * igt@gem_huc_copy@huc-copy:
    - {bat-dg2-8}:        [FAIL][18] ([i915#7029]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/bat-dg2-8/igt@gem_huc_copy@huc-copy.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/bat-dg2-8/igt@gem_huc_copy@huc-copy.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-cfl-8109u:       [DMESG-FAIL][20] ([i915#5334]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
    - fi-bxt-dsi:         [DMESG-FAIL][22] ([i915#5334]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_lrc:
    - fi-rkl-guc:         [INCOMPLETE][24] ([i915#4983]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@hangcheck:
    - {bat-dg2-8}:        [INCOMPLETE][26] -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/bat-dg2-8/igt@i915_selftest@live@hangcheck.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/bat-dg2-8/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@hugepages:
    - {bat-adln-1}:       [DMESG-WARN][28] ([i915#5278]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/bat-adln-1/igt@i915_selftest@live@hugepages.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/bat-adln-1/igt@i915_selftest@live@hugepages.html

  * igt@i915_selftest@live@requests:
    - {bat-rpls-1}:       [INCOMPLETE][30] ([i915#4983]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/bat-rpls-1/igt@i915_selftest@live@requests.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/bat-rpls-1/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@reset:
    - {bat-rpls-2}:       [DMESG-FAIL][32] ([i915#4983] / [i915#5828]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/bat-rpls-2/igt@i915_selftest@live@reset.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/bat-rpls-2/igt@i915_selftest@live@reset.html

  * igt@kms_frontbuffer_tracking@basic:
    - {bat-rpls-2}:       [SKIP][34] ([i915#1849]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/bat-rpls-2/igt@kms_frontbuffer_tracking@basic.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/bat-rpls-2/igt@kms_frontbuffer_tracking@basic.html

  * igt@prime_vgem@basic-fence-flip:
    - {bat-rpls-2}:       [SKIP][36] ([fdo#109295] / [i915#1845] / [i915#3708]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/bat-rpls-2/igt@prime_vgem@basic-fence-flip.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/bat-rpls-2/igt@prime_vgem@basic-fence-flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
  [i915#5828]: https://gitlab.freedesktop.org/drm/intel/issues/5828
  [i915#6559]: https://gitlab.freedesktop.org/drm/intel/issues/6559
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7029]: https://gitlab.freedesktop.org/drm/intel/issues/7029


Build changes
-------------

  * Linux: CI_DRM_12313 -> Patchwork_110237v1

  CI-20190529: 20190529
  CI_DRM_12313: 9d6a004b1594b83b2d94776daa23757892423837 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7028: 9e635a1c502970e7e6d64112d409392a2f01c688 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110237v1: 9d6a004b1594b83b2d94776daa23757892423837 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

717d06ff3794 drm/i915/mtl: don't expose GSC command streamer to the user
f752097b56bb drm/i915/mtl: add GSC CS reset support
759d622b1cea drm/i915/mtl: add GSC CS interrupt support
15f7d66230ba drm/i915/mtl: pass the GSC CS info to the GuC
abe0b1df84ed drm/i915/mtl: add initial definitions for GSC CS

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/index.html

[-- Attachment #2: Type: text/html, Size: 13017 bytes --]

Re: [PATCH 2/5] drm/i915/mtl: pass the GSC CS info to the GuC

[Matt Roper]

On Thu, Oct 27, 2022 at 03:15:51PM -0700, Daniele Ceraolo Spurio wrote:
> We need to tell the GuC that the GSC CS is there. The GuC interface
> swaps COMPUTE and OTHER class, so we also need to handle that.

When I first read the second sentence here, I thought you were saying
that the GuC interface had changed and redefined its own enums, but
that's not the case.  I think you just meant that the FOO_CLASS and
GUC_FOO_CLASS enums are nearly the same except that they order COMPUTE
and OTHER classes differently.  Honestly I think that's already pretty
clear from the existing values and mapping tables, even before this
patch, so I'd just leave this sentence off to avoid confusion.

Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  | 11 +++++------
>  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h |  7 +++++--
>  2 files changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 34ef4f36e660..63e3d98788bd 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -478,6 +478,11 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
>  	info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], BCS_MASK(gt));
>  	info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));
>  	info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));
> +
> +	/* The GSC engine is an instance (6) of OTHER_CLASS */
> +	if (gt->engine[GSC0])
> +		info_map_write(info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],
> +			       BIT(gt->engine[GSC0]->instance));
>  }
>  
>  #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
> @@ -519,9 +524,6 @@ static int guc_prep_golden_context(struct intel_guc *guc)
>  	}
>  
>  	for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
> -		if (engine_class == OTHER_CLASS)
> -			continue;
> -
>  		guc_class = engine_class_to_guc_class(engine_class);
>  
>  		if (!info_map_read(&info_map, engine_enabled_masks[guc_class]))
> @@ -599,9 +601,6 @@ static void guc_init_golden_context(struct intel_guc *guc)
>  	addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
>  
>  	for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
> -		if (engine_class == OTHER_CLASS)
> -			continue;
> -
>  		guc_class = engine_class_to_guc_class(engine_class);
>  		if (!ads_blob_read(guc, system_info.engine_enabled_masks[guc_class]))
>  			continue;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index 968ebd79dce7..4ae5fc2f6002 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -47,7 +47,8 @@
>  #define GUC_VIDEOENHANCE_CLASS		2
>  #define GUC_BLITTER_CLASS		3
>  #define GUC_COMPUTE_CLASS		4
> -#define GUC_LAST_ENGINE_CLASS		GUC_COMPUTE_CLASS
> +#define GUC_GSC_OTHER_CLASS		5
> +#define GUC_LAST_ENGINE_CLASS		GUC_GSC_OTHER_CLASS
>  #define GUC_MAX_ENGINE_CLASSES		16
>  #define GUC_MAX_INSTANCES_PER_CLASS	32
>  
> @@ -169,6 +170,7 @@ static u8 engine_class_guc_class_map[] = {
>  	[COPY_ENGINE_CLASS]       = GUC_BLITTER_CLASS,
>  	[VIDEO_DECODE_CLASS]      = GUC_VIDEO_CLASS,
>  	[VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS,
> +	[OTHER_CLASS]             = GUC_GSC_OTHER_CLASS,
>  	[COMPUTE_CLASS]           = GUC_COMPUTE_CLASS,
>  };
>  
> @@ -178,12 +180,13 @@ static u8 guc_class_engine_class_map[] = {
>  	[GUC_VIDEO_CLASS]        = VIDEO_DECODE_CLASS,
>  	[GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS,
>  	[GUC_COMPUTE_CLASS]      = COMPUTE_CLASS,
> +	[GUC_GSC_OTHER_CLASS]    = OTHER_CLASS,
>  };
>  
>  static inline u8 engine_class_to_guc_class(u8 class)
>  {
>  	BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1);
> -	GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
> +	GEM_BUG_ON(class > MAX_ENGINE_CLASS);
>  
>  	return engine_class_guc_class_map[class];
>  }
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 2/5] drm/i915/mtl: pass the GSC CS info to the GuC

[Matt Roper]

On Thu, Oct 27, 2022 at 03:15:51PM -0700, Daniele Ceraolo Spurio wrote:
> We need to tell the GuC that the GSC CS is there. The GuC interface
> swaps COMPUTE and OTHER class, so we also need to handle that.

When I first read the second sentence here, I thought you were saying
that the GuC interface had changed and redefined its own enums, but
that's not the case.  I think you just meant that the FOO_CLASS and
GUC_FOO_CLASS enums are nearly the same except that they order COMPUTE
and OTHER classes differently.  Honestly I think that's already pretty
clear from the existing values and mapping tables, even before this
patch, so I'd just leave this sentence off to avoid confusion.

Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  | 11 +++++------
>  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h |  7 +++++--
>  2 files changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 34ef4f36e660..63e3d98788bd 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -478,6 +478,11 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
>  	info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], BCS_MASK(gt));
>  	info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt));
>  	info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));
> +
> +	/* The GSC engine is an instance (6) of OTHER_CLASS */
> +	if (gt->engine[GSC0])
> +		info_map_write(info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],
> +			       BIT(gt->engine[GSC0]->instance));
>  }
>  
>  #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
> @@ -519,9 +524,6 @@ static int guc_prep_golden_context(struct intel_guc *guc)
>  	}
>  
>  	for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
> -		if (engine_class == OTHER_CLASS)
> -			continue;
> -
>  		guc_class = engine_class_to_guc_class(engine_class);
>  
>  		if (!info_map_read(&info_map, engine_enabled_masks[guc_class]))
> @@ -599,9 +601,6 @@ static void guc_init_golden_context(struct intel_guc *guc)
>  	addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
>  
>  	for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
> -		if (engine_class == OTHER_CLASS)
> -			continue;
> -
>  		guc_class = engine_class_to_guc_class(engine_class);
>  		if (!ads_blob_read(guc, system_info.engine_enabled_masks[guc_class]))
>  			continue;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index 968ebd79dce7..4ae5fc2f6002 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -47,7 +47,8 @@
>  #define GUC_VIDEOENHANCE_CLASS		2
>  #define GUC_BLITTER_CLASS		3
>  #define GUC_COMPUTE_CLASS		4
> -#define GUC_LAST_ENGINE_CLASS		GUC_COMPUTE_CLASS
> +#define GUC_GSC_OTHER_CLASS		5
> +#define GUC_LAST_ENGINE_CLASS		GUC_GSC_OTHER_CLASS
>  #define GUC_MAX_ENGINE_CLASSES		16
>  #define GUC_MAX_INSTANCES_PER_CLASS	32
>  
> @@ -169,6 +170,7 @@ static u8 engine_class_guc_class_map[] = {
>  	[COPY_ENGINE_CLASS]       = GUC_BLITTER_CLASS,
>  	[VIDEO_DECODE_CLASS]      = GUC_VIDEO_CLASS,
>  	[VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS,
> +	[OTHER_CLASS]             = GUC_GSC_OTHER_CLASS,
>  	[COMPUTE_CLASS]           = GUC_COMPUTE_CLASS,
>  };
>  
> @@ -178,12 +180,13 @@ static u8 guc_class_engine_class_map[] = {
>  	[GUC_VIDEO_CLASS]        = VIDEO_DECODE_CLASS,
>  	[GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS,
>  	[GUC_COMPUTE_CLASS]      = COMPUTE_CLASS,
> +	[GUC_GSC_OTHER_CLASS]    = OTHER_CLASS,
>  };
>  
>  static inline u8 engine_class_to_guc_class(u8 class)
>  {
>  	BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1);
> -	GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
> +	GEM_BUG_ON(class > MAX_ENGINE_CLASS);
>  
>  	return engine_class_guc_class_map[class];
>  }
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [PATCH 3/5] drm/i915/mtl: add GSC CS interrupt support

[Matt Roper]

On Thu, Oct 27, 2022 at 03:15:52PM -0700, Daniele Ceraolo Spurio wrote:
> The GSC CS re-uses the same interrupt bits that the GSC used in older
> platforms. This means that we can now have an engine interrupt coming
> out of OTHER_CLASS, so we need to handle that appropriately.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_gt_irq.c | 78 ++++++++++++++------------
>  1 file changed, 43 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index f26882fdc24c..34ff1ee7e931 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
>  		  instance, iir);
>  }
>  
> -static void
> -gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
> -			 const u8 instance, const u16 iir)
> +static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)
>  {
> -	struct intel_engine_cs *engine;
> -
> -	/*
> -	 * Platforms with standalone media have their media engines in another
> -	 * GT.
> -	 */
> -	if (MEDIA_VER(gt->i915) >= 13 &&
> -	    (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
> -		if (!gt->i915->media_gt)
> -			goto err;
> +	struct intel_gt *media_gt = gt->i915->media_gt;
>  
> -		gt = gt->i915->media_gt;
> +	/* we expect the non-media gt to be passed in */
> +	GEM_BUG_ON(gt == media_gt);
> +
> +	if (!media_gt)
> +		return gt;
> +
> +	switch (class) {
> +	case VIDEO_DECODE_CLASS:
> +	case VIDEO_ENHANCEMENT_CLASS:
> +		return media_gt;
> +	case OTHER_CLASS:
> +		if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
> +			return media_gt;
> +		fallthrough;
> +	default:
> +		return gt;
>  	}
> -
> -	if (instance <= MAX_ENGINE_INSTANCE)
> -		engine = gt->engine_class[class][instance];
> -	else
> -		engine = NULL;
> -
> -	if (likely(engine))
> -		return intel_engine_cs_irq(engine, iir);
> -
> -err:
> -	WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
> -		  class, instance);
>  }
>  
>  static void
> @@ -118,12 +110,24 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
>  	const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
>  	const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
>  	const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
> +	struct intel_engine_cs *engine;
>  
>  	if (unlikely(!intr))
>  		return;
>  
> -	if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
> -		return gen11_engine_irq_handler(gt, class, instance, intr);
> +	/*
> +	 * Platforms with standalone media have the media and GSC engines in
> +	 * another GT.
> +	 */
> +	gt = pick_gt(gt, class, instance);
> +
> +	if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE)
> +		engine = gt->engine_class[class][instance];
> +	else
> +		engine = NULL;
> +
> +	if (engine)
> +		return intel_engine_cs_irq(engine, intr);
>  
>  	if (class == OTHER_CLASS)
>  		return gen11_other_irq_handler(gt, instance, intr);
> @@ -206,7 +210,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
>  	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,	  0);
>  	if (CCS_MASK(gt))
>  		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
> -	if (HAS_HECI_GSC(gt->i915))
> +	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
>  		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
>  
>  	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> @@ -233,7 +237,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
>  		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
>  	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
>  		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
> -	if (HAS_HECI_GSC(gt->i915))
> +	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
>  		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
>  
>  	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
> @@ -249,7 +253,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>  {
>  	struct intel_uncore *uncore = gt->uncore;
>  	u32 irqs = GT_RENDER_USER_INTERRUPT;
> -	const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
> +	u32 gsc_mask = 0;
>  	u32 dmask;
>  	u32 smask;
>  
> @@ -261,6 +265,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>  	dmask = irqs << 16 | irqs;
>  	smask = irqs << 16;
>  
> +	if (HAS_ENGINE(gt, GSC0))
> +		gsc_mask = irqs;
> +	else if (HAS_HECI_GSC(gt->i915))
> +		gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
> +
>  	BUILD_BUG_ON(irqs & 0xffff0000);
>  
>  	/* Enable RCS, BCS, VCS and VECS class interrupts. */
> @@ -268,9 +277,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>  	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
>  	if (CCS_MASK(gt))
>  		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
> -	if (HAS_HECI_GSC(gt->i915))
> -		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
> -				   gsc_mask);
> +	if (gsc_mask)
> +		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask);
>  
>  	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
>  	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
> @@ -296,7 +304,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>  		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
>  	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
>  		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
> -	if (HAS_HECI_GSC(gt->i915))
> +	if (gsc_mask)
>  		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
>  
>  	/*
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: add GSC CS interrupt support

[Matt Roper]

On Thu, Oct 27, 2022 at 03:15:52PM -0700, Daniele Ceraolo Spurio wrote:
> The GSC CS re-uses the same interrupt bits that the GSC used in older
> platforms. This means that we can now have an engine interrupt coming
> out of OTHER_CLASS, so we need to handle that appropriately.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_gt_irq.c | 78 ++++++++++++++------------
>  1 file changed, 43 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index f26882fdc24c..34ff1ee7e931 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
>  		  instance, iir);
>  }
>  
> -static void
> -gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
> -			 const u8 instance, const u16 iir)
> +static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)
>  {
> -	struct intel_engine_cs *engine;
> -
> -	/*
> -	 * Platforms with standalone media have their media engines in another
> -	 * GT.
> -	 */
> -	if (MEDIA_VER(gt->i915) >= 13 &&
> -	    (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
> -		if (!gt->i915->media_gt)
> -			goto err;
> +	struct intel_gt *media_gt = gt->i915->media_gt;
>  
> -		gt = gt->i915->media_gt;
> +	/* we expect the non-media gt to be passed in */
> +	GEM_BUG_ON(gt == media_gt);
> +
> +	if (!media_gt)
> +		return gt;
> +
> +	switch (class) {
> +	case VIDEO_DECODE_CLASS:
> +	case VIDEO_ENHANCEMENT_CLASS:
> +		return media_gt;
> +	case OTHER_CLASS:
> +		if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
> +			return media_gt;
> +		fallthrough;
> +	default:
> +		return gt;
>  	}
> -
> -	if (instance <= MAX_ENGINE_INSTANCE)
> -		engine = gt->engine_class[class][instance];
> -	else
> -		engine = NULL;
> -
> -	if (likely(engine))
> -		return intel_engine_cs_irq(engine, iir);
> -
> -err:
> -	WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
> -		  class, instance);
>  }
>  
>  static void
> @@ -118,12 +110,24 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
>  	const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
>  	const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
>  	const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
> +	struct intel_engine_cs *engine;
>  
>  	if (unlikely(!intr))
>  		return;
>  
> -	if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
> -		return gen11_engine_irq_handler(gt, class, instance, intr);
> +	/*
> +	 * Platforms with standalone media have the media and GSC engines in
> +	 * another GT.
> +	 */
> +	gt = pick_gt(gt, class, instance);
> +
> +	if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE)
> +		engine = gt->engine_class[class][instance];
> +	else
> +		engine = NULL;
> +
> +	if (engine)
> +		return intel_engine_cs_irq(engine, intr);
>  
>  	if (class == OTHER_CLASS)
>  		return gen11_other_irq_handler(gt, instance, intr);
> @@ -206,7 +210,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
>  	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,	  0);
>  	if (CCS_MASK(gt))
>  		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
> -	if (HAS_HECI_GSC(gt->i915))
> +	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
>  		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
>  
>  	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> @@ -233,7 +237,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
>  		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
>  	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
>  		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
> -	if (HAS_HECI_GSC(gt->i915))
> +	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
>  		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
>  
>  	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
> @@ -249,7 +253,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>  {
>  	struct intel_uncore *uncore = gt->uncore;
>  	u32 irqs = GT_RENDER_USER_INTERRUPT;
> -	const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
> +	u32 gsc_mask = 0;
>  	u32 dmask;
>  	u32 smask;
>  
> @@ -261,6 +265,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>  	dmask = irqs << 16 | irqs;
>  	smask = irqs << 16;
>  
> +	if (HAS_ENGINE(gt, GSC0))
> +		gsc_mask = irqs;
> +	else if (HAS_HECI_GSC(gt->i915))
> +		gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
> +
>  	BUILD_BUG_ON(irqs & 0xffff0000);
>  
>  	/* Enable RCS, BCS, VCS and VECS class interrupts. */
> @@ -268,9 +277,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>  	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
>  	if (CCS_MASK(gt))
>  		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
> -	if (HAS_HECI_GSC(gt->i915))
> -		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
> -				   gsc_mask);
> +	if (gsc_mask)
> +		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask);
>  
>  	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
>  	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
> @@ -296,7 +304,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>  		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
>  	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
>  		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
> -	if (HAS_HECI_GSC(gt->i915))
> +	if (gsc_mask)
>  		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
>  
>  	/*
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [PATCH 4/5] drm/i915/mtl: add GSC CS reset support

[Matt Roper]

On Thu, Oct 27, 2022 at 03:15:53PM -0700, Daniele Ceraolo Spurio wrote:
> The GSC CS has its own dedicated bit in the GDRST register.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Bspec: 52549
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index e0fbfac03979..f63829abf66c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -423,6 +423,7 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
>  			[CCS1]  = GEN11_GRDOM_RENDER,
>  			[CCS2]  = GEN11_GRDOM_RENDER,
>  			[CCS3]  = GEN11_GRDOM_RENDER,
> +			[GSC0]  = GEN12_GRDOM_GSC,
>  		};
>  		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
>  			   !engine_reset_domains[id]);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 23844ba7e824..16cf90306085 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -640,6 +640,7 @@
>  #define   XEHPC_GRDOM_BLT3			REG_BIT(26)
>  #define   XEHPC_GRDOM_BLT2			REG_BIT(25)
>  #define   XEHPC_GRDOM_BLT1			REG_BIT(24)
> +#define   GEN12_GRDOM_GSC			REG_BIT(21)
>  #define   GEN11_GRDOM_SFC3			REG_BIT(20)
>  #define   GEN11_GRDOM_SFC2			REG_BIT(19)
>  #define   GEN11_GRDOM_SFC1			REG_BIT(18)
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 4/5] drm/i915/mtl: add GSC CS reset support

[Matt Roper]

On Thu, Oct 27, 2022 at 03:15:53PM -0700, Daniele Ceraolo Spurio wrote:
> The GSC CS has its own dedicated bit in the GDRST register.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Bspec: 52549
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index e0fbfac03979..f63829abf66c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -423,6 +423,7 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
>  			[CCS1]  = GEN11_GRDOM_RENDER,
>  			[CCS2]  = GEN11_GRDOM_RENDER,
>  			[CCS3]  = GEN11_GRDOM_RENDER,
> +			[GSC0]  = GEN12_GRDOM_GSC,
>  		};
>  		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
>  			   !engine_reset_domains[id]);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 23844ba7e824..16cf90306085 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -640,6 +640,7 @@
>  #define   XEHPC_GRDOM_BLT3			REG_BIT(26)
>  #define   XEHPC_GRDOM_BLT2			REG_BIT(25)
>  #define   XEHPC_GRDOM_BLT1			REG_BIT(24)
> +#define   GEN12_GRDOM_GSC			REG_BIT(21)
>  #define   GEN11_GRDOM_SFC3			REG_BIT(20)
>  #define   GEN11_GRDOM_SFC2			REG_BIT(19)
>  #define   GEN11_GRDOM_SFC1			REG_BIT(18)
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [PATCH 5/5] drm/i915/mtl: don't expose GSC command streamer to the user

[Matt Roper]

On Thu, Oct 27, 2022 at 03:15:54PM -0700, Daniele Ceraolo Spurio wrote:
> There is no userspace user for this CS yet, we only need it for internal
> kernel ops (e.g. HuC, PXP), so don't expose it.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Since we never expose it to userspace, we also never get to the point of
doing an engine rename and removing the apostrophe.  I assume we're okay
with this engine continuing to show up as "other'6" in debug logs?

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 79312b734690..ca795daca116 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -211,6 +211,10 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
>  		if (intel_gt_has_unrecoverable_error(engine->gt))
>  			continue; /* ignore incomplete engines */
>  
> +		/* don't expose GSC engine to user */
> +		if (engine->class == OTHER_CLASS)
> +			continue;
> +
>  		GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
>  		engine->uabi_class = uabi_classes[engine->class];
>  
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 5/5] drm/i915/mtl: don't expose GSC command streamer to the user

[Matt Roper]

On Thu, Oct 27, 2022 at 03:15:54PM -0700, Daniele Ceraolo Spurio wrote:
> There is no userspace user for this CS yet, we only need it for internal
> kernel ops (e.g. HuC, PXP), so don't expose it.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Since we never expose it to userspace, we also never get to the point of
doing an engine rename and removing the apostrophe.  I assume we're okay
with this engine continuing to show up as "other'6" in debug logs?

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 79312b734690..ca795daca116 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -211,6 +211,10 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
>  		if (intel_gt_has_unrecoverable_error(engine->gt))
>  			continue; /* ignore incomplete engines */
>  
> +		/* don't expose GSC engine to user */
> +		if (engine->class == OTHER_CLASS)
> +			continue;
> +
>  		GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
>  		engine->uabi_class = uabi_classes[engine->class];
>  
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: add GSC CS interrupt support

[Tvrtko Ursulin]

On 27/10/2022 23:15, Daniele Ceraolo Spurio wrote:
> The GSC CS re-uses the same interrupt bits that the GSC used in older
> platforms. This means that we can now have an engine interrupt coming
> out of OTHER_CLASS, so we need to handle that appropriately.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_gt_irq.c | 78 ++++++++++++++------------
>   1 file changed, 43 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index f26882fdc24c..34ff1ee7e931 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
>   		  instance, iir);
>   }
>   
> -static void
> -gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
> -			 const u8 instance, const u16 iir)
> +static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance)
>   {
> -	struct intel_engine_cs *engine;
> -
> -	/*
> -	 * Platforms with standalone media have their media engines in another
> -	 * GT.
> -	 */
> -	if (MEDIA_VER(gt->i915) >= 13 &&
> -	    (class == VIDEO_DECODE_CLASS || class == VIDEO_ENHANCEMENT_CLASS)) {
> -		if (!gt->i915->media_gt)
> -			goto err;
> +	struct intel_gt *media_gt = gt->i915->media_gt;
>   
> -		gt = gt->i915->media_gt;
> +	/* we expect the non-media gt to be passed in */
> +	GEM_BUG_ON(gt == media_gt);
> +
> +	if (!media_gt)
> +		return gt;
> +
> +	switch (class) {
> +	case VIDEO_DECODE_CLASS:
> +	case VIDEO_ENHANCEMENT_CLASS:
> +		return media_gt;
> +	case OTHER_CLASS:
> +		if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, GSC0))
> +			return media_gt;
> +		fallthrough;
> +	default:
> +		return gt;
>   	}
> -
> -	if (instance <= MAX_ENGINE_INSTANCE)
> -		engine = gt->engine_class[class][instance];
> -	else
> -		engine = NULL;
> -
> -	if (likely(engine))
> -		return intel_engine_cs_irq(engine, iir);
> -
> -err:
> -	WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
> -		  class, instance);
>   }
>   
>   static void
> @@ -118,12 +110,24 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
>   	const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
>   	const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
>   	const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
> +	struct intel_engine_cs *engine;
>   
>   	if (unlikely(!intr))
>   		return;
>   
> -	if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
> -		return gen11_engine_irq_handler(gt, class, instance, intr);
> +	/*
> +	 * Platforms with standalone media have the media and GSC engines in
> +	 * another GT.
> +	 */
> +	gt = pick_gt(gt, class, instance);
> +
> +	if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE)
> +		engine = gt->engine_class[class][instance];
> +	else
> +		engine = NULL;
> +
> +	if (engine)
> +		return intel_engine_cs_irq(engine, intr);

Drive by observation - you could fold the above two ifs into one since 
engine appears unused afterwards.

Regards,

Tvrtko

>   
>   	if (class == OTHER_CLASS)
>   		return gen11_other_irq_handler(gt, instance, intr);
> @@ -206,7 +210,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
>   	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,	  0);
>   	if (CCS_MASK(gt))
>   		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
> -	if (HAS_HECI_GSC(gt->i915))
> +	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
>   		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
>   
>   	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> @@ -233,7 +237,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
>   		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
>   	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
>   		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
> -	if (HAS_HECI_GSC(gt->i915))
> +	if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
>   		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
>   
>   	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
> @@ -249,7 +253,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>   {
>   	struct intel_uncore *uncore = gt->uncore;
>   	u32 irqs = GT_RENDER_USER_INTERRUPT;
> -	const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
> +	u32 gsc_mask = 0;
>   	u32 dmask;
>   	u32 smask;
>   
> @@ -261,6 +265,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>   	dmask = irqs << 16 | irqs;
>   	smask = irqs << 16;
>   
> +	if (HAS_ENGINE(gt, GSC0))
> +		gsc_mask = irqs;
> +	else if (HAS_HECI_GSC(gt->i915))
> +		gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
> +
>   	BUILD_BUG_ON(irqs & 0xffff0000);
>   
>   	/* Enable RCS, BCS, VCS and VECS class interrupts. */
> @@ -268,9 +277,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>   	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
>   	if (CCS_MASK(gt))
>   		intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
> -	if (HAS_HECI_GSC(gt->i915))
> -		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
> -				   gsc_mask);
> +	if (gsc_mask)
> +		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask);
>   
>   	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
>   	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
> @@ -296,7 +304,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>   		intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
>   	if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
>   		intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
> -	if (HAS_HECI_GSC(gt->i915))
> +	if (gsc_mask)
>   		intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
>   
>   	/*

[Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce the GSC CS

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 27195 bytes --]

== Series Details ==

Series: Introduce the GSC CS
URL   : https://patchwork.freedesktop.org/series/110237/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12313_full -> Patchwork_110237v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_110237v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110237v1_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_110237v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-iclb2/igt@i915_pm_dc@dc9-dpms.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb7/igt@i915_pm_dc@dc9-dpms.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1:
    - shard-skl:          [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-skl4/igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl9/igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_pread@exhaustion:
    - {shard-rkl}:        [SKIP][5] ([i915#3282]) -> [INCOMPLETE][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-1/igt@gem_pread@exhaustion.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-5/igt@gem_pread@exhaustion.html

  
Known issues
------------

  Here are the changes found in Patchwork_110237v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([i915#658])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-iclb2/igt@feature_discovery@psr2.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb3/igt@feature_discovery@psr2.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglb:         [PASS][9] -> [FAIL][10] ([i915#6268])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-tglb2/igt@gem_ctx_exec@basic-nohangcheck.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-tglb1/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([i915#4525])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb6/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-tglb:         [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-tglb6/igt@gem_exec_fair@basic-none-share@rcs0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-tglb7/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-skl:          NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl10/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
    - shard-skl:          [PASS][16] -> [FAIL][17] ([i915#2521])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3886]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl7/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3886]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl10/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-edid-change-during-suspend:
    - shard-apl:          NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl7/igt@kms_chamelium@dp-edid-change-during-suspend.html

  * igt@kms_chamelium@hdmi-crc-multiple:
    - shard-skl:          NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl10/igt@kms_chamelium@hdmi-crc-multiple.html

  * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
    - shard-skl:          [PASS][22] -> [FAIL][23] ([i915#2346])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [PASS][24] -> [DMESG-WARN][25] ([i915#180])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip@plain-flip-ts-check@c-edp1:
    - shard-skl:          [PASS][26] -> [FAIL][27] ([i915#2122])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-skl4/igt@kms_flip@plain-flip-ts-check@c-edp1.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl6/igt@kms_flip@plain-flip-ts-check@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][28] ([i915#2672]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-iclb:         NOTRUN -> [SKIP][29] ([i915#2587] / [i915#2672])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][30] ([i915#3555]) +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
    - shard-skl:          NOTRUN -> [SKIP][31] ([fdo#109271]) +48 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl10/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render:
    - shard-apl:          NOTRUN -> [SKIP][32] ([fdo#109271]) +19 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [PASS][33] -> [SKIP][34] ([fdo#109441])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb3/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@perf@blocking:
    - shard-skl:          [PASS][35] -> [FAIL][36] ([i915#1542])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-skl6/igt@perf@blocking.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl6/igt@perf@blocking.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [PASS][37] -> [FAIL][38] ([i915#5639])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-skl7/igt@perf@polling-parameterized.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl1/igt@perf@polling-parameterized.html

  * igt@perf@stress-open-close:
    - shard-glk:          [PASS][39] -> [INCOMPLETE][40] ([i915#5213])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-glk3/igt@perf@stress-open-close.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-glk9/igt@perf@stress-open-close.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@engines-hang@bcs0:
    - {shard-rkl}:        [SKIP][41] ([i915#6252]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@bcs0.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-1/igt@gem_ctx_persistence@engines-hang@bcs0.html

  * igt@gem_eio@unwedge-stress:
    - {shard-dg1}:        [FAIL][43] ([i915#5784]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-dg1-12/igt@gem_eio@unwedge-stress.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-dg1-15/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-iclb:         [SKIP][45] ([i915#4525]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-iclb7/igt@gem_exec_balancer@parallel-contexts.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb2/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_endless@dispatch@rcs0:
    - {shard-rkl}:        [INCOMPLETE][47] ([i915#3778]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-3/igt@gem_exec_endless@dispatch@rcs0.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-5/igt@gem_exec_endless@dispatch@rcs0.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [FAIL][49] ([i915#2842]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][51] ([i915#2842]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_reloc@basic-write-read-noreloc:
    - {shard-rkl}:        [SKIP][53] ([i915#3281]) -> [PASS][54] +8 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-1/igt@gem_exec_reloc@basic-write-read-noreloc.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-noreloc.html

  * igt@gem_set_tiling_vs_pwrite:
    - {shard-rkl}:        [SKIP][55] ([i915#3282]) -> [PASS][56] +6 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-1/igt@gem_set_tiling_vs_pwrite.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-5/igt@gem_set_tiling_vs_pwrite.html

  * igt@gem_softpin@evict-single-offset:
    - shard-tglb:         [FAIL][57] ([i915#4171]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-tglb1/igt@gem_softpin@evict-single-offset.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-tglb1/igt@gem_softpin@evict-single-offset.html
    - {shard-rkl}:        [FAIL][59] ([i915#4171]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-5/igt@gem_softpin@evict-single-offset.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-1/igt@gem_softpin@evict-single-offset.html

  * igt@gen9_exec_parse@bb-start-far:
    - {shard-rkl}:        [SKIP][61] ([i915#2527]) -> [PASS][62] +2 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-1/igt@gen9_exec_parse@bb-start-far.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-5/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_hangman@gt-engine-error@bcs0:
    - {shard-rkl}:        [SKIP][63] ([i915#6258]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-5/igt@i915_hangman@gt-engine-error@bcs0.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-3/igt@i915_hangman@gt-engine-error@bcs0.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [FAIL][65] ([i915#3989] / [i915#454]) -> [PASS][66] +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_dc@dc9-dpms:
    - {shard-rkl}:        [SKIP][67] ([i915#3361]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-5/igt@i915_pm_dc@dc9-dpms.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-4/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rc6_residency@rc6-idle@bcs0:
    - {shard-dg1}:        [FAIL][69] ([i915#3591]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
    - shard-glk:          [FAIL][71] ([i915#2346]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-skl:          [FAIL][73] ([i915#79]) -> [PASS][74] +1 similar issue
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
    - shard-skl:          [FAIL][75] ([i915#2122]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][77] ([fdo#109441]) -> [PASS][78] +2 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  * igt@perf@mi-rpc:
    - {shard-rkl}:        [SKIP][79] ([i915#2434]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-1/igt@perf@mi-rpc.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-5/igt@perf@mi-rpc.html

  * igt@perf@polling-small-buf:
    - {shard-rkl}:        [FAIL][81] ([i915#1722]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-3/igt@perf@polling-small-buf.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-5/igt@perf@polling-small-buf.html

  * igt@perf_pmu@module-unload:
    - shard-skl:          [DMESG-WARN][83] ([i915#1982]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-skl7/igt@perf_pmu@module-unload.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl1/igt@perf_pmu@module-unload.html

  * igt@prime_vgem@basic-write:
    - {shard-rkl}:        [SKIP][85] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-1/igt@prime_vgem@basic-write.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-5/igt@prime_vgem@basic-write.html

  
#### Warnings ####

  * igt@dmabuf@all@dma_fence_chain:
    - shard-skl:          [INCOMPLETE][87] ([i915#6949] / [i915#7165]) -> [INCOMPLETE][88] ([i915#6949] / [i915#7065] / [i915#7165])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-skl9/igt@dmabuf@all@dma_fence_chain.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl6/igt@dmabuf@all@dma_fence_chain.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-iclb:         [SKIP][89] ([i915#4525]) -> [FAIL][90] ([i915#6117])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-iclb5/igt@gem_exec_balancer@parallel-ordering.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_pread@exhaustion:
    - shard-apl:          [WARN][91] ([i915#2658]) -> [INCOMPLETE][92] ([i915#7248])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-apl7/igt@gem_pread@exhaustion.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl7/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-tglb:         [INCOMPLETE][93] ([i915#7248]) -> [WARN][94] ([i915#2658])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-tglb6/igt@gem_pwrite@basic-exhaustion.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-tglb6/igt@gem_pwrite@basic-exhaustion.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
    - shard-iclb:         [SKIP][95] ([i915#658]) -> [SKIP][96] ([i915#2920])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-iclb7/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103]) ([i915#3002] / [i915#4312]) -> ([FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110]) ([i915#180] / [i915#3002] / [i915#4312])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-apl6/igt@runner@aborted.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-apl7/igt@runner@aborted.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-apl6/igt@runner@aborted.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-apl3/igt@runner@aborted.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-apl3/igt@runner@aborted.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-apl7/igt@runner@aborted.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-apl6/igt@runner@aborted.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl6/igt@runner@aborted.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl3/igt@runner@aborted.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl8/igt@runner@aborted.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl8/igt@runner@aborted.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl7/igt@runner@aborted.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl7/igt@runner@aborted.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl8/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
  [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6949]: https://gitlab.freedesktop.org/drm/intel/issues/6949
  [i915#7065]: https://gitlab.freedesktop.org/drm/intel/issues/7065
  [i915#7142]: https://gitlab.freedesktop.org/drm/intel/issues/7142
  [i915#7165]: https://gitlab.freedesktop.org/drm/intel/issues/7165
  [i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
  [i915#7316]: https://gitlab.freedesktop.org/drm/intel/issues/7316
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * Linux: CI_DRM_12313 -> Patchwork_110237v1

  CI-20190529: 20190529
  CI_DRM_12313: 9d6a004b1594b83b2d94776daa23757892423837 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7028: 9e635a1c502970e7e6d64112d409392a2f01c688 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110237v1: 9d6a004b1594b83b2d94776daa23757892423837 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/index.html

[-- Attachment #2: Type: text/html, Size: 29130 bytes --]

Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: add GSC CS interrupt support

[Ceraolo Spurio, Daniele]

On 10/28/2022 1:38 AM, Tvrtko Ursulin wrote:
>
> On 27/10/2022 23:15, Daniele Ceraolo Spurio wrote:
>> The GSC CS re-uses the same interrupt bits that the GSC used in older
>> platforms. This means that we can now have an engine interrupt coming
>> out of OTHER_CLASS, so we need to handle that appropriately.
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_gt_irq.c | 78 ++++++++++++++------------
>>   1 file changed, 43 insertions(+), 35 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c 
>> b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> index f26882fdc24c..34ff1ee7e931 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> @@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, 
>> const u8 instance,
>>             instance, iir);
>>   }
>>   -static void
>> -gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
>> -             const u8 instance, const u16 iir)
>> +static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 
>> instance)
>>   {
>> -    struct intel_engine_cs *engine;
>> -
>> -    /*
>> -     * Platforms with standalone media have their media engines in 
>> another
>> -     * GT.
>> -     */
>> -    if (MEDIA_VER(gt->i915) >= 13 &&
>> -        (class == VIDEO_DECODE_CLASS || class == 
>> VIDEO_ENHANCEMENT_CLASS)) {
>> -        if (!gt->i915->media_gt)
>> -            goto err;
>> +    struct intel_gt *media_gt = gt->i915->media_gt;
>>   -        gt = gt->i915->media_gt;
>> +    /* we expect the non-media gt to be passed in */
>> +    GEM_BUG_ON(gt == media_gt);
>> +
>> +    if (!media_gt)
>> +        return gt;
>> +
>> +    switch (class) {
>> +    case VIDEO_DECODE_CLASS:
>> +    case VIDEO_ENHANCEMENT_CLASS:
>> +        return media_gt;
>> +    case OTHER_CLASS:
>> +        if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, 
>> GSC0))
>> +            return media_gt;
>> +        fallthrough;
>> +    default:
>> +        return gt;
>>       }
>> -
>> -    if (instance <= MAX_ENGINE_INSTANCE)
>> -        engine = gt->engine_class[class][instance];
>> -    else
>> -        engine = NULL;
>> -
>> -    if (likely(engine))
>> -        return intel_engine_cs_irq(engine, iir);
>> -
>> -err:
>> -    WARN_ONCE(1, "unhandled engine interrupt class=0x%x, 
>> instance=0x%x\n",
>> -          class, instance);
>>   }
>>     static void
>> @@ -118,12 +110,24 @@ gen11_gt_identity_handler(struct intel_gt *gt, 
>> const u32 identity)
>>       const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
>>       const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
>>       const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
>> +    struct intel_engine_cs *engine;
>>         if (unlikely(!intr))
>>           return;
>>   -    if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
>> -        return gen11_engine_irq_handler(gt, class, instance, intr);
>> +    /*
>> +     * Platforms with standalone media have the media and GSC 
>> engines in
>> +     * another GT.
>> +     */
>> +    gt = pick_gt(gt, class, instance);
>> +
>> +    if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE)
>> +        engine = gt->engine_class[class][instance];
>> +    else
>> +        engine = NULL;
>> +
>> +    if (engine)
>> +        return intel_engine_cs_irq(engine, intr);
>
> Drive by observation - you could fold the above two ifs into one since 
> engine appears unused afterwards.

engine can be NULL in both branches of the if statement, so to get a 
unified if we'd have to do something like:

if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) {
         struct intel_engine_cs *engine = gt->engine_class[class][instance];
         if (engine)
                 return intel_engine_cs_irq(engine, intr);
}

Is this what you are suggesting?

Daniele

>
> Regards,
>
> Tvrtko
>
>>         if (class == OTHER_CLASS)
>>           return gen11_other_irq_handler(gt, instance, intr);
>> @@ -206,7 +210,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
>>       intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,      0);
>>       if (CCS_MASK(gt))
>>           intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
>> -    if (HAS_HECI_GSC(gt->i915))
>> +    if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
>>           intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
>>         /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
>> @@ -233,7 +237,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
>>           intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
>>       if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
>>           intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
>> -    if (HAS_HECI_GSC(gt->i915))
>> +    if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
>>           intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
>>         intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
>> @@ -249,7 +253,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>>   {
>>       struct intel_uncore *uncore = gt->uncore;
>>       u32 irqs = GT_RENDER_USER_INTERRUPT;
>> -    const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
>> +    u32 gsc_mask = 0;
>>       u32 dmask;
>>       u32 smask;
>>   @@ -261,6 +265,11 @@ void gen11_gt_irq_postinstall(struct intel_gt 
>> *gt)
>>       dmask = irqs << 16 | irqs;
>>       smask = irqs << 16;
>>   +    if (HAS_ENGINE(gt, GSC0))
>> +        gsc_mask = irqs;
>> +    else if (HAS_HECI_GSC(gt->i915))
>> +        gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
>> +
>>       BUILD_BUG_ON(irqs & 0xffff0000);
>>         /* Enable RCS, BCS, VCS and VECS class interrupts. */
>> @@ -268,9 +277,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>>       intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
>>       if (CCS_MASK(gt))
>>           intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
>> -    if (HAS_HECI_GSC(gt->i915))
>> -        intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
>> -                   gsc_mask);
>> +    if (gsc_mask)
>> +        intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 
>> gsc_mask);
>>         /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
>>       intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
>> @@ -296,7 +304,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
>>           intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
>>       if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
>>           intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
>> -    if (HAS_HECI_GSC(gt->i915))
>> +    if (gsc_mask)
>>           intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, 
>> ~gsc_mask);
>>         /*

Re: [PATCH 5/5] drm/i915/mtl: don't expose GSC command streamer to the user

[Ceraolo Spurio, Daniele]

On 10/27/2022 8:40 PM, Matt Roper wrote:
> On Thu, Oct 27, 2022 at 03:15:54PM -0700, Daniele Ceraolo Spurio wrote:
>> There is no userspace user for this CS yet, we only need it for internal
>> kernel ops (e.g. HuC, PXP), so don't expose it.
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
> Since we never expose it to userspace, we also never get to the point of
> doing an engine rename and removing the apostrophe.  I assume we're okay
> with this engine continuing to show up as "other'6" in debug logs?

I don't think it matters a lot in debug logs, but anyway it wouldn't be 
hard to rename it to something different. What do you suggest to rename 
it to? Since OTHER_CLASS doesn't have a uabi_class defined we can't use 
a count of engines of that type like we do for the other classes. Just 
rename it straight to hardcoded gsc0 ?

Daniele

>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> index 79312b734690..ca795daca116 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> @@ -211,6 +211,10 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
>>   		if (intel_gt_has_unrecoverable_error(engine->gt))
>>   			continue; /* ignore incomplete engines */
>>   
>> +		/* don't expose GSC engine to user */
>> +		if (engine->class == OTHER_CLASS)
>> +			continue;
>> +
>>   		GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
>>   		engine->uabi_class = uabi_classes[engine->class];
>>   
>> -- 
>> 2.37.3
>>

Re: [Intel-gfx] [PATCH 5/5] drm/i915/mtl: don't expose GSC command streamer to the user

[Ceraolo Spurio, Daniele]

On 10/27/2022 8:40 PM, Matt Roper wrote:
> On Thu, Oct 27, 2022 at 03:15:54PM -0700, Daniele Ceraolo Spurio wrote:
>> There is no userspace user for this CS yet, we only need it for internal
>> kernel ops (e.g. HuC, PXP), so don't expose it.
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
> Since we never expose it to userspace, we also never get to the point of
> doing an engine rename and removing the apostrophe.  I assume we're okay
> with this engine continuing to show up as "other'6" in debug logs?

I don't think it matters a lot in debug logs, but anyway it wouldn't be 
hard to rename it to something different. What do you suggest to rename 
it to? Since OTHER_CLASS doesn't have a uabi_class defined we can't use 
a count of engines of that type like we do for the other classes. Just 
rename it straight to hardcoded gsc0 ?

Daniele

>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> index 79312b734690..ca795daca116 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> @@ -211,6 +211,10 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
>>   		if (intel_gt_has_unrecoverable_error(engine->gt))
>>   			continue; /* ignore incomplete engines */
>>   
>> +		/* don't expose GSC engine to user */
>> +		if (engine->class == OTHER_CLASS)
>> +			continue;
>> +
>>   		GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
>>   		engine->uabi_class = uabi_classes[engine->class];
>>   
>> -- 
>> 2.37.3
>>

Re: [PATCH 5/5] drm/i915/mtl: don't expose GSC command streamer to the user

[Matt Roper]

On Fri, Oct 28, 2022 at 10:14:05AM -0700, Ceraolo Spurio, Daniele wrote:
> 
> 
> On 10/27/2022 8:40 PM, Matt Roper wrote:
> > On Thu, Oct 27, 2022 at 03:15:54PM -0700, Daniele Ceraolo Spurio wrote:
> > > There is no userspace user for this CS yet, we only need it for internal
> > > kernel ops (e.g. HuC, PXP), so don't expose it.
> > > 
> > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Since we never expose it to userspace, we also never get to the point of
> > doing an engine rename and removing the apostrophe.  I assume we're okay
> > with this engine continuing to show up as "other'6" in debug logs?
> 
> I don't think it matters a lot in debug logs, but anyway it wouldn't be hard
> to rename it to something different. What do you suggest to rename it to?
> Since OTHER_CLASS doesn't have a uabi_class defined we can't use a count of
> engines of that type like we do for the other classes. Just rename it
> straight to hardcoded gsc0 ?

Yeah, a hardcoded "gsc0" seems fine to me.  I agree it doesn't matter
too much either way, so I'll leave it up to you whether you add that
rename or not.


Matt

> 
> Daniele
> 
> > 
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > 
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 ++++
> > >   1 file changed, 4 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > index 79312b734690..ca795daca116 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > @@ -211,6 +211,10 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
> > >   		if (intel_gt_has_unrecoverable_error(engine->gt))
> > >   			continue; /* ignore incomplete engines */
> > > +		/* don't expose GSC engine to user */
> > > +		if (engine->class == OTHER_CLASS)
> > > +			continue;
> > > +
> > >   		GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
> > >   		engine->uabi_class = uabi_classes[engine->class];
> > > -- 
> > > 2.37.3
> > > 
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 5/5] drm/i915/mtl: don't expose GSC command streamer to the user

[Matt Roper]

On Fri, Oct 28, 2022 at 10:14:05AM -0700, Ceraolo Spurio, Daniele wrote:
> 
> 
> On 10/27/2022 8:40 PM, Matt Roper wrote:
> > On Thu, Oct 27, 2022 at 03:15:54PM -0700, Daniele Ceraolo Spurio wrote:
> > > There is no userspace user for this CS yet, we only need it for internal
> > > kernel ops (e.g. HuC, PXP), so don't expose it.
> > > 
> > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Since we never expose it to userspace, we also never get to the point of
> > doing an engine rename and removing the apostrophe.  I assume we're okay
> > with this engine continuing to show up as "other'6" in debug logs?
> 
> I don't think it matters a lot in debug logs, but anyway it wouldn't be hard
> to rename it to something different. What do you suggest to rename it to?
> Since OTHER_CLASS doesn't have a uabi_class defined we can't use a count of
> engines of that type like we do for the other classes. Just rename it
> straight to hardcoded gsc0 ?

Yeah, a hardcoded "gsc0" seems fine to me.  I agree it doesn't matter
too much either way, so I'll leave it up to you whether you add that
rename or not.


Matt

> 
> Daniele
> 
> > 
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > 
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 ++++
> > >   1 file changed, 4 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > index 79312b734690..ca795daca116 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > @@ -211,6 +211,10 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
> > >   		if (intel_gt_has_unrecoverable_error(engine->gt))
> > >   			continue; /* ignore incomplete engines */
> > > +		/* don't expose GSC engine to user */
> > > +		if (engine->class == OTHER_CLASS)
> > > +			continue;
> > > +
> > >   		GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
> > >   		engine->uabi_class = uabi_classes[engine->class];
> > > -- 
> > > 2.37.3
> > > 
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: add GSC CS interrupt support

[Tvrtko Ursulin]

On 28/10/2022 18:00, Ceraolo Spurio, Daniele wrote:
> On 10/28/2022 1:38 AM, Tvrtko Ursulin wrote:
>>
>> On 27/10/2022 23:15, Daniele Ceraolo Spurio wrote:
>>> The GSC CS re-uses the same interrupt bits that the GSC used in older
>>> platforms. This means that we can now have an engine interrupt coming
>>> out of OTHER_CLASS, so we need to handle that appropriately.
>>>
>>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/gt/intel_gt_irq.c | 78 ++++++++++++++------------
>>>   1 file changed, 43 insertions(+), 35 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c 
>>> b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>>> index f26882fdc24c..34ff1ee7e931 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>>> @@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, 
>>> const u8 instance,
>>>             instance, iir);
>>>   }
>>>   -static void
>>> -gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
>>> -             const u8 instance, const u16 iir)
>>> +static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 
>>> instance)
>>>   {
>>> -    struct intel_engine_cs *engine;
>>> -
>>> -    /*
>>> -     * Platforms with standalone media have their media engines in 
>>> another
>>> -     * GT.
>>> -     */
>>> -    if (MEDIA_VER(gt->i915) >= 13 &&
>>> -        (class == VIDEO_DECODE_CLASS || class == 
>>> VIDEO_ENHANCEMENT_CLASS)) {
>>> -        if (!gt->i915->media_gt)
>>> -            goto err;
>>> +    struct intel_gt *media_gt = gt->i915->media_gt;
>>>   -        gt = gt->i915->media_gt;
>>> +    /* we expect the non-media gt to be passed in */
>>> +    GEM_BUG_ON(gt == media_gt);
>>> +
>>> +    if (!media_gt)
>>> +        return gt;
>>> +
>>> +    switch (class) {
>>> +    case VIDEO_DECODE_CLASS:
>>> +    case VIDEO_ENHANCEMENT_CLASS:
>>> +        return media_gt;
>>> +    case OTHER_CLASS:
>>> +        if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, 
>>> GSC0))
>>> +            return media_gt;
>>> +        fallthrough;
>>> +    default:
>>> +        return gt;
>>>       }
>>> -
>>> -    if (instance <= MAX_ENGINE_INSTANCE)
>>> -        engine = gt->engine_class[class][instance];
>>> -    else
>>> -        engine = NULL;
>>> -
>>> -    if (likely(engine))
>>> -        return intel_engine_cs_irq(engine, iir);
>>> -
>>> -err:
>>> -    WARN_ONCE(1, "unhandled engine interrupt class=0x%x, 
>>> instance=0x%x\n",
>>> -          class, instance);
>>>   }
>>>     static void
>>> @@ -118,12 +110,24 @@ gen11_gt_identity_handler(struct intel_gt *gt, 
>>> const u32 identity)
>>>       const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
>>>       const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
>>>       const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
>>> +    struct intel_engine_cs *engine;
>>>         if (unlikely(!intr))
>>>           return;
>>>   -    if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
>>> -        return gen11_engine_irq_handler(gt, class, instance, intr);
>>> +    /*
>>> +     * Platforms with standalone media have the media and GSC 
>>> engines in
>>> +     * another GT.
>>> +     */
>>> +    gt = pick_gt(gt, class, instance);
>>> +
>>> +    if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE)
>>> +        engine = gt->engine_class[class][instance];
>>> +    else
>>> +        engine = NULL;
>>> +
>>> +    if (engine)
>>> +        return intel_engine_cs_irq(engine, intr);
>>
>> Drive by observation - you could fold the above two ifs into one since 
>> engine appears unused afterwards.
> 
> engine can be NULL in both branches of the if statement, so to get a 
> unified if we'd have to do something like:
> 
> if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) {
>          struct intel_engine_cs *engine = 
> gt->engine_class[class][instance];
>          if (engine)
>                  return intel_engine_cs_irq(engine, intr);
> }
> 
> Is this what you are suggesting?

Right, two ifs are needed after all. Well at least it would avoid the 
pointless engine = NULL assignment. Up to you.

Absence of any out-of-range class/instance logging is intentional?

Regards,

Tvrtko

Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: add GSC CS interrupt support

[Ceraolo Spurio, Daniele]

On 10/31/2022 5:55 AM, Tvrtko Ursulin wrote:
>
> On 28/10/2022 18:00, Ceraolo Spurio, Daniele wrote:
>> On 10/28/2022 1:38 AM, Tvrtko Ursulin wrote:
>>>
>>> On 27/10/2022 23:15, Daniele Ceraolo Spurio wrote:
>>>> The GSC CS re-uses the same interrupt bits that the GSC used in older
>>>> platforms. This means that we can now have an engine interrupt coming
>>>> out of OTHER_CLASS, so we need to handle that appropriately.
>>>>
>>>> Signed-off-by: Daniele Ceraolo Spurio 
>>>> <daniele.ceraolospurio@intel.com>
>>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/i915/gt/intel_gt_irq.c | 78 
>>>> ++++++++++++++------------
>>>>   1 file changed, 43 insertions(+), 35 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c 
>>>> b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>>>> index f26882fdc24c..34ff1ee7e931 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>>>> @@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, 
>>>> const u8 instance,
>>>>             instance, iir);
>>>>   }
>>>>   -static void
>>>> -gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
>>>> -             const u8 instance, const u16 iir)
>>>> +static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 
>>>> instance)
>>>>   {
>>>> -    struct intel_engine_cs *engine;
>>>> -
>>>> -    /*
>>>> -     * Platforms with standalone media have their media engines in 
>>>> another
>>>> -     * GT.
>>>> -     */
>>>> -    if (MEDIA_VER(gt->i915) >= 13 &&
>>>> -        (class == VIDEO_DECODE_CLASS || class == 
>>>> VIDEO_ENHANCEMENT_CLASS)) {
>>>> -        if (!gt->i915->media_gt)
>>>> -            goto err;
>>>> +    struct intel_gt *media_gt = gt->i915->media_gt;
>>>>   -        gt = gt->i915->media_gt;
>>>> +    /* we expect the non-media gt to be passed in */
>>>> +    GEM_BUG_ON(gt == media_gt);
>>>> +
>>>> +    if (!media_gt)
>>>> +        return gt;
>>>> +
>>>> +    switch (class) {
>>>> +    case VIDEO_DECODE_CLASS:
>>>> +    case VIDEO_ENHANCEMENT_CLASS:
>>>> +        return media_gt;
>>>> +    case OTHER_CLASS:
>>>> +        if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, 
>>>> GSC0))
>>>> +            return media_gt;
>>>> +        fallthrough;
>>>> +    default:
>>>> +        return gt;
>>>>       }
>>>> -
>>>> -    if (instance <= MAX_ENGINE_INSTANCE)
>>>> -        engine = gt->engine_class[class][instance];
>>>> -    else
>>>> -        engine = NULL;
>>>> -
>>>> -    if (likely(engine))
>>>> -        return intel_engine_cs_irq(engine, iir);
>>>> -
>>>> -err:
>>>> -    WARN_ONCE(1, "unhandled engine interrupt class=0x%x, 
>>>> instance=0x%x\n",
>>>> -          class, instance);
>>>>   }
>>>>     static void
>>>> @@ -118,12 +110,24 @@ gen11_gt_identity_handler(struct intel_gt 
>>>> *gt, const u32 identity)
>>>>       const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
>>>>       const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
>>>>       const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
>>>> +    struct intel_engine_cs *engine;
>>>>         if (unlikely(!intr))
>>>>           return;
>>>>   -    if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
>>>> -        return gen11_engine_irq_handler(gt, class, instance, intr);
>>>> +    /*
>>>> +     * Platforms with standalone media have the media and GSC 
>>>> engines in
>>>> +     * another GT.
>>>> +     */
>>>> +    gt = pick_gt(gt, class, instance);
>>>> +
>>>> +    if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE)
>>>> +        engine = gt->engine_class[class][instance];
>>>> +    else
>>>> +        engine = NULL;
>>>> +
>>>> +    if (engine)
>>>> +        return intel_engine_cs_irq(engine, intr);
>>>
>>> Drive by observation - you could fold the above two ifs into one 
>>> since engine appears unused afterwards.
>>
>> engine can be NULL in both branches of the if statement, so to get a 
>> unified if we'd have to do something like:
>>
>> if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) {
>>          struct intel_engine_cs *engine = 
>> gt->engine_class[class][instance];
>>          if (engine)
>>                  return intel_engine_cs_irq(engine, intr);
>> }
>>
>> Is this what you are suggesting?
>
> Right, two ifs are needed after all. Well at least it would avoid the 
> pointless engine = NULL assignment. Up to you.
>
> Absence of any out-of-range class/instance logging is intentional?

There is already a log further down in this function.

Daniele

>
> Regards,
>
> Tvrtko

Re: [Intel-gfx] [PATCH 1/5] drm/i915/mtl: add initial definitions for GSC CS

[Matt Roper]

On Thu, Oct 27, 2022 at 03:15:50PM -0700, Daniele Ceraolo Spurio wrote:
> Starting on MTL, the GSC is no longer managed with direct MMIO access,
> but we instead have a dedicated command streamer for it. As a first step
> for adding support for this CS, add the required definitions.
> Note that, although it is now a CS, the GSC retains its old
> class:instance value (OTHER_CLASS instance 6)
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Now that we have an OTHER_CLASS engine, I think we also need to deal
with the class -> reg mapping table in mmio_invalidate_full().  I think
the register we want is 0xCF04?

Matt

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
>  drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
>  drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
>  drivers/gpu/drm/i915/i915_reg.h              | 1 +
>  4 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 3b7d750ad054..e0fbfac03979 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
>  			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
>  		}
>  	},
> +	[GSC0] = {
> +		.class = OTHER_CLASS,
> +		.instance = OTHER_GSC_INSTANCE,
> +		.mmio_bases = {
> +			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
> +		}
> +	},
>  };
>  
>  /**
> @@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
>  	case VIDEO_DECODE_CLASS:
>  	case VIDEO_ENHANCEMENT_CLASS:
>  	case COPY_ENGINE_CLASS:
> +	case OTHER_CLASS:
>  		if (GRAPHICS_VER(gt->i915) < 8)
>  			return 0;
>  		return GEN8_LR_CONTEXT_OTHER_SIZE;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 6b5d4ea22b67..4fd54fb8810f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -136,6 +136,7 @@ enum intel_engine_id {
>  	CCS2,
>  	CCS3,
>  #define _CCS(n) (CCS0 + (n))
> +	GSC0,
>  	I915_NUM_ENGINES
>  #define INVALID_ENGINE ((enum intel_engine_id)-1)
>  };
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 46a174f8aa00..79312b734690 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
>  		[COPY_ENGINE_CLASS] = "bcs",
>  		[VIDEO_DECODE_CLASS] = "vcs",
>  		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
> +		[OTHER_CLASS] = "other",
>  		[COMPUTE_CLASS] = "ccs",
>  	};
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1c0da50c0dc7..d056c3117ef2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -970,6 +970,7 @@
>  #define GEN11_VEBOX2_RING_BASE		0x1d8000
>  #define XEHP_VEBOX3_RING_BASE		0x1e8000
>  #define XEHP_VEBOX4_RING_BASE		0x1f8000
> +#define MTL_GSC_RING_BASE		0x11a000
>  #define GEN12_COMPUTE0_RING_BASE	0x1a000
>  #define GEN12_COMPUTE1_RING_BASE	0x1c000
>  #define GEN12_COMPUTE2_RING_BASE	0x1e000
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [PATCH 1/5] drm/i915/mtl: add initial definitions for GSC CS

[Matt Roper]

On Thu, Oct 27, 2022 at 03:15:50PM -0700, Daniele Ceraolo Spurio wrote:
> Starting on MTL, the GSC is no longer managed with direct MMIO access,
> but we instead have a dedicated command streamer for it. As a first step
> for adding support for this CS, add the required definitions.
> Note that, although it is now a CS, the GSC retains its old
> class:instance value (OTHER_CLASS instance 6)
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>

Now that we have an OTHER_CLASS engine, I think we also need to deal
with the class -> reg mapping table in mmio_invalidate_full().  I think
the register we want is 0xCF04?

Matt

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
>  drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
>  drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
>  drivers/gpu/drm/i915/i915_reg.h              | 1 +
>  4 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 3b7d750ad054..e0fbfac03979 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
>  			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
>  		}
>  	},
> +	[GSC0] = {
> +		.class = OTHER_CLASS,
> +		.instance = OTHER_GSC_INSTANCE,
> +		.mmio_bases = {
> +			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
> +		}
> +	},
>  };
>  
>  /**
> @@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
>  	case VIDEO_DECODE_CLASS:
>  	case VIDEO_ENHANCEMENT_CLASS:
>  	case COPY_ENGINE_CLASS:
> +	case OTHER_CLASS:
>  		if (GRAPHICS_VER(gt->i915) < 8)
>  			return 0;
>  		return GEN8_LR_CONTEXT_OTHER_SIZE;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 6b5d4ea22b67..4fd54fb8810f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -136,6 +136,7 @@ enum intel_engine_id {
>  	CCS2,
>  	CCS3,
>  #define _CCS(n) (CCS0 + (n))
> +	GSC0,
>  	I915_NUM_ENGINES
>  #define INVALID_ENGINE ((enum intel_engine_id)-1)
>  };
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 46a174f8aa00..79312b734690 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
>  		[COPY_ENGINE_CLASS] = "bcs",
>  		[VIDEO_DECODE_CLASS] = "vcs",
>  		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
> +		[OTHER_CLASS] = "other",
>  		[COMPUTE_CLASS] = "ccs",
>  	};
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1c0da50c0dc7..d056c3117ef2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -970,6 +970,7 @@
>  #define GEN11_VEBOX2_RING_BASE		0x1d8000
>  #define XEHP_VEBOX3_RING_BASE		0x1e8000
>  #define XEHP_VEBOX4_RING_BASE		0x1f8000
> +#define MTL_GSC_RING_BASE		0x11a000
>  #define GEN12_COMPUTE0_RING_BASE	0x1a000
>  #define GEN12_COMPUTE1_RING_BASE	0x1c000
>  #define GEN12_COMPUTE2_RING_BASE	0x1e000
> -- 
> 2.37.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [PATCH 1/5] drm/i915/mtl: add initial definitions for GSC CS

[Ceraolo Spurio, Daniele]

On 10/31/2022 9:26 AM, Matt Roper wrote:
> On Thu, Oct 27, 2022 at 03:15:50PM -0700, Daniele Ceraolo Spurio wrote:
>> Starting on MTL, the GSC is no longer managed with direct MMIO access,
>> but we instead have a dedicated command streamer for it. As a first step
>> for adding support for this CS, add the required definitions.
>> Note that, although it is now a CS, the GSC retains its old
>> class:instance value (OTHER_CLASS instance 6)
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
> Now that we have an OTHER_CLASS engine, I think we also need to deal
> with the class -> reg mapping table in mmio_invalidate_full().  I think
> the register we want is 0xCF04?

I missed that. Looks like the the situation is a bit more complex than 
just adding the new register, because on pre-MTL platforms CF04 is the 
compute class invalidation register. On MTL as you said CF04 is marked 
as the GSC CS invalidation register, but I can't find the compute one. 
Do you know if it re-uses the render one or something like that?
Given that there seem to be non-GSC related changes as well, IMO this 
should probably be a separate patch to specifically handle the TLB inval 
changes on MTL.

Daniele

>
> Matt
>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
>>   drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
>>   drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
>>   drivers/gpu/drm/i915/i915_reg.h              | 1 +
>>   4 files changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 3b7d750ad054..e0fbfac03979 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
>>   			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
>>   		}
>>   	},
>> +	[GSC0] = {
>> +		.class = OTHER_CLASS,
>> +		.instance = OTHER_GSC_INSTANCE,
>> +		.mmio_bases = {
>> +			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
>> +		}
>> +	},
>>   };
>>   
>>   /**
>> @@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
>>   	case VIDEO_DECODE_CLASS:
>>   	case VIDEO_ENHANCEMENT_CLASS:
>>   	case COPY_ENGINE_CLASS:
>> +	case OTHER_CLASS:
>>   		if (GRAPHICS_VER(gt->i915) < 8)
>>   			return 0;
>>   		return GEN8_LR_CONTEXT_OTHER_SIZE;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> index 6b5d4ea22b67..4fd54fb8810f 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> @@ -136,6 +136,7 @@ enum intel_engine_id {
>>   	CCS2,
>>   	CCS3,
>>   #define _CCS(n) (CCS0 + (n))
>> +	GSC0,
>>   	I915_NUM_ENGINES
>>   #define INVALID_ENGINE ((enum intel_engine_id)-1)
>>   };
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> index 46a174f8aa00..79312b734690 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> @@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
>>   		[COPY_ENGINE_CLASS] = "bcs",
>>   		[VIDEO_DECODE_CLASS] = "vcs",
>>   		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
>> +		[OTHER_CLASS] = "other",
>>   		[COMPUTE_CLASS] = "ccs",
>>   	};
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 1c0da50c0dc7..d056c3117ef2 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -970,6 +970,7 @@
>>   #define GEN11_VEBOX2_RING_BASE		0x1d8000
>>   #define XEHP_VEBOX3_RING_BASE		0x1e8000
>>   #define XEHP_VEBOX4_RING_BASE		0x1f8000
>> +#define MTL_GSC_RING_BASE		0x11a000
>>   #define GEN12_COMPUTE0_RING_BASE	0x1a000
>>   #define GEN12_COMPUTE1_RING_BASE	0x1c000
>>   #define GEN12_COMPUTE2_RING_BASE	0x1e000
>> -- 
>> 2.37.3
>>

Re: [Intel-gfx] [PATCH 1/5] drm/i915/mtl: add initial definitions for GSC CS

[Ceraolo Spurio, Daniele]

On 10/31/2022 9:26 AM, Matt Roper wrote:
> On Thu, Oct 27, 2022 at 03:15:50PM -0700, Daniele Ceraolo Spurio wrote:
>> Starting on MTL, the GSC is no longer managed with direct MMIO access,
>> but we instead have a dedicated command streamer for it. As a first step
>> for adding support for this CS, add the required definitions.
>> Note that, although it is now a CS, the GSC retains its old
>> class:instance value (OTHER_CLASS instance 6)
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
> Now that we have an OTHER_CLASS engine, I think we also need to deal
> with the class -> reg mapping table in mmio_invalidate_full().  I think
> the register we want is 0xCF04?

I missed that. Looks like the the situation is a bit more complex than 
just adding the new register, because on pre-MTL platforms CF04 is the 
compute class invalidation register. On MTL as you said CF04 is marked 
as the GSC CS invalidation register, but I can't find the compute one. 
Do you know if it re-uses the render one or something like that?
Given that there seem to be non-GSC related changes as well, IMO this 
should probably be a separate patch to specifically handle the TLB inval 
changes on MTL.

Daniele

>
> Matt
>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
>>   drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
>>   drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
>>   drivers/gpu/drm/i915/i915_reg.h              | 1 +
>>   4 files changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 3b7d750ad054..e0fbfac03979 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
>>   			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
>>   		}
>>   	},
>> +	[GSC0] = {
>> +		.class = OTHER_CLASS,
>> +		.instance = OTHER_GSC_INSTANCE,
>> +		.mmio_bases = {
>> +			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
>> +		}
>> +	},
>>   };
>>   
>>   /**
>> @@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
>>   	case VIDEO_DECODE_CLASS:
>>   	case VIDEO_ENHANCEMENT_CLASS:
>>   	case COPY_ENGINE_CLASS:
>> +	case OTHER_CLASS:
>>   		if (GRAPHICS_VER(gt->i915) < 8)
>>   			return 0;
>>   		return GEN8_LR_CONTEXT_OTHER_SIZE;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> index 6b5d4ea22b67..4fd54fb8810f 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> @@ -136,6 +136,7 @@ enum intel_engine_id {
>>   	CCS2,
>>   	CCS3,
>>   #define _CCS(n) (CCS0 + (n))
>> +	GSC0,
>>   	I915_NUM_ENGINES
>>   #define INVALID_ENGINE ((enum intel_engine_id)-1)
>>   };
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> index 46a174f8aa00..79312b734690 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
>> @@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
>>   		[COPY_ENGINE_CLASS] = "bcs",
>>   		[VIDEO_DECODE_CLASS] = "vcs",
>>   		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
>> +		[OTHER_CLASS] = "other",
>>   		[COMPUTE_CLASS] = "ccs",
>>   	};
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 1c0da50c0dc7..d056c3117ef2 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -970,6 +970,7 @@
>>   #define GEN11_VEBOX2_RING_BASE		0x1d8000
>>   #define XEHP_VEBOX3_RING_BASE		0x1e8000
>>   #define XEHP_VEBOX4_RING_BASE		0x1f8000
>> +#define MTL_GSC_RING_BASE		0x11a000
>>   #define GEN12_COMPUTE0_RING_BASE	0x1a000
>>   #define GEN12_COMPUTE1_RING_BASE	0x1c000
>>   #define GEN12_COMPUTE2_RING_BASE	0x1e000
>> -- 
>> 2.37.3
>>

Re: [PATCH 1/5] drm/i915/mtl: add initial definitions for GSC CS

[Matt Roper]

On Mon, Oct 31, 2022 at 09:43:33AM -0700, Ceraolo Spurio, Daniele wrote:
> 
> 
> On 10/31/2022 9:26 AM, Matt Roper wrote:
> > On Thu, Oct 27, 2022 at 03:15:50PM -0700, Daniele Ceraolo Spurio wrote:
> > > Starting on MTL, the GSC is no longer managed with direct MMIO access,
> > > but we instead have a dedicated command streamer for it. As a first step
> > > for adding support for this CS, add the required definitions.
> > > Note that, although it is now a CS, the GSC retains its old
> > > class:instance value (OTHER_CLASS instance 6)
> > > 
> > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Now that we have an OTHER_CLASS engine, I think we also need to deal
> > with the class -> reg mapping table in mmio_invalidate_full().  I think
> > the register we want is 0xCF04?
> 
> I missed that. Looks like the the situation is a bit more complex than just
> adding the new register, because on pre-MTL platforms CF04 is the compute
> class invalidation register. On MTL as you said CF04 is marked as the GSC CS
> invalidation register, but I can't find the compute one. Do you know if it
> re-uses the render one or something like that?
> Given that there seem to be non-GSC related changes as well, IMO this should
> probably be a separate patch to specifically handle the TLB inval changes on
> MTL.

Yeah, makes sense; we can follow up with separate patches for this.

+Cc Fei since he's done a lot of work on TLB invalidation and may know
what happens to compute class invalidation on MTL when the GSC takes
over that register.


Matt

> 
> Daniele
> 
> > 
> > Matt
> > 
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
> > >   drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
> > >   drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
> > >   drivers/gpu/drm/i915/i915_reg.h              | 1 +
> > >   4 files changed, 11 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > index 3b7d750ad054..e0fbfac03979 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > @@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
> > >   			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
> > >   		}
> > >   	},
> > > +	[GSC0] = {
> > > +		.class = OTHER_CLASS,
> > > +		.instance = OTHER_GSC_INSTANCE,
> > > +		.mmio_bases = {
> > > +			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
> > > +		}
> > > +	},
> > >   };
> > >   /**
> > > @@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
> > >   	case VIDEO_DECODE_CLASS:
> > >   	case VIDEO_ENHANCEMENT_CLASS:
> > >   	case COPY_ENGINE_CLASS:
> > > +	case OTHER_CLASS:
> > >   		if (GRAPHICS_VER(gt->i915) < 8)
> > >   			return 0;
> > >   		return GEN8_LR_CONTEXT_OTHER_SIZE;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > index 6b5d4ea22b67..4fd54fb8810f 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > @@ -136,6 +136,7 @@ enum intel_engine_id {
> > >   	CCS2,
> > >   	CCS3,
> > >   #define _CCS(n) (CCS0 + (n))
> > > +	GSC0,
> > >   	I915_NUM_ENGINES
> > >   #define INVALID_ENGINE ((enum intel_engine_id)-1)
> > >   };
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > index 46a174f8aa00..79312b734690 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > @@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
> > >   		[COPY_ENGINE_CLASS] = "bcs",
> > >   		[VIDEO_DECODE_CLASS] = "vcs",
> > >   		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
> > > +		[OTHER_CLASS] = "other",
> > >   		[COMPUTE_CLASS] = "ccs",
> > >   	};
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 1c0da50c0dc7..d056c3117ef2 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -970,6 +970,7 @@
> > >   #define GEN11_VEBOX2_RING_BASE		0x1d8000
> > >   #define XEHP_VEBOX3_RING_BASE		0x1e8000
> > >   #define XEHP_VEBOX4_RING_BASE		0x1f8000
> > > +#define MTL_GSC_RING_BASE		0x11a000
> > >   #define GEN12_COMPUTE0_RING_BASE	0x1a000
> > >   #define GEN12_COMPUTE1_RING_BASE	0x1c000
> > >   #define GEN12_COMPUTE2_RING_BASE	0x1e000
> > > -- 
> > > 2.37.3
> > > 
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 1/5] drm/i915/mtl: add initial definitions for GSC CS

[Matt Roper]

On Mon, Oct 31, 2022 at 09:43:33AM -0700, Ceraolo Spurio, Daniele wrote:
> 
> 
> On 10/31/2022 9:26 AM, Matt Roper wrote:
> > On Thu, Oct 27, 2022 at 03:15:50PM -0700, Daniele Ceraolo Spurio wrote:
> > > Starting on MTL, the GSC is no longer managed with direct MMIO access,
> > > but we instead have a dedicated command streamer for it. As a first step
> > > for adding support for this CS, add the required definitions.
> > > Note that, although it is now a CS, the GSC retains its old
> > > class:instance value (OTHER_CLASS instance 6)
> > > 
> > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Now that we have an OTHER_CLASS engine, I think we also need to deal
> > with the class -> reg mapping table in mmio_invalidate_full().  I think
> > the register we want is 0xCF04?
> 
> I missed that. Looks like the the situation is a bit more complex than just
> adding the new register, because on pre-MTL platforms CF04 is the compute
> class invalidation register. On MTL as you said CF04 is marked as the GSC CS
> invalidation register, but I can't find the compute one. Do you know if it
> re-uses the render one or something like that?
> Given that there seem to be non-GSC related changes as well, IMO this should
> probably be a separate patch to specifically handle the TLB inval changes on
> MTL.

Yeah, makes sense; we can follow up with separate patches for this.

+Cc Fei since he's done a lot of work on TLB invalidation and may know
what happens to compute class invalidation on MTL when the GSC takes
over that register.


Matt

> 
> Daniele
> 
> > 
> > Matt
> > 
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_engine_cs.c    | 8 ++++++++
> > >   drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
> > >   drivers/gpu/drm/i915/gt/intel_engine_user.c  | 1 +
> > >   drivers/gpu/drm/i915/i915_reg.h              | 1 +
> > >   4 files changed, 11 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > index 3b7d750ad054..e0fbfac03979 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > @@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
> > >   			{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
> > >   		}
> > >   	},
> > > +	[GSC0] = {
> > > +		.class = OTHER_CLASS,
> > > +		.instance = OTHER_GSC_INSTANCE,
> > > +		.mmio_bases = {
> > > +			{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
> > > +		}
> > > +	},
> > >   };
> > >   /**
> > > @@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
> > >   	case VIDEO_DECODE_CLASS:
> > >   	case VIDEO_ENHANCEMENT_CLASS:
> > >   	case COPY_ENGINE_CLASS:
> > > +	case OTHER_CLASS:
> > >   		if (GRAPHICS_VER(gt->i915) < 8)
> > >   			return 0;
> > >   		return GEN8_LR_CONTEXT_OTHER_SIZE;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > index 6b5d4ea22b67..4fd54fb8810f 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > @@ -136,6 +136,7 @@ enum intel_engine_id {
> > >   	CCS2,
> > >   	CCS3,
> > >   #define _CCS(n) (CCS0 + (n))
> > > +	GSC0,
> > >   	I915_NUM_ENGINES
> > >   #define INVALID_ENGINE ((enum intel_engine_id)-1)
> > >   };
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > index 46a174f8aa00..79312b734690 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > @@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
> > >   		[COPY_ENGINE_CLASS] = "bcs",
> > >   		[VIDEO_DECODE_CLASS] = "vcs",
> > >   		[VIDEO_ENHANCEMENT_CLASS] = "vecs",
> > > +		[OTHER_CLASS] = "other",
> > >   		[COMPUTE_CLASS] = "ccs",
> > >   	};
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 1c0da50c0dc7..d056c3117ef2 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -970,6 +970,7 @@
> > >   #define GEN11_VEBOX2_RING_BASE		0x1d8000
> > >   #define XEHP_VEBOX3_RING_BASE		0x1e8000
> > >   #define XEHP_VEBOX4_RING_BASE		0x1f8000
> > > +#define MTL_GSC_RING_BASE		0x11a000
> > >   #define GEN12_COMPUTE0_RING_BASE	0x1a000
> > >   #define GEN12_COMPUTE1_RING_BASE	0x1c000
> > >   #define GEN12_COMPUTE2_RING_BASE	0x1e000
> > > -- 
> > > 2.37.3
> > > 
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation