[Intel-gfx] [PATCH v2 0/9] drm/i915/tgl+: Enable DC power states on all eDP ports

[Intel-gfx] [PATCH v2 0/9] drm/i915/tgl+: Enable DC power states on all eDP ports

[Imre Deak]

This is v2 of [1] addressing the review comments from Ville and Jani:

- Select the AUX power domain based on PSR capability instead of is_edp().
- Split out change using AUX vs AUX_IO on port A without PSR.
- Don't enable AUX_IO on eDP w/o PSR and external DP combo PHY ports.
- Simplify intel_display_power_(get/put)_in_set().

[1] https://lore.kernel.org/intel-gfx/20221102171530.3261282-1-imre.deak@intel.com/T/#t

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>

Imre Deak (9):
  drm/i915: Allocate power domain set wakerefs dynamically
  drm/i915: Move the POWER_DOMAIN_AUX_IO_A definition to its logical
    place
  drm/i915: Use the AUX_IO power domain only for eDP/PSR port
  drm/i915/tgl+: Enable display DC power states on all eDP ports
  drm/i915: Add missing AUX_IO_A power domain->well mappings
  drm/i915: Add missing DC_OFF power domain->well mappings
  drm/i915: Factor out function to get/put AUX_IO power for main link
  drm/i915: Don't enable the AUX_IO power for combo-PHY external DP port
    main links
  drm/i915/mtl+: Don't enable the AUX_IO power for non-eDP port main
    links

 drivers/gpu/drm/i915/display/intel_crtc.c     |   4 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |  89 +++++++-----
 .../drm/i915/display/intel_display_power.c    | 129 ++++++++++++++----
 .../drm/i915/display/intel_display_power.h    |  14 +-
 .../i915/display/intel_display_power_map.c    |  69 ++++++++--
 5 files changed, 237 insertions(+), 68 deletions(-)

-- 
2.37.1

[Intel-gfx] [PATCH v2 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Imre Deak]

Since the intel_display_power_domain_set struct, currently its current
size close 1kB, can be allocated on the stack, it's better to allocate
the per-domain wakeref pointer array - used for debugging - within the
struct dynamically, so do this.

The memory freeing is guaranteed by the fact that the acquired domain
references tracked by struct can't be leaked either.

v2:
- Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
- Simplify intel_display_power_get/put_in_set(). (Jani)
- Check in intel_crtc_destroy() that the wakerefs array has been freed.

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc.c     |  4 +
 .../drm/i915/display/intel_display_power.c    | 95 +++++++++++++++----
 .../drm/i915/display/intel_display_power.h    |  2 +-
 3 files changed, 79 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 037fc140b585c..2c8d564e73182 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -205,6 +205,10 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
 	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
 
 	drm_crtc_cleanup(&crtc->base);
+
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
+	drm_WARN_ON(crtc->base.dev, crtc->enabled_power_domains.wakerefs);
+#endif
 	kfree(crtc);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4c1de91e56ff9..db235b79c9629 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
 }
 #endif
 
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
+static void
+add_domain_to_set(struct drm_i915_private *i915,
+		  struct intel_display_power_domain_set *power_domain_set,
+		  enum intel_display_power_domain domain,
+		  intel_wakeref_t wf)
+{
+	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
+
+	if (!power_domain_set->wakerefs)
+		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
+						     sizeof(*power_domain_set->wakerefs),
+						     GFP_KERNEL);
+
+	if (power_domain_set->wakerefs)
+		power_domain_set->wakerefs[domain] = wf;
+
+	set_bit(domain, power_domain_set->mask.bits);
+}
+
+static intel_wakeref_t
+remove_domain_from_set(struct drm_i915_private *i915,
+		       struct intel_display_power_domain_set *power_domain_set,
+		       enum intel_display_power_domain domain)
+{
+	intel_wakeref_t wf;
+
+	drm_WARN_ON(&i915->drm, !test_bit(domain, power_domain_set->mask.bits));
+
+	clear_bit(domain, power_domain_set->mask.bits);
+
+	if (!power_domain_set->wakerefs)
+		return -1;
+
+	wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
+
+	if (bitmap_empty(power_domain_set->mask.bits, POWER_DOMAIN_NUM)) {
+		kfree(power_domain_set->wakerefs);
+		power_domain_set->wakerefs = NULL;
+	}
+
+	return wf;
+
+}
+#else
+static void
+add_domain_to_set(struct drm_i915_private *i915,
+		  struct intel_display_power_domain_set *power_domain_set,
+		  enum intel_display_power_domain domain,
+		  intel_wakeref_t wf)
+{
+	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
+
+	set_bit(domain, power_domain_set->mask.bits);
+}
+
+static intel_wakeref_t
+remove_domain_from_set(struct drm_i915_private *i915,
+		       struct intel_display_power_domain_set *power_domain_set,
+		       enum intel_display_power_domain domain)
+{
+	drm_WARN_ON(&i915->drm, !test_bit(domain, power_domain_set->mask.bits));
+
+	clear_bit(domain, power_domain_set->mask.bits);
+
+	return -1;
+}
+#endif
+
 void
 intel_display_power_get_in_set(struct drm_i915_private *i915,
 			       struct intel_display_power_domain_set *power_domain_set,
 			       enum intel_display_power_domain domain)
 {
-	intel_wakeref_t __maybe_unused wf;
-
-	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
+	intel_wakeref_t wf;
 
 	wf = intel_display_power_get(i915, domain);
-#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-	power_domain_set->wakerefs[domain] = wf;
-#endif
-	set_bit(domain, power_domain_set->mask.bits);
+
+	add_domain_to_set(i915, power_domain_set, domain, wf);
 }
 
 bool
@@ -853,16 +918,11 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
 {
 	intel_wakeref_t wf;
 
-	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
-
 	wf = intel_display_power_get_if_enabled(i915, domain);
 	if (!wf)
 		return false;
 
-#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-	power_domain_set->wakerefs[domain] = wf;
-#endif
-	set_bit(domain, power_domain_set->mask.bits);
+	add_domain_to_set(i915, power_domain_set, domain, wf);
 
 	return true;
 }
@@ -874,17 +934,10 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
 {
 	enum intel_display_power_domain domain;
 
-	drm_WARN_ON(&i915->drm,
-		    !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
-
 	for_each_power_domain(domain, mask) {
-		intel_wakeref_t __maybe_unused wf = -1;
+		intel_wakeref_t wf = remove_domain_from_set(i915, power_domain_set, domain);
 
-#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-		wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
-#endif
 		intel_display_power_put(i915, domain, wf);
-		clear_bit(domain, power_domain_set->mask.bits);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 1e77e52c87fec..662123d260a7a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -147,7 +147,7 @@ struct i915_power_domains {
 struct intel_display_power_domain_set {
 	struct intel_power_domain_mask mask;
 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
-	intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
+	intel_wakeref_t *wakerefs;
 #endif
 };
 
-- 
2.37.1

[Intel-gfx] [PATCH v2 2/9] drm/i915: Move the POWER_DOMAIN_AUX_IO_A definition to its logical place

[Imre Deak]

Move the definition of the AUX_IO_A power domain, requiring only the
corresponding AUX_IO_A power well to be enabled, before all the
AUX_<port> power domains, which require both the AUX_IO_<port> and the
DC_OFF power wells to be enabled.

No functional change.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c     | 4 ++--
 drivers/gpu/drm/i915/display/intel_display_power.h     | 5 +++--
 drivers/gpu/drm/i915/display/intel_display_power_map.c | 6 +++---
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index db235b79c9629..75d6c24c1d144 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -129,6 +129,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "AUDIO_MMIO";
 	case POWER_DOMAIN_AUDIO_PLAYBACK:
 		return "AUDIO_PLAYBACK";
+	case POWER_DOMAIN_AUX_IO_A:
+		return "AUX_IO_A";
 	case POWER_DOMAIN_AUX_A:
 		return "AUX_A";
 	case POWER_DOMAIN_AUX_B:
@@ -153,8 +155,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "AUX_USBC5";
 	case POWER_DOMAIN_AUX_USBC6:
 		return "AUX_USBC6";
-	case POWER_DOMAIN_AUX_IO_A:
-		return "AUX_IO_A";
 	case POWER_DOMAIN_AUX_TBT1:
 		return "AUX_TBT1";
 	case POWER_DOMAIN_AUX_TBT2:
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 662123d260a7a..2169864f3f044 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -77,6 +77,9 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_VGA,
 	POWER_DOMAIN_AUDIO_MMIO,
 	POWER_DOMAIN_AUDIO_PLAYBACK,
+
+	POWER_DOMAIN_AUX_IO_A,
+
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
@@ -91,8 +94,6 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_AUX_USBC5,
 	POWER_DOMAIN_AUX_USBC6,
 
-	POWER_DOMAIN_AUX_IO_A,
-
 	POWER_DOMAIN_AUX_TBT1,
 	POWER_DOMAIN_AUX_TBT2,
 	POWER_DOMAIN_AUX_TBT3,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index dc04afc6cc8ff..43454022e6a66 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -518,8 +518,8 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
-	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_IO_A,
+	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
@@ -658,8 +658,8 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e,	POWER_DOMAIN_PORT_DDI_IO_E);
 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f,	POWER_DOMAIN_PORT_DDI_IO_F);
 
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
-	POWER_DOMAIN_AUX_A,
-	POWER_DOMAIN_AUX_IO_A);
+	POWER_DOMAIN_AUX_IO_A,
+	POWER_DOMAIN_AUX_A);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,		POWER_DOMAIN_AUX_B);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,		POWER_DOMAIN_AUX_C);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,		POWER_DOMAIN_AUX_D);
-- 
2.37.1

[Intel-gfx] [PATCH v2 3/9] drm/i915: Use the AUX_IO power domain only for eDP/PSR port

[Imre Deak]

Use the AUX_IO_A display power domain only for eDP on port A where PSR
is also supported. This is the case where DC states need to be enabled
while the output is enabled - ensured by AUX_IO_A domain not enabling
the DC_OFF power well. Otherwise port A can be treated the same way as
other ports with an external DP output: using the AUX_<port> domain
which disables the unrequired DC states.

This change prepares for the next patch enabling DC states on all ports
supporting eDP/PSR besides port A.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e95bde5cf060e..4154f454ab52a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -846,7 +846,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 }
 
 static enum intel_display_power_domain
-intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
+intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
+			       const struct intel_crtc_state *crtc_state)
 {
 	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 	 * DC states enabled at the same time, while for driver initiated AUX
@@ -860,8 +861,10 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 	 * Note that PSR is enabled only on Port A even though this function
 	 * returns the correct domain for other ports too.
 	 */
-	return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
-					      intel_aux_power_domain(dig_port);
+	if (dig_port->aux_ch == AUX_CH_A && crtc_state->has_psr)
+		return POWER_DOMAIN_AUX_IO_A;
+	else
+		return intel_aux_power_domain(dig_port);
 }
 
 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
@@ -897,7 +900,8 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
 		dig_port->aux_wakeref =
 			intel_display_power_get(dev_priv,
-						intel_ddi_main_link_aux_domain(dig_port));
+						intel_ddi_main_link_aux_domain(dig_port,
+									       crtc_state));
 	}
 }
 
@@ -2739,7 +2743,8 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
 
 	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
 		intel_display_power_put(dev_priv,
-					intel_ddi_main_link_aux_domain(dig_port),
+					intel_ddi_main_link_aux_domain(dig_port,
+								       old_crtc_state),
 					fetch_and_zero(&dig_port->aux_wakeref));
 
 	if (is_tc_port)
@@ -3065,7 +3070,8 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
 		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
 		dig_port->aux_wakeref =
 			intel_display_power_get(dev_priv,
-						intel_ddi_main_link_aux_domain(dig_port));
+						intel_ddi_main_link_aux_domain(dig_port,
+									       crtc_state));
 	}
 
 	if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
-- 
2.37.1

[Intel-gfx] [PATCH v2 4/9] drm/i915/tgl+: Enable display DC power states on all eDP ports

[Imre Deak]

Starting with TGL eDP is supported on ports B+ (besides port A), so make
sure DC states are not blocked on any such ports. For this add an
AUX_IO_<port> power domain for each port with eDP support. These domains
similarly to AUX_IO_A enable only the AUX_IO_<port> power well for an
enabled port, whereas the existing AUX_<port> domains enable both the
AUX_IO_<port> and the DC_OFF power wells as required by DP AUX transfers.

v2: (Ville)
- Split the change using AUX vs. AUX_IO on port A to a separate patch.
- Select AUX_IO vs. AUX based on crtc_state->has_psr instead of
  is_edp().

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  6 ++-
 .../drm/i915/display/intel_display_power.c    | 30 +++++++++++
 .../drm/i915/display/intel_display_power.h    |  7 +++
 .../i915/display/intel_display_power_map.c    | 53 +++++++++++++++++--
 4 files changed, 89 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4154f454ab52a..d2953bf503765 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -849,6 +849,8 @@ static enum intel_display_power_domain
 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
 			       const struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
 	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 	 * DC states enabled at the same time, while for driver initiated AUX
 	 * transfers we need the same AUX IOs to be powered but with DC states
@@ -861,8 +863,8 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
 	 * Note that PSR is enabled only on Port A even though this function
 	 * returns the correct domain for other ports too.
 	 */
-	if (dig_port->aux_ch == AUX_CH_A && crtc_state->has_psr)
-		return POWER_DOMAIN_AUX_IO_A;
+	if (crtc_state->has_psr)
+		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
 	else
 		return intel_aux_power_domain(dig_port);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 75d6c24c1d144..c2df60cfdcf17 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -131,6 +131,16 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "AUDIO_PLAYBACK";
 	case POWER_DOMAIN_AUX_IO_A:
 		return "AUX_IO_A";
+	case POWER_DOMAIN_AUX_IO_B:
+		return "AUX_IO_B";
+	case POWER_DOMAIN_AUX_IO_C:
+		return "AUX_IO_C";
+	case POWER_DOMAIN_AUX_IO_D:
+		return "AUX_IO_D";
+	case POWER_DOMAIN_AUX_IO_E:
+		return "AUX_IO_E";
+	case POWER_DOMAIN_AUX_IO_F:
+		return "AUX_IO_F";
 	case POWER_DOMAIN_AUX_A:
 		return "AUX_A";
 	case POWER_DOMAIN_AUX_B:
@@ -2342,6 +2352,7 @@ struct intel_ddi_port_domains {
 
 	enum intel_display_power_domain ddi_lanes;
 	enum intel_display_power_domain ddi_io;
+	enum intel_display_power_domain aux_io;
 	enum intel_display_power_domain aux_legacy_usbc;
 	enum intel_display_power_domain aux_tbt;
 };
@@ -2356,6 +2367,7 @@ i9xx_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+		.aux_io = POWER_DOMAIN_AUX_IO_A,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
 		.aux_tbt = POWER_DOMAIN_INVALID,
 	},
@@ -2371,6 +2383,7 @@ d11_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+		.aux_io = POWER_DOMAIN_AUX_IO_A,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
 		.aux_tbt = POWER_DOMAIN_INVALID,
 	}, {
@@ -2381,6 +2394,7 @@ d11_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
+		.aux_io = POWER_DOMAIN_AUX_IO_C,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_C,
 		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
 	},
@@ -2396,6 +2410,7 @@ d12_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+		.aux_io = POWER_DOMAIN_AUX_IO_A,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
 		.aux_tbt = POWER_DOMAIN_INVALID,
 	}, {
@@ -2406,6 +2421,7 @@ d12_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
+		.aux_io = POWER_DOMAIN_INVALID,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
 		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
 	},
@@ -2421,6 +2437,7 @@ d13_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+		.aux_io = POWER_DOMAIN_AUX_IO_A,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
 		.aux_tbt = POWER_DOMAIN_INVALID,
 	}, {
@@ -2431,6 +2448,7 @@ d13_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
+		.aux_io = POWER_DOMAIN_INVALID,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
 		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
 	}, {
@@ -2441,6 +2459,7 @@ d13_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
+		.aux_io = POWER_DOMAIN_AUX_IO_D,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_D,
 		.aux_tbt = POWER_DOMAIN_INVALID,
 	},
@@ -2518,6 +2537,17 @@ intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
 	return NULL;
 }
 
+enum intel_display_power_domain
+intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
+{
+	const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
+
+	if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_io == POWER_DOMAIN_INVALID)
+		return POWER_DOMAIN_AUX_IO_A;
+
+	return domains->aux_io + (int)(aux_ch - domains->aux_ch_start);
+}
+
 enum intel_display_power_domain
 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 2169864f3f044..25beed7eb9566 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -79,6 +79,11 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_AUDIO_PLAYBACK,
 
 	POWER_DOMAIN_AUX_IO_A,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
+	POWER_DOMAIN_AUX_IO_D,
+	POWER_DOMAIN_AUX_IO_E,
+	POWER_DOMAIN_AUX_IO_F,
 
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
@@ -251,6 +256,8 @@ intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port po
 enum intel_display_power_domain
 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
 enum intel_display_power_domain
+intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
+enum intel_display_power_domain
 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
 enum intel_display_power_domain
 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 43454022e6a66..b82c0d0a80c5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -170,6 +170,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
 	POWER_DOMAIN_VGA,
 	POWER_DOMAIN_AUDIO_MMIO,
 	POWER_DOMAIN_AUDIO_PLAYBACK,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_GMBUS,
@@ -179,6 +181,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
 	POWER_DOMAIN_PORT_DDI_LANES_B,
 	POWER_DOMAIN_PORT_DDI_LANES_C,
 	POWER_DOMAIN_PORT_CRT,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_INIT);
@@ -186,6 +190,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
 	POWER_DOMAIN_PORT_DDI_LANES_B,
 	POWER_DOMAIN_PORT_DDI_LANES_C,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_INIT);
@@ -243,6 +249,9 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_display,
 	POWER_DOMAIN_VGA,
 	POWER_DOMAIN_AUDIO_MMIO,
 	POWER_DOMAIN_AUDIO_PLAYBACK,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
+	POWER_DOMAIN_AUX_IO_D,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_AUX_D,
@@ -252,12 +261,15 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_display,
 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
 	POWER_DOMAIN_PORT_DDI_LANES_B,
 	POWER_DOMAIN_PORT_DDI_LANES_C,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
 	POWER_DOMAIN_PORT_DDI_LANES_D,
+	POWER_DOMAIN_AUX_IO_D,
 	POWER_DOMAIN_AUX_D,
 	POWER_DOMAIN_INIT);
 
@@ -305,6 +317,9 @@ static const struct i915_power_well_desc_list chv_power_wells[] = {
 	POWER_DOMAIN_VGA, \
 	POWER_DOMAIN_AUDIO_MMIO, \
 	POWER_DOMAIN_AUDIO_PLAYBACK, \
+	POWER_DOMAIN_AUX_IO_B, \
+	POWER_DOMAIN_AUX_IO_C, \
+	POWER_DOMAIN_AUX_IO_D, \
 	POWER_DOMAIN_AUX_B, \
 	POWER_DOMAIN_AUX_C, \
 	POWER_DOMAIN_AUX_D
@@ -407,6 +422,8 @@ static const struct i915_power_well_desc_list skl_power_wells[] = {
 	POWER_DOMAIN_VGA, \
 	POWER_DOMAIN_AUDIO_MMIO, \
 	POWER_DOMAIN_AUDIO_PLAYBACK, \
+	POWER_DOMAIN_AUX_IO_B, \
+	POWER_DOMAIN_AUX_IO_C, \
 	POWER_DOMAIN_AUX_B, \
 	POWER_DOMAIN_AUX_C
 
@@ -430,6 +447,8 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
 	POWER_DOMAIN_PORT_DDI_LANES_B,
 	POWER_DOMAIN_PORT_DDI_LANES_C,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_INIT);
@@ -483,6 +502,8 @@ static const struct i915_power_well_desc_list bxt_power_wells[] = {
 	POWER_DOMAIN_VGA, \
 	POWER_DOMAIN_AUDIO_MMIO, \
 	POWER_DOMAIN_AUDIO_PLAYBACK, \
+	POWER_DOMAIN_AUX_IO_B, \
+	POWER_DOMAIN_AUX_IO_C, \
 	POWER_DOMAIN_AUX_B, \
 	POWER_DOMAIN_AUX_C
 
@@ -509,11 +530,13 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
 	POWER_DOMAIN_PORT_DDI_LANES_B,
+	POWER_DOMAIN_AUX_IO_B,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
 	POWER_DOMAIN_PORT_DDI_LANES_C,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_INIT);
 
@@ -523,10 +546,12 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
+	POWER_DOMAIN_AUX_IO_B,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_INIT);
 
@@ -617,6 +642,11 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
 	POWER_DOMAIN_VGA, \
 	POWER_DOMAIN_AUDIO_MMIO, \
 	POWER_DOMAIN_AUDIO_PLAYBACK, \
+	POWER_DOMAIN_AUX_IO_B, \
+	POWER_DOMAIN_AUX_IO_C, \
+	POWER_DOMAIN_AUX_IO_D, \
+	POWER_DOMAIN_AUX_IO_E, \
+	POWER_DOMAIN_AUX_IO_F, \
 	POWER_DOMAIN_AUX_B, \
 	POWER_DOMAIN_AUX_C, \
 	POWER_DOMAIN_AUX_D, \
@@ -660,11 +690,21 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f,	POWER_DOMAIN_PORT_DDI_IO_F);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
 	POWER_DOMAIN_AUX_IO_A,
 	POWER_DOMAIN_AUX_A);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,		POWER_DOMAIN_AUX_B);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,		POWER_DOMAIN_AUX_C);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,		POWER_DOMAIN_AUX_D);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,		POWER_DOMAIN_AUX_E);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,		POWER_DOMAIN_AUX_F);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_B);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,
+	POWER_DOMAIN_AUX_IO_C,
+	POWER_DOMAIN_AUX_C);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,
+	POWER_DOMAIN_AUX_IO_D,
+	POWER_DOMAIN_AUX_D);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,
+	POWER_DOMAIN_AUX_IO_E,
+	POWER_DOMAIN_AUX_E);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,
+	POWER_DOMAIN_AUX_IO_F,
+	POWER_DOMAIN_AUX_F);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1,	POWER_DOMAIN_AUX_TBT1);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2,	POWER_DOMAIN_AUX_TBT2);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3,	POWER_DOMAIN_AUX_TBT3);
@@ -1215,6 +1255,9 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
 	POWER_DOMAIN_PORT_DDI_LANES_TC4, \
 	POWER_DOMAIN_VGA, \
 	POWER_DOMAIN_AUDIO_PLAYBACK, \
+	POWER_DOMAIN_AUX_IO_C, \
+	POWER_DOMAIN_AUX_IO_D, \
+	POWER_DOMAIN_AUX_IO_E, \
 	POWER_DOMAIN_AUX_C, \
 	POWER_DOMAIN_AUX_D, \
 	POWER_DOMAIN_AUX_E, \
-- 
2.37.1

[Intel-gfx] [PATCH v2 5/9] drm/i915: Add missing AUX_IO_A power domain->well mappings

[Imre Deak]

BXT and GLK were missing the AUX_IO_A power domain -> PHY A common power
well mapping, add these now. This didn't cause a problem as the
AUX_IO_A and DDI_LANES_A power domains are acquired together.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power_map.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index b82c0d0a80c5f..aa9d1ae9e8a26 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -441,6 +441,7 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
 
 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
 	POWER_DOMAIN_PORT_DDI_LANES_A,
+	POWER_DOMAIN_AUX_IO_A,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_INIT);
 
@@ -525,6 +526,7 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c,	POWER_DOMAIN_PORT_DDI_IO_C);
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
 	POWER_DOMAIN_PORT_DDI_LANES_A,
+	POWER_DOMAIN_AUX_IO_A,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_INIT);
 
-- 
2.37.1

[Intel-gfx] [PATCH v2 6/9] drm/i915: Add missing DC_OFF power domain->well mappings

[Imre Deak]

Add the missing DC_OFF power domain -> DC_OFF power well mappings on all
platforms. This didn't cause a problem as the DC_OFF power domain is
only used on JSL, where the mapping was already correct.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power_map.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index aa9d1ae9e8a26..f5d66ca85b19b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -333,6 +333,7 @@ I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_MODESET,
 	POWER_DOMAIN_GT_IRQ,
+	POWER_DOMAIN_DC_OFF,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e,
@@ -437,6 +438,7 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
 	POWER_DOMAIN_GMBUS,
 	POWER_DOMAIN_MODESET,
 	POWER_DOMAIN_GT_IRQ,
+	POWER_DOMAIN_DC_OFF,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
@@ -518,6 +520,7 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
 	POWER_DOMAIN_GMBUS,
 	POWER_DOMAIN_MODESET,
 	POWER_DOMAIN_GT_IRQ,
+	POWER_DOMAIN_DC_OFF,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a,	POWER_DOMAIN_PORT_DDI_IO_A);
@@ -858,6 +861,7 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_MODESET,
+	POWER_DOMAIN_DC_OFF,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1,	POWER_DOMAIN_PORT_DDI_IO_TC1);
@@ -1054,6 +1058,7 @@ I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_MODESET,
+	POWER_DOMAIN_DC_OFF,
 	POWER_DOMAIN_INIT);
 
 static const struct i915_power_well_desc rkl_power_wells_main[] = {
@@ -1136,6 +1141,7 @@ I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_MODESET,
+	POWER_DOMAIN_DC_OFF,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
@@ -1300,6 +1306,7 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_MODESET,
+	POWER_DOMAIN_DC_OFF,
 	POWER_DOMAIN_INIT);
 
 static const struct i915_power_well_desc xelpd_power_wells_main[] = {
@@ -1421,6 +1428,7 @@ I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
 	POWER_DOMAIN_MODESET,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
+	POWER_DOMAIN_DC_OFF,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
-- 
2.37.1

[Intel-gfx] [PATCH v2 7/9] drm/i915: Factor out function to get/put AUX_IO power for main link

[Imre Deak]

Factor out functions to get/put the AUX_IO power domain for the main
link on DDI ports.

While at it clarify the corresponding code comment.

No functional change.

v2:
- s/(get/put)_aux_power_for_main_link/main_link_aux_power_domain_(get/put)
  (Jani)
- Clarify in the code comment that AUX_IO is needed only by TypeC besides
  eDP/PSR.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 84 ++++++++++++++----------
 1 file changed, 49 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d2953bf503765..b1f9bb45d90a2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -850,23 +850,59 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
 			       const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 
-	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
+	/*
+	 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 	 * DC states enabled at the same time, while for driver initiated AUX
 	 * transfers we need the same AUX IOs to be powered but with DC states
-	 * disabled. Accordingly use the AUX power domain here which leaves DC
-	 * states enabled.
-	 * However, for non-A AUX ports the corresponding non-EDP transcoders
-	 * would have already enabled power well 2 and DC_OFF. This means we can
-	 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
-	 * specific AUX_IO reference without powering up any extra wells.
-	 * Note that PSR is enabled only on Port A even though this function
-	 * returns the correct domain for other ports too.
+	 * disabled. Accordingly use the AUX_IO_<port> power domain here which
+	 * leaves DC states enabled.
+	 *
+	 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
+	 * AUX IO to be enabled, but all these require DC_OFF to be enabled as
+	 * well, so we can acquire a wider AUX_<port> power domain reference
+	 * instead of a specific AUX_IO_<port> reference without powering up any
+	 * extra wells.
 	 */
 	if (crtc_state->has_psr)
 		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
-	else
+	else if (intel_crtc_has_dp_encoder(crtc_state) ||
+		 intel_phy_is_tc(i915, phy))
 		return intel_aux_power_domain(dig_port);
+	else
+		return POWER_DOMAIN_INVALID;
+}
+
+static void
+main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
+			       const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum intel_display_power_domain domain =
+		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
+
+	drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
+
+	if (domain == POWER_DOMAIN_INVALID)
+		return;
+
+	dig_port->aux_wakeref = intel_display_power_get(i915, domain);
+}
+
+static void
+main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
+			       const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	intel_wakeref_t wf = fetch_and_zero(&dig_port->aux_wakeref);
+	enum intel_display_power_domain domain =
+		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
+
+	if (!wf)
+		return;
+
+	intel_display_power_put(i915, domain, wf);
 }
 
 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
@@ -874,7 +910,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port;
-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	/*
 	 * TODO: Add support for MST encoders. Atm, the following should never
@@ -893,18 +928,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 								   dig_port->ddi_io_power_domain);
 	}
 
-	/*
-	 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
-	 * ports.
-	 */
-	if (intel_crtc_has_dp_encoder(crtc_state) ||
-	    intel_phy_is_tc(dev_priv, phy)) {
-		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
-		dig_port->aux_wakeref =
-			intel_display_power_get(dev_priv,
-						intel_ddi_main_link_aux_domain(dig_port,
-									       crtc_state));
-	}
+	main_link_aux_power_domain_get(dig_port, crtc_state);
 }
 
 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
@@ -2743,11 +2767,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
 		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
 					  old_conn_state);
 
-	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
-		intel_display_power_put(dev_priv,
-					intel_ddi_main_link_aux_domain(dig_port,
-								       old_crtc_state),
-					fetch_and_zero(&dig_port->aux_wakeref));
+	main_link_aux_power_domain_put(dig_port, old_crtc_state);
 
 	if (is_tc_port)
 		intel_tc_port_put_link(dig_port);
@@ -3068,13 +3088,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
 	if (is_tc_port)
 		intel_tc_port_get_link(dig_port, crtc_state->lane_count);
 
-	if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
-		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
-		dig_port->aux_wakeref =
-			intel_display_power_get(dev_priv,
-						intel_ddi_main_link_aux_domain(dig_port,
-									       crtc_state));
-	}
+	main_link_aux_power_domain_get(dig_port, crtc_state);
 
 	if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
 		/*
-- 
2.37.1

[Intel-gfx] [PATCH v2 8/9] drm/i915: Don't enable the AUX_IO power for combo-PHY external DP port main links

[Imre Deak]

Combo PHY ports require the AUX_IO power only for eDP/PSR, so don't
enable it otherwise on these ports. So far the external DP and eDP case
was handled the same way due to unclarity when AUX_IO for the main link
is needed. However Bspec is clear in which cases it's required:

- eDP/PSR on all ports and platforms (presumably due to HW/FW initiated
  PSR transactions that won't enable AUX_IO)
  Bspec: 4301, 49296
- TypeC PHY ports on platforms before MTL in all TypeC modes (TBT,
  DP-alt, legacy) and for both HDMI and DP. The next patch will take
  into account the pre-MTL platform dependency.
  Bspec: 22243, 53339, 21750, 49190, 49191, 55424, 65448, 65750, 49294,
         55480, 65380

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b1f9bb45d90a2..b36c34f9adbee 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -867,8 +867,7 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
 	 */
 	if (crtc_state->has_psr)
 		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
-	else if (intel_crtc_has_dp_encoder(crtc_state) ||
-		 intel_phy_is_tc(i915, phy))
+	else if (intel_phy_is_tc(i915, phy))
 		return intel_aux_power_domain(dig_port);
 	else
 		return POWER_DOMAIN_INVALID;
-- 
2.37.1

[Intel-gfx] [PATCH v2 9/9] drm/i915/mtl+: Don't enable the AUX_IO power for non-eDP port main links

[Imre Deak]

MTL+ requires the AUX_IO power for the main link only on eDP, so don't
enable it in other cases.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b36c34f9adbee..73f06e870323d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -867,7 +867,7 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
 	 */
 	if (crtc_state->has_psr)
 		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
-	else if (intel_phy_is_tc(i915, phy))
+	else if (DISPLAY_VER(i915) < 14 && intel_phy_is_tc(i915, phy))
 		return intel_aux_power_domain(dig_port);
 	else
 		return POWER_DOMAIN_INVALID;
-- 
2.37.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl+: Enable DC power states on all eDP ports (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl+: Enable DC power states on all eDP ports (rev2)
URL   : https://patchwork.freedesktop.org/series/110433/
State : warning

== Summary ==

Error: dim checkpatch failed
8e83b3cd5464 drm/i915: Allocate power domain set wakerefs dynamically
-:88: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#88: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:876:
+
+}

total: 0 errors, 0 warnings, 1 checks, 145 lines checked
bbf87c1d17af drm/i915: Move the POWER_DOMAIN_AUX_IO_A definition to its logical place
fea870709c3e drm/i915: Use the AUX_IO power domain only for eDP/PSR port
00456395d38a drm/i915/tgl+: Enable display DC power states on all eDP ports
-:328: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#328: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:694:
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,
+	POWER_DOMAIN_AUX_IO_B,

-:331: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#331: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:697:
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,
+	POWER_DOMAIN_AUX_IO_C,

-:334: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#334: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:700:
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,
+	POWER_DOMAIN_AUX_IO_D,

-:337: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#337: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:703:
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,
+	POWER_DOMAIN_AUX_IO_E,

-:340: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#340: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:706:
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,
+	POWER_DOMAIN_AUX_IO_F,

total: 0 errors, 0 warnings, 5 checks, 285 lines checked
29aa00a91b71 drm/i915: Add missing AUX_IO_A power domain->well mappings
10eb378f3e2e drm/i915: Add missing DC_OFF power domain->well mappings
4c692af55f17 drm/i915: Factor out function to get/put AUX_IO power for main link
b819f56d0036 drm/i915: Don't enable the AUX_IO power for combo-PHY external DP port main links
c1312c9ff4ed drm/i915/mtl+: Don't enable the AUX_IO power for non-eDP port main links

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl+: Enable DC power states on all eDP ports (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl+: Enable DC power states on all eDP ports (rev2)
URL   : https://patchwork.freedesktop.org/series/110433/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl+: Enable DC power states on all eDP ports (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6361 bytes --]

== Series Details ==

Series: drm/i915/tgl+: Enable DC power states on all eDP ports (rev2)
URL   : https://patchwork.freedesktop.org/series/110433/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12353 -> Patchwork_110433v2
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/index.html

Participating hosts (41 -> 28)
------------------------------

  Additional (1): fi-rkl-11600 
  Missing    (14): fi-ilk-m540 fi-bdw-samus fi-tgl-dsi bat-dg2-8 bat-dg2-9 bat-adlp-6 bat-adlp-4 fi-ctg-p8600 bat-adln-1 bat-rplp-1 bat-rpls-1 bat-rpls-2 bat-dg2-11 bat-jsl-1 

Known issues
------------

  Here are the changes found in Patchwork_110433v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - fi-rkl-11600:       NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-rkl-11600:       NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
    - fi-rkl-11600:       NOTRUN -> [SKIP][3] ([i915#3282])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
    - fi-rkl-11600:       NOTRUN -> [SKIP][4] ([i915#3012])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-rkl-11600:       NOTRUN -> [INCOMPLETE][5] ([i915#4817])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-rkl-11600:       NOTRUN -> [SKIP][6] ([fdo#111827]) +7 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/fi-rkl-11600/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
    - fi-rkl-11600:       NOTRUN -> [SKIP][7] ([i915#4103])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-rkl-11600:       NOTRUN -> [SKIP][8] ([fdo#109285] / [i915#4098])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_psr@sprite_plane_onoff:
    - fi-rkl-11600:       NOTRUN -> [SKIP][9] ([i915#1072]) +3 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/fi-rkl-11600/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-rkl-11600:       NOTRUN -> [SKIP][10] ([i915#3555] / [i915#4098])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-read:
    - fi-rkl-11600:       NOTRUN -> [SKIP][11] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/fi-rkl-11600/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-userptr:
    - fi-rkl-11600:       NOTRUN -> [SKIP][12] ([fdo#109295] / [i915#3301] / [i915#3708])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/fi-rkl-11600/igt@prime_vgem@basic-userptr.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
  [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456


Build changes
-------------

  * Linux: CI_DRM_12353 -> Patchwork_110433v2

  CI-20190529: 20190529
  CI_DRM_12353: fb2b3ddb471df2f8d305b1bb7f3705e7e0fbf6e4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7046: c58d96d0fe237474b074e3472ce09c57c830d5de @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110433v2: fb2b3ddb471df2f8d305b1bb7f3705e7e0fbf6e4 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

7fc72fc15a18 drm/i915/mtl+: Don't enable the AUX_IO power for non-eDP port main links
4455a2f6b69e drm/i915: Don't enable the AUX_IO power for combo-PHY external DP port main links
be160a165b83 drm/i915: Factor out function to get/put AUX_IO power for main link
9abec186cddb drm/i915: Add missing DC_OFF power domain->well mappings
920505a51861 drm/i915: Add missing AUX_IO_A power domain->well mappings
5ba382d6ecab drm/i915/tgl+: Enable display DC power states on all eDP ports
8616f4b4a644 drm/i915: Use the AUX_IO power domain only for eDP/PSR port
d6b2d5b19e36 drm/i915: Move the POWER_DOMAIN_AUX_IO_A definition to its logical place
e900f09a6ddc drm/i915: Allocate power domain set wakerefs dynamically

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/index.html

[-- Attachment #2: Type: text/html, Size: 7314 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Enable DC power states on all eDP ports (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 34315 bytes --]

== Series Details ==

Series: drm/i915/tgl+: Enable DC power states on all eDP ports (rev2)
URL   : https://patchwork.freedesktop.org/series/110433/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12353_full -> Patchwork_110433v2_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_110433v2_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110433v2_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_110433v2_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][1] -> [DMESG-WARN][2] +20 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-iclb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-skl:          NOTRUN -> [DMESG-WARN][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
    - shard-skl:          [PASS][4] -> [DMESG-WARN][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu:
    - shard-tglb:         [PASS][6] -> [DMESG-WARN][7] +12 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-tglb6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb5/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-slowdraw:
    - shard-iclb:         [PASS][8] -> [INCOMPLETE][9] +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-iclb6/igt@kms_frontbuffer_tracking@psr-slowdraw.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb2/igt@kms_frontbuffer_tracking@psr-slowdraw.html
    - shard-tglb:         [PASS][10] -> [INCOMPLETE][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-tglb2/igt@kms_frontbuffer_tracking@psr-slowdraw.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb5/igt@kms_frontbuffer_tracking@psr-slowdraw.html

  
Known issues
------------

  Here are the changes found in Patchwork_110433v2_full that come from known issues:

### CI changes ###

#### Possible fixes ####

  * boot:
    - shard-glk:          ([PASS][12], [PASS][13], [PASS][14], [PASS][15], [FAIL][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35]) ([i915#4392]) -> ([PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk1/boot.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk1/boot.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk1/boot.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk2/boot.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk2/boot.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk2/boot.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk2/boot.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk3/boot.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk3/boot.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk3/boot.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk5/boot.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk5/boot.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk5/boot.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk6/boot.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk6/boot.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk7/boot.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk7/boot.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk7/boot.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk8/boot.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk8/boot.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk8/boot.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk9/boot.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk9/boot.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk9/boot.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk1/boot.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk1/boot.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk2/boot.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk2/boot.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk2/boot.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk3/boot.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk3/boot.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk3/boot.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk5/boot.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk5/boot.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk5/boot.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk6/boot.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk6/boot.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk6/boot.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk6/boot.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk7/boot.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk7/boot.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk7/boot.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk8/boot.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk8/boot.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk8/boot.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk9/boot.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk9/boot.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk9/boot.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk9/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [PASS][61] -> [SKIP][62] ([i915#658])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-iclb2/igt@feature_discovery@psr2.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb3/igt@feature_discovery@psr2.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][63] -> [FAIL][64] ([i915#2842])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_lmem_swapping@basic:
    - shard-glk:          NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#4613])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk2/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-apl:          NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#4613])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-apl2/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-skl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#4613])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl6/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-glk:          NOTRUN -> [INCOMPLETE][68] ([i915#7248])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk7/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-apl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#3323])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-apl2/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [PASS][70] -> [DMESG-WARN][71] ([i915#5566] / [i915#716])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-apl7/igt@gen9_exec_parse@allowed-all.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-apl1/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_sseu@full-enable:
    - shard-skl:          [PASS][72] -> [FAIL][73] ([i915#6991])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-skl3/igt@i915_pm_sseu@full-enable.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl1/igt@i915_pm_sseu@full-enable.html

  * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#3886]) +5 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk2/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3886]) +1 similar issue
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl6/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#3886]) +2 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-apl2/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_chamelium@hdmi-hpd:
    - shard-apl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [fdo#111827])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-apl2/igt@kms_chamelium@hdmi-hpd.html

  * igt@kms_color_chamelium@ctm-limited-range:
    - shard-skl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl6/igt@kms_color_chamelium@ctm-limited-range.html

  * igt@kms_color_chamelium@ctm-red-to-blue:
    - shard-glk:          NOTRUN -> [SKIP][79] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk2/igt@kms_color_chamelium@ctm-red-to-blue.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1:
    - shard-skl:          [PASS][80] -> [INCOMPLETE][81] ([i915#6951])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-skl10/igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl3/igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1.html

  * igt@kms_flip@flip-vs-suspend@a-edp1:
    - shard-tglb:         [PASS][82] -> [INCOMPLETE][83] ([i915#2411])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-tglb5/igt@kms_flip@flip-vs-suspend@a-edp1.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb5/igt@kms_flip@flip-vs-suspend@a-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
    - shard-skl:          [PASS][84] -> [FAIL][85] ([i915#2122])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a2:
    - shard-glk:          [PASS][86] -> [FAIL][87] ([i915#2122])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk7/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a2.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk6/igt@kms_flip@plain-flip-ts-check-interruptible@a-hdmi-a2.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-tglb:         [PASS][88] -> [DMESG-WARN][89] ([i915#1982]) +9 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt:
    - shard-glk:          NOTRUN -> [SKIP][90] ([fdo#109271]) +80 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-iclb:         [PASS][91] -> [DMESG-WARN][92] ([i915#1982]) +1 similar issue
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-iclb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-skl:          [PASS][93] -> [DMESG-WARN][94] ([i915#1982]) +17 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-slowdraw:
    - shard-skl:          [PASS][95] -> [INCOMPLETE][96] ([i915#1982])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-skl7/igt@kms_frontbuffer_tracking@psr-slowdraw.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl6/igt@kms_frontbuffer_tracking@psr-slowdraw.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
    - shard-apl:          [PASS][97] -> [FAIL][98] ([i915#1188])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-apl7/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-apl1/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html

  * igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][99] ([i915#4573]) +2 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk7/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-edp-1:
    - shard-skl:          NOTRUN -> [SKIP][100] ([fdo#109271]) +37 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-edp-1.html

  * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-dp-1:
    - shard-apl:          NOTRUN -> [SKIP][101] ([fdo#109271]) +68 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-apl2/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-dp-1.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
    - shard-apl:          NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#658])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-apl7/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-glk:          NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#658])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk7/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][104] -> [SKIP][105] ([fdo#109441])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb3/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-apl:          [PASS][106] -> [DMESG-WARN][107] ([i915#180]) +4 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-apl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-apl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html

  * igt@sysfs_clients@sema-25:
    - shard-skl:          NOTRUN -> [SKIP][108] ([fdo#109271] / [i915#2994])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl6/igt@sysfs_clients@sema-25.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - shard-apl:          [DMESG-WARN][109] ([i915#180]) -> [PASS][110] +1 similar issue
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-apl8/igt@gem_ctx_isolation@preservation-s3@vcs0.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-apl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-glk:          [FAIL][111] ([i915#2842]) -> [PASS][112] +1 similar issue
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk3/igt@gem_exec_fair@basic-none@vecs0.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk6/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_reloc@basic-gtt-wc-noreloc:
    - shard-skl:          [DMESG-WARN][113] ([i915#1982]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-skl10/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl3/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-apl:          [DMESG-WARN][115] ([i915#5566] / [i915#716]) -> [PASS][116]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-apl1/igt@gen9_exec_parse@allowed-single.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-apl1/igt@gen9_exec_parse@allowed-single.html
    - shard-glk:          [DMESG-WARN][117] ([i915#5566] / [i915#716]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk7/igt@gen9_exec_parse@allowed-single.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk3/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [FAIL][119] ([i915#3989] / [i915#454]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_sseu@full-enable:
    - shard-glk:          [FAIL][121] ([i915#3524]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk1/igt@i915_pm_sseu@full-enable.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk2/igt@i915_pm_sseu@full-enable.html

  * igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait@pipe-a-hdmi-a-1:
    - shard-glk:          [DMESG-WARN][123] ([i915#118]) -> [PASS][124] +1 similar issue
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk2/igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait@pipe-a-hdmi-a-1.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk5/igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait@pipe-a-hdmi-a-1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
    - shard-glk:          [FAIL][125] ([i915#79]) -> [PASS][126]
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html

  
#### Warnings ####

  * igt@runner@aborted:
    - shard-tglb:         ([FAIL][127], [FAIL][128]) ([i915#3002] / [i915#4312]) -> ([FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152]) ([i915#4312])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-tglb2/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-tglb8/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb3/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb8/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb7/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb6/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb6/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb3/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb8/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb3/igt@runner@aborted.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb2/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb7/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb5/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb6/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb6/igt@runner@aborted.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb7/igt@runner@aborted.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb3/igt@runner@aborted.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb8/igt@runner@aborted.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb8/igt@runner@aborted.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb5/igt@runner@aborted.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb6/igt@runner@aborted.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb5/igt@runner@aborted.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb5/igt@runner@aborted.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb7/igt@runner@aborted.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb2/igt@runner@aborted.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-tglb2/igt@runner@aborted.html
    - shard-skl:          ([FAIL][153], [FAIL][154], [FAIL][155]) ([i915#3002] / [i915#4312] / [i915#6949]) -> ([FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161], [FAIL][162], [FAIL][163], [FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170], [FAIL][171], [FAIL][172], [FAIL][173], [FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177]) ([i915#3002] / [i915#4312])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-skl10/igt@runner@aborted.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-skl6/igt@runner@aborted.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-skl7/igt@runner@aborted.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl10/igt@runner@aborted.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl10/igt@runner@aborted.html
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl1/igt@runner@aborted.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl1/igt@runner@aborted.html
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl1/igt@runner@aborted.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl10/igt@runner@aborted.html
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl9/igt@runner@aborted.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl6/igt@runner@aborted.html
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl6/igt@runner@aborted.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl9/igt@runner@aborted.html
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl6/igt@runner@aborted.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl3/igt@runner@aborted.html
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl3/igt@runner@aborted.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl1/igt@runner@aborted.html
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl6/igt@runner@aborted.html
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl9/igt@runner@aborted.html
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl4/igt@runner@aborted.html
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl4/igt@runner@aborted.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl7/igt@runner@aborted.html
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl9/igt@runner@aborted.html
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl7/igt@runner@aborted.html
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-skl7/igt@runner@aborted.html
    - shard-iclb:         ([FAIL][178], [FAIL][179]) ([i915#3002] / [i915#4312]) -> ([FAIL][180], [FAIL][181], [FAIL][182], [FAIL][183], [FAIL][184], [FAIL][185], [FAIL][186], [FAIL][187], [FAIL][188], [FAIL][189], [FAIL][190], [FAIL][191], [FAIL][192], [FAIL][193], [FAIL][194], [FAIL][195], [FAIL][196], [FAIL][197], [FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202], [FAIL][203], [FAIL][204]) ([i915#4312])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-iclb2/igt@runner@aborted.html
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12353/shard-iclb6/igt@runner@aborted.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb3/igt@runner@aborted.html
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb7/igt@runner@aborted.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb2/igt@runner@aborted.html
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb5/igt@runner@aborted.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb3/igt@runner@aborted.html
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb7/igt@runner@aborted.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb5/igt@runner@aborted.html
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb1/igt@runner@aborted.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb8/igt@runner@aborted.html
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb5/igt@runner@aborted.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb1/igt@runner@aborted.html
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb8/igt@runner@aborted.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb6/igt@runner@aborted.html
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb5/igt@runner@aborted.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb2/igt@runner@aborted.html
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb6/igt@runner@aborted.html
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb2/igt@runner@aborted.html
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb3/igt@runner@aborted.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb7/igt@runner@aborted.html
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb8/igt@runner@aborted.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb3/igt@runner@aborted.html
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb2/igt@runner@aborted.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb6/igt@runner@aborted.html
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb1/igt@runner@aborted.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/shard-iclb8/igt@runner@aborted.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3524]: https://gitlab.freedesktop.org/drm/intel/issues/3524
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6949]: https://gitlab.freedesktop.org/drm/intel/issues/6949
  [i915#6951]: https://gitlab.freedesktop.org/drm/intel/issues/6951
  [i915#6991]: https://gitlab.freedesktop.org/drm/intel/issues/6991
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * Linux: CI_DRM_12353 -> Patchwork_110433v2

  CI-20190529: 20190529
  CI_DRM_12353: fb2b3ddb471df2f8d305b1bb7f3705e7e0fbf6e4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7046: c58d96d0fe237474b074e3472ce09c57c830d5de @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110433v2: fb2b3ddb471df2f8d305b1bb7f3705e7e0fbf6e4 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v2/index.html

[-- Attachment #2: Type: text/html, Size: 39033 bytes --]

Re: [Intel-gfx] [PATCH v2 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Jani Nikula]

On Mon, 07 Nov 2022, Imre Deak <imre.deak@intel.com> wrote:
> Since the intel_display_power_domain_set struct, currently its current
> size close 1kB, can be allocated on the stack, it's better to allocate
> the per-domain wakeref pointer array - used for debugging - within the
> struct dynamically, so do this.
>
> The memory freeing is guaranteed by the fact that the acquired domain
> references tracked by struct can't be leaked either.
>
> v2:
> - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> - Simplify intel_display_power_get/put_in_set(). (Jani)
> - Check in intel_crtc_destroy() that the wakerefs array has been freed.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crtc.c     |  4 +
>  .../drm/i915/display/intel_display_power.c    | 95 +++++++++++++++----
>  .../drm/i915/display/intel_display_power.h    |  2 +-
>  3 files changed, 79 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 037fc140b585c..2c8d564e73182 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -205,6 +205,10 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
>  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
>  
>  	drm_crtc_cleanup(&crtc->base);
> +
> +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> +	drm_WARN_ON(crtc->base.dev, crtc->enabled_power_domains.wakerefs);
> +#endif

Can we please not add this kind of asserts without abstractions? The
#ifdef is ugly, looking at crtc->enabled_power_domains.wakerefs directly
is ugly.

Maybe add an assert_something_or_other(crtc) that does the right thing?
Similar to the other assert_*() functions we have?

Does it even need to depend on the config? If it's worth having, maybe
worth having unconditionally?

BR,
Jani.

>  	kfree(crtc);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 4c1de91e56ff9..db235b79c9629 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
>  }
>  #endif
>  
> +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> +static void
> +add_domain_to_set(struct drm_i915_private *i915,
> +		  struct intel_display_power_domain_set *power_domain_set,
> +		  enum intel_display_power_domain domain,
> +		  intel_wakeref_t wf)
> +{
> +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> +
> +	if (!power_domain_set->wakerefs)
> +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> +						     sizeof(*power_domain_set->wakerefs),
> +						     GFP_KERNEL);
> +
> +	if (power_domain_set->wakerefs)
> +		power_domain_set->wakerefs[domain] = wf;
> +
> +	set_bit(domain, power_domain_set->mask.bits);
> +}
> +
> +static intel_wakeref_t
> +remove_domain_from_set(struct drm_i915_private *i915,
> +		       struct intel_display_power_domain_set *power_domain_set,
> +		       enum intel_display_power_domain domain)
> +{
> +	intel_wakeref_t wf;
> +
> +	drm_WARN_ON(&i915->drm, !test_bit(domain, power_domain_set->mask.bits));
> +
> +	clear_bit(domain, power_domain_set->mask.bits);
> +
> +	if (!power_domain_set->wakerefs)
> +		return -1;
> +
> +	wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
> +
> +	if (bitmap_empty(power_domain_set->mask.bits, POWER_DOMAIN_NUM)) {
> +		kfree(power_domain_set->wakerefs);
> +		power_domain_set->wakerefs = NULL;
> +	}
> +
> +	return wf;
> +
> +}
> +#else
> +static void
> +add_domain_to_set(struct drm_i915_private *i915,
> +		  struct intel_display_power_domain_set *power_domain_set,
> +		  enum intel_display_power_domain domain,
> +		  intel_wakeref_t wf)
> +{
> +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> +
> +	set_bit(domain, power_domain_set->mask.bits);
> +}
> +
> +static intel_wakeref_t
> +remove_domain_from_set(struct drm_i915_private *i915,
> +		       struct intel_display_power_domain_set *power_domain_set,
> +		       enum intel_display_power_domain domain)
> +{
> +	drm_WARN_ON(&i915->drm, !test_bit(domain, power_domain_set->mask.bits));
> +
> +	clear_bit(domain, power_domain_set->mask.bits);
> +
> +	return -1;
> +}
> +#endif
> +
>  void
>  intel_display_power_get_in_set(struct drm_i915_private *i915,
>  			       struct intel_display_power_domain_set *power_domain_set,
>  			       enum intel_display_power_domain domain)
>  {
> -	intel_wakeref_t __maybe_unused wf;
> -
> -	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> +	intel_wakeref_t wf;
>  
>  	wf = intel_display_power_get(i915, domain);
> -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> -	power_domain_set->wakerefs[domain] = wf;
> -#endif
> -	set_bit(domain, power_domain_set->mask.bits);
> +
> +	add_domain_to_set(i915, power_domain_set, domain, wf);
>  }
>  
>  bool
> @@ -853,16 +918,11 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
>  {
>  	intel_wakeref_t wf;
>  
> -	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> -
>  	wf = intel_display_power_get_if_enabled(i915, domain);
>  	if (!wf)
>  		return false;
>  
> -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> -	power_domain_set->wakerefs[domain] = wf;
> -#endif
> -	set_bit(domain, power_domain_set->mask.bits);
> +	add_domain_to_set(i915, power_domain_set, domain, wf);
>  
>  	return true;
>  }
> @@ -874,17 +934,10 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
>  {
>  	enum intel_display_power_domain domain;
>  
> -	drm_WARN_ON(&i915->drm,
> -		    !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
> -
>  	for_each_power_domain(domain, mask) {
> -		intel_wakeref_t __maybe_unused wf = -1;
> +		intel_wakeref_t wf = remove_domain_from_set(i915, power_domain_set, domain);
>  
> -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> -		wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
> -#endif
>  		intel_display_power_put(i915, domain, wf);
> -		clear_bit(domain, power_domain_set->mask.bits);
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 1e77e52c87fec..662123d260a7a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -147,7 +147,7 @@ struct i915_power_domains {
>  struct intel_display_power_domain_set {
>  	struct intel_power_domain_mask mask;
>  #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
> -	intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
> +	intel_wakeref_t *wakerefs;
>  #endif
>  };

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Imre Deak]

On Tue, Nov 08, 2022 at 10:54:21AM +0200, Jani Nikula wrote:
> On Mon, 07 Nov 2022, Imre Deak <imre.deak@intel.com> wrote:
> > Since the intel_display_power_domain_set struct, currently its current
> > size close 1kB, can be allocated on the stack, it's better to allocate
> > the per-domain wakeref pointer array - used for debugging - within the
> > struct dynamically, so do this.
> >
> > The memory freeing is guaranteed by the fact that the acquired domain
> > references tracked by struct can't be leaked either.
> >
> > v2:
> > - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> > - Simplify intel_display_power_get/put_in_set(). (Jani)
> > - Check in intel_crtc_destroy() that the wakerefs array has been freed.
> >
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_crtc.c     |  4 +
> >  .../drm/i915/display/intel_display_power.c    | 95 +++++++++++++++----
> >  .../drm/i915/display/intel_display_power.h    |  2 +-
> >  3 files changed, 79 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index 037fc140b585c..2c8d564e73182 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -205,6 +205,10 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
> >  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
> >  
> >  	drm_crtc_cleanup(&crtc->base);
> > +
> > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > +	drm_WARN_ON(crtc->base.dev, crtc->enabled_power_domains.wakerefs);
> > +#endif
> 
> Can we please not add this kind of asserts without abstractions? The
> #ifdef is ugly, looking at crtc->enabled_power_domains.wakerefs directly
> is ugly.
>
> Maybe add an assert_something_or_other(crtc) that does the right thing?
> Similar to the other assert_*() functions we have?

Yes, can add assert_power_domains_disabled(crtc) to this file.

> Does it even need to depend on the config? If it's worth having, maybe
> worth having unconditionally?

The wakerefs array exists only when the config is enabled, but the
non-debug crtc->enabled_power_domains.mask should be checked as well.

> BR,
> Jani.
> 
> >  	kfree(crtc);
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 4c1de91e56ff9..db235b79c9629 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
> >  }
> >  #endif
> >  
> > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > +static void
> > +add_domain_to_set(struct drm_i915_private *i915,
> > +		  struct intel_display_power_domain_set *power_domain_set,
> > +		  enum intel_display_power_domain domain,
> > +		  intel_wakeref_t wf)
> > +{
> > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > +
> > +	if (!power_domain_set->wakerefs)
> > +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> > +						     sizeof(*power_domain_set->wakerefs),
> > +						     GFP_KERNEL);
> > +
> > +	if (power_domain_set->wakerefs)
> > +		power_domain_set->wakerefs[domain] = wf;
> > +
> > +	set_bit(domain, power_domain_set->mask.bits);
> > +}
> > +
> > +static intel_wakeref_t
> > +remove_domain_from_set(struct drm_i915_private *i915,
> > +		       struct intel_display_power_domain_set *power_domain_set,
> > +		       enum intel_display_power_domain domain)
> > +{
> > +	intel_wakeref_t wf;
> > +
> > +	drm_WARN_ON(&i915->drm, !test_bit(domain, power_domain_set->mask.bits));
> > +
> > +	clear_bit(domain, power_domain_set->mask.bits);
> > +
> > +	if (!power_domain_set->wakerefs)
> > +		return -1;
> > +
> > +	wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
> > +
> > +	if (bitmap_empty(power_domain_set->mask.bits, POWER_DOMAIN_NUM)) {
> > +		kfree(power_domain_set->wakerefs);
> > +		power_domain_set->wakerefs = NULL;
> > +	}
> > +
> > +	return wf;
> > +
> > +}
> > +#else
> > +static void
> > +add_domain_to_set(struct drm_i915_private *i915,
> > +		  struct intel_display_power_domain_set *power_domain_set,
> > +		  enum intel_display_power_domain domain,
> > +		  intel_wakeref_t wf)
> > +{
> > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > +
> > +	set_bit(domain, power_domain_set->mask.bits);
> > +}
> > +
> > +static intel_wakeref_t
> > +remove_domain_from_set(struct drm_i915_private *i915,
> > +		       struct intel_display_power_domain_set *power_domain_set,
> > +		       enum intel_display_power_domain domain)
> > +{
> > +	drm_WARN_ON(&i915->drm, !test_bit(domain, power_domain_set->mask.bits));
> > +
> > +	clear_bit(domain, power_domain_set->mask.bits);
> > +
> > +	return -1;
> > +}
> > +#endif
> > +
> >  void
> >  intel_display_power_get_in_set(struct drm_i915_private *i915,
> >  			       struct intel_display_power_domain_set *power_domain_set,
> >  			       enum intel_display_power_domain domain)
> >  {
> > -	intel_wakeref_t __maybe_unused wf;
> > -
> > -	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > +	intel_wakeref_t wf;
> >  
> >  	wf = intel_display_power_get(i915, domain);
> > -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > -	power_domain_set->wakerefs[domain] = wf;
> > -#endif
> > -	set_bit(domain, power_domain_set->mask.bits);
> > +
> > +	add_domain_to_set(i915, power_domain_set, domain, wf);
> >  }
> >  
> >  bool
> > @@ -853,16 +918,11 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
> >  {
> >  	intel_wakeref_t wf;
> >  
> > -	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > -
> >  	wf = intel_display_power_get_if_enabled(i915, domain);
> >  	if (!wf)
> >  		return false;
> >  
> > -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > -	power_domain_set->wakerefs[domain] = wf;
> > -#endif
> > -	set_bit(domain, power_domain_set->mask.bits);
> > +	add_domain_to_set(i915, power_domain_set, domain, wf);
> >  
> >  	return true;
> >  }
> > @@ -874,17 +934,10 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> >  {
> >  	enum intel_display_power_domain domain;
> >  
> > -	drm_WARN_ON(&i915->drm,
> > -		    !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
> > -
> >  	for_each_power_domain(domain, mask) {
> > -		intel_wakeref_t __maybe_unused wf = -1;
> > +		intel_wakeref_t wf = remove_domain_from_set(i915, power_domain_set, domain);
> >  
> > -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > -		wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
> > -#endif
> >  		intel_display_power_put(i915, domain, wf);
> > -		clear_bit(domain, power_domain_set->mask.bits);
> >  	}
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> > index 1e77e52c87fec..662123d260a7a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > @@ -147,7 +147,7 @@ struct i915_power_domains {
> >  struct intel_display_power_domain_set {
> >  	struct intel_power_domain_mask mask;
> >  #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
> > -	intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
> > +	intel_wakeref_t *wakerefs;
> >  #endif
> >  };
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH v3 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Imre Deak]

Since the intel_display_power_domain_set struct, currently its current
size close to 1kB, can be allocated on the stack, it's better to
allocate the per-domain wakeref pointer array - used for debugging -
within the struct dynamically, so do this.

The memory freeing is guaranteed by the fact that the acquired domain
references tracked by the struct can't be leaked either.

v2:
- Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
- Simplify intel_display_power_get/put_in_set(). (Jani)
- Check in intel_crtc_destroy() that the wakerefs array has been freed.
v3:
- Add intel_display_power_set_disabled() and a separate assert
  function instead of open coding these. (Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc.c     |  11 ++
 .../drm/i915/display/intel_display_power.c    | 109 ++++++++++++++----
 .../drm/i915/display/intel_display_power.h    |   6 +-
 3 files changed, 104 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 037fc140b585c..c18d98bfe1a7c 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -21,6 +21,7 @@
 #include "intel_crtc.h"
 #include "intel_cursor.h"
 #include "intel_display_debugfs.h"
+#include "intel_display_power.h"
 #include "intel_display_trace.h"
 #include "intel_display_types.h"
 #include "intel_drrs.h"
@@ -37,6 +38,14 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
 		drm_crtc_vblank_put(crtc);
 }
 
+static void assert_power_domains_disabled(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+	drm_WARN_ON(&i915->drm,
+		    !intel_display_power_set_disabled(i915, &crtc->enabled_power_domains));
+}
+
 struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
 {
 	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
@@ -204,6 +213,8 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
 
 	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
 
+	assert_power_domains_disabled(crtc);
+
 	drm_crtc_cleanup(&crtc->base);
 	kfree(crtc);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4c1de91e56ff9..ca63b4f1af41b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
 }
 #endif
 
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
+static void
+add_domain_to_set(struct drm_i915_private *i915,
+		  struct intel_display_power_domain_set *power_domain_set,
+		  enum intel_display_power_domain domain,
+		  intel_wakeref_t wf)
+{
+	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
+
+	if (!power_domain_set->wakerefs)
+		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
+						     sizeof(*power_domain_set->wakerefs),
+						     GFP_KERNEL);
+
+	if (power_domain_set->wakerefs)
+		power_domain_set->wakerefs[domain] = wf;
+
+	set_bit(domain, power_domain_set->mask.bits);
+}
+
+static intel_wakeref_t
+remove_domain_from_set(struct drm_i915_private *i915,
+		       struct intel_display_power_domain_set *power_domain_set,
+		       enum intel_display_power_domain domain)
+{
+	intel_wakeref_t wf;
+
+	drm_WARN_ON(&i915->drm, !test_bit(domain, power_domain_set->mask.bits));
+
+	clear_bit(domain, power_domain_set->mask.bits);
+
+	if (!power_domain_set->wakerefs)
+		return -1;
+
+	wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
+
+	if (bitmap_empty(power_domain_set->mask.bits, POWER_DOMAIN_NUM)) {
+		kfree(power_domain_set->wakerefs);
+		power_domain_set->wakerefs = NULL;
+	}
+
+	return wf;
+
+}
+#else
+static void
+add_domain_to_set(struct drm_i915_private *i915,
+		  struct intel_display_power_domain_set *power_domain_set,
+		  enum intel_display_power_domain domain,
+		  intel_wakeref_t wf)
+{
+	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
+
+	set_bit(domain, power_domain_set->mask.bits);
+}
+
+static intel_wakeref_t
+remove_domain_from_set(struct drm_i915_private *i915,
+		       struct intel_display_power_domain_set *power_domain_set,
+		       enum intel_display_power_domain domain)
+{
+	drm_WARN_ON(&i915->drm, !test_bit(domain, power_domain_set->mask.bits));
+
+	clear_bit(domain, power_domain_set->mask.bits);
+
+	return -1;
+}
+#endif
+
 void
 intel_display_power_get_in_set(struct drm_i915_private *i915,
 			       struct intel_display_power_domain_set *power_domain_set,
 			       enum intel_display_power_domain domain)
 {
-	intel_wakeref_t __maybe_unused wf;
-
-	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
+	intel_wakeref_t wf;
 
 	wf = intel_display_power_get(i915, domain);
-#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-	power_domain_set->wakerefs[domain] = wf;
-#endif
-	set_bit(domain, power_domain_set->mask.bits);
+
+	add_domain_to_set(i915, power_domain_set, domain, wf);
 }
 
 bool
@@ -853,16 +918,11 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
 {
 	intel_wakeref_t wf;
 
-	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
-
 	wf = intel_display_power_get_if_enabled(i915, domain);
 	if (!wf)
 		return false;
 
-#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-	power_domain_set->wakerefs[domain] = wf;
-#endif
-	set_bit(domain, power_domain_set->mask.bits);
+	add_domain_to_set(i915, power_domain_set, domain, wf);
 
 	return true;
 }
@@ -874,20 +934,27 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
 {
 	enum intel_display_power_domain domain;
 
-	drm_WARN_ON(&i915->drm,
-		    !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
-
 	for_each_power_domain(domain, mask) {
-		intel_wakeref_t __maybe_unused wf = -1;
+		intel_wakeref_t wf = remove_domain_from_set(i915, power_domain_set, domain);
 
-#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-		wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
-#endif
 		intel_display_power_put(i915, domain, wf);
-		clear_bit(domain, power_domain_set->mask.bits);
 	}
 }
 
+bool
+intel_display_power_set_disabled(struct drm_i915_private *i915,
+				 struct intel_display_power_domain_set *power_domain_set)
+{
+	if (!bitmap_empty(power_domain_set->mask.bits, POWER_DOMAIN_NUM))
+		return false;
+
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
+	drm_WARN_ON(&i915->drm, power_domain_set->wakerefs);
+#endif
+
+	return true;
+}
+
 static int
 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
 				   int disable_power_well)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 1e77e52c87fec..31b0e9ae863c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -147,7 +147,7 @@ struct i915_power_domains {
 struct intel_display_power_domain_set {
 	struct intel_power_domain_mask mask;
 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
-	intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
+	intel_wakeref_t *wakerefs;
 #endif
 };
 
@@ -243,6 +243,10 @@ intel_display_power_put_all_in_set(struct drm_i915_private *i915,
 	intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
 }
 
+bool
+intel_display_power_set_disabled(struct drm_i915_private *i915,
+				 struct intel_display_power_domain_set *power_domain_set);
+
 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
 
 enum intel_display_power_domain
-- 
2.37.1

[Intel-gfx] [PATCH v3 3/9] drm/i915: Use the AUX_IO power domain only for eDP/PSR port

[Imre Deak]

Use the AUX_IO_A display power domain only for eDP on port A where PSR
is also supported. This is the case where DC states need to be enabled
while the output is enabled - ensured by AUX_IO_A domain not enabling
the DC_OFF power well. Otherwise port A can be treated the same way as
other ports with an external DP output: using the AUX_<port> domain
which disables the unrequired DC states.

This change prepares for the next patch enabling DC states on all ports
supporting eDP/PSR besides port A.

v2:
- Check the encoder PSR capability instead of PSR being enabled in the
  crtc_state, as the latter can be changed with a fastset.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e95bde5cf060e..ca236cd7f9b76 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -860,8 +860,10 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 	 * Note that PSR is enabled only on Port A even though this function
 	 * returns the correct domain for other ports too.
 	 */
-	return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
-					      intel_aux_power_domain(dig_port);
+	if (dig_port->aux_ch == AUX_CH_A && intel_encoder_can_psr(&dig_port->base))
+		return POWER_DOMAIN_AUX_IO_A;
+	else
+		return intel_aux_power_domain(dig_port);
 }
 
 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
-- 
2.37.1

[Intel-gfx] [PATCH v3 4/9] drm/i915/tgl+: Enable display DC power states on all eDP ports

[Imre Deak]

Starting with TGL eDP is supported on ports B+ (besides port A), so make
sure DC states are not blocked on any such ports. For this add an
AUX_IO_<port> power domain for each port with eDP support. These domains
similarly to AUX_IO_A enable only the AUX_IO_<port> power well for an
enabled port, whereas the existing AUX_<port> domains enable both the
AUX_IO_<port> and the DC_OFF power wells as required by DP AUX transfers.

v2: (Ville)
- Split the change using AUX vs. AUX_IO on port A to a separate patch.
- Select AUX_IO vs. AUX based on crtc_state->has_psr instead of
  is_edp().
v3:
- Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  6 ++-
 .../drm/i915/display/intel_display_power.c    | 30 +++++++++++
 .../drm/i915/display/intel_display_power.h    |  7 +++
 .../i915/display/intel_display_power_map.c    | 53 +++++++++++++++++--
 4 files changed, 89 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ca236cd7f9b76..a087609223c60 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -848,6 +848,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 static enum intel_display_power_domain
 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 {
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
 	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 	 * DC states enabled at the same time, while for driver initiated AUX
 	 * transfers we need the same AUX IOs to be powered but with DC states
@@ -860,8 +862,8 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 	 * Note that PSR is enabled only on Port A even though this function
 	 * returns the correct domain for other ports too.
 	 */
-	if (dig_port->aux_ch == AUX_CH_A && intel_encoder_can_psr(&dig_port->base))
-		return POWER_DOMAIN_AUX_IO_A;
+	if (intel_encoder_can_psr(&dig_port->base))
+		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
 	else
 		return intel_aux_power_domain(dig_port);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 78f1749397e1d..61c6a3616db08 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -131,6 +131,16 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "AUDIO_PLAYBACK";
 	case POWER_DOMAIN_AUX_IO_A:
 		return "AUX_IO_A";
+	case POWER_DOMAIN_AUX_IO_B:
+		return "AUX_IO_B";
+	case POWER_DOMAIN_AUX_IO_C:
+		return "AUX_IO_C";
+	case POWER_DOMAIN_AUX_IO_D:
+		return "AUX_IO_D";
+	case POWER_DOMAIN_AUX_IO_E:
+		return "AUX_IO_E";
+	case POWER_DOMAIN_AUX_IO_F:
+		return "AUX_IO_F";
 	case POWER_DOMAIN_AUX_A:
 		return "AUX_A";
 	case POWER_DOMAIN_AUX_B:
@@ -2356,6 +2366,7 @@ struct intel_ddi_port_domains {
 
 	enum intel_display_power_domain ddi_lanes;
 	enum intel_display_power_domain ddi_io;
+	enum intel_display_power_domain aux_io;
 	enum intel_display_power_domain aux_legacy_usbc;
 	enum intel_display_power_domain aux_tbt;
 };
@@ -2370,6 +2381,7 @@ i9xx_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+		.aux_io = POWER_DOMAIN_AUX_IO_A,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
 		.aux_tbt = POWER_DOMAIN_INVALID,
 	},
@@ -2385,6 +2397,7 @@ d11_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+		.aux_io = POWER_DOMAIN_AUX_IO_A,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
 		.aux_tbt = POWER_DOMAIN_INVALID,
 	}, {
@@ -2395,6 +2408,7 @@ d11_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
+		.aux_io = POWER_DOMAIN_AUX_IO_C,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_C,
 		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
 	},
@@ -2410,6 +2424,7 @@ d12_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+		.aux_io = POWER_DOMAIN_AUX_IO_A,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
 		.aux_tbt = POWER_DOMAIN_INVALID,
 	}, {
@@ -2420,6 +2435,7 @@ d12_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
+		.aux_io = POWER_DOMAIN_INVALID,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
 		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
 	},
@@ -2435,6 +2451,7 @@ d13_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+		.aux_io = POWER_DOMAIN_AUX_IO_A,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
 		.aux_tbt = POWER_DOMAIN_INVALID,
 	}, {
@@ -2445,6 +2462,7 @@ d13_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
+		.aux_io = POWER_DOMAIN_INVALID,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
 		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
 	}, {
@@ -2455,6 +2473,7 @@ d13_port_domains[] = {
 
 		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
 		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
+		.aux_io = POWER_DOMAIN_AUX_IO_D,
 		.aux_legacy_usbc = POWER_DOMAIN_AUX_D,
 		.aux_tbt = POWER_DOMAIN_INVALID,
 	},
@@ -2532,6 +2551,17 @@ intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
 	return NULL;
 }
 
+enum intel_display_power_domain
+intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
+{
+	const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
+
+	if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_io == POWER_DOMAIN_INVALID)
+		return POWER_DOMAIN_AUX_IO_A;
+
+	return domains->aux_io + (int)(aux_ch - domains->aux_ch_start);
+}
+
 enum intel_display_power_domain
 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index dd0ad99f17056..73c7db969dde6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -79,6 +79,11 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_AUDIO_PLAYBACK,
 
 	POWER_DOMAIN_AUX_IO_A,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
+	POWER_DOMAIN_AUX_IO_D,
+	POWER_DOMAIN_AUX_IO_E,
+	POWER_DOMAIN_AUX_IO_F,
 
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
@@ -255,6 +260,8 @@ intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port po
 enum intel_display_power_domain
 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
 enum intel_display_power_domain
+intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
+enum intel_display_power_domain
 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
 enum intel_display_power_domain
 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 43454022e6a66..b82c0d0a80c5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -170,6 +170,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
 	POWER_DOMAIN_VGA,
 	POWER_DOMAIN_AUDIO_MMIO,
 	POWER_DOMAIN_AUDIO_PLAYBACK,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_GMBUS,
@@ -179,6 +181,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
 	POWER_DOMAIN_PORT_DDI_LANES_B,
 	POWER_DOMAIN_PORT_DDI_LANES_C,
 	POWER_DOMAIN_PORT_CRT,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_INIT);
@@ -186,6 +190,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
 	POWER_DOMAIN_PORT_DDI_LANES_B,
 	POWER_DOMAIN_PORT_DDI_LANES_C,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_INIT);
@@ -243,6 +249,9 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_display,
 	POWER_DOMAIN_VGA,
 	POWER_DOMAIN_AUDIO_MMIO,
 	POWER_DOMAIN_AUDIO_PLAYBACK,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
+	POWER_DOMAIN_AUX_IO_D,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_AUX_D,
@@ -252,12 +261,15 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_display,
 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
 	POWER_DOMAIN_PORT_DDI_LANES_B,
 	POWER_DOMAIN_PORT_DDI_LANES_C,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
 	POWER_DOMAIN_PORT_DDI_LANES_D,
+	POWER_DOMAIN_AUX_IO_D,
 	POWER_DOMAIN_AUX_D,
 	POWER_DOMAIN_INIT);
 
@@ -305,6 +317,9 @@ static const struct i915_power_well_desc_list chv_power_wells[] = {
 	POWER_DOMAIN_VGA, \
 	POWER_DOMAIN_AUDIO_MMIO, \
 	POWER_DOMAIN_AUDIO_PLAYBACK, \
+	POWER_DOMAIN_AUX_IO_B, \
+	POWER_DOMAIN_AUX_IO_C, \
+	POWER_DOMAIN_AUX_IO_D, \
 	POWER_DOMAIN_AUX_B, \
 	POWER_DOMAIN_AUX_C, \
 	POWER_DOMAIN_AUX_D
@@ -407,6 +422,8 @@ static const struct i915_power_well_desc_list skl_power_wells[] = {
 	POWER_DOMAIN_VGA, \
 	POWER_DOMAIN_AUDIO_MMIO, \
 	POWER_DOMAIN_AUDIO_PLAYBACK, \
+	POWER_DOMAIN_AUX_IO_B, \
+	POWER_DOMAIN_AUX_IO_C, \
 	POWER_DOMAIN_AUX_B, \
 	POWER_DOMAIN_AUX_C
 
@@ -430,6 +447,8 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
 	POWER_DOMAIN_PORT_DDI_LANES_B,
 	POWER_DOMAIN_PORT_DDI_LANES_C,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_INIT);
@@ -483,6 +502,8 @@ static const struct i915_power_well_desc_list bxt_power_wells[] = {
 	POWER_DOMAIN_VGA, \
 	POWER_DOMAIN_AUDIO_MMIO, \
 	POWER_DOMAIN_AUDIO_PLAYBACK, \
+	POWER_DOMAIN_AUX_IO_B, \
+	POWER_DOMAIN_AUX_IO_C, \
 	POWER_DOMAIN_AUX_B, \
 	POWER_DOMAIN_AUX_C
 
@@ -509,11 +530,13 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
 	POWER_DOMAIN_PORT_DDI_LANES_B,
+	POWER_DOMAIN_AUX_IO_B,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
 	POWER_DOMAIN_PORT_DDI_LANES_C,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_INIT);
 
@@ -523,10 +546,12 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
+	POWER_DOMAIN_AUX_IO_B,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_INIT);
 
 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
+	POWER_DOMAIN_AUX_IO_C,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_INIT);
 
@@ -617,6 +642,11 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
 	POWER_DOMAIN_VGA, \
 	POWER_DOMAIN_AUDIO_MMIO, \
 	POWER_DOMAIN_AUDIO_PLAYBACK, \
+	POWER_DOMAIN_AUX_IO_B, \
+	POWER_DOMAIN_AUX_IO_C, \
+	POWER_DOMAIN_AUX_IO_D, \
+	POWER_DOMAIN_AUX_IO_E, \
+	POWER_DOMAIN_AUX_IO_F, \
 	POWER_DOMAIN_AUX_B, \
 	POWER_DOMAIN_AUX_C, \
 	POWER_DOMAIN_AUX_D, \
@@ -660,11 +690,21 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f,	POWER_DOMAIN_PORT_DDI_IO_F);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
 	POWER_DOMAIN_AUX_IO_A,
 	POWER_DOMAIN_AUX_A);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,		POWER_DOMAIN_AUX_B);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,		POWER_DOMAIN_AUX_C);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,		POWER_DOMAIN_AUX_D);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,		POWER_DOMAIN_AUX_E);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,		POWER_DOMAIN_AUX_F);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,
+	POWER_DOMAIN_AUX_IO_B,
+	POWER_DOMAIN_AUX_B);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,
+	POWER_DOMAIN_AUX_IO_C,
+	POWER_DOMAIN_AUX_C);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,
+	POWER_DOMAIN_AUX_IO_D,
+	POWER_DOMAIN_AUX_D);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,
+	POWER_DOMAIN_AUX_IO_E,
+	POWER_DOMAIN_AUX_E);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,
+	POWER_DOMAIN_AUX_IO_F,
+	POWER_DOMAIN_AUX_F);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1,	POWER_DOMAIN_AUX_TBT1);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2,	POWER_DOMAIN_AUX_TBT2);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3,	POWER_DOMAIN_AUX_TBT3);
@@ -1215,6 +1255,9 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
 	POWER_DOMAIN_PORT_DDI_LANES_TC4, \
 	POWER_DOMAIN_VGA, \
 	POWER_DOMAIN_AUDIO_PLAYBACK, \
+	POWER_DOMAIN_AUX_IO_C, \
+	POWER_DOMAIN_AUX_IO_D, \
+	POWER_DOMAIN_AUX_IO_E, \
 	POWER_DOMAIN_AUX_C, \
 	POWER_DOMAIN_AUX_D, \
 	POWER_DOMAIN_AUX_E, \
-- 
2.37.1

[Intel-gfx] [PATCH v3 7/9] drm/i915: Factor out function to get/put AUX_IO power for main link

[Imre Deak]

Factor out functions to get/put the AUX_IO power domain for the main
link on DDI ports.

While at it clarify the corresponding code comment.

No functional change.

v2:
- s/(get/put)_aux_power_for_main_link/main_link_aux_power_domain_(get/put)
  (Jani)
- Clarify in the code comment that AUX_IO is needed only by TypeC besides
  eDP/PSR.
v3:
- Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 84 ++++++++++++++----------
 1 file changed, 51 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a087609223c60..21f1a68a57598 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -846,26 +846,63 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 }
 
 static enum intel_display_power_domain
-intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
+intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
+			       const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 
-	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
+	/*
+	 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 	 * DC states enabled at the same time, while for driver initiated AUX
 	 * transfers we need the same AUX IOs to be powered but with DC states
-	 * disabled. Accordingly use the AUX power domain here which leaves DC
-	 * states enabled.
-	 * However, for non-A AUX ports the corresponding non-EDP transcoders
-	 * would have already enabled power well 2 and DC_OFF. This means we can
-	 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
-	 * specific AUX_IO reference without powering up any extra wells.
-	 * Note that PSR is enabled only on Port A even though this function
-	 * returns the correct domain for other ports too.
+	 * disabled. Accordingly use the AUX_IO_<port> power domain here which
+	 * leaves DC states enabled.
+	 *
+	 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
+	 * AUX IO to be enabled, but all these require DC_OFF to be enabled as
+	 * well, so we can acquire a wider AUX_<port> power domain reference
+	 * instead of a specific AUX_IO_<port> reference without powering up any
+	 * extra wells.
 	 */
 	if (intel_encoder_can_psr(&dig_port->base))
 		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
-	else
+	else if (intel_crtc_has_dp_encoder(crtc_state) ||
+		 intel_phy_is_tc(i915, phy))
 		return intel_aux_power_domain(dig_port);
+	else
+		return POWER_DOMAIN_INVALID;
+}
+
+static void
+main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
+			       const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum intel_display_power_domain domain =
+		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
+
+	drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
+
+	if (domain == POWER_DOMAIN_INVALID)
+		return;
+
+	dig_port->aux_wakeref = intel_display_power_get(i915, domain);
+}
+
+static void
+main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
+			       const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	intel_wakeref_t wf = fetch_and_zero(&dig_port->aux_wakeref);
+	enum intel_display_power_domain domain =
+		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
+
+	if (!wf)
+		return;
+
+	intel_display_power_put(i915, domain, wf);
 }
 
 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
@@ -873,7 +910,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port;
-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	/*
 	 * TODO: Add support for MST encoders. Atm, the following should never
@@ -892,17 +928,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 								   dig_port->ddi_io_power_domain);
 	}
 
-	/*
-	 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
-	 * ports.
-	 */
-	if (intel_crtc_has_dp_encoder(crtc_state) ||
-	    intel_phy_is_tc(dev_priv, phy)) {
-		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
-		dig_port->aux_wakeref =
-			intel_display_power_get(dev_priv,
-						intel_ddi_main_link_aux_domain(dig_port));
-	}
+	main_link_aux_power_domain_get(dig_port, crtc_state);
 }
 
 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
@@ -2741,10 +2767,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
 		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
 					  old_conn_state);
 
-	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
-		intel_display_power_put(dev_priv,
-					intel_ddi_main_link_aux_domain(dig_port),
-					fetch_and_zero(&dig_port->aux_wakeref));
+	main_link_aux_power_domain_put(dig_port, old_crtc_state);
 
 	if (is_tc_port)
 		intel_tc_port_put_link(dig_port);
@@ -3065,12 +3088,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
 	if (is_tc_port)
 		intel_tc_port_get_link(dig_port, crtc_state->lane_count);
 
-	if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
-		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
-		dig_port->aux_wakeref =
-			intel_display_power_get(dev_priv,
-						intel_ddi_main_link_aux_domain(dig_port));
-	}
+	main_link_aux_power_domain_get(dig_port, crtc_state);
 
 	if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
 		/*
-- 
2.37.1

[Intel-gfx] [PATCH v3 8/9] drm/i915: Don't enable the AUX_IO power for combo-PHY external DP port main links

[Imre Deak]

Combo PHY ports require the AUX_IO power only for eDP/PSR, so don't
enable it otherwise on these ports. So far the external DP and eDP case
was handled the same way due to unclarity when AUX_IO for the main link
is needed. However Bspec is clear in which cases it's required:

- eDP/PSR on all ports and platforms (presumably due to HW/FW initiated
  PSR transactions that won't enable AUX_IO)
  Bspec: 4301, 49296
- TypeC PHY ports on platforms before MTL in all TypeC modes (TBT,
  DP-alt, legacy) and for both HDMI and DP. The next patch will take
  into account the pre-MTL platform dependency.
  Bspec: 22243, 53339, 21750, 49190, 49191, 55424, 65448, 65750, 49294,
         55480, 65380

v2:
- Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 22 +++++++++-------------
 1 file changed, 9 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 21f1a68a57598..cc4bc529a78a5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -846,8 +846,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 }
 
 static enum intel_display_power_domain
-intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
-			       const struct intel_crtc_state *crtc_state)
+intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
@@ -867,20 +866,18 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
 	 */
 	if (intel_encoder_can_psr(&dig_port->base))
 		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
-	else if (intel_crtc_has_dp_encoder(crtc_state) ||
-		 intel_phy_is_tc(i915, phy))
+	else if (intel_phy_is_tc(i915, phy))
 		return intel_aux_power_domain(dig_port);
 	else
 		return POWER_DOMAIN_INVALID;
 }
 
 static void
-main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
-			       const struct intel_crtc_state *crtc_state)
+main_link_aux_power_domain_get(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 	enum intel_display_power_domain domain =
-		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
+		intel_ddi_main_link_aux_domain(dig_port);
 
 	drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
 
@@ -891,13 +888,12 @@ main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
 }
 
 static void
-main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
-			       const struct intel_crtc_state *crtc_state)
+main_link_aux_power_domain_put(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 	intel_wakeref_t wf = fetch_and_zero(&dig_port->aux_wakeref);
 	enum intel_display_power_domain domain =
-		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
+		intel_ddi_main_link_aux_domain(dig_port);
 
 	if (!wf)
 		return;
@@ -928,7 +924,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 								   dig_port->ddi_io_power_domain);
 	}
 
-	main_link_aux_power_domain_get(dig_port, crtc_state);
+	main_link_aux_power_domain_get(dig_port);
 }
 
 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
@@ -2767,7 +2763,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
 		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
 					  old_conn_state);
 
-	main_link_aux_power_domain_put(dig_port, old_crtc_state);
+	main_link_aux_power_domain_put(dig_port);
 
 	if (is_tc_port)
 		intel_tc_port_put_link(dig_port);
@@ -3088,7 +3084,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
 	if (is_tc_port)
 		intel_tc_port_get_link(dig_port, crtc_state->lane_count);
 
-	main_link_aux_power_domain_get(dig_port, crtc_state);
+	main_link_aux_power_domain_get(dig_port);
 
 	if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
 		/*
-- 
2.37.1

[Intel-gfx] [PATCH v3 9/9] drm/i915/mtl+: Don't enable the AUX_IO power for non-eDP port main links

[Imre Deak]

MTL+ requires the AUX_IO power for the main link only on eDP, so don't
enable it in other cases.

v2:
- Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index cc4bc529a78a5..7a4b5a7d2ec66 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -866,7 +866,7 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 	 */
 	if (intel_encoder_can_psr(&dig_port->base))
 		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
-	else if (intel_phy_is_tc(i915, phy))
+	else if (DISPLAY_VER(i915) < 14 && intel_phy_is_tc(i915, phy))
 		return intel_aux_power_domain(dig_port);
 	else
 		return POWER_DOMAIN_INVALID;
-- 
2.37.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl+: Enable DC power states on all eDP ports (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl+: Enable DC power states on all eDP ports (rev8)
URL   : https://patchwork.freedesktop.org/series/110433/
State : warning

== Summary ==

Error: dim checkpatch failed
f6043b9389ee drm/i915: Allocate power domain set wakerefs dynamically
-:112: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#112: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:876:
+
+}

total: 0 errors, 0 warnings, 1 checks, 191 lines checked
86c2dfc43e8b drm/i915: Move the POWER_DOMAIN_AUX_IO_A definition to its logical place
31dbe0fcb5c6 drm/i915: Use the AUX_IO power domain only for eDP/PSR port
6d2e3fc68ba2 drm/i915/tgl+: Enable display DC power states on all eDP ports
-:330: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#330: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:694:
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,
+	POWER_DOMAIN_AUX_IO_B,

-:333: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#333: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:697:
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,
+	POWER_DOMAIN_AUX_IO_C,

-:336: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#336: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:700:
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,
+	POWER_DOMAIN_AUX_IO_D,

-:339: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#339: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:703:
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,
+	POWER_DOMAIN_AUX_IO_E,

-:342: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#342: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:706:
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,
+	POWER_DOMAIN_AUX_IO_F,

total: 0 errors, 0 warnings, 5 checks, 285 lines checked
da361d14d8ef drm/i915: Add missing AUX_IO_A power domain->well mappings
8384e7066e8d drm/i915: Add missing DC_OFF power domain->well mappings
6237dc05ca11 drm/i915: Factor out function to get/put AUX_IO power for main link
4770b792f5fb drm/i915: Don't enable the AUX_IO power for combo-PHY external DP port main links
94f242b405f3 drm/i915/mtl+: Don't enable the AUX_IO power for non-eDP port main links

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl+: Enable DC power states on all eDP ports (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl+: Enable DC power states on all eDP ports (rev8)
URL   : https://patchwork.freedesktop.org/series/110433/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl+: Enable DC power states on all eDP ports (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6954 bytes --]

== Series Details ==

Series: drm/i915/tgl+: Enable DC power states on all eDP ports (rev8)
URL   : https://patchwork.freedesktop.org/series/110433/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12355 -> Patchwork_110433v8
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/index.html

Participating hosts (42 -> 39)
------------------------------

  Additional (1): fi-hsw-4770 
  Missing    (4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-tgl-dsi 

Known issues
------------

  Here are the changes found in Patchwork_110433v8 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_render_tiled_blits@basic:
    - fi-apl-guc:         [PASS][1] -> [INCOMPLETE][2] ([i915#7056])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/fi-apl-guc/igt@gem_render_tiled_blits@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/fi-apl-guc/igt@gem_render_tiled_blits@basic.html

  * igt@gem_softpin@allocator-basic-reserve:
    - fi-hsw-4770:        NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/fi-hsw-4770/igt@gem_softpin@allocator-basic-reserve.html

  * igt@i915_pm_backlight@basic-brightness:
    - fi-hsw-4770:        NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#3012])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/fi-hsw-4770/igt@i915_pm_backlight@basic-brightness.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - bat-adlp-4:         NOTRUN -> [SKIP][5] ([fdo#111827])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/bat-adlp-4/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-hsw-4770:        NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/fi-hsw-4770/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - bat-adlp-4:         NOTRUN -> [SKIP][7] ([i915#3546])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/bat-adlp-4/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_psr@sprite_plane_onoff:
    - fi-hsw-4770:        NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1072]) +3 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - {bat-rplp-1}:       [DMESG-WARN][9] ([i915#2867]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_selftest@live@migrate:
    - bat-adlp-4:         [INCOMPLETE][11] ([i915#7308] / [i915#7348]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/bat-adlp-4/igt@i915_selftest@live@migrate.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/bat-adlp-4/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@reset:
    - {bat-rpls-2}:       [DMESG-FAIL][13] ([i915#4983]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/bat-rpls-2/igt@i915_selftest@live@reset.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/bat-rpls-2/igt@i915_selftest@live@reset.html

  * igt@i915_selftest@live@slpc:
    - {bat-adln-1}:       [DMESG-FAIL][15] ([i915#6997]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/bat-adln-1/igt@i915_selftest@live@slpc.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/bat-adln-1/igt@i915_selftest@live@slpc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-edp-1:
    - fi-bsw-kefka:       [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/fi-bsw-kefka/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-edp-1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/fi-bsw-kefka/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-edp-1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
  [i915#6559]: https://gitlab.freedesktop.org/drm/intel/issues/6559
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7056]: https://gitlab.freedesktop.org/drm/intel/issues/7056
  [i915#7308]: https://gitlab.freedesktop.org/drm/intel/issues/7308
  [i915#7346]: https://gitlab.freedesktop.org/drm/intel/issues/7346
  [i915#7348]: https://gitlab.freedesktop.org/drm/intel/issues/7348


Build changes
-------------

  * Linux: CI_DRM_12355 -> Patchwork_110433v8

  CI-20190529: 20190529
  CI_DRM_12355: 6e09529cef7c2dfdf199c3af1adb9c828d281d9b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7048: 5edd5c539f1fdf1c02157bf43fa1fd22d4ad2c75 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110433v8: 6e09529cef7c2dfdf199c3af1adb9c828d281d9b @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

d0e51dbe3dfd drm/i915/mtl+: Don't enable the AUX_IO power for non-eDP port main links
4f476024ef21 drm/i915: Don't enable the AUX_IO power for combo-PHY external DP port main links
0feabf222413 drm/i915: Factor out function to get/put AUX_IO power for main link
7371bd95fd91 drm/i915: Add missing DC_OFF power domain->well mappings
19f368269a1b drm/i915: Add missing AUX_IO_A power domain->well mappings
2e418536a8e1 drm/i915/tgl+: Enable display DC power states on all eDP ports
42d61cca14bb drm/i915: Use the AUX_IO power domain only for eDP/PSR port
64c8af8666bb drm/i915: Move the POWER_DOMAIN_AUX_IO_A definition to its logical place
143f0cfdedcf drm/i915: Allocate power domain set wakerefs dynamically

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/index.html

[-- Attachment #2: Type: text/html, Size: 7775 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl+: Enable DC power states on all eDP ports (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 32891 bytes --]

== Series Details ==

Series: drm/i915/tgl+: Enable DC power states on all eDP ports (rev8)
URL   : https://patchwork.freedesktop.org/series/110433/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12355_full -> Patchwork_110433v8_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_110433v8_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
    - shard-apl:          [PASS][1] -> [DMESG-WARN][2] ([i915#180])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-apl2/igt@gem_ctx_isolation@preservation-s3@vecs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl2/igt@gem_ctx_isolation@preservation-s3@vecs0.html

  * igt@gem_eio@hibernate:
    - shard-glk:          [PASS][3] -> [DMESG-WARN][4] ([i915#118])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-glk7/igt@gem_eio@hibernate.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-glk1/igt@gem_eio@hibernate.html

  * igt@gem_eio@kms:
    - shard-tglb:         NOTRUN -> [FAIL][5] ([i915#5784])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-tglb2/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-iclb:         [PASS][6] -> [SKIP][7] ([i915#4525]) +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb3/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-glk:          [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-glk6/igt@gem_exec_fair@basic-none@vecs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-glk9/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [PASS][12] -> [SKIP][13] ([i915#2190])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-tglb2/igt@gem_huc_copy@huc-copy.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-tglb6/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-skl:          NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl7/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-skl:          [PASS][15] -> [DMESG-WARN][16] ([i915#5566] / [i915#716])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl10/igt@gen9_exec_parse@allowed-single.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl6/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([i915#3989] / [i915#454])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl7/igt@i915_pm_dc@dc6-psr.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl10/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
    - shard-tglb:         NOTRUN -> [WARN][19] ([i915#2681]) +3 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-tglb2/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
    - shard-skl:          [PASS][20] -> [FAIL][21] ([i915#2521])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-1:
    - shard-glk:          [PASS][22] -> [FAIL][23] ([i915#2521])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-glk7/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-1.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-glk1/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-apl:          NOTRUN -> [SKIP][24] ([fdo#109271]) +54 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][25] ([fdo#111614])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-tglb2/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
    - shard-iclb:         NOTRUN -> [SKIP][26] ([fdo#110725] / [fdo#111614])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb8/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3886]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl2/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl4/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@vga-hpd-after-suspend:
    - shard-apl:          NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl2/igt@kms_chamelium@vga-hpd-after-suspend.html

  * igt@kms_color_chamelium@ctm-max:
    - shard-skl:          NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl7/igt@kms_color_chamelium@ctm-max.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1:
    - shard-apl:          NOTRUN -> [DMESG-WARN][31] ([i915#180]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [PASS][32] -> [FAIL][33] ([i915#72])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
    - shard-glk:          [PASS][34] -> [FAIL][35] ([i915#2346]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-rmfb:
    - shard-skl:          NOTRUN -> [SKIP][36] ([fdo#109271]) +51 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl7/igt@kms_flip@2x-flip-vs-rmfb.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1:
    - shard-skl:          [PASS][37] -> [FAIL][38] ([i915#2122])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl9/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
    - shard-glk:          [PASS][39] -> [FAIL][40] ([i915#79]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-iclb:         NOTRUN -> [SKIP][41] ([i915#2587] / [i915#2672]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][42] ([i915#2672]) +2 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][43] ([i915#2672] / [i915#3555])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-tglb:         NOTRUN -> [SKIP][44] ([i915#6497])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-iclb:         NOTRUN -> [SKIP][45] ([fdo#109280])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
    - shard-tglb:         NOTRUN -> [SKIP][46] ([fdo#109280] / [fdo#111825])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-tglb2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
    - shard-skl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#658]) +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1:
    - shard-iclb:         NOTRUN -> [FAIL][48] ([i915#5939]) +2 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb2/igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [PASS][49] -> [SKIP][50] ([fdo#109441]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb8/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-iclb:         [PASS][51] -> [SKIP][52] ([i915#5519])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-iclb8/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_vblank@pipe-c-accuracy-idle:
    - shard-skl:          [PASS][53] -> [FAIL][54] ([i915#43])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl9/igt@kms_vblank@pipe-c-accuracy-idle.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl3/igt@kms_vblank@pipe-c-accuracy-idle.html

  * igt@sysfs_clients@fair-0:
    - shard-apl:          NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2994])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl2/igt@sysfs_clients@fair-0.html

  
#### Possible fixes ####

  * igt@gem_ctx_exec@basic-nohangcheck:
    - {shard-rkl}:        [FAIL][56] ([i915#6268]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-rkl-3/igt@gem_ctx_exec@basic-nohangcheck.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_eio@in-flight-suspend:
    - {shard-rkl}:        [FAIL][58] ([fdo#103375]) -> [PASS][59] +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-rkl-4/igt@gem_eio@in-flight-suspend.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-rkl-1/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_fair@basic-deadline:
    - {shard-rkl}:        [FAIL][60] ([i915#2846]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-rkl-6/igt@gem_exec_fair@basic-deadline.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-rkl-5/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [FAIL][62] ([i915#2842]) -> [PASS][63] +1 similar issue
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][64] ([i915#2842]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-iclb:         [FAIL][66] ([i915#2842]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-iclb8/igt@gem_exec_fair@basic-pace@vecs0.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb7/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
    - {shard-rkl}:        [SKIP][68] ([i915#6251]) -> [PASS][69]
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-rkl-5/igt@gem_exec_fence@basic-busy@bcs0.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-rkl-4/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_exec_reloc@basic-write-read-noreloc:
    - {shard-rkl}:        [SKIP][70] ([i915#3281]) -> [PASS][71] +14 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-rkl-4/igt@gem_exec_reloc@basic-write-read-noreloc.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-noreloc.html

  * igt@gem_readwrite@read-bad-handle:
    - {shard-rkl}:        [SKIP][72] ([i915#3282]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-rkl-6/igt@gem_readwrite@read-bad-handle.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-rkl-5/igt@gem_readwrite@read-bad-handle.html

  * igt@gem_softpin@evict-single-offset:
    - shard-tglb:         [FAIL][74] ([i915#4171]) -> [PASS][75]
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-tglb6/igt@gem_softpin@evict-single-offset.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-tglb3/igt@gem_softpin@evict-single-offset.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-skl:          [DMESG-WARN][76] ([i915#5566] / [i915#716]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl7/igt@gen9_exec_parse@allowed-all.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl4/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-apl:          [DMESG-WARN][78] ([i915#5566] / [i915#716]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-apl7/igt@gen9_exec_parse@allowed-single.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl3/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-chained:
    - {shard-rkl}:        [SKIP][80] ([i915#2527]) -> [PASS][81] +2 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-rkl-4/igt@gen9_exec_parse@bb-chained.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-rkl-5/igt@gen9_exec_parse@bb-chained.html

  * igt@i915_pm_backlight@fade_with_suspend:
    - {shard-rkl}:        [SKIP][82] ([i915#3012]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-rkl-4/igt@i915_pm_backlight@fade_with_suspend.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-rkl-6/igt@i915_pm_backlight@fade_with_suspend.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - {shard-rkl}:        [WARN][84] ([i915#2681]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-rkl-6/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_selftest@live@execlists:
    - shard-skl:          [INCOMPLETE][86] -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl6/igt@i915_selftest@live@execlists.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl7/igt@i915_selftest@live@execlists.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-edp-1:
    - shard-skl:          [FAIL][88] ([i915#7230]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-edp-1.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl6/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-edp-1.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - {shard-rkl}:        [SKIP][90] ([i915#1845] / [i915#4098]) -> [PASS][91] +13 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-rkl-4/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-rkl-6/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-linear:
    - {shard-rkl}:        [SKIP][92] ([i915#1849] / [i915#4098]) -> [PASS][93] +10 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
    - shard-iclb:         [SKIP][94] ([i915#5176]) -> [PASS][95] +1 similar issue
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb2/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html

  * igt@kms_psr@psr2_primary_blt:
    - shard-iclb:         [SKIP][96] ([fdo#109441]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-iclb3/igt@kms_psr@psr2_primary_blt.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb2/igt@kms_psr@psr2_primary_blt.html

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-apl:          [DMESG-WARN][98] ([i915#180]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-apl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html

  * igt@perf_pmu@busy-double-start@vecs0:
    - {shard-dg1}:        [FAIL][100] ([i915#4349]) -> [PASS][101] +1 similar issue
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-dg1-16/igt@perf_pmu@busy-double-start@vecs0.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-dg1-16/igt@perf_pmu@busy-double-start@vecs0.html

  
#### Warnings ####

  * igt@gem_pread@exhaustion:
    - shard-glk:          [INCOMPLETE][102] ([i915#7248]) -> [WARN][103] ([i915#2658])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-glk2/igt@gem_pread@exhaustion.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-glk2/igt@gem_pread@exhaustion.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
    - shard-iclb:         [SKIP][104] ([i915#2920]) -> [SKIP][105] ([i915#658])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb8/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
    - shard-iclb:         [SKIP][106] ([i915#2920]) -> [SKIP][107] ([fdo#111068] / [i915#658])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-iclb8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111]) ([fdo#109271] / [i915#3002] / [i915#4312]) -> ([FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115]) ([i915#180] / [i915#3002] / [i915#4312])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-apl7/igt@runner@aborted.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-apl7/igt@runner@aborted.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-apl6/igt@runner@aborted.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-apl1/igt@runner@aborted.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl6/igt@runner@aborted.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl6/igt@runner@aborted.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl3/igt@runner@aborted.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-apl2/igt@runner@aborted.html
    - shard-skl:          ([FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121]) ([i915#3002] / [i915#4312] / [i915#6949]) -> ([FAIL][122], [FAIL][123], [FAIL][124]) ([i915#3002] / [i915#4312])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl10/igt@runner@aborted.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl4/igt@runner@aborted.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl4/igt@runner@aborted.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl7/igt@runner@aborted.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl3/igt@runner@aborted.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12355/shard-skl6/igt@runner@aborted.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl3/igt@runner@aborted.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl6/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/shard-skl10/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6949]: https://gitlab.freedesktop.org/drm/intel/issues/6949
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7142]: https://gitlab.freedesktop.org/drm/intel/issues/7142
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#7230]: https://gitlab.freedesktop.org/drm/intel/issues/7230
  [i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * Linux: CI_DRM_12355 -> Patchwork_110433v8

  CI-20190529: 20190529
  CI_DRM_12355: 6e09529cef7c2dfdf199c3af1adb9c828d281d9b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7048: 5edd5c539f1fdf1c02157bf43fa1fd22d4ad2c75 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110433v8: 6e09529cef7c2dfdf199c3af1adb9c828d281d9b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110433v8/index.html

[-- Attachment #2: Type: text/html, Size: 34213 bytes --]

Re: [Intel-gfx] [PATCH v3 7/9] drm/i915: Factor out function to get/put AUX_IO power for main link

[Ville Syrjälä]

On Tue, Nov 08, 2022 at 05:18:26PM +0200, Imre Deak wrote:
> Factor out functions to get/put the AUX_IO power domain for the main
> link on DDI ports.
> 
> While at it clarify the corresponding code comment.
> 
> No functional change.
> 
> v2:
> - s/(get/put)_aux_power_for_main_link/main_link_aux_power_domain_(get/put)
>   (Jani)
> - Clarify in the code comment that AUX_IO is needed only by TypeC besides
>   eDP/PSR.
> v3:
> - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 84 ++++++++++++++----------
>  1 file changed, 51 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a087609223c60..21f1a68a57598 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -846,26 +846,63 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
>  }
>  
>  static enum intel_display_power_domain
> -intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
> +intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
> +			       const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>  
> -	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
> +	/*
> +	 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
>  	 * DC states enabled at the same time, while for driver initiated AUX
>  	 * transfers we need the same AUX IOs to be powered but with DC states
> -	 * disabled. Accordingly use the AUX power domain here which leaves DC
> -	 * states enabled.
> -	 * However, for non-A AUX ports the corresponding non-EDP transcoders
> -	 * would have already enabled power well 2 and DC_OFF. This means we can
> -	 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
> -	 * specific AUX_IO reference without powering up any extra wells.
> -	 * Note that PSR is enabled only on Port A even though this function
> -	 * returns the correct domain for other ports too.
> +	 * disabled. Accordingly use the AUX_IO_<port> power domain here which
> +	 * leaves DC states enabled.
> +	 *
> +	 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
> +	 * AUX IO to be enabled, but all these require DC_OFF to be enabled as
> +	 * well, so we can acquire a wider AUX_<port> power domain reference
> +	 * instead of a specific AUX_IO_<port> reference without powering up any
> +	 * extra wells.
>  	 */
>  	if (intel_encoder_can_psr(&dig_port->base))
>  		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
> -	else
> +	else if (intel_crtc_has_dp_encoder(crtc_state) ||
> +		 intel_phy_is_tc(i915, phy))
>  		return intel_aux_power_domain(dig_port);
> +	else
> +		return POWER_DOMAIN_INVALID;
> +}
> +
> +static void
> +main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
> +			       const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	enum intel_display_power_domain domain =
> +		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
> +
> +	drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
> +
> +	if (domain == POWER_DOMAIN_INVALID)
> +		return;
> +
> +	dig_port->aux_wakeref = intel_display_power_get(i915, domain);
> +}
> +
> +static void
> +main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
> +			       const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	intel_wakeref_t wf = fetch_and_zero(&dig_port->aux_wakeref);

Please don't call functions with side effects in variable
declaration blocks. Far too easy to miss them and then you end up
scratching your head for a day or two debugging the wrong thing.

> +	enum intel_display_power_domain domain =
> +		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
> +
> +	if (!wf)
> +		return;
> +
> +	intel_display_power_put(i915, domain, wf);
>  }
>  
>  static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
> @@ -873,7 +910,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_digital_port *dig_port;
> -	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>  
>  	/*
>  	 * TODO: Add support for MST encoders. Atm, the following should never
> @@ -892,17 +928,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
>  								   dig_port->ddi_io_power_domain);
>  	}
>  
> -	/*
> -	 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
> -	 * ports.
> -	 */
> -	if (intel_crtc_has_dp_encoder(crtc_state) ||
> -	    intel_phy_is_tc(dev_priv, phy)) {
> -		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
> -		dig_port->aux_wakeref =
> -			intel_display_power_get(dev_priv,
> -						intel_ddi_main_link_aux_domain(dig_port));
> -	}
> +	main_link_aux_power_domain_get(dig_port, crtc_state);
>  }
>  
>  void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
> @@ -2741,10 +2767,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
>  		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
>  					  old_conn_state);
>  
> -	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
> -		intel_display_power_put(dev_priv,
> -					intel_ddi_main_link_aux_domain(dig_port),
> -					fetch_and_zero(&dig_port->aux_wakeref));
> +	main_link_aux_power_domain_put(dig_port, old_crtc_state);
>  
>  	if (is_tc_port)
>  		intel_tc_port_put_link(dig_port);
> @@ -3065,12 +3088,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
>  	if (is_tc_port)
>  		intel_tc_port_get_link(dig_port, crtc_state->lane_count);
>  
> -	if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
> -		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
> -		dig_port->aux_wakeref =
> -			intel_display_power_get(dev_priv,
> -						intel_ddi_main_link_aux_domain(dig_port));
> -	}
> +	main_link_aux_power_domain_get(dig_port, crtc_state);
>  
>  	if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
>  		/*
> -- 
> 2.37.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v3 8/9] drm/i915: Don't enable the AUX_IO power for combo-PHY external DP port main links

[Ville Syrjälä]

On Tue, Nov 08, 2022 at 05:18:27PM +0200, Imre Deak wrote:
> Combo PHY ports require the AUX_IO power only for eDP/PSR, so don't
> enable it otherwise on these ports. So far the external DP and eDP case
> was handled the same way due to unclarity when AUX_IO for the main link
> is needed. However Bspec is clear in which cases it's required:
> 
> - eDP/PSR on all ports and platforms (presumably due to HW/FW initiated
>   PSR transactions that won't enable AUX_IO)
>   Bspec: 4301, 49296
> - TypeC PHY ports on platforms before MTL in all TypeC modes (TBT,
>   DP-alt, legacy) and for both HDMI and DP. The next patch will take
>   into account the pre-MTL platform dependency.
>   Bspec: 22243, 53339, 21750, 49190, 49191, 55424, 65448, 65750, 49294,
>          55480, 65380
> 
> v2:
> - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 22 +++++++++-------------
>  1 file changed, 9 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 21f1a68a57598..cc4bc529a78a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -846,8 +846,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
>  }
>  
>  static enum intel_display_power_domain
> -intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
> -			       const struct intel_crtc_state *crtc_state)
> +intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>  	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> @@ -867,20 +866,18 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
>  	 */
>  	if (intel_encoder_can_psr(&dig_port->base))
>  		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
> -	else if (intel_crtc_has_dp_encoder(crtc_state) ||
> -		 intel_phy_is_tc(i915, phy))
> +	else if (intel_phy_is_tc(i915, phy))
>  		return intel_aux_power_domain(dig_port);

I was pondering this a bit more the other day and came to the conclusion
that getting rid of the full aux domain is desirable, if for no other
reason that perhaps testing the dmc interactions a little bit more when
psr isn't supported. I guess nothing much should actually happen on the
dmc firware side without psr, but at least we might end up poking
the DC_STATE_EN register occasionally?

>  	else
>  		return POWER_DOMAIN_INVALID;
>  }
>  
>  static void
> -main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
> -			       const struct intel_crtc_state *crtc_state)
> +main_link_aux_power_domain_get(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>  	enum intel_display_power_domain domain =
> -		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
> +		intel_ddi_main_link_aux_domain(dig_port);
>  
>  	drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
>  
> @@ -891,13 +888,12 @@ main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
>  }
>  
>  static void
> -main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
> -			       const struct intel_crtc_state *crtc_state)
> +main_link_aux_power_domain_put(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>  	intel_wakeref_t wf = fetch_and_zero(&dig_port->aux_wakeref);
>  	enum intel_display_power_domain domain =
> -		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
> +		intel_ddi_main_link_aux_domain(dig_port);
>  
>  	if (!wf)
>  		return;
> @@ -928,7 +924,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
>  								   dig_port->ddi_io_power_domain);
>  	}
>  
> -	main_link_aux_power_domain_get(dig_port, crtc_state);
> +	main_link_aux_power_domain_get(dig_port);
>  }
>  
>  void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
> @@ -2767,7 +2763,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
>  		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
>  					  old_conn_state);
>  
> -	main_link_aux_power_domain_put(dig_port, old_crtc_state);
> +	main_link_aux_power_domain_put(dig_port);
>  
>  	if (is_tc_port)
>  		intel_tc_port_put_link(dig_port);
> @@ -3088,7 +3084,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
>  	if (is_tc_port)
>  		intel_tc_port_get_link(dig_port, crtc_state->lane_count);
>  
> -	main_link_aux_power_domain_get(dig_port, crtc_state);
> +	main_link_aux_power_domain_get(dig_port);
>  
>  	if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
>  		/*
> -- 
> 2.37.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v3 7/9] drm/i915: Factor out function to get/put AUX_IO power for main link

[Jani Nikula]

On Thu, 10 Nov 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Nov 08, 2022 at 05:18:26PM +0200, Imre Deak wrote:
>> +static void
>> +main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
>> +			       const struct intel_crtc_state *crtc_state)
>> +{
>> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>> +	intel_wakeref_t wf = fetch_and_zero(&dig_port->aux_wakeref);
>
> Please don't call functions with side effects in variable
> declaration blocks. Far too easy to miss them and then you end up
> scratching your head for a day or two debugging the wrong thing.

Side note, if I got to decide, I'd probably nuke "fetch_and_zero" out of
existence.

It's not that I don't find the concept useful, it's the naming that
gives the impression of atomicity that the macro utterly lacks. I find
that dangerous.

It's a helper that feels like should be part of a core kernel header
(and you might mistakenly think it already is!) but I doubt would ever
pass muster because of the above.


BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v3 8/9] drm/i915: Don't enable the AUX_IO power for combo-PHY external DP port main links

[Imre Deak]

On Thu, Nov 10, 2022 at 12:37:30PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 08, 2022 at 05:18:27PM +0200, Imre Deak wrote:
> > Combo PHY ports require the AUX_IO power only for eDP/PSR, so don't
> > enable it otherwise on these ports. So far the external DP and eDP case
> > was handled the same way due to unclarity when AUX_IO for the main link
> > is needed. However Bspec is clear in which cases it's required:
> > 
> > - eDP/PSR on all ports and platforms (presumably due to HW/FW initiated
> >   PSR transactions that won't enable AUX_IO)
> >   Bspec: 4301, 49296
> > - TypeC PHY ports on platforms before MTL in all TypeC modes (TBT,
> >   DP-alt, legacy) and for both HDMI and DP. The next patch will take
> >   into account the pre-MTL platform dependency.
> >   Bspec: 22243, 53339, 21750, 49190, 49191, 55424, 65448, 65750, 49294,
> >          55480, 65380
> > 
> > v2:
> > - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 22 +++++++++-------------
> >  1 file changed, 9 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 21f1a68a57598..cc4bc529a78a5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -846,8 +846,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> >  }
> >  
> >  static enum intel_display_power_domain
> > -intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
> > -			       const struct intel_crtc_state *crtc_state)
> > +intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> >  	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> > @@ -867,20 +866,18 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
> >  	 */
> >  	if (intel_encoder_can_psr(&dig_port->base))
> >  		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
> > -	else if (intel_crtc_has_dp_encoder(crtc_state) ||
> > -		 intel_phy_is_tc(i915, phy))
> > +	else if (intel_phy_is_tc(i915, phy))
> >  		return intel_aux_power_domain(dig_port);
> 
> I was pondering this a bit more the other day and came to the conclusion
> that getting rid of the full aux domain is desirable, if for no other
> reason that perhaps testing the dmc interactions a little bit more when
> psr isn't supported. I guess nothing much should actually happen on the
> dmc firware side without psr, but at least we might end up poking
> the DC_STATE_EN register occasionally?

Yes, that's how things work already now on port A. I think the DMC
context save handler is either not started when an external output is
enabled on the port (like HDMI) or the handler will check if PSR is
enabled and if not it won't do anything. So enabling/disabling DC state
via the DC_STATE_EN register shouldn't cause actual DC state entry/exit
transitions.

> >  	else
> >  		return POWER_DOMAIN_INVALID;
> >  }
> >  
> >  static void
> > -main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
> > -			       const struct intel_crtc_state *crtc_state)
> > +main_link_aux_power_domain_get(struct intel_digital_port *dig_port)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> >  	enum intel_display_power_domain domain =
> > -		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
> > +		intel_ddi_main_link_aux_domain(dig_port);
> >  
> >  	drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
> >  
> > @@ -891,13 +888,12 @@ main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
> >  }
> >  
> >  static void
> > -main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
> > -			       const struct intel_crtc_state *crtc_state)
> > +main_link_aux_power_domain_put(struct intel_digital_port *dig_port)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> >  	intel_wakeref_t wf = fetch_and_zero(&dig_port->aux_wakeref);
> >  	enum intel_display_power_domain domain =
> > -		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
> > +		intel_ddi_main_link_aux_domain(dig_port);
> >  
> >  	if (!wf)
> >  		return;
> > @@ -928,7 +924,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
> >  								   dig_port->ddi_io_power_domain);
> >  	}
> >  
> > -	main_link_aux_power_domain_get(dig_port, crtc_state);
> > +	main_link_aux_power_domain_get(dig_port);
> >  }
> >  
> >  void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
> > @@ -2767,7 +2763,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
> >  		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
> >  					  old_conn_state);
> >  
> > -	main_link_aux_power_domain_put(dig_port, old_crtc_state);
> > +	main_link_aux_power_domain_put(dig_port);
> >  
> >  	if (is_tc_port)
> >  		intel_tc_port_put_link(dig_port);
> > @@ -3088,7 +3084,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
> >  	if (is_tc_port)
> >  		intel_tc_port_get_link(dig_port, crtc_state->lane_count);
> >  
> > -	main_link_aux_power_domain_get(dig_port, crtc_state);
> > +	main_link_aux_power_domain_get(dig_port);
> >  
> >  	if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
> >  		/*
> > -- 
> > 2.37.1
> 
> -- 
> Ville Syrjälä
> Intel

Re: [Intel-gfx] [PATCH v3 7/9] drm/i915: Factor out function to get/put AUX_IO power for main link

[Imre Deak]

On Thu, Nov 10, 2022 at 12:21:26PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 08, 2022 at 05:18:26PM +0200, Imre Deak wrote:
> > Factor out functions to get/put the AUX_IO power domain for the main
> > link on DDI ports.
> > 
> > While at it clarify the corresponding code comment.
> > 
> > No functional change.
> > 
> > v2:
> > - s/(get/put)_aux_power_for_main_link/main_link_aux_power_domain_(get/put)
> >   (Jani)
> > - Clarify in the code comment that AUX_IO is needed only by TypeC besides
> >   eDP/PSR.
> > v3:
> > - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.
> > 
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 84 ++++++++++++++----------
> >  1 file changed, 51 insertions(+), 33 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index a087609223c60..21f1a68a57598 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -846,26 +846,63 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> >  }
> >  
> >  static enum intel_display_power_domain
> > -intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
> > +intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
> > +			       const struct intel_crtc_state *crtc_state)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > +	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> >  
> > -	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
> > +	/*
> > +	 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
> >  	 * DC states enabled at the same time, while for driver initiated AUX
> >  	 * transfers we need the same AUX IOs to be powered but with DC states
> > -	 * disabled. Accordingly use the AUX power domain here which leaves DC
> > -	 * states enabled.
> > -	 * However, for non-A AUX ports the corresponding non-EDP transcoders
> > -	 * would have already enabled power well 2 and DC_OFF. This means we can
> > -	 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
> > -	 * specific AUX_IO reference without powering up any extra wells.
> > -	 * Note that PSR is enabled only on Port A even though this function
> > -	 * returns the correct domain for other ports too.
> > +	 * disabled. Accordingly use the AUX_IO_<port> power domain here which
> > +	 * leaves DC states enabled.
> > +	 *
> > +	 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
> > +	 * AUX IO to be enabled, but all these require DC_OFF to be enabled as
> > +	 * well, so we can acquire a wider AUX_<port> power domain reference
> > +	 * instead of a specific AUX_IO_<port> reference without powering up any
> > +	 * extra wells.
> >  	 */
> >  	if (intel_encoder_can_psr(&dig_port->base))
> >  		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
> > -	else
> > +	else if (intel_crtc_has_dp_encoder(crtc_state) ||
> > +		 intel_phy_is_tc(i915, phy))
> >  		return intel_aux_power_domain(dig_port);
> > +	else
> > +		return POWER_DOMAIN_INVALID;
> > +}
> > +
> > +static void
> > +main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
> > +			       const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > +	enum intel_display_power_domain domain =
> > +		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
> > +
> > +	drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
> > +
> > +	if (domain == POWER_DOMAIN_INVALID)
> > +		return;
> > +
> > +	dig_port->aux_wakeref = intel_display_power_get(i915, domain);
> > +}
> > +
> > +static void
> > +main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
> > +			       const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > +	intel_wakeref_t wf = fetch_and_zero(&dig_port->aux_wakeref);
> 
> Please don't call functions with side effects in variable
> declaration blocks. Far too easy to miss them and then you end up
> scratching your head for a day or two debugging the wrong thing.

Ok, can change this.

> > +	enum intel_display_power_domain domain =
> > +		intel_ddi_main_link_aux_domain(dig_port, crtc_state);
> > +
> > +	if (!wf)
> > +		return;
> > +
> > +	intel_display_power_put(i915, domain, wf);
> >  }
> >  
> >  static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
> > @@ -873,7 +910,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	struct intel_digital_port *dig_port;
> > -	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> >  
> >  	/*
> >  	 * TODO: Add support for MST encoders. Atm, the following should never
> > @@ -892,17 +928,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
> >  								   dig_port->ddi_io_power_domain);
> >  	}
> >  
> > -	/*
> > -	 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
> > -	 * ports.
> > -	 */
> > -	if (intel_crtc_has_dp_encoder(crtc_state) ||
> > -	    intel_phy_is_tc(dev_priv, phy)) {
> > -		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
> > -		dig_port->aux_wakeref =
> > -			intel_display_power_get(dev_priv,
> > -						intel_ddi_main_link_aux_domain(dig_port));
> > -	}
> > +	main_link_aux_power_domain_get(dig_port, crtc_state);
> >  }
> >  
> >  void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
> > @@ -2741,10 +2767,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
> >  		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
> >  					  old_conn_state);
> >  
> > -	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
> > -		intel_display_power_put(dev_priv,
> > -					intel_ddi_main_link_aux_domain(dig_port),
> > -					fetch_and_zero(&dig_port->aux_wakeref));
> > +	main_link_aux_power_domain_put(dig_port, old_crtc_state);
> >  
> >  	if (is_tc_port)
> >  		intel_tc_port_put_link(dig_port);
> > @@ -3065,12 +3088,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
> >  	if (is_tc_port)
> >  		intel_tc_port_get_link(dig_port, crtc_state->lane_count);
> >  
> > -	if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
> > -		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
> > -		dig_port->aux_wakeref =
> > -			intel_display_power_get(dev_priv,
> > -						intel_ddi_main_link_aux_domain(dig_port));
> > -	}
> > +	main_link_aux_power_domain_get(dig_port, crtc_state);
> >  
> >  	if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
> >  		/*
> > -- 
> > 2.37.1
> 
> -- 
> Ville Syrjälä
> Intel

Re: [Intel-gfx] [PATCH v3 4/9] drm/i915/tgl+: Enable display DC power states on all eDP ports

[Ville Syrjälä]

On Tue, Nov 08, 2022 at 05:18:25PM +0200, Imre Deak wrote:
> Starting with TGL eDP is supported on ports B+ (besides port A), so make
> sure DC states are not blocked on any such ports. For this add an
> AUX_IO_<port> power domain for each port with eDP support. These domains
> similarly to AUX_IO_A enable only the AUX_IO_<port> power well for an
> enabled port, whereas the existing AUX_<port> domains enable both the
> AUX_IO_<port> and the DC_OFF power wells as required by DP AUX transfers.
> 
> v2: (Ville)
> - Split the change using AUX vs. AUX_IO on port A to a separate patch.
> - Select AUX_IO vs. AUX based on crtc_state->has_psr instead of
>   is_edp().
> v3:
> - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  6 ++-
>  .../drm/i915/display/intel_display_power.c    | 30 +++++++++++
>  .../drm/i915/display/intel_display_power.h    |  7 +++
>  .../i915/display/intel_display_power_map.c    | 53 +++++++++++++++++--
>  4 files changed, 89 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ca236cd7f9b76..a087609223c60 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -848,6 +848,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
>  static enum intel_display_power_domain
>  intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
>  {
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +
>  	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
>  	 * DC states enabled at the same time, while for driver initiated AUX
>  	 * transfers we need the same AUX IOs to be powered but with DC states
> @@ -860,8 +862,8 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
>  	 * Note that PSR is enabled only on Port A even though this function
>  	 * returns the correct domain for other ports too.
>  	 */
> -	if (dig_port->aux_ch == AUX_CH_A && intel_encoder_can_psr(&dig_port->base))
> -		return POWER_DOMAIN_AUX_IO_A;
> +	if (intel_encoder_can_psr(&dig_port->base))
> +		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
>  	else
>  		return intel_aux_power_domain(dig_port);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 78f1749397e1d..61c6a3616db08 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -131,6 +131,16 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
>  		return "AUDIO_PLAYBACK";
>  	case POWER_DOMAIN_AUX_IO_A:
>  		return "AUX_IO_A";
> +	case POWER_DOMAIN_AUX_IO_B:
> +		return "AUX_IO_B";
> +	case POWER_DOMAIN_AUX_IO_C:
> +		return "AUX_IO_C";
> +	case POWER_DOMAIN_AUX_IO_D:
> +		return "AUX_IO_D";
> +	case POWER_DOMAIN_AUX_IO_E:
> +		return "AUX_IO_E";
> +	case POWER_DOMAIN_AUX_IO_F:
> +		return "AUX_IO_F";
>  	case POWER_DOMAIN_AUX_A:
>  		return "AUX_A";
>  	case POWER_DOMAIN_AUX_B:
> @@ -2356,6 +2366,7 @@ struct intel_ddi_port_domains {
>  
>  	enum intel_display_power_domain ddi_lanes;
>  	enum intel_display_power_domain ddi_io;
> +	enum intel_display_power_domain aux_io;
>  	enum intel_display_power_domain aux_legacy_usbc;
>  	enum intel_display_power_domain aux_tbt;
>  };
> @@ -2370,6 +2381,7 @@ i9xx_port_domains[] = {
>  
>  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
>  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
> +		.aux_io = POWER_DOMAIN_AUX_IO_A,
>  		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
>  		.aux_tbt = POWER_DOMAIN_INVALID,
>  	},
> @@ -2385,6 +2397,7 @@ d11_port_domains[] = {
>  
>  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
>  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
> +		.aux_io = POWER_DOMAIN_AUX_IO_A,
>  		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
>  		.aux_tbt = POWER_DOMAIN_INVALID,
>  	}, {
> @@ -2395,6 +2408,7 @@ d11_port_domains[] = {
>  
>  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
>  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
> +		.aux_io = POWER_DOMAIN_AUX_IO_C,
>  		.aux_legacy_usbc = POWER_DOMAIN_AUX_C,
>  		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
>  	},
> @@ -2410,6 +2424,7 @@ d12_port_domains[] = {
>  
>  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
>  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
> +		.aux_io = POWER_DOMAIN_AUX_IO_A,
>  		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
>  		.aux_tbt = POWER_DOMAIN_INVALID,
>  	}, {
> @@ -2420,6 +2435,7 @@ d12_port_domains[] = {
>  
>  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
>  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
> +		.aux_io = POWER_DOMAIN_INVALID,
>  		.aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
>  		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
>  	},
> @@ -2435,6 +2451,7 @@ d13_port_domains[] = {
>  
>  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
>  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
> +		.aux_io = POWER_DOMAIN_AUX_IO_A,
>  		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
>  		.aux_tbt = POWER_DOMAIN_INVALID,
>  	}, {
> @@ -2445,6 +2462,7 @@ d13_port_domains[] = {
>  
>  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
>  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
> +		.aux_io = POWER_DOMAIN_INVALID,
>  		.aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
>  		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
>  	}, {
> @@ -2455,6 +2473,7 @@ d13_port_domains[] = {
>  
>  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
>  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
> +		.aux_io = POWER_DOMAIN_AUX_IO_D,
>  		.aux_legacy_usbc = POWER_DOMAIN_AUX_D,
>  		.aux_tbt = POWER_DOMAIN_INVALID,
>  	},
> @@ -2532,6 +2551,17 @@ intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
>  	return NULL;
>  }
>  
> +enum intel_display_power_domain
> +intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
> +{
> +	const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
> +
> +	if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_io == POWER_DOMAIN_INVALID)

Was there some valid use case for the INVALID? If not I'd include
it in the warn as well.

> +		return POWER_DOMAIN_AUX_IO_A;
> +
> +	return domains->aux_io + (int)(aux_ch - domains->aux_ch_start);
> +}
> +
>  enum intel_display_power_domain
>  intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index dd0ad99f17056..73c7db969dde6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -79,6 +79,11 @@ enum intel_display_power_domain {
>  	POWER_DOMAIN_AUDIO_PLAYBACK,
>  
>  	POWER_DOMAIN_AUX_IO_A,
> +	POWER_DOMAIN_AUX_IO_B,
> +	POWER_DOMAIN_AUX_IO_C,
> +	POWER_DOMAIN_AUX_IO_D,
> +	POWER_DOMAIN_AUX_IO_E,
> +	POWER_DOMAIN_AUX_IO_F,
>  
>  	POWER_DOMAIN_AUX_A,
>  	POWER_DOMAIN_AUX_B,
> @@ -255,6 +260,8 @@ intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port po
>  enum intel_display_power_domain
>  intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
>  enum intel_display_power_domain
> +intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
> +enum intel_display_power_domain
>  intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
>  enum intel_display_power_domain
>  intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 43454022e6a66..b82c0d0a80c5f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -170,6 +170,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
>  	POWER_DOMAIN_VGA,
>  	POWER_DOMAIN_AUDIO_MMIO,
>  	POWER_DOMAIN_AUDIO_PLAYBACK,
> +	POWER_DOMAIN_AUX_IO_B,
> +	POWER_DOMAIN_AUX_IO_C,
>  	POWER_DOMAIN_AUX_B,
>  	POWER_DOMAIN_AUX_C,
>  	POWER_DOMAIN_GMBUS,
> @@ -179,6 +181,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
>  	POWER_DOMAIN_PORT_DDI_LANES_B,
>  	POWER_DOMAIN_PORT_DDI_LANES_C,
>  	POWER_DOMAIN_PORT_CRT,
> +	POWER_DOMAIN_AUX_IO_B,
> +	POWER_DOMAIN_AUX_IO_C,
>  	POWER_DOMAIN_AUX_B,
>  	POWER_DOMAIN_AUX_C,
>  	POWER_DOMAIN_INIT);
> @@ -186,6 +190,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
>  I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
>  	POWER_DOMAIN_PORT_DDI_LANES_B,
>  	POWER_DOMAIN_PORT_DDI_LANES_C,
> +	POWER_DOMAIN_AUX_IO_B,
> +	POWER_DOMAIN_AUX_IO_C,
>  	POWER_DOMAIN_AUX_B,
>  	POWER_DOMAIN_AUX_C,
>  	POWER_DOMAIN_INIT);
> @@ -243,6 +249,9 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_display,
>  	POWER_DOMAIN_VGA,
>  	POWER_DOMAIN_AUDIO_MMIO,
>  	POWER_DOMAIN_AUDIO_PLAYBACK,
> +	POWER_DOMAIN_AUX_IO_B,
> +	POWER_DOMAIN_AUX_IO_C,
> +	POWER_DOMAIN_AUX_IO_D,
>  	POWER_DOMAIN_AUX_B,
>  	POWER_DOMAIN_AUX_C,
>  	POWER_DOMAIN_AUX_D,
> @@ -252,12 +261,15 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_display,
>  I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
>  	POWER_DOMAIN_PORT_DDI_LANES_B,
>  	POWER_DOMAIN_PORT_DDI_LANES_C,
> +	POWER_DOMAIN_AUX_IO_B,
> +	POWER_DOMAIN_AUX_IO_C,
>  	POWER_DOMAIN_AUX_B,
>  	POWER_DOMAIN_AUX_C,
>  	POWER_DOMAIN_INIT);
>  
>  I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
>  	POWER_DOMAIN_PORT_DDI_LANES_D,
> +	POWER_DOMAIN_AUX_IO_D,
>  	POWER_DOMAIN_AUX_D,
>  	POWER_DOMAIN_INIT);
>  
> @@ -305,6 +317,9 @@ static const struct i915_power_well_desc_list chv_power_wells[] = {
>  	POWER_DOMAIN_VGA, \
>  	POWER_DOMAIN_AUDIO_MMIO, \
>  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> +	POWER_DOMAIN_AUX_IO_B, \
> +	POWER_DOMAIN_AUX_IO_C, \
> +	POWER_DOMAIN_AUX_IO_D, \
>  	POWER_DOMAIN_AUX_B, \
>  	POWER_DOMAIN_AUX_C, \
>  	POWER_DOMAIN_AUX_D
> @@ -407,6 +422,8 @@ static const struct i915_power_well_desc_list skl_power_wells[] = {
>  	POWER_DOMAIN_VGA, \
>  	POWER_DOMAIN_AUDIO_MMIO, \
>  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> +	POWER_DOMAIN_AUX_IO_B, \
> +	POWER_DOMAIN_AUX_IO_C, \
>  	POWER_DOMAIN_AUX_B, \
>  	POWER_DOMAIN_AUX_C
>  
> @@ -430,6 +447,8 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
>  I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
>  	POWER_DOMAIN_PORT_DDI_LANES_B,
>  	POWER_DOMAIN_PORT_DDI_LANES_C,
> +	POWER_DOMAIN_AUX_IO_B,
> +	POWER_DOMAIN_AUX_IO_C,
>  	POWER_DOMAIN_AUX_B,
>  	POWER_DOMAIN_AUX_C,
>  	POWER_DOMAIN_INIT);
> @@ -483,6 +502,8 @@ static const struct i915_power_well_desc_list bxt_power_wells[] = {
>  	POWER_DOMAIN_VGA, \
>  	POWER_DOMAIN_AUDIO_MMIO, \
>  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> +	POWER_DOMAIN_AUX_IO_B, \
> +	POWER_DOMAIN_AUX_IO_C, \
>  	POWER_DOMAIN_AUX_B, \
>  	POWER_DOMAIN_AUX_C
>  
> @@ -509,11 +530,13 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
>  
>  I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
>  	POWER_DOMAIN_PORT_DDI_LANES_B,
> +	POWER_DOMAIN_AUX_IO_B,
>  	POWER_DOMAIN_AUX_B,
>  	POWER_DOMAIN_INIT);
>  
>  I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
>  	POWER_DOMAIN_PORT_DDI_LANES_C,
> +	POWER_DOMAIN_AUX_IO_C,
>  	POWER_DOMAIN_AUX_C,
>  	POWER_DOMAIN_INIT);
>  
> @@ -523,10 +546,12 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
>  	POWER_DOMAIN_INIT);
>  
>  I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
> +	POWER_DOMAIN_AUX_IO_B,
>  	POWER_DOMAIN_AUX_B,
>  	POWER_DOMAIN_INIT);
>  
>  I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
> +	POWER_DOMAIN_AUX_IO_C,
>  	POWER_DOMAIN_AUX_C,
>  	POWER_DOMAIN_INIT);
>  
> @@ -617,6 +642,11 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
>  	POWER_DOMAIN_VGA, \
>  	POWER_DOMAIN_AUDIO_MMIO, \
>  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> +	POWER_DOMAIN_AUX_IO_B, \
> +	POWER_DOMAIN_AUX_IO_C, \
> +	POWER_DOMAIN_AUX_IO_D, \
> +	POWER_DOMAIN_AUX_IO_E, \
> +	POWER_DOMAIN_AUX_IO_F, \
>  	POWER_DOMAIN_AUX_B, \
>  	POWER_DOMAIN_AUX_C, \
>  	POWER_DOMAIN_AUX_D, \
> @@ -660,11 +690,21 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f,	POWER_DOMAIN_PORT_DDI_IO_F);
>  I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
>  	POWER_DOMAIN_AUX_IO_A,
>  	POWER_DOMAIN_AUX_A);
> -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,		POWER_DOMAIN_AUX_B);
> -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,		POWER_DOMAIN_AUX_C);
> -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,		POWER_DOMAIN_AUX_D);
> -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,		POWER_DOMAIN_AUX_E);
> -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,		POWER_DOMAIN_AUX_F);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,
> +	POWER_DOMAIN_AUX_IO_B,
> +	POWER_DOMAIN_AUX_B);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,
> +	POWER_DOMAIN_AUX_IO_C,
> +	POWER_DOMAIN_AUX_C);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,
> +	POWER_DOMAIN_AUX_IO_D,
> +	POWER_DOMAIN_AUX_D);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,
> +	POWER_DOMAIN_AUX_IO_E,
> +	POWER_DOMAIN_AUX_E);
> +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,
> +	POWER_DOMAIN_AUX_IO_F,
> +	POWER_DOMAIN_AUX_F);
>  I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1,	POWER_DOMAIN_AUX_TBT1);
>  I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2,	POWER_DOMAIN_AUX_TBT2);
>  I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3,	POWER_DOMAIN_AUX_TBT3);
> @@ -1215,6 +1255,9 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
>  	POWER_DOMAIN_PORT_DDI_LANES_TC4, \
>  	POWER_DOMAIN_VGA, \
>  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> +	POWER_DOMAIN_AUX_IO_C, \
> +	POWER_DOMAIN_AUX_IO_D, \
> +	POWER_DOMAIN_AUX_IO_E, \
>  	POWER_DOMAIN_AUX_C, \
>  	POWER_DOMAIN_AUX_D, \
>  	POWER_DOMAIN_AUX_E, \
> -- 
> 2.37.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v3 4/9] drm/i915/tgl+: Enable display DC power states on all eDP ports

[Ville Syrjälä]

On Thu, Nov 10, 2022 at 08:52:00PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 08, 2022 at 05:18:25PM +0200, Imre Deak wrote:
> > Starting with TGL eDP is supported on ports B+ (besides port A), so make
> > sure DC states are not blocked on any such ports. For this add an
> > AUX_IO_<port> power domain for each port with eDP support. These domains
> > similarly to AUX_IO_A enable only the AUX_IO_<port> power well for an
> > enabled port, whereas the existing AUX_<port> domains enable both the
> > AUX_IO_<port> and the DC_OFF power wells as required by DP AUX transfers.
> > 
> > v2: (Ville)
> > - Split the change using AUX vs. AUX_IO on port A to a separate patch.
> > - Select AUX_IO vs. AUX based on crtc_state->has_psr instead of
> >   is_edp().
> > v3:
> > - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c      |  6 ++-
> >  .../drm/i915/display/intel_display_power.c    | 30 +++++++++++
> >  .../drm/i915/display/intel_display_power.h    |  7 +++
> >  .../i915/display/intel_display_power_map.c    | 53 +++++++++++++++++--
> >  4 files changed, 89 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index ca236cd7f9b76..a087609223c60 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -848,6 +848,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> >  static enum intel_display_power_domain
> >  intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
> >  {
> > +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > +
> >  	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
> >  	 * DC states enabled at the same time, while for driver initiated AUX
> >  	 * transfers we need the same AUX IOs to be powered but with DC states
> > @@ -860,8 +862,8 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
> >  	 * Note that PSR is enabled only on Port A even though this function
> >  	 * returns the correct domain for other ports too.
> >  	 */
> > -	if (dig_port->aux_ch == AUX_CH_A && intel_encoder_can_psr(&dig_port->base))
> > -		return POWER_DOMAIN_AUX_IO_A;
> > +	if (intel_encoder_can_psr(&dig_port->base))
> > +		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
> >  	else
> >  		return intel_aux_power_domain(dig_port);
> >  }
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 78f1749397e1d..61c6a3616db08 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -131,6 +131,16 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> >  		return "AUDIO_PLAYBACK";
> >  	case POWER_DOMAIN_AUX_IO_A:
> >  		return "AUX_IO_A";
> > +	case POWER_DOMAIN_AUX_IO_B:
> > +		return "AUX_IO_B";
> > +	case POWER_DOMAIN_AUX_IO_C:
> > +		return "AUX_IO_C";
> > +	case POWER_DOMAIN_AUX_IO_D:
> > +		return "AUX_IO_D";
> > +	case POWER_DOMAIN_AUX_IO_E:
> > +		return "AUX_IO_E";
> > +	case POWER_DOMAIN_AUX_IO_F:
> > +		return "AUX_IO_F";
> >  	case POWER_DOMAIN_AUX_A:
> >  		return "AUX_A";
> >  	case POWER_DOMAIN_AUX_B:
> > @@ -2356,6 +2366,7 @@ struct intel_ddi_port_domains {
> >  
> >  	enum intel_display_power_domain ddi_lanes;
> >  	enum intel_display_power_domain ddi_io;
> > +	enum intel_display_power_domain aux_io;
> >  	enum intel_display_power_domain aux_legacy_usbc;
> >  	enum intel_display_power_domain aux_tbt;
> >  };
> > @@ -2370,6 +2381,7 @@ i9xx_port_domains[] = {
> >  
> >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
> >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
> > +		.aux_io = POWER_DOMAIN_AUX_IO_A,
> >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
> >  		.aux_tbt = POWER_DOMAIN_INVALID,
> >  	},
> > @@ -2385,6 +2397,7 @@ d11_port_domains[] = {
> >  
> >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
> >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
> > +		.aux_io = POWER_DOMAIN_AUX_IO_A,
> >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
> >  		.aux_tbt = POWER_DOMAIN_INVALID,
> >  	}, {
> > @@ -2395,6 +2408,7 @@ d11_port_domains[] = {
> >  
> >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
> >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
> > +		.aux_io = POWER_DOMAIN_AUX_IO_C,
> >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_C,
> >  		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
> >  	},
> > @@ -2410,6 +2424,7 @@ d12_port_domains[] = {
> >  
> >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
> >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
> > +		.aux_io = POWER_DOMAIN_AUX_IO_A,
> >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
> >  		.aux_tbt = POWER_DOMAIN_INVALID,
> >  	}, {
> > @@ -2420,6 +2435,7 @@ d12_port_domains[] = {
> >  
> >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
> >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
> > +		.aux_io = POWER_DOMAIN_INVALID,
> >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
> >  		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
> >  	},
> > @@ -2435,6 +2451,7 @@ d13_port_domains[] = {
> >  
> >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
> >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
> > +		.aux_io = POWER_DOMAIN_AUX_IO_A,
> >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
> >  		.aux_tbt = POWER_DOMAIN_INVALID,
> >  	}, {
> > @@ -2445,6 +2462,7 @@ d13_port_domains[] = {
> >  
> >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
> >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
> > +		.aux_io = POWER_DOMAIN_INVALID,
> >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
> >  		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
> >  	}, {
> > @@ -2455,6 +2473,7 @@ d13_port_domains[] = {
> >  
> >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
> >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
> > +		.aux_io = POWER_DOMAIN_AUX_IO_D,
> >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_D,
> >  		.aux_tbt = POWER_DOMAIN_INVALID,
> >  	},
> > @@ -2532,6 +2551,17 @@ intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
> >  	return NULL;
> >  }
> >  
> > +enum intel_display_power_domain
> > +intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
> > +{
> > +	const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
> > +
> > +	if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_io == POWER_DOMAIN_INVALID)
> 
> Was there some valid use case for the INVALID? If not I'd include
> it in the warn as well.
> 
> > +		return POWER_DOMAIN_AUX_IO_A;

Hmm. And should we just return INVALID here? I think you added a check
for that in the caller.

> > +
> > +	return domains->aux_io + (int)(aux_ch - domains->aux_ch_start);
> > +}
> > +
> >  enum intel_display_power_domain
> >  intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
> >  {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> > index dd0ad99f17056..73c7db969dde6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > @@ -79,6 +79,11 @@ enum intel_display_power_domain {
> >  	POWER_DOMAIN_AUDIO_PLAYBACK,
> >  
> >  	POWER_DOMAIN_AUX_IO_A,
> > +	POWER_DOMAIN_AUX_IO_B,
> > +	POWER_DOMAIN_AUX_IO_C,
> > +	POWER_DOMAIN_AUX_IO_D,
> > +	POWER_DOMAIN_AUX_IO_E,
> > +	POWER_DOMAIN_AUX_IO_F,
> >  
> >  	POWER_DOMAIN_AUX_A,
> >  	POWER_DOMAIN_AUX_B,
> > @@ -255,6 +260,8 @@ intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port po
> >  enum intel_display_power_domain
> >  intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
> >  enum intel_display_power_domain
> > +intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
> > +enum intel_display_power_domain
> >  intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
> >  enum intel_display_power_domain
> >  intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > index 43454022e6a66..b82c0d0a80c5f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > @@ -170,6 +170,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
> >  	POWER_DOMAIN_VGA,
> >  	POWER_DOMAIN_AUDIO_MMIO,
> >  	POWER_DOMAIN_AUDIO_PLAYBACK,
> > +	POWER_DOMAIN_AUX_IO_B,
> > +	POWER_DOMAIN_AUX_IO_C,
> >  	POWER_DOMAIN_AUX_B,
> >  	POWER_DOMAIN_AUX_C,
> >  	POWER_DOMAIN_GMBUS,
> > @@ -179,6 +181,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
> >  	POWER_DOMAIN_PORT_DDI_LANES_B,
> >  	POWER_DOMAIN_PORT_DDI_LANES_C,
> >  	POWER_DOMAIN_PORT_CRT,
> > +	POWER_DOMAIN_AUX_IO_B,
> > +	POWER_DOMAIN_AUX_IO_C,
> >  	POWER_DOMAIN_AUX_B,
> >  	POWER_DOMAIN_AUX_C,
> >  	POWER_DOMAIN_INIT);
> > @@ -186,6 +190,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
> >  I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
> >  	POWER_DOMAIN_PORT_DDI_LANES_B,
> >  	POWER_DOMAIN_PORT_DDI_LANES_C,
> > +	POWER_DOMAIN_AUX_IO_B,
> > +	POWER_DOMAIN_AUX_IO_C,
> >  	POWER_DOMAIN_AUX_B,
> >  	POWER_DOMAIN_AUX_C,
> >  	POWER_DOMAIN_INIT);
> > @@ -243,6 +249,9 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_display,
> >  	POWER_DOMAIN_VGA,
> >  	POWER_DOMAIN_AUDIO_MMIO,
> >  	POWER_DOMAIN_AUDIO_PLAYBACK,
> > +	POWER_DOMAIN_AUX_IO_B,
> > +	POWER_DOMAIN_AUX_IO_C,
> > +	POWER_DOMAIN_AUX_IO_D,
> >  	POWER_DOMAIN_AUX_B,
> >  	POWER_DOMAIN_AUX_C,
> >  	POWER_DOMAIN_AUX_D,
> > @@ -252,12 +261,15 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_display,
> >  I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
> >  	POWER_DOMAIN_PORT_DDI_LANES_B,
> >  	POWER_DOMAIN_PORT_DDI_LANES_C,
> > +	POWER_DOMAIN_AUX_IO_B,
> > +	POWER_DOMAIN_AUX_IO_C,
> >  	POWER_DOMAIN_AUX_B,
> >  	POWER_DOMAIN_AUX_C,
> >  	POWER_DOMAIN_INIT);
> >  
> >  I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
> >  	POWER_DOMAIN_PORT_DDI_LANES_D,
> > +	POWER_DOMAIN_AUX_IO_D,
> >  	POWER_DOMAIN_AUX_D,
> >  	POWER_DOMAIN_INIT);
> >  
> > @@ -305,6 +317,9 @@ static const struct i915_power_well_desc_list chv_power_wells[] = {
> >  	POWER_DOMAIN_VGA, \
> >  	POWER_DOMAIN_AUDIO_MMIO, \
> >  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> > +	POWER_DOMAIN_AUX_IO_B, \
> > +	POWER_DOMAIN_AUX_IO_C, \
> > +	POWER_DOMAIN_AUX_IO_D, \
> >  	POWER_DOMAIN_AUX_B, \
> >  	POWER_DOMAIN_AUX_C, \
> >  	POWER_DOMAIN_AUX_D
> > @@ -407,6 +422,8 @@ static const struct i915_power_well_desc_list skl_power_wells[] = {
> >  	POWER_DOMAIN_VGA, \
> >  	POWER_DOMAIN_AUDIO_MMIO, \
> >  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> > +	POWER_DOMAIN_AUX_IO_B, \
> > +	POWER_DOMAIN_AUX_IO_C, \
> >  	POWER_DOMAIN_AUX_B, \
> >  	POWER_DOMAIN_AUX_C
> >  
> > @@ -430,6 +447,8 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
> >  I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
> >  	POWER_DOMAIN_PORT_DDI_LANES_B,
> >  	POWER_DOMAIN_PORT_DDI_LANES_C,
> > +	POWER_DOMAIN_AUX_IO_B,
> > +	POWER_DOMAIN_AUX_IO_C,
> >  	POWER_DOMAIN_AUX_B,
> >  	POWER_DOMAIN_AUX_C,
> >  	POWER_DOMAIN_INIT);
> > @@ -483,6 +502,8 @@ static const struct i915_power_well_desc_list bxt_power_wells[] = {
> >  	POWER_DOMAIN_VGA, \
> >  	POWER_DOMAIN_AUDIO_MMIO, \
> >  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> > +	POWER_DOMAIN_AUX_IO_B, \
> > +	POWER_DOMAIN_AUX_IO_C, \
> >  	POWER_DOMAIN_AUX_B, \
> >  	POWER_DOMAIN_AUX_C
> >  
> > @@ -509,11 +530,13 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
> >  
> >  I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
> >  	POWER_DOMAIN_PORT_DDI_LANES_B,
> > +	POWER_DOMAIN_AUX_IO_B,
> >  	POWER_DOMAIN_AUX_B,
> >  	POWER_DOMAIN_INIT);
> >  
> >  I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
> >  	POWER_DOMAIN_PORT_DDI_LANES_C,
> > +	POWER_DOMAIN_AUX_IO_C,
> >  	POWER_DOMAIN_AUX_C,
> >  	POWER_DOMAIN_INIT);
> >  
> > @@ -523,10 +546,12 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
> >  	POWER_DOMAIN_INIT);
> >  
> >  I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
> > +	POWER_DOMAIN_AUX_IO_B,
> >  	POWER_DOMAIN_AUX_B,
> >  	POWER_DOMAIN_INIT);
> >  
> >  I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
> > +	POWER_DOMAIN_AUX_IO_C,
> >  	POWER_DOMAIN_AUX_C,
> >  	POWER_DOMAIN_INIT);
> >  
> > @@ -617,6 +642,11 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
> >  	POWER_DOMAIN_VGA, \
> >  	POWER_DOMAIN_AUDIO_MMIO, \
> >  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> > +	POWER_DOMAIN_AUX_IO_B, \
> > +	POWER_DOMAIN_AUX_IO_C, \
> > +	POWER_DOMAIN_AUX_IO_D, \
> > +	POWER_DOMAIN_AUX_IO_E, \
> > +	POWER_DOMAIN_AUX_IO_F, \
> >  	POWER_DOMAIN_AUX_B, \
> >  	POWER_DOMAIN_AUX_C, \
> >  	POWER_DOMAIN_AUX_D, \
> > @@ -660,11 +690,21 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f,	POWER_DOMAIN_PORT_DDI_IO_F);
> >  I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
> >  	POWER_DOMAIN_AUX_IO_A,
> >  	POWER_DOMAIN_AUX_A);
> > -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,		POWER_DOMAIN_AUX_B);
> > -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,		POWER_DOMAIN_AUX_C);
> > -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,		POWER_DOMAIN_AUX_D);
> > -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,		POWER_DOMAIN_AUX_E);
> > -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,		POWER_DOMAIN_AUX_F);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,
> > +	POWER_DOMAIN_AUX_IO_B,
> > +	POWER_DOMAIN_AUX_B);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,
> > +	POWER_DOMAIN_AUX_IO_C,
> > +	POWER_DOMAIN_AUX_C);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,
> > +	POWER_DOMAIN_AUX_IO_D,
> > +	POWER_DOMAIN_AUX_D);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,
> > +	POWER_DOMAIN_AUX_IO_E,
> > +	POWER_DOMAIN_AUX_E);
> > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,
> > +	POWER_DOMAIN_AUX_IO_F,
> > +	POWER_DOMAIN_AUX_F);
> >  I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1,	POWER_DOMAIN_AUX_TBT1);
> >  I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2,	POWER_DOMAIN_AUX_TBT2);
> >  I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3,	POWER_DOMAIN_AUX_TBT3);
> > @@ -1215,6 +1255,9 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
> >  	POWER_DOMAIN_PORT_DDI_LANES_TC4, \
> >  	POWER_DOMAIN_VGA, \
> >  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> > +	POWER_DOMAIN_AUX_IO_C, \
> > +	POWER_DOMAIN_AUX_IO_D, \
> > +	POWER_DOMAIN_AUX_IO_E, \
> >  	POWER_DOMAIN_AUX_C, \
> >  	POWER_DOMAIN_AUX_D, \
> >  	POWER_DOMAIN_AUX_E, \
> > -- 
> > 2.37.1
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v3 4/9] drm/i915/tgl+: Enable display DC power states on all eDP ports

[Imre Deak]

On Thu, Nov 10, 2022 at 08:57:43PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 10, 2022 at 08:52:00PM +0200, Ville Syrjälä wrote:
> > On Tue, Nov 08, 2022 at 05:18:25PM +0200, Imre Deak wrote:
> > > Starting with TGL eDP is supported on ports B+ (besides port A), so make
> > > sure DC states are not blocked on any such ports. For this add an
> > > AUX_IO_<port> power domain for each port with eDP support. These domains
> > > similarly to AUX_IO_A enable only the AUX_IO_<port> power well for an
> > > enabled port, whereas the existing AUX_<port> domains enable both the
> > > AUX_IO_<port> and the DC_OFF power wells as required by DP AUX transfers.
> > > 
> > > v2: (Ville)
> > > - Split the change using AUX vs. AUX_IO on port A to a separate patch.
> > > - Select AUX_IO vs. AUX based on crtc_state->has_psr instead of
> > >   is_edp().
> > > v3:
> > > - Rebased on checking intel_encoder_can_psr() instead of crtc->has_psr.
> > > 
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_ddi.c      |  6 ++-
> > >  .../drm/i915/display/intel_display_power.c    | 30 +++++++++++
> > >  .../drm/i915/display/intel_display_power.h    |  7 +++
> > >  .../i915/display/intel_display_power_map.c    | 53 +++++++++++++++++--
> > >  4 files changed, 89 insertions(+), 7 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index ca236cd7f9b76..a087609223c60 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -848,6 +848,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> > >  static enum intel_display_power_domain
> > >  intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
> > >  {
> > > +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > +
> > >  	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
> > >  	 * DC states enabled at the same time, while for driver initiated AUX
> > >  	 * transfers we need the same AUX IOs to be powered but with DC states
> > > @@ -860,8 +862,8 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
> > >  	 * Note that PSR is enabled only on Port A even though this function
> > >  	 * returns the correct domain for other ports too.
> > >  	 */
> > > -	if (dig_port->aux_ch == AUX_CH_A && intel_encoder_can_psr(&dig_port->base))
> > > -		return POWER_DOMAIN_AUX_IO_A;
> > > +	if (intel_encoder_can_psr(&dig_port->base))
> > > +		return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
> > >  	else
> > >  		return intel_aux_power_domain(dig_port);
> > >  }
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 78f1749397e1d..61c6a3616db08 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -131,6 +131,16 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
> > >  		return "AUDIO_PLAYBACK";
> > >  	case POWER_DOMAIN_AUX_IO_A:
> > >  		return "AUX_IO_A";
> > > +	case POWER_DOMAIN_AUX_IO_B:
> > > +		return "AUX_IO_B";
> > > +	case POWER_DOMAIN_AUX_IO_C:
> > > +		return "AUX_IO_C";
> > > +	case POWER_DOMAIN_AUX_IO_D:
> > > +		return "AUX_IO_D";
> > > +	case POWER_DOMAIN_AUX_IO_E:
> > > +		return "AUX_IO_E";
> > > +	case POWER_DOMAIN_AUX_IO_F:
> > > +		return "AUX_IO_F";
> > >  	case POWER_DOMAIN_AUX_A:
> > >  		return "AUX_A";
> > >  	case POWER_DOMAIN_AUX_B:
> > > @@ -2356,6 +2366,7 @@ struct intel_ddi_port_domains {
> > >  
> > >  	enum intel_display_power_domain ddi_lanes;
> > >  	enum intel_display_power_domain ddi_io;
> > > +	enum intel_display_power_domain aux_io;
> > >  	enum intel_display_power_domain aux_legacy_usbc;
> > >  	enum intel_display_power_domain aux_tbt;
> > >  };
> > > @@ -2370,6 +2381,7 @@ i9xx_port_domains[] = {
> > >  
> > >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
> > >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
> > > +		.aux_io = POWER_DOMAIN_AUX_IO_A,
> > >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
> > >  		.aux_tbt = POWER_DOMAIN_INVALID,
> > >  	},
> > > @@ -2385,6 +2397,7 @@ d11_port_domains[] = {
> > >  
> > >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
> > >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
> > > +		.aux_io = POWER_DOMAIN_AUX_IO_A,
> > >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
> > >  		.aux_tbt = POWER_DOMAIN_INVALID,
> > >  	}, {
> > > @@ -2395,6 +2408,7 @@ d11_port_domains[] = {
> > >  
> > >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
> > >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
> > > +		.aux_io = POWER_DOMAIN_AUX_IO_C,
> > >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_C,
> > >  		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
> > >  	},
> > > @@ -2410,6 +2424,7 @@ d12_port_domains[] = {
> > >  
> > >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
> > >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
> > > +		.aux_io = POWER_DOMAIN_AUX_IO_A,
> > >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
> > >  		.aux_tbt = POWER_DOMAIN_INVALID,
> > >  	}, {
> > > @@ -2420,6 +2435,7 @@ d12_port_domains[] = {
> > >  
> > >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
> > >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
> > > +		.aux_io = POWER_DOMAIN_INVALID,
> > >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
> > >  		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
> > >  	},
> > > @@ -2435,6 +2451,7 @@ d13_port_domains[] = {
> > >  
> > >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
> > >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
> > > +		.aux_io = POWER_DOMAIN_AUX_IO_A,
> > >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_A,
> > >  		.aux_tbt = POWER_DOMAIN_INVALID,
> > >  	}, {
> > > @@ -2445,6 +2462,7 @@ d13_port_domains[] = {
> > >  
> > >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
> > >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
> > > +		.aux_io = POWER_DOMAIN_INVALID,
> > >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
> > >  		.aux_tbt = POWER_DOMAIN_AUX_TBT1,
> > >  	}, {
> > > @@ -2455,6 +2473,7 @@ d13_port_domains[] = {
> > >  
> > >  		.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
> > >  		.ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
> > > +		.aux_io = POWER_DOMAIN_AUX_IO_D,
> > >  		.aux_legacy_usbc = POWER_DOMAIN_AUX_D,
> > >  		.aux_tbt = POWER_DOMAIN_INVALID,
> > >  	},
> > > @@ -2532,6 +2551,17 @@ intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
> > >  	return NULL;
> > >  }
> > >  
> > > +enum intel_display_power_domain
> > > +intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
> > > +{
> > > +	const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
> > > +
> > > +	if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_io == POWER_DOMAIN_INVALID)
> > 
> > Was there some valid use case for the INVALID? If not I'd include
> > it in the warn as well.
> > 
> > > +		return POWER_DOMAIN_AUX_IO_A;
> 
> Hmm. And should we just return INVALID here? I think you added a check
> for that in the caller.

These functions should always return a valid domain, so yes, the warn
condition should be fixed above, will do that.

For TypeC ports a full TBT or USBC AUX domain is used instead, so the
caller should always get a valid domain.

> > > +
> > > +	return domains->aux_io + (int)(aux_ch - domains->aux_ch_start);
> > > +}
> > > +
> > >  enum intel_display_power_domain
> > >  intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
> > >  {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> > > index dd0ad99f17056..73c7db969dde6 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > > @@ -79,6 +79,11 @@ enum intel_display_power_domain {
> > >  	POWER_DOMAIN_AUDIO_PLAYBACK,
> > >  
> > >  	POWER_DOMAIN_AUX_IO_A,
> > > +	POWER_DOMAIN_AUX_IO_B,
> > > +	POWER_DOMAIN_AUX_IO_C,
> > > +	POWER_DOMAIN_AUX_IO_D,
> > > +	POWER_DOMAIN_AUX_IO_E,
> > > +	POWER_DOMAIN_AUX_IO_F,
> > >  
> > >  	POWER_DOMAIN_AUX_A,
> > >  	POWER_DOMAIN_AUX_B,
> > > @@ -255,6 +260,8 @@ intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port po
> > >  enum intel_display_power_domain
> > >  intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
> > >  enum intel_display_power_domain
> > > +intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
> > > +enum intel_display_power_domain
> > >  intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
> > >  enum intel_display_power_domain
> > >  intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > > index 43454022e6a66..b82c0d0a80c5f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > > @@ -170,6 +170,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
> > >  	POWER_DOMAIN_VGA,
> > >  	POWER_DOMAIN_AUDIO_MMIO,
> > >  	POWER_DOMAIN_AUDIO_PLAYBACK,
> > > +	POWER_DOMAIN_AUX_IO_B,
> > > +	POWER_DOMAIN_AUX_IO_C,
> > >  	POWER_DOMAIN_AUX_B,
> > >  	POWER_DOMAIN_AUX_C,
> > >  	POWER_DOMAIN_GMBUS,
> > > @@ -179,6 +181,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
> > >  	POWER_DOMAIN_PORT_DDI_LANES_B,
> > >  	POWER_DOMAIN_PORT_DDI_LANES_C,
> > >  	POWER_DOMAIN_PORT_CRT,
> > > +	POWER_DOMAIN_AUX_IO_B,
> > > +	POWER_DOMAIN_AUX_IO_C,
> > >  	POWER_DOMAIN_AUX_B,
> > >  	POWER_DOMAIN_AUX_C,
> > >  	POWER_DOMAIN_INIT);
> > > @@ -186,6 +190,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
> > >  I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
> > >  	POWER_DOMAIN_PORT_DDI_LANES_B,
> > >  	POWER_DOMAIN_PORT_DDI_LANES_C,
> > > +	POWER_DOMAIN_AUX_IO_B,
> > > +	POWER_DOMAIN_AUX_IO_C,
> > >  	POWER_DOMAIN_AUX_B,
> > >  	POWER_DOMAIN_AUX_C,
> > >  	POWER_DOMAIN_INIT);
> > > @@ -243,6 +249,9 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_display,
> > >  	POWER_DOMAIN_VGA,
> > >  	POWER_DOMAIN_AUDIO_MMIO,
> > >  	POWER_DOMAIN_AUDIO_PLAYBACK,
> > > +	POWER_DOMAIN_AUX_IO_B,
> > > +	POWER_DOMAIN_AUX_IO_C,
> > > +	POWER_DOMAIN_AUX_IO_D,
> > >  	POWER_DOMAIN_AUX_B,
> > >  	POWER_DOMAIN_AUX_C,
> > >  	POWER_DOMAIN_AUX_D,
> > > @@ -252,12 +261,15 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_display,
> > >  I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
> > >  	POWER_DOMAIN_PORT_DDI_LANES_B,
> > >  	POWER_DOMAIN_PORT_DDI_LANES_C,
> > > +	POWER_DOMAIN_AUX_IO_B,
> > > +	POWER_DOMAIN_AUX_IO_C,
> > >  	POWER_DOMAIN_AUX_B,
> > >  	POWER_DOMAIN_AUX_C,
> > >  	POWER_DOMAIN_INIT);
> > >  
> > >  I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
> > >  	POWER_DOMAIN_PORT_DDI_LANES_D,
> > > +	POWER_DOMAIN_AUX_IO_D,
> > >  	POWER_DOMAIN_AUX_D,
> > >  	POWER_DOMAIN_INIT);
> > >  
> > > @@ -305,6 +317,9 @@ static const struct i915_power_well_desc_list chv_power_wells[] = {
> > >  	POWER_DOMAIN_VGA, \
> > >  	POWER_DOMAIN_AUDIO_MMIO, \
> > >  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> > > +	POWER_DOMAIN_AUX_IO_B, \
> > > +	POWER_DOMAIN_AUX_IO_C, \
> > > +	POWER_DOMAIN_AUX_IO_D, \
> > >  	POWER_DOMAIN_AUX_B, \
> > >  	POWER_DOMAIN_AUX_C, \
> > >  	POWER_DOMAIN_AUX_D
> > > @@ -407,6 +422,8 @@ static const struct i915_power_well_desc_list skl_power_wells[] = {
> > >  	POWER_DOMAIN_VGA, \
> > >  	POWER_DOMAIN_AUDIO_MMIO, \
> > >  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> > > +	POWER_DOMAIN_AUX_IO_B, \
> > > +	POWER_DOMAIN_AUX_IO_C, \
> > >  	POWER_DOMAIN_AUX_B, \
> > >  	POWER_DOMAIN_AUX_C
> > >  
> > > @@ -430,6 +447,8 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
> > >  I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
> > >  	POWER_DOMAIN_PORT_DDI_LANES_B,
> > >  	POWER_DOMAIN_PORT_DDI_LANES_C,
> > > +	POWER_DOMAIN_AUX_IO_B,
> > > +	POWER_DOMAIN_AUX_IO_C,
> > >  	POWER_DOMAIN_AUX_B,
> > >  	POWER_DOMAIN_AUX_C,
> > >  	POWER_DOMAIN_INIT);
> > > @@ -483,6 +502,8 @@ static const struct i915_power_well_desc_list bxt_power_wells[] = {
> > >  	POWER_DOMAIN_VGA, \
> > >  	POWER_DOMAIN_AUDIO_MMIO, \
> > >  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> > > +	POWER_DOMAIN_AUX_IO_B, \
> > > +	POWER_DOMAIN_AUX_IO_C, \
> > >  	POWER_DOMAIN_AUX_B, \
> > >  	POWER_DOMAIN_AUX_C
> > >  
> > > @@ -509,11 +530,13 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
> > >  
> > >  I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
> > >  	POWER_DOMAIN_PORT_DDI_LANES_B,
> > > +	POWER_DOMAIN_AUX_IO_B,
> > >  	POWER_DOMAIN_AUX_B,
> > >  	POWER_DOMAIN_INIT);
> > >  
> > >  I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
> > >  	POWER_DOMAIN_PORT_DDI_LANES_C,
> > > +	POWER_DOMAIN_AUX_IO_C,
> > >  	POWER_DOMAIN_AUX_C,
> > >  	POWER_DOMAIN_INIT);
> > >  
> > > @@ -523,10 +546,12 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
> > >  	POWER_DOMAIN_INIT);
> > >  
> > >  I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
> > > +	POWER_DOMAIN_AUX_IO_B,
> > >  	POWER_DOMAIN_AUX_B,
> > >  	POWER_DOMAIN_INIT);
> > >  
> > >  I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
> > > +	POWER_DOMAIN_AUX_IO_C,
> > >  	POWER_DOMAIN_AUX_C,
> > >  	POWER_DOMAIN_INIT);
> > >  
> > > @@ -617,6 +642,11 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
> > >  	POWER_DOMAIN_VGA, \
> > >  	POWER_DOMAIN_AUDIO_MMIO, \
> > >  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> > > +	POWER_DOMAIN_AUX_IO_B, \
> > > +	POWER_DOMAIN_AUX_IO_C, \
> > > +	POWER_DOMAIN_AUX_IO_D, \
> > > +	POWER_DOMAIN_AUX_IO_E, \
> > > +	POWER_DOMAIN_AUX_IO_F, \
> > >  	POWER_DOMAIN_AUX_B, \
> > >  	POWER_DOMAIN_AUX_C, \
> > >  	POWER_DOMAIN_AUX_D, \
> > > @@ -660,11 +690,21 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f,	POWER_DOMAIN_PORT_DDI_IO_F);
> > >  I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
> > >  	POWER_DOMAIN_AUX_IO_A,
> > >  	POWER_DOMAIN_AUX_A);
> > > -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,		POWER_DOMAIN_AUX_B);
> > > -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,		POWER_DOMAIN_AUX_C);
> > > -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,		POWER_DOMAIN_AUX_D);
> > > -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,		POWER_DOMAIN_AUX_E);
> > > -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,		POWER_DOMAIN_AUX_F);
> > > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,
> > > +	POWER_DOMAIN_AUX_IO_B,
> > > +	POWER_DOMAIN_AUX_B);
> > > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,
> > > +	POWER_DOMAIN_AUX_IO_C,
> > > +	POWER_DOMAIN_AUX_C);
> > > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,
> > > +	POWER_DOMAIN_AUX_IO_D,
> > > +	POWER_DOMAIN_AUX_D);
> > > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,
> > > +	POWER_DOMAIN_AUX_IO_E,
> > > +	POWER_DOMAIN_AUX_E);
> > > +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,
> > > +	POWER_DOMAIN_AUX_IO_F,
> > > +	POWER_DOMAIN_AUX_F);
> > >  I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1,	POWER_DOMAIN_AUX_TBT1);
> > >  I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2,	POWER_DOMAIN_AUX_TBT2);
> > >  I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3,	POWER_DOMAIN_AUX_TBT3);
> > > @@ -1215,6 +1255,9 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
> > >  	POWER_DOMAIN_PORT_DDI_LANES_TC4, \
> > >  	POWER_DOMAIN_VGA, \
> > >  	POWER_DOMAIN_AUDIO_PLAYBACK, \
> > > +	POWER_DOMAIN_AUX_IO_C, \
> > > +	POWER_DOMAIN_AUX_IO_D, \
> > > +	POWER_DOMAIN_AUX_IO_E, \
> > >  	POWER_DOMAIN_AUX_C, \
> > >  	POWER_DOMAIN_AUX_D, \
> > >  	POWER_DOMAIN_AUX_E, \
> > > -- 
> > > 2.37.1
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 
> -- 
> Ville Syrjälä
> Intel

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Ville Syrjälä]

On Tue, Nov 08, 2022 at 05:18:23PM +0200, Imre Deak wrote:
> Since the intel_display_power_domain_set struct, currently its current
> size close to 1kB, can be allocated on the stack, it's better to
> allocate the per-domain wakeref pointer array - used for debugging -
> within the struct dynamically, so do this.
> 
> The memory freeing is guaranteed by the fact that the acquired domain
> references tracked by the struct can't be leaked either.
> 
> v2:
> - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> - Simplify intel_display_power_get/put_in_set(). (Jani)
> - Check in intel_crtc_destroy() that the wakerefs array has been freed.
> v3:
> - Add intel_display_power_set_disabled() and a separate assert
>   function instead of open coding these. (Jani)
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crtc.c     |  11 ++
>  .../drm/i915/display/intel_display_power.c    | 109 ++++++++++++++----
>  .../drm/i915/display/intel_display_power.h    |   6 +-
>  3 files changed, 104 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 037fc140b585c..c18d98bfe1a7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -21,6 +21,7 @@
>  #include "intel_crtc.h"
>  #include "intel_cursor.h"
>  #include "intel_display_debugfs.h"
> +#include "intel_display_power.h"
>  #include "intel_display_trace.h"
>  #include "intel_display_types.h"
>  #include "intel_drrs.h"
> @@ -37,6 +38,14 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
>  		drm_crtc_vblank_put(crtc);
>  }
>  
> +static void assert_power_domains_disabled(struct intel_crtc *crtc)
> +{
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +
> +	drm_WARN_ON(&i915->drm,
> +		    !intel_display_power_set_disabled(i915, &crtc->enabled_power_domains));
> +}
> +
>  struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
>  {
>  	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
> @@ -204,6 +213,8 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
>  
>  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
>  
> +	assert_power_domains_disabled(crtc);
> +
>  	drm_crtc_cleanup(&crtc->base);
>  	kfree(crtc);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 4c1de91e56ff9..ca63b4f1af41b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
>  }
>  #endif
>  
> +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> +static void
> +add_domain_to_set(struct drm_i915_private *i915,
> +		  struct intel_display_power_domain_set *power_domain_set,
> +		  enum intel_display_power_domain domain,
> +		  intel_wakeref_t wf)
> +{
> +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> +
> +	if (!power_domain_set->wakerefs)
> +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> +						     sizeof(*power_domain_set->wakerefs),
> +						     GFP_KERNEL);
> +
> +	if (power_domain_set->wakerefs)
> +		power_domain_set->wakerefs[domain] = wf;

So if the kcalloc() fails is it going to look like
we're leaking power wakerefs?

> +
> +	set_bit(domain, power_domain_set->mask.bits);
> +}
> +
> +static intel_wakeref_t
> +remove_domain_from_set(struct drm_i915_private *i915,
> +		       struct intel_display_power_domain_set *power_domain_set,
> +		       enum intel_display_power_domain domain)
> +{
> +	intel_wakeref_t wf;
> +
> +	drm_WARN_ON(&i915->drm, !test_bit(domain, power_domain_set->mask.bits));
> +
> +	clear_bit(domain, power_domain_set->mask.bits);
> +
> +	if (!power_domain_set->wakerefs)
> +		return -1;
> +
> +	wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
> +
> +	if (bitmap_empty(power_domain_set->mask.bits, POWER_DOMAIN_NUM)) {
> +		kfree(power_domain_set->wakerefs);
> +		power_domain_set->wakerefs = NULL;
> +	}
> +
> +	return wf;
> +
> +}
> +#else
> +static void
> +add_domain_to_set(struct drm_i915_private *i915,
> +		  struct intel_display_power_domain_set *power_domain_set,
> +		  enum intel_display_power_domain domain,
> +		  intel_wakeref_t wf)
> +{
> +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> +
> +	set_bit(domain, power_domain_set->mask.bits);
> +}
> +
> +static intel_wakeref_t
> +remove_domain_from_set(struct drm_i915_private *i915,
> +		       struct intel_display_power_domain_set *power_domain_set,
> +		       enum intel_display_power_domain domain)
> +{
> +	drm_WARN_ON(&i915->drm, !test_bit(domain, power_domain_set->mask.bits));
> +
> +	clear_bit(domain, power_domain_set->mask.bits);
> +
> +	return -1;
> +}
> +#endif
> +
>  void
>  intel_display_power_get_in_set(struct drm_i915_private *i915,
>  			       struct intel_display_power_domain_set *power_domain_set,
>  			       enum intel_display_power_domain domain)
>  {
> -	intel_wakeref_t __maybe_unused wf;
> -
> -	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> +	intel_wakeref_t wf;
>  
>  	wf = intel_display_power_get(i915, domain);
> -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> -	power_domain_set->wakerefs[domain] = wf;
> -#endif
> -	set_bit(domain, power_domain_set->mask.bits);
> +
> +	add_domain_to_set(i915, power_domain_set, domain, wf);
>  }
>  
>  bool
> @@ -853,16 +918,11 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
>  {
>  	intel_wakeref_t wf;
>  
> -	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> -
>  	wf = intel_display_power_get_if_enabled(i915, domain);
>  	if (!wf)
>  		return false;
>  
> -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> -	power_domain_set->wakerefs[domain] = wf;
> -#endif
> -	set_bit(domain, power_domain_set->mask.bits);
> +	add_domain_to_set(i915, power_domain_set, domain, wf);
>  
>  	return true;
>  }
> @@ -874,20 +934,27 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
>  {
>  	enum intel_display_power_domain domain;
>  
> -	drm_WARN_ON(&i915->drm,
> -		    !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
> -
>  	for_each_power_domain(domain, mask) {
> -		intel_wakeref_t __maybe_unused wf = -1;
> +		intel_wakeref_t wf = remove_domain_from_set(i915, power_domain_set, domain);
>  
> -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> -		wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
> -#endif
>  		intel_display_power_put(i915, domain, wf);
> -		clear_bit(domain, power_domain_set->mask.bits);
>  	}
>  }
>  
> +bool
> +intel_display_power_set_disabled(struct drm_i915_private *i915,
> +				 struct intel_display_power_domain_set *power_domain_set)
> +{
> +	if (!bitmap_empty(power_domain_set->mask.bits, POWER_DOMAIN_NUM))
> +		return false;
> +
> +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> +	drm_WARN_ON(&i915->drm, power_domain_set->wakerefs);
> +#endif
> +
> +	return true;
> +}
> +
>  static int
>  sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
>  				   int disable_power_well)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 1e77e52c87fec..31b0e9ae863c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -147,7 +147,7 @@ struct i915_power_domains {
>  struct intel_display_power_domain_set {
>  	struct intel_power_domain_mask mask;
>  #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
> -	intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
> +	intel_wakeref_t *wakerefs;
>  #endif
>  };
>  
> @@ -243,6 +243,10 @@ intel_display_power_put_all_in_set(struct drm_i915_private *i915,
>  	intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
>  }
>  
> +bool
> +intel_display_power_set_disabled(struct drm_i915_private *i915,
> +				 struct intel_display_power_domain_set *power_domain_set);
> +
>  void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
>  
>  enum intel_display_power_domain
> -- 
> 2.37.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Imre Deak]

On Thu, Nov 10, 2022 at 09:11:20PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 08, 2022 at 05:18:23PM +0200, Imre Deak wrote:
> > Since the intel_display_power_domain_set struct, currently its current
> > size close to 1kB, can be allocated on the stack, it's better to
> > allocate the per-domain wakeref pointer array - used for debugging -
> > within the struct dynamically, so do this.
> > 
> > The memory freeing is guaranteed by the fact that the acquired domain
> > references tracked by the struct can't be leaked either.
> > 
> > v2:
> > - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> > - Simplify intel_display_power_get/put_in_set(). (Jani)
> > - Check in intel_crtc_destroy() that the wakerefs array has been freed.
> > v3:
> > - Add intel_display_power_set_disabled() and a separate assert
> >   function instead of open coding these. (Jani)
> > 
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_crtc.c     |  11 ++
> >  .../drm/i915/display/intel_display_power.c    | 109 ++++++++++++++----
> >  .../drm/i915/display/intel_display_power.h    |   6 +-
> >  3 files changed, 104 insertions(+), 22 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index 037fc140b585c..c18d98bfe1a7c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -21,6 +21,7 @@
> >  #include "intel_crtc.h"
> >  #include "intel_cursor.h"
> >  #include "intel_display_debugfs.h"
> > +#include "intel_display_power.h"
> >  #include "intel_display_trace.h"
> >  #include "intel_display_types.h"
> >  #include "intel_drrs.h"
> > @@ -37,6 +38,14 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
> >  		drm_crtc_vblank_put(crtc);
> >  }
> >  
> > +static void assert_power_domains_disabled(struct intel_crtc *crtc)
> > +{
> > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > +
> > +	drm_WARN_ON(&i915->drm,
> > +		    !intel_display_power_set_disabled(i915, &crtc->enabled_power_domains));
> > +}
> > +
> >  struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
> >  {
> >  	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
> > @@ -204,6 +213,8 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
> >  
> >  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
> >  
> > +	assert_power_domains_disabled(crtc);
> > +
> >  	drm_crtc_cleanup(&crtc->base);
> >  	kfree(crtc);
> >  }
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 4c1de91e56ff9..ca63b4f1af41b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
> >  }
> >  #endif
> >  
> > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > +static void
> > +add_domain_to_set(struct drm_i915_private *i915,
> > +		  struct intel_display_power_domain_set *power_domain_set,
> > +		  enum intel_display_power_domain domain,
> > +		  intel_wakeref_t wf)
> > +{
> > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > +
> > +	if (!power_domain_set->wakerefs)
> > +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> > +						     sizeof(*power_domain_set->wakerefs),
> > +						     GFP_KERNEL);
> > +
> > +	if (power_domain_set->wakerefs)
> > +		power_domain_set->wakerefs[domain] = wf;
> 
> So if the kcalloc() fails is it going to look like
> we're leaking power wakerefs?

Yes, along with the alloc failure which is also logged. I assumed this
is enough to explain why wakeref tracking doesn't work afterwards, but I
suppose the wakeref could be untracked here in this case.

> > +
> > +	set_bit(domain, power_domain_set->mask.bits);
> > +}
> > +
> > +static intel_wakeref_t
> > +remove_domain_from_set(struct drm_i915_private *i915,
> > +		       struct intel_display_power_domain_set *power_domain_set,
> > +		       enum intel_display_power_domain domain)
> > +{
> > +	intel_wakeref_t wf;
> > +
> > +	drm_WARN_ON(&i915->drm, !test_bit(domain, power_domain_set->mask.bits));
> > +
> > +	clear_bit(domain, power_domain_set->mask.bits);
> > +
> > +	if (!power_domain_set->wakerefs)
> > +		return -1;
> > +
> > +	wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
> > +
> > +	if (bitmap_empty(power_domain_set->mask.bits, POWER_DOMAIN_NUM)) {
> > +		kfree(power_domain_set->wakerefs);
> > +		power_domain_set->wakerefs = NULL;
> > +	}
> > +
> > +	return wf;
> > +
> > +}
> > +#else
> > +static void
> > +add_domain_to_set(struct drm_i915_private *i915,
> > +		  struct intel_display_power_domain_set *power_domain_set,
> > +		  enum intel_display_power_domain domain,
> > +		  intel_wakeref_t wf)
> > +{
> > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > +
> > +	set_bit(domain, power_domain_set->mask.bits);
> > +}
> > +
> > +static intel_wakeref_t
> > +remove_domain_from_set(struct drm_i915_private *i915,
> > +		       struct intel_display_power_domain_set *power_domain_set,
> > +		       enum intel_display_power_domain domain)
> > +{
> > +	drm_WARN_ON(&i915->drm, !test_bit(domain, power_domain_set->mask.bits));
> > +
> > +	clear_bit(domain, power_domain_set->mask.bits);
> > +
> > +	return -1;
> > +}
> > +#endif
> > +
> >  void
> >  intel_display_power_get_in_set(struct drm_i915_private *i915,
> >  			       struct intel_display_power_domain_set *power_domain_set,
> >  			       enum intel_display_power_domain domain)
> >  {
> > -	intel_wakeref_t __maybe_unused wf;
> > -
> > -	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > +	intel_wakeref_t wf;
> >  
> >  	wf = intel_display_power_get(i915, domain);
> > -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > -	power_domain_set->wakerefs[domain] = wf;
> > -#endif
> > -	set_bit(domain, power_domain_set->mask.bits);
> > +
> > +	add_domain_to_set(i915, power_domain_set, domain, wf);
> >  }
> >  
> >  bool
> > @@ -853,16 +918,11 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
> >  {
> >  	intel_wakeref_t wf;
> >  
> > -	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > -
> >  	wf = intel_display_power_get_if_enabled(i915, domain);
> >  	if (!wf)
> >  		return false;
> >  
> > -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > -	power_domain_set->wakerefs[domain] = wf;
> > -#endif
> > -	set_bit(domain, power_domain_set->mask.bits);
> > +	add_domain_to_set(i915, power_domain_set, domain, wf);
> >  
> >  	return true;
> >  }
> > @@ -874,20 +934,27 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> >  {
> >  	enum intel_display_power_domain domain;
> >  
> > -	drm_WARN_ON(&i915->drm,
> > -		    !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
> > -
> >  	for_each_power_domain(domain, mask) {
> > -		intel_wakeref_t __maybe_unused wf = -1;
> > +		intel_wakeref_t wf = remove_domain_from_set(i915, power_domain_set, domain);
> >  
> > -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > -		wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
> > -#endif
> >  		intel_display_power_put(i915, domain, wf);
> > -		clear_bit(domain, power_domain_set->mask.bits);
> >  	}
> >  }
> >  
> > +bool
> > +intel_display_power_set_disabled(struct drm_i915_private *i915,
> > +				 struct intel_display_power_domain_set *power_domain_set)
> > +{
> > +	if (!bitmap_empty(power_domain_set->mask.bits, POWER_DOMAIN_NUM))
> > +		return false;
> > +
> > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > +	drm_WARN_ON(&i915->drm, power_domain_set->wakerefs);
> > +#endif
> > +
> > +	return true;
> > +}
> > +
> >  static int
> >  sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
> >  				   int disable_power_well)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> > index 1e77e52c87fec..31b0e9ae863c3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > @@ -147,7 +147,7 @@ struct i915_power_domains {
> >  struct intel_display_power_domain_set {
> >  	struct intel_power_domain_mask mask;
> >  #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
> > -	intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
> > +	intel_wakeref_t *wakerefs;
> >  #endif
> >  };
> >  
> > @@ -243,6 +243,10 @@ intel_display_power_put_all_in_set(struct drm_i915_private *i915,
> >  	intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
> >  }
> >  
> > +bool
> > +intel_display_power_set_disabled(struct drm_i915_private *i915,
> > +				 struct intel_display_power_domain_set *power_domain_set);
> > +
> >  void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
> >  
> >  enum intel_display_power_domain
> > -- 
> > 2.37.1
> 
> -- 
> Ville Syrjälä
> Intel

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Ville Syrjälä]

On Thu, Nov 10, 2022 at 09:55:55PM +0200, Imre Deak wrote:
> On Thu, Nov 10, 2022 at 09:11:20PM +0200, Ville Syrjälä wrote:
> > On Tue, Nov 08, 2022 at 05:18:23PM +0200, Imre Deak wrote:
> > > Since the intel_display_power_domain_set struct, currently its current
> > > size close to 1kB, can be allocated on the stack, it's better to
> > > allocate the per-domain wakeref pointer array - used for debugging -
> > > within the struct dynamically, so do this.
> > > 
> > > The memory freeing is guaranteed by the fact that the acquired domain
> > > references tracked by the struct can't be leaked either.
> > > 
> > > v2:
> > > - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> > > - Simplify intel_display_power_get/put_in_set(). (Jani)
> > > - Check in intel_crtc_destroy() that the wakerefs array has been freed.
> > > v3:
> > > - Add intel_display_power_set_disabled() and a separate assert
> > >   function instead of open coding these. (Jani)
> > > 
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_crtc.c     |  11 ++
> > >  .../drm/i915/display/intel_display_power.c    | 109 ++++++++++++++----
> > >  .../drm/i915/display/intel_display_power.h    |   6 +-
> > >  3 files changed, 104 insertions(+), 22 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > index 037fc140b585c..c18d98bfe1a7c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > @@ -21,6 +21,7 @@
> > >  #include "intel_crtc.h"
> > >  #include "intel_cursor.h"
> > >  #include "intel_display_debugfs.h"
> > > +#include "intel_display_power.h"
> > >  #include "intel_display_trace.h"
> > >  #include "intel_display_types.h"
> > >  #include "intel_drrs.h"
> > > @@ -37,6 +38,14 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
> > >  		drm_crtc_vblank_put(crtc);
> > >  }
> > >  
> > > +static void assert_power_domains_disabled(struct intel_crtc *crtc)
> > > +{
> > > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > +
> > > +	drm_WARN_ON(&i915->drm,
> > > +		    !intel_display_power_set_disabled(i915, &crtc->enabled_power_domains));
> > > +}
> > > +
> > >  struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
> > >  {
> > >  	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
> > > @@ -204,6 +213,8 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
> > >  
> > >  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
> > >  
> > > +	assert_power_domains_disabled(crtc);
> > > +
> > >  	drm_crtc_cleanup(&crtc->base);
> > >  	kfree(crtc);
> > >  }
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 4c1de91e56ff9..ca63b4f1af41b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
> > >  }
> > >  #endif
> > >  
> > > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > > +static void
> > > +add_domain_to_set(struct drm_i915_private *i915,
> > > +		  struct intel_display_power_domain_set *power_domain_set,
> > > +		  enum intel_display_power_domain domain,
> > > +		  intel_wakeref_t wf)
> > > +{
> > > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > > +
> > > +	if (!power_domain_set->wakerefs)
> > > +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> > > +						     sizeof(*power_domain_set->wakerefs),
> > > +						     GFP_KERNEL);
> > > +
> > > +	if (power_domain_set->wakerefs)
> > > +		power_domain_set->wakerefs[domain] = wf;
> > 
> > So if the kcalloc() fails is it going to look like
> > we're leaking power wakerefs?
> 
> Yes, along with the alloc failure which is also logged. I assumed this
> is enough to explain why wakeref tracking doesn't work afterwards, but I
> suppose the wakeref could be untracked here in this case.

I think a more clear message what is going on would be good.
And probably preventing the spam from the wakerefs would
also be good to make sure the whole thing doesn't get
misdiagnosed as a real power ref leak.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Imre Deak]

On Thu, Nov 10, 2022 at 11:49:19PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 10, 2022 at 09:55:55PM +0200, Imre Deak wrote:
> > On Thu, Nov 10, 2022 at 09:11:20PM +0200, Ville Syrjälä wrote:
> > > On Tue, Nov 08, 2022 at 05:18:23PM +0200, Imre Deak wrote:
> > > > Since the intel_display_power_domain_set struct, currently its current
> > > > size close to 1kB, can be allocated on the stack, it's better to
> > > > allocate the per-domain wakeref pointer array - used for debugging -
> > > > within the struct dynamically, so do this.
> > > > 
> > > > The memory freeing is guaranteed by the fact that the acquired domain
> > > > references tracked by the struct can't be leaked either.
> > > > 
> > > > v2:
> > > > - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> > > > - Simplify intel_display_power_get/put_in_set(). (Jani)
> > > > - Check in intel_crtc_destroy() that the wakerefs array has been freed.
> > > > v3:
> > > > - Add intel_display_power_set_disabled() and a separate assert
> > > >   function instead of open coding these. (Jani)
> > > > 
> > > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_crtc.c     |  11 ++
> > > >  .../drm/i915/display/intel_display_power.c    | 109 ++++++++++++++----
> > > >  .../drm/i915/display/intel_display_power.h    |   6 +-
> > > >  3 files changed, 104 insertions(+), 22 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > index 037fc140b585c..c18d98bfe1a7c 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > @@ -21,6 +21,7 @@
> > > >  #include "intel_crtc.h"
> > > >  #include "intel_cursor.h"
> > > >  #include "intel_display_debugfs.h"
> > > > +#include "intel_display_power.h"
> > > >  #include "intel_display_trace.h"
> > > >  #include "intel_display_types.h"
> > > >  #include "intel_drrs.h"
> > > > @@ -37,6 +38,14 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
> > > >  		drm_crtc_vblank_put(crtc);
> > > >  }
> > > >  
> > > > +static void assert_power_domains_disabled(struct intel_crtc *crtc)
> > > > +{
> > > > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > > +
> > > > +	drm_WARN_ON(&i915->drm,
> > > > +		    !intel_display_power_set_disabled(i915, &crtc->enabled_power_domains));
> > > > +}
> > > > +
> > > >  struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
> > > >  {
> > > >  	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
> > > > @@ -204,6 +213,8 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
> > > >  
> > > >  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
> > > >  
> > > > +	assert_power_domains_disabled(crtc);
> > > > +
> > > >  	drm_crtc_cleanup(&crtc->base);
> > > >  	kfree(crtc);
> > > >  }
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > index 4c1de91e56ff9..ca63b4f1af41b 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
> > > >  }
> > > >  #endif
> > > >  
> > > > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > > > +static void
> > > > +add_domain_to_set(struct drm_i915_private *i915,
> > > > +		  struct intel_display_power_domain_set *power_domain_set,
> > > > +		  enum intel_display_power_domain domain,
> > > > +		  intel_wakeref_t wf)
> > > > +{
> > > > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > > > +
> > > > +	if (!power_domain_set->wakerefs)
> > > > +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> > > > +						     sizeof(*power_domain_set->wakerefs),
> > > > +						     GFP_KERNEL);
> > > > +
> > > > +	if (power_domain_set->wakerefs)
> > > > +		power_domain_set->wakerefs[domain] = wf;
> > > 
> > > So if the kcalloc() fails is it going to look like
> > > we're leaking power wakerefs?
> > 
> > Yes, along with the alloc failure which is also logged. I assumed this
> > is enough to explain why wakeref tracking doesn't work afterwards, but I
> > suppose the wakeref could be untracked here in this case.
> 
> I think a more clear message what is going on would be good.
> And probably preventing the spam from the wakerefs would
> also be good to make sure the whole thing doesn't get
> misdiagnosed as a real power ref leak.

Ok, I can add a debug print about the failure and untrack the wakeref.

> 
> -- 
> Ville Syrjälä
> Intel

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Ville Syrjälä]

On Fri, Nov 11, 2022 at 02:37:13PM +0200, Imre Deak wrote:
> On Thu, Nov 10, 2022 at 11:49:19PM +0200, Ville Syrjälä wrote:
> > On Thu, Nov 10, 2022 at 09:55:55PM +0200, Imre Deak wrote:
> > > On Thu, Nov 10, 2022 at 09:11:20PM +0200, Ville Syrjälä wrote:
> > > > On Tue, Nov 08, 2022 at 05:18:23PM +0200, Imre Deak wrote:
> > > > > Since the intel_display_power_domain_set struct, currently its current
> > > > > size close to 1kB, can be allocated on the stack, it's better to
> > > > > allocate the per-domain wakeref pointer array - used for debugging -
> > > > > within the struct dynamically, so do this.
> > > > > 
> > > > > The memory freeing is guaranteed by the fact that the acquired domain
> > > > > references tracked by the struct can't be leaked either.
> > > > > 
> > > > > v2:
> > > > > - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> > > > > - Simplify intel_display_power_get/put_in_set(). (Jani)
> > > > > - Check in intel_crtc_destroy() that the wakerefs array has been freed.
> > > > > v3:
> > > > > - Add intel_display_power_set_disabled() and a separate assert
> > > > >   function instead of open coding these. (Jani)
> > > > > 
> > > > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_crtc.c     |  11 ++
> > > > >  .../drm/i915/display/intel_display_power.c    | 109 ++++++++++++++----
> > > > >  .../drm/i915/display/intel_display_power.h    |   6 +-
> > > > >  3 files changed, 104 insertions(+), 22 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > index 037fc140b585c..c18d98bfe1a7c 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > @@ -21,6 +21,7 @@
> > > > >  #include "intel_crtc.h"
> > > > >  #include "intel_cursor.h"
> > > > >  #include "intel_display_debugfs.h"
> > > > > +#include "intel_display_power.h"
> > > > >  #include "intel_display_trace.h"
> > > > >  #include "intel_display_types.h"
> > > > >  #include "intel_drrs.h"
> > > > > @@ -37,6 +38,14 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
> > > > >  		drm_crtc_vblank_put(crtc);
> > > > >  }
> > > > >  
> > > > > +static void assert_power_domains_disabled(struct intel_crtc *crtc)
> > > > > +{
> > > > > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > > > +
> > > > > +	drm_WARN_ON(&i915->drm,
> > > > > +		    !intel_display_power_set_disabled(i915, &crtc->enabled_power_domains));
> > > > > +}
> > > > > +
> > > > >  struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
> > > > >  {
> > > > >  	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
> > > > > @@ -204,6 +213,8 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
> > > > >  
> > > > >  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
> > > > >  
> > > > > +	assert_power_domains_disabled(crtc);
> > > > > +
> > > > >  	drm_crtc_cleanup(&crtc->base);
> > > > >  	kfree(crtc);
> > > > >  }
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > index 4c1de91e56ff9..ca63b4f1af41b 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
> > > > >  }
> > > > >  #endif
> > > > >  
> > > > > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > > > > +static void
> > > > > +add_domain_to_set(struct drm_i915_private *i915,
> > > > > +		  struct intel_display_power_domain_set *power_domain_set,
> > > > > +		  enum intel_display_power_domain domain,
> > > > > +		  intel_wakeref_t wf)
> > > > > +{
> > > > > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > > > > +
> > > > > +	if (!power_domain_set->wakerefs)
> > > > > +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> > > > > +						     sizeof(*power_domain_set->wakerefs),
> > > > > +						     GFP_KERNEL);
> > > > > +
> > > > > +	if (power_domain_set->wakerefs)
> > > > > +		power_domain_set->wakerefs[domain] = wf;
> > > > 
> > > > So if the kcalloc() fails is it going to look like
> > > > we're leaking power wakerefs?
> > > 
> > > Yes, along with the alloc failure which is also logged. I assumed this
> > > is enough to explain why wakeref tracking doesn't work afterwards, but I
> > > suppose the wakeref could be untracked here in this case.
> > 
> > I think a more clear message what is going on would be good.
> > And probably preventing the spam from the wakerefs would
> > also be good to make sure the whole thing doesn't get
> > misdiagnosed as a real power ref leak.
> 
> Ok, I can add a debug print about the failure and untrack the wakeref.

The other idea that came to mind was to just preallocate this
somehow. Looks like the only place where this even matters
currently is hsw_get_pipe_config(). The other instance of
this structure is already embedded in a kmalloced thing
(struct intel_crtc).

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Ville Syrjälä]

On Fri, Nov 11, 2022 at 03:43:54PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 11, 2022 at 02:37:13PM +0200, Imre Deak wrote:
> > On Thu, Nov 10, 2022 at 11:49:19PM +0200, Ville Syrjälä wrote:
> > > On Thu, Nov 10, 2022 at 09:55:55PM +0200, Imre Deak wrote:
> > > > On Thu, Nov 10, 2022 at 09:11:20PM +0200, Ville Syrjälä wrote:
> > > > > On Tue, Nov 08, 2022 at 05:18:23PM +0200, Imre Deak wrote:
> > > > > > Since the intel_display_power_domain_set struct, currently its current
> > > > > > size close to 1kB, can be allocated on the stack, it's better to
> > > > > > allocate the per-domain wakeref pointer array - used for debugging -
> > > > > > within the struct dynamically, so do this.
> > > > > > 
> > > > > > The memory freeing is guaranteed by the fact that the acquired domain
> > > > > > references tracked by the struct can't be leaked either.
> > > > > > 
> > > > > > v2:
> > > > > > - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> > > > > > - Simplify intel_display_power_get/put_in_set(). (Jani)
> > > > > > - Check in intel_crtc_destroy() that the wakerefs array has been freed.
> > > > > > v3:
> > > > > > - Add intel_display_power_set_disabled() and a separate assert
> > > > > >   function instead of open coding these. (Jani)
> > > > > > 
> > > > > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/display/intel_crtc.c     |  11 ++
> > > > > >  .../drm/i915/display/intel_display_power.c    | 109 ++++++++++++++----
> > > > > >  .../drm/i915/display/intel_display_power.h    |   6 +-
> > > > > >  3 files changed, 104 insertions(+), 22 deletions(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > index 037fc140b585c..c18d98bfe1a7c 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > @@ -21,6 +21,7 @@
> > > > > >  #include "intel_crtc.h"
> > > > > >  #include "intel_cursor.h"
> > > > > >  #include "intel_display_debugfs.h"
> > > > > > +#include "intel_display_power.h"
> > > > > >  #include "intel_display_trace.h"
> > > > > >  #include "intel_display_types.h"
> > > > > >  #include "intel_drrs.h"
> > > > > > @@ -37,6 +38,14 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
> > > > > >  		drm_crtc_vblank_put(crtc);
> > > > > >  }
> > > > > >  
> > > > > > +static void assert_power_domains_disabled(struct intel_crtc *crtc)
> > > > > > +{
> > > > > > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > > > > +
> > > > > > +	drm_WARN_ON(&i915->drm,
> > > > > > +		    !intel_display_power_set_disabled(i915, &crtc->enabled_power_domains));
> > > > > > +}
> > > > > > +
> > > > > >  struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
> > > > > >  {
> > > > > >  	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
> > > > > > @@ -204,6 +213,8 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
> > > > > >  
> > > > > >  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
> > > > > >  
> > > > > > +	assert_power_domains_disabled(crtc);
> > > > > > +
> > > > > >  	drm_crtc_cleanup(&crtc->base);
> > > > > >  	kfree(crtc);
> > > > > >  }
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > index 4c1de91e56ff9..ca63b4f1af41b 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
> > > > > >  }
> > > > > >  #endif
> > > > > >  
> > > > > > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > > > > > +static void
> > > > > > +add_domain_to_set(struct drm_i915_private *i915,
> > > > > > +		  struct intel_display_power_domain_set *power_domain_set,
> > > > > > +		  enum intel_display_power_domain domain,
> > > > > > +		  intel_wakeref_t wf)
> > > > > > +{
> > > > > > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > > > > > +
> > > > > > +	if (!power_domain_set->wakerefs)
> > > > > > +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> > > > > > +						     sizeof(*power_domain_set->wakerefs),
> > > > > > +						     GFP_KERNEL);
> > > > > > +
> > > > > > +	if (power_domain_set->wakerefs)
> > > > > > +		power_domain_set->wakerefs[domain] = wf;
> > > > > 
> > > > > So if the kcalloc() fails is it going to look like
> > > > > we're leaking power wakerefs?
> > > > 
> > > > Yes, along with the alloc failure which is also logged. I assumed this
> > > > is enough to explain why wakeref tracking doesn't work afterwards, but I
> > > > suppose the wakeref could be untracked here in this case.
> > > 
> > > I think a more clear message what is going on would be good.
> > > And probably preventing the spam from the wakerefs would
> > > also be good to make sure the whole thing doesn't get
> > > misdiagnosed as a real power ref leak.
> > 
> > Ok, I can add a debug print about the failure and untrack the wakeref.
> 
> The other idea that came to mind was to just preallocate this
> somehow. Looks like the only place where this even matters
> currently is hsw_get_pipe_config(). The other instance of
> this structure is already embedded in a kmalloced thing
> (struct intel_crtc).

Hmm. I wonder if this wakeref tracking is even really useful
in the readout path. We just do a put_all_in_set() in the end,
so can it even leak?

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Imre Deak]

On Fri, Nov 11, 2022 at 03:52:08PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 11, 2022 at 03:43:54PM +0200, Ville Syrjälä wrote:
> > On Fri, Nov 11, 2022 at 02:37:13PM +0200, Imre Deak wrote:
> > > On Thu, Nov 10, 2022 at 11:49:19PM +0200, Ville Syrjälä wrote:
> > > > On Thu, Nov 10, 2022 at 09:55:55PM +0200, Imre Deak wrote:
> > > > > On Thu, Nov 10, 2022 at 09:11:20PM +0200, Ville Syrjälä wrote:
> > > > > > On Tue, Nov 08, 2022 at 05:18:23PM +0200, Imre Deak wrote:
> > > > > > > Since the intel_display_power_domain_set struct, currently its current
> > > > > > > size close to 1kB, can be allocated on the stack, it's better to
> > > > > > > allocate the per-domain wakeref pointer array - used for debugging -
> > > > > > > within the struct dynamically, so do this.
> > > > > > > 
> > > > > > > The memory freeing is guaranteed by the fact that the acquired domain
> > > > > > > references tracked by the struct can't be leaked either.
> > > > > > > 
> > > > > > > v2:
> > > > > > > - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> > > > > > > - Simplify intel_display_power_get/put_in_set(). (Jani)
> > > > > > > - Check in intel_crtc_destroy() that the wakerefs array has been freed.
> > > > > > > v3:
> > > > > > > - Add intel_display_power_set_disabled() and a separate assert
> > > > > > >   function instead of open coding these. (Jani)
> > > > > > > 
> > > > > > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > > > ---
> > > > > > >  drivers/gpu/drm/i915/display/intel_crtc.c     |  11 ++
> > > > > > >  .../drm/i915/display/intel_display_power.c    | 109 ++++++++++++++----
> > > > > > >  .../drm/i915/display/intel_display_power.h    |   6 +-
> > > > > > >  3 files changed, 104 insertions(+), 22 deletions(-)
> > > > > > > 
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > index 037fc140b585c..c18d98bfe1a7c 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > @@ -21,6 +21,7 @@
> > > > > > >  #include "intel_crtc.h"
> > > > > > >  #include "intel_cursor.h"
> > > > > > >  #include "intel_display_debugfs.h"
> > > > > > > +#include "intel_display_power.h"
> > > > > > >  #include "intel_display_trace.h"
> > > > > > >  #include "intel_display_types.h"
> > > > > > >  #include "intel_drrs.h"
> > > > > > > @@ -37,6 +38,14 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
> > > > > > >  		drm_crtc_vblank_put(crtc);
> > > > > > >  }
> > > > > > >  
> > > > > > > +static void assert_power_domains_disabled(struct intel_crtc *crtc)
> > > > > > > +{
> > > > > > > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > > > > > +
> > > > > > > +	drm_WARN_ON(&i915->drm,
> > > > > > > +		    !intel_display_power_set_disabled(i915, &crtc->enabled_power_domains));
> > > > > > > +}
> > > > > > > +
> > > > > > >  struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
> > > > > > >  {
> > > > > > >  	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
> > > > > > > @@ -204,6 +213,8 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
> > > > > > >  
> > > > > > >  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
> > > > > > >  
> > > > > > > +	assert_power_domains_disabled(crtc);
> > > > > > > +
> > > > > > >  	drm_crtc_cleanup(&crtc->base);
> > > > > > >  	kfree(crtc);
> > > > > > >  }
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > index 4c1de91e56ff9..ca63b4f1af41b 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
> > > > > > >  }
> > > > > > >  #endif
> > > > > > >  
> > > > > > > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > > > > > > +static void
> > > > > > > +add_domain_to_set(struct drm_i915_private *i915,
> > > > > > > +		  struct intel_display_power_domain_set *power_domain_set,
> > > > > > > +		  enum intel_display_power_domain domain,
> > > > > > > +		  intel_wakeref_t wf)
> > > > > > > +{
> > > > > > > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > > > > > > +
> > > > > > > +	if (!power_domain_set->wakerefs)
> > > > > > > +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> > > > > > > +						     sizeof(*power_domain_set->wakerefs),
> > > > > > > +						     GFP_KERNEL);
> > > > > > > +
> > > > > > > +	if (power_domain_set->wakerefs)
> > > > > > > +		power_domain_set->wakerefs[domain] = wf;
> > > > > > 
> > > > > > So if the kcalloc() fails is it going to look like
> > > > > > we're leaking power wakerefs?
> > > > > 
> > > > > Yes, along with the alloc failure which is also logged. I assumed this
> > > > > is enough to explain why wakeref tracking doesn't work afterwards, but I
> > > > > suppose the wakeref could be untracked here in this case.
> > > > 
> > > > I think a more clear message what is going on would be good.
> > > > And probably preventing the spam from the wakerefs would
> > > > also be good to make sure the whole thing doesn't get
> > > > misdiagnosed as a real power ref leak.
> > > 
> > > Ok, I can add a debug print about the failure and untrack the wakeref.
> > 
> > The other idea that came to mind was to just preallocate this
> > somehow. Looks like the only place where this even matters
> > currently is hsw_get_pipe_config(). The other instance of
> > this structure is already embedded in a kmalloced thing
> > (struct intel_crtc).

Can't think of a good way to allocate the whole struct, as the domain
mask within it is still needed if the allocation failed. The API is
simpler imo if the allocation happens internally, but yes not a big
change if there is a good way to allocate only the array part.

> Hmm. I wonder if this wakeref tracking is even really useful
> in the readout path. We just do a put_all_in_set() in the end,
> so can it even leak?

If the function would incorrectly do an early return, the domains
wouldn't be put. I think it makes sense to keep wakerefs working for
this case as well.

> -- 
> Ville Syrjälä
> Intel

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Ville Syrjälä]

On Fri, Nov 11, 2022 at 05:47:05PM +0200, Imre Deak wrote:
> On Fri, Nov 11, 2022 at 03:52:08PM +0200, Ville Syrjälä wrote:
> > On Fri, Nov 11, 2022 at 03:43:54PM +0200, Ville Syrjälä wrote:
> > > On Fri, Nov 11, 2022 at 02:37:13PM +0200, Imre Deak wrote:
> > > > On Thu, Nov 10, 2022 at 11:49:19PM +0200, Ville Syrjälä wrote:
> > > > > On Thu, Nov 10, 2022 at 09:55:55PM +0200, Imre Deak wrote:
> > > > > > On Thu, Nov 10, 2022 at 09:11:20PM +0200, Ville Syrjälä wrote:
> > > > > > > On Tue, Nov 08, 2022 at 05:18:23PM +0200, Imre Deak wrote:
> > > > > > > > Since the intel_display_power_domain_set struct, currently its current
> > > > > > > > size close to 1kB, can be allocated on the stack, it's better to
> > > > > > > > allocate the per-domain wakeref pointer array - used for debugging -
> > > > > > > > within the struct dynamically, so do this.
> > > > > > > > 
> > > > > > > > The memory freeing is guaranteed by the fact that the acquired domain
> > > > > > > > references tracked by the struct can't be leaked either.
> > > > > > > > 
> > > > > > > > v2:
> > > > > > > > - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> > > > > > > > - Simplify intel_display_power_get/put_in_set(). (Jani)
> > > > > > > > - Check in intel_crtc_destroy() that the wakerefs array has been freed.
> > > > > > > > v3:
> > > > > > > > - Add intel_display_power_set_disabled() and a separate assert
> > > > > > > >   function instead of open coding these. (Jani)
> > > > > > > > 
> > > > > > > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > > > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > > > > ---
> > > > > > > >  drivers/gpu/drm/i915/display/intel_crtc.c     |  11 ++
> > > > > > > >  .../drm/i915/display/intel_display_power.c    | 109 ++++++++++++++----
> > > > > > > >  .../drm/i915/display/intel_display_power.h    |   6 +-
> > > > > > > >  3 files changed, 104 insertions(+), 22 deletions(-)
> > > > > > > > 
> > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > > index 037fc140b585c..c18d98bfe1a7c 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > > @@ -21,6 +21,7 @@
> > > > > > > >  #include "intel_crtc.h"
> > > > > > > >  #include "intel_cursor.h"
> > > > > > > >  #include "intel_display_debugfs.h"
> > > > > > > > +#include "intel_display_power.h"
> > > > > > > >  #include "intel_display_trace.h"
> > > > > > > >  #include "intel_display_types.h"
> > > > > > > >  #include "intel_drrs.h"
> > > > > > > > @@ -37,6 +38,14 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
> > > > > > > >  		drm_crtc_vblank_put(crtc);
> > > > > > > >  }
> > > > > > > >  
> > > > > > > > +static void assert_power_domains_disabled(struct intel_crtc *crtc)
> > > > > > > > +{
> > > > > > > > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > > > > > > +
> > > > > > > > +	drm_WARN_ON(&i915->drm,
> > > > > > > > +		    !intel_display_power_set_disabled(i915, &crtc->enabled_power_domains));
> > > > > > > > +}
> > > > > > > > +
> > > > > > > >  struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
> > > > > > > >  {
> > > > > > > >  	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
> > > > > > > > @@ -204,6 +213,8 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
> > > > > > > >  
> > > > > > > >  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
> > > > > > > >  
> > > > > > > > +	assert_power_domains_disabled(crtc);
> > > > > > > > +
> > > > > > > >  	drm_crtc_cleanup(&crtc->base);
> > > > > > > >  	kfree(crtc);
> > > > > > > >  }
> > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > > index 4c1de91e56ff9..ca63b4f1af41b 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > > @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
> > > > > > > >  }
> > > > > > > >  #endif
> > > > > > > >  
> > > > > > > > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > > > > > > > +static void
> > > > > > > > +add_domain_to_set(struct drm_i915_private *i915,
> > > > > > > > +		  struct intel_display_power_domain_set *power_domain_set,
> > > > > > > > +		  enum intel_display_power_domain domain,
> > > > > > > > +		  intel_wakeref_t wf)
> > > > > > > > +{
> > > > > > > > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > > > > > > > +
> > > > > > > > +	if (!power_domain_set->wakerefs)
> > > > > > > > +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> > > > > > > > +						     sizeof(*power_domain_set->wakerefs),
> > > > > > > > +						     GFP_KERNEL);
> > > > > > > > +
> > > > > > > > +	if (power_domain_set->wakerefs)
> > > > > > > > +		power_domain_set->wakerefs[domain] = wf;
> > > > > > > 
> > > > > > > So if the kcalloc() fails is it going to look like
> > > > > > > we're leaking power wakerefs?
> > > > > > 
> > > > > > Yes, along with the alloc failure which is also logged. I assumed this
> > > > > > is enough to explain why wakeref tracking doesn't work afterwards, but I
> > > > > > suppose the wakeref could be untracked here in this case.
> > > > > 
> > > > > I think a more clear message what is going on would be good.
> > > > > And probably preventing the spam from the wakerefs would
> > > > > also be good to make sure the whole thing doesn't get
> > > > > misdiagnosed as a real power ref leak.
> > > > 
> > > > Ok, I can add a debug print about the failure and untrack the wakeref.
> > > 
> > > The other idea that came to mind was to just preallocate this
> > > somehow. Looks like the only place where this even matters
> > > currently is hsw_get_pipe_config(). The other instance of
> > > this structure is already embedded in a kmalloced thing
> > > (struct intel_crtc).
> 
> Can't think of a good way to allocate the whole struct, as the domain
> mask within it is still needed if the allocation failed. The API is
> simpler imo if the allocation happens internally, but yes not a big
> change if there is a good way to allocate only the array part.

I mean just allocate eg. during driver init.

> 
> > Hmm. I wonder if this wakeref tracking is even really useful
> > in the readout path. We just do a put_all_in_set() in the end,
> > so can it even leak?
> 
> If the function would incorrectly do an early return, the domains
> wouldn't be put. I think it makes sense to keep wakerefs working for
> this case as well.
> 
> > -- 
> > Ville Syrjälä
> > Intel

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Imre Deak]

On Fri, Nov 11, 2022 at 08:30:41PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 11, 2022 at 05:47:05PM +0200, Imre Deak wrote:
> > On Fri, Nov 11, 2022 at 03:52:08PM +0200, Ville Syrjälä wrote:
> > > On Fri, Nov 11, 2022 at 03:43:54PM +0200, Ville Syrjälä wrote:
> > > > On Fri, Nov 11, 2022 at 02:37:13PM +0200, Imre Deak wrote:
> > > > > On Thu, Nov 10, 2022 at 11:49:19PM +0200, Ville Syrjälä wrote:
> > > > > > On Thu, Nov 10, 2022 at 09:55:55PM +0200, Imre Deak wrote:
> > > > > > > On Thu, Nov 10, 2022 at 09:11:20PM +0200, Ville Syrjälä wrote:
> > > > > > > > On Tue, Nov 08, 2022 at 05:18:23PM +0200, Imre Deak wrote:
> > > > > > > > > Since the intel_display_power_domain_set struct, currently its current
> > > > > > > > > size close to 1kB, can be allocated on the stack, it's better to
> > > > > > > > > allocate the per-domain wakeref pointer array - used for debugging -
> > > > > > > > > within the struct dynamically, so do this.
> > > > > > > > > 
> > > > > > > > > The memory freeing is guaranteed by the fact that the acquired domain
> > > > > > > > > references tracked by the struct can't be leaked either.
> > > > > > > > > 
> > > > > > > > > v2:
> > > > > > > > > - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> > > > > > > > > - Simplify intel_display_power_get/put_in_set(). (Jani)
> > > > > > > > > - Check in intel_crtc_destroy() that the wakerefs array has been freed.
> > > > > > > > > v3:
> > > > > > > > > - Add intel_display_power_set_disabled() and a separate assert
> > > > > > > > >   function instead of open coding these. (Jani)
> > > > > > > > > 
> > > > > > > > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > > > > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > > > > > ---
> > > > > > > > >  drivers/gpu/drm/i915/display/intel_crtc.c     |  11 ++
> > > > > > > > >  .../drm/i915/display/intel_display_power.c    | 109 ++++++++++++++----
> > > > > > > > >  .../drm/i915/display/intel_display_power.h    |   6 +-
> > > > > > > > >  3 files changed, 104 insertions(+), 22 deletions(-)
> > > > > > > > > 
> > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > > > index 037fc140b585c..c18d98bfe1a7c 100644
> > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > > > @@ -21,6 +21,7 @@
> > > > > > > > >  #include "intel_crtc.h"
> > > > > > > > >  #include "intel_cursor.h"
> > > > > > > > >  #include "intel_display_debugfs.h"
> > > > > > > > > +#include "intel_display_power.h"
> > > > > > > > >  #include "intel_display_trace.h"
> > > > > > > > >  #include "intel_display_types.h"
> > > > > > > > >  #include "intel_drrs.h"
> > > > > > > > > @@ -37,6 +38,14 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
> > > > > > > > >  		drm_crtc_vblank_put(crtc);
> > > > > > > > >  }
> > > > > > > > >  
> > > > > > > > > +static void assert_power_domains_disabled(struct intel_crtc *crtc)
> > > > > > > > > +{
> > > > > > > > > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > > > > > > > +
> > > > > > > > > +	drm_WARN_ON(&i915->drm,
> > > > > > > > > +		    !intel_display_power_set_disabled(i915, &crtc->enabled_power_domains));
> > > > > > > > > +}
> > > > > > > > > +
> > > > > > > > >  struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
> > > > > > > > >  {
> > > > > > > > >  	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
> > > > > > > > > @@ -204,6 +213,8 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
> > > > > > > > >  
> > > > > > > > >  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
> > > > > > > > >  
> > > > > > > > > +	assert_power_domains_disabled(crtc);
> > > > > > > > > +
> > > > > > > > >  	drm_crtc_cleanup(&crtc->base);
> > > > > > > > >  	kfree(crtc);
> > > > > > > > >  }
> > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > > > index 4c1de91e56ff9..ca63b4f1af41b 100644
> > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > > > @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
> > > > > > > > >  }
> > > > > > > > >  #endif
> > > > > > > > >  
> > > > > > > > > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > > > > > > > > +static void
> > > > > > > > > +add_domain_to_set(struct drm_i915_private *i915,
> > > > > > > > > +		  struct intel_display_power_domain_set *power_domain_set,
> > > > > > > > > +		  enum intel_display_power_domain domain,
> > > > > > > > > +		  intel_wakeref_t wf)
> > > > > > > > > +{
> > > > > > > > > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > > > > > > > > +
> > > > > > > > > +	if (!power_domain_set->wakerefs)
> > > > > > > > > +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> > > > > > > > > +						     sizeof(*power_domain_set->wakerefs),
> > > > > > > > > +						     GFP_KERNEL);
> > > > > > > > > +
> > > > > > > > > +	if (power_domain_set->wakerefs)
> > > > > > > > > +		power_domain_set->wakerefs[domain] = wf;
> > > > > > > > 
> > > > > > > > So if the kcalloc() fails is it going to look like
> > > > > > > > we're leaking power wakerefs?
> > > > > > > 
> > > > > > > Yes, along with the alloc failure which is also logged. I assumed this
> > > > > > > is enough to explain why wakeref tracking doesn't work afterwards, but I
> > > > > > > suppose the wakeref could be untracked here in this case.
> > > > > > 
> > > > > > I think a more clear message what is going on would be good.
> > > > > > And probably preventing the spam from the wakerefs would
> > > > > > also be good to make sure the whole thing doesn't get
> > > > > > misdiagnosed as a real power ref leak.
> > > > > 
> > > > > Ok, I can add a debug print about the failure and untrack the wakeref.
> > > > 
> > > > The other idea that came to mind was to just preallocate this
> > > > somehow. Looks like the only place where this even matters
> > > > currently is hsw_get_pipe_config(). The other instance of
> > > > this structure is already embedded in a kmalloced thing
> > > > (struct intel_crtc).
> > 
> > Can't think of a good way to allocate the whole struct, as the domain
> > mask within it is still needed if the allocation failed. The API is
> > simpler imo if the allocation happens internally, but yes not a big
> > change if there is a good way to allocate only the array part.
> 
> I mean just allocate eg. during driver init.

Ok, it'd work for this case if it's per-crtc. We could add a
'readout_hw_domains' power_domain_set struct to intel_crtc and simply
use that in hsw_get_pipe_config() instead of this patch, would that be
ok?

> > > Hmm. I wonder if this wakeref tracking is even really useful
> > > in the readout path. We just do a put_all_in_set() in the end,
> > > so can it even leak?
> > 
> > If the function would incorrectly do an early return, the domains
> > wouldn't be put. I think it makes sense to keep wakerefs working for
> > this case as well.
> > 
> > > -- 
> > > Ville Syrjälä
> > > Intel
> 
> -- 
> Ville Syrjälä
> Intel

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Ville Syrjälä]

On Fri, Nov 11, 2022 at 08:56:16PM +0200, Imre Deak wrote:
> On Fri, Nov 11, 2022 at 08:30:41PM +0200, Ville Syrjälä wrote:
> > On Fri, Nov 11, 2022 at 05:47:05PM +0200, Imre Deak wrote:
> > > On Fri, Nov 11, 2022 at 03:52:08PM +0200, Ville Syrjälä wrote:
> > > > On Fri, Nov 11, 2022 at 03:43:54PM +0200, Ville Syrjälä wrote:
> > > > > On Fri, Nov 11, 2022 at 02:37:13PM +0200, Imre Deak wrote:
> > > > > > On Thu, Nov 10, 2022 at 11:49:19PM +0200, Ville Syrjälä wrote:
> > > > > > > On Thu, Nov 10, 2022 at 09:55:55PM +0200, Imre Deak wrote:
> > > > > > > > On Thu, Nov 10, 2022 at 09:11:20PM +0200, Ville Syrjälä wrote:
> > > > > > > > > On Tue, Nov 08, 2022 at 05:18:23PM +0200, Imre Deak wrote:
> > > > > > > > > > Since the intel_display_power_domain_set struct, currently its current
> > > > > > > > > > size close to 1kB, can be allocated on the stack, it's better to
> > > > > > > > > > allocate the per-domain wakeref pointer array - used for debugging -
> > > > > > > > > > within the struct dynamically, so do this.
> > > > > > > > > > 
> > > > > > > > > > The memory freeing is guaranteed by the fact that the acquired domain
> > > > > > > > > > references tracked by the struct can't be leaked either.
> > > > > > > > > > 
> > > > > > > > > > v2:
> > > > > > > > > > - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> > > > > > > > > > - Simplify intel_display_power_get/put_in_set(). (Jani)
> > > > > > > > > > - Check in intel_crtc_destroy() that the wakerefs array has been freed.
> > > > > > > > > > v3:
> > > > > > > > > > - Add intel_display_power_set_disabled() and a separate assert
> > > > > > > > > >   function instead of open coding these. (Jani)
> > > > > > > > > > 
> > > > > > > > > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > > > > > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > > > > > > ---
> > > > > > > > > >  drivers/gpu/drm/i915/display/intel_crtc.c     |  11 ++
> > > > > > > > > >  .../drm/i915/display/intel_display_power.c    | 109 ++++++++++++++----
> > > > > > > > > >  .../drm/i915/display/intel_display_power.h    |   6 +-
> > > > > > > > > >  3 files changed, 104 insertions(+), 22 deletions(-)
> > > > > > > > > > 
> > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > > > > index 037fc140b585c..c18d98bfe1a7c 100644
> > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > > > > @@ -21,6 +21,7 @@
> > > > > > > > > >  #include "intel_crtc.h"
> > > > > > > > > >  #include "intel_cursor.h"
> > > > > > > > > >  #include "intel_display_debugfs.h"
> > > > > > > > > > +#include "intel_display_power.h"
> > > > > > > > > >  #include "intel_display_trace.h"
> > > > > > > > > >  #include "intel_display_types.h"
> > > > > > > > > >  #include "intel_drrs.h"
> > > > > > > > > > @@ -37,6 +38,14 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
> > > > > > > > > >  		drm_crtc_vblank_put(crtc);
> > > > > > > > > >  }
> > > > > > > > > >  
> > > > > > > > > > +static void assert_power_domains_disabled(struct intel_crtc *crtc)
> > > > > > > > > > +{
> > > > > > > > > > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > > > > > > > > +
> > > > > > > > > > +	drm_WARN_ON(&i915->drm,
> > > > > > > > > > +		    !intel_display_power_set_disabled(i915, &crtc->enabled_power_domains));
> > > > > > > > > > +}
> > > > > > > > > > +
> > > > > > > > > >  struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
> > > > > > > > > >  {
> > > > > > > > > >  	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
> > > > > > > > > > @@ -204,6 +213,8 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
> > > > > > > > > >  
> > > > > > > > > >  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
> > > > > > > > > >  
> > > > > > > > > > +	assert_power_domains_disabled(crtc);
> > > > > > > > > > +
> > > > > > > > > >  	drm_crtc_cleanup(&crtc->base);
> > > > > > > > > >  	kfree(crtc);
> > > > > > > > > >  }
> > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > > > > index 4c1de91e56ff9..ca63b4f1af41b 100644
> > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > > > > @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
> > > > > > > > > >  }
> > > > > > > > > >  #endif
> > > > > > > > > >  
> > > > > > > > > > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > > > > > > > > > +static void
> > > > > > > > > > +add_domain_to_set(struct drm_i915_private *i915,
> > > > > > > > > > +		  struct intel_display_power_domain_set *power_domain_set,
> > > > > > > > > > +		  enum intel_display_power_domain domain,
> > > > > > > > > > +		  intel_wakeref_t wf)
> > > > > > > > > > +{
> > > > > > > > > > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > > > > > > > > > +
> > > > > > > > > > +	if (!power_domain_set->wakerefs)
> > > > > > > > > > +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> > > > > > > > > > +						     sizeof(*power_domain_set->wakerefs),
> > > > > > > > > > +						     GFP_KERNEL);
> > > > > > > > > > +
> > > > > > > > > > +	if (power_domain_set->wakerefs)
> > > > > > > > > > +		power_domain_set->wakerefs[domain] = wf;
> > > > > > > > > 
> > > > > > > > > So if the kcalloc() fails is it going to look like
> > > > > > > > > we're leaking power wakerefs?
> > > > > > > > 
> > > > > > > > Yes, along with the alloc failure which is also logged. I assumed this
> > > > > > > > is enough to explain why wakeref tracking doesn't work afterwards, but I
> > > > > > > > suppose the wakeref could be untracked here in this case.
> > > > > > > 
> > > > > > > I think a more clear message what is going on would be good.
> > > > > > > And probably preventing the spam from the wakerefs would
> > > > > > > also be good to make sure the whole thing doesn't get
> > > > > > > misdiagnosed as a real power ref leak.
> > > > > > 
> > > > > > Ok, I can add a debug print about the failure and untrack the wakeref.
> > > > > 
> > > > > The other idea that came to mind was to just preallocate this
> > > > > somehow. Looks like the only place where this even matters
> > > > > currently is hsw_get_pipe_config(). The other instance of
> > > > > this structure is already embedded in a kmalloced thing
> > > > > (struct intel_crtc).
> > > 
> > > Can't think of a good way to allocate the whole struct, as the domain
> > > mask within it is still needed if the allocation failed. The API is
> > > simpler imo if the allocation happens internally, but yes not a big
> > > change if there is a good way to allocate only the array part.
> > 
> > I mean just allocate eg. during driver init.
> 
> Ok, it'd work for this case if it's per-crtc. We could add a
> 'readout_hw_domains' power_domain_set struct to intel_crtc and simply
> use that in hsw_get_pipe_config() instead of this patch, would that be
> ok?

That seems like an easier fix for now at least. I think we could
live with it. But if you can make the internal alloc handle the
failures a bit more gracefully I think that would be ok too.
I'll let you pick ;)

> 
> > > > Hmm. I wonder if this wakeref tracking is even really useful
> > > > in the readout path. We just do a put_all_in_set() in the end,
> > > > so can it even leak?
> > > 
> > > If the function would incorrectly do an early return, the domains
> > > wouldn't be put. I think it makes sense to keep wakerefs working for
> > > this case as well.
> > > 
> > > > -- 
> > > > Ville Syrjälä
> > > > Intel
> > 
> > -- 
> > Ville Syrjälä
> > Intel

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v3 1/9] drm/i915: Allocate power domain set wakerefs dynamically

[Imre Deak]

On Fri, Nov 11, 2022 at 09:23:59PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 11, 2022 at 08:56:16PM +0200, Imre Deak wrote:
> > On Fri, Nov 11, 2022 at 08:30:41PM +0200, Ville Syrjälä wrote:
> > > On Fri, Nov 11, 2022 at 05:47:05PM +0200, Imre Deak wrote:
> > > > On Fri, Nov 11, 2022 at 03:52:08PM +0200, Ville Syrjälä wrote:
> > > > > On Fri, Nov 11, 2022 at 03:43:54PM +0200, Ville Syrjälä wrote:
> > > > > > On Fri, Nov 11, 2022 at 02:37:13PM +0200, Imre Deak wrote:
> > > > > > > On Thu, Nov 10, 2022 at 11:49:19PM +0200, Ville Syrjälä wrote:
> > > > > > > > On Thu, Nov 10, 2022 at 09:55:55PM +0200, Imre Deak wrote:
> > > > > > > > > On Thu, Nov 10, 2022 at 09:11:20PM +0200, Ville Syrjälä wrote:
> > > > > > > > > > On Tue, Nov 08, 2022 at 05:18:23PM +0200, Imre Deak wrote:
> > > > > > > > > > > Since the intel_display_power_domain_set struct, currently its current
> > > > > > > > > > > size close to 1kB, can be allocated on the stack, it's better to
> > > > > > > > > > > allocate the per-domain wakeref pointer array - used for debugging -
> > > > > > > > > > > within the struct dynamically, so do this.
> > > > > > > > > > > 
> > > > > > > > > > > The memory freeing is guaranteed by the fact that the acquired domain
> > > > > > > > > > > references tracked by the struct can't be leaked either.
> > > > > > > > > > > 
> > > > > > > > > > > v2:
> > > > > > > > > > > - Don't use fetch_and_zero() when freeing the wakerefs array. (Jani)
> > > > > > > > > > > - Simplify intel_display_power_get/put_in_set(). (Jani)
> > > > > > > > > > > - Check in intel_crtc_destroy() that the wakerefs array has been freed.
> > > > > > > > > > > v3:
> > > > > > > > > > > - Add intel_display_power_set_disabled() and a separate assert
> > > > > > > > > > >   function instead of open coding these. (Jani)
> > > > > > > > > > > 
> > > > > > > > > > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > > > > > > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > > > > > > > ---
> > > > > > > > > > >  drivers/gpu/drm/i915/display/intel_crtc.c     |  11 ++
> > > > > > > > > > >  .../drm/i915/display/intel_display_power.c    | 109 ++++++++++++++----
> > > > > > > > > > >  .../drm/i915/display/intel_display_power.h    |   6 +-
> > > > > > > > > > >  3 files changed, 104 insertions(+), 22 deletions(-)
> > > > > > > > > > > 
> > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > > > > > index 037fc140b585c..c18d98bfe1a7c 100644
> > > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > > > > > @@ -21,6 +21,7 @@
> > > > > > > > > > >  #include "intel_crtc.h"
> > > > > > > > > > >  #include "intel_cursor.h"
> > > > > > > > > > >  #include "intel_display_debugfs.h"
> > > > > > > > > > > +#include "intel_display_power.h"
> > > > > > > > > > >  #include "intel_display_trace.h"
> > > > > > > > > > >  #include "intel_display_types.h"
> > > > > > > > > > >  #include "intel_drrs.h"
> > > > > > > > > > > @@ -37,6 +38,14 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
> > > > > > > > > > >  		drm_crtc_vblank_put(crtc);
> > > > > > > > > > >  }
> > > > > > > > > > >  
> > > > > > > > > > > +static void assert_power_domains_disabled(struct intel_crtc *crtc)
> > > > > > > > > > > +{
> > > > > > > > > > > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > > > > > > > > > +
> > > > > > > > > > > +	drm_WARN_ON(&i915->drm,
> > > > > > > > > > > +		    !intel_display_power_set_disabled(i915, &crtc->enabled_power_domains));
> > > > > > > > > > > +}
> > > > > > > > > > > +
> > > > > > > > > > >  struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915)
> > > > > > > > > > >  {
> > > > > > > > > > >  	return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0));
> > > > > > > > > > > @@ -204,6 +213,8 @@ static void intel_crtc_destroy(struct drm_crtc *_crtc)
> > > > > > > > > > >  
> > > > > > > > > > >  	cpu_latency_qos_remove_request(&crtc->vblank_pm_qos);
> > > > > > > > > > >  
> > > > > > > > > > > +	assert_power_domains_disabled(crtc);
> > > > > > > > > > > +
> > > > > > > > > > >  	drm_crtc_cleanup(&crtc->base);
> > > > > > > > > > >  	kfree(crtc);
> > > > > > > > > > >  }
> > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > > > > > index 4c1de91e56ff9..ca63b4f1af41b 100644
> > > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > > > > > > > @@ -830,20 +830,85 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
> > > > > > > > > > >  }
> > > > > > > > > > >  #endif
> > > > > > > > > > >  
> > > > > > > > > > > +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> > > > > > > > > > > +static void
> > > > > > > > > > > +add_domain_to_set(struct drm_i915_private *i915,
> > > > > > > > > > > +		  struct intel_display_power_domain_set *power_domain_set,
> > > > > > > > > > > +		  enum intel_display_power_domain domain,
> > > > > > > > > > > +		  intel_wakeref_t wf)
> > > > > > > > > > > +{
> > > > > > > > > > > +	drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
> > > > > > > > > > > +
> > > > > > > > > > > +	if (!power_domain_set->wakerefs)
> > > > > > > > > > > +		power_domain_set->wakerefs = kcalloc(POWER_DOMAIN_NUM,
> > > > > > > > > > > +						     sizeof(*power_domain_set->wakerefs),
> > > > > > > > > > > +						     GFP_KERNEL);
> > > > > > > > > > > +
> > > > > > > > > > > +	if (power_domain_set->wakerefs)
> > > > > > > > > > > +		power_domain_set->wakerefs[domain] = wf;
> > > > > > > > > > 
> > > > > > > > > > So if the kcalloc() fails is it going to look like
> > > > > > > > > > we're leaking power wakerefs?
> > > > > > > > > 
> > > > > > > > > Yes, along with the alloc failure which is also logged. I assumed this
> > > > > > > > > is enough to explain why wakeref tracking doesn't work afterwards, but I
> > > > > > > > > suppose the wakeref could be untracked here in this case.
> > > > > > > > 
> > > > > > > > I think a more clear message what is going on would be good.
> > > > > > > > And probably preventing the spam from the wakerefs would
> > > > > > > > also be good to make sure the whole thing doesn't get
> > > > > > > > misdiagnosed as a real power ref leak.
> > > > > > > 
> > > > > > > Ok, I can add a debug print about the failure and untrack the wakeref.
> > > > > > 
> > > > > > The other idea that came to mind was to just preallocate this
> > > > > > somehow. Looks like the only place where this even matters
> > > > > > currently is hsw_get_pipe_config(). The other instance of
> > > > > > this structure is already embedded in a kmalloced thing
> > > > > > (struct intel_crtc).
> > > > 
> > > > Can't think of a good way to allocate the whole struct, as the domain
> > > > mask within it is still needed if the allocation failed. The API is
> > > > simpler imo if the allocation happens internally, but yes not a big
> > > > change if there is a good way to allocate only the array part.
> > > 
> > > I mean just allocate eg. during driver init.
> > 
> > Ok, it'd work for this case if it's per-crtc. We could add a
> > 'readout_hw_domains' power_domain_set struct to intel_crtc and simply
> > use that in hsw_get_pipe_config() instead of this patch, would that be
> > ok?
> 
> That seems like an easier fix for now at least. I think we could
> live with it. But if you can make the internal alloc handle the
> failures a bit more gracefully I think that would be ok too.
> I'll let you pick ;)

Ok. The simpler approach looks better, making it more generic would make
sense only with more users for it.

> > > > > Hmm. I wonder if this wakeref tracking is even really useful
> > > > > in the readout path. We just do a put_all_in_set() in the end,
> > > > > so can it even leak?
> > > > 
> > > > If the function would incorrectly do an early return, the domains
> > > > wouldn't be put. I think it makes sense to keep wakerefs working for
> > > > this case as well.
> > > > 
> > > > > -- 
> > > > > Ville Syrjälä
> > > > > Intel
> > > 
> > > -- 
> > > Ville Syrjälä
> > > Intel
> 
> -- 
> Ville Syrjälä
> Intel