From: Mark Brown <broonie@kernel.org>
To: Rob Herring <robh@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>, Will Deacon <will@kernel.org>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Jiri Olsa <jolsa@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Mark Rutland <mark.rutland@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Ingo Molnar <mingo@redhat.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org,
linux-kernel@vger.kernel.org, James Clark <james.clark@arm.com>,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH v3 3/8] arm64/sysreg: Convert SPE registers to automatic generation
Date: Mon, 7 Nov 2022 15:11:07 +0000 [thread overview]
Message-ID: <Y2kgC9QlBwvXTLe6@sirena.org.uk> (raw)
In-Reply-To: <20220825-arm-spe-v8-7-v3-3-87682f78caac@kernel.org>
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On Fri, Nov 04, 2022 at 10:55:03AM -0500, Rob Herring wrote:
> Convert all the SPE register defines to automatic generation. No
> functional changes.
>
> New registers and fields for SPEv1.2 are added with the conversion.
>
> Some of the PMBSR MSS field defines are kept as the automatic generation
> has no way to create multiple names for the same register bits. The
> meaning of the MSS field depends on other bits.
Reviewed-by: Mark Brown <broonie@kernel.org>
> +Sysreg PMSNEVFR_EL1 3 0 9 9 1
> +Field 63:0 E
> +EndSysreg
JFTR as noted last time this looks nothing like the spec but is clearly
a sensible interpretation.
I do note that one advantage of doing this register by register rather
than en masse is that it makes it a lot easier to avoid re-reviewing the
same register...
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WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie@kernel.org>
To: Rob Herring <robh@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Catalin Marinas <catalin.marinas@arm.com>,
linux-kernel@vger.kernel.org,
Arnaldo Carvalho de Melo <acme@kernel.org>,
linux-perf-users@vger.kernel.org,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Ingo Molnar <mingo@redhat.com>, Jiri Olsa <jolsa@kernel.org>,
Marc Zyngier <maz@kernel.org>,
kvmarm@lists.linux.dev, Namhyung Kim <namhyung@kernel.org>,
Will Deacon <will@kernel.org>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org,
James Clark <james.clark@arm.com>
Subject: Re: [PATCH v3 3/8] arm64/sysreg: Convert SPE registers to automatic generation
Date: Mon, 7 Nov 2022 15:11:07 +0000 [thread overview]
Message-ID: <Y2kgC9QlBwvXTLe6@sirena.org.uk> (raw)
In-Reply-To: <20220825-arm-spe-v8-7-v3-3-87682f78caac@kernel.org>
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On Fri, Nov 04, 2022 at 10:55:03AM -0500, Rob Herring wrote:
> Convert all the SPE register defines to automatic generation. No
> functional changes.
>
> New registers and fields for SPEv1.2 are added with the conversion.
>
> Some of the PMBSR MSS field defines are kept as the automatic generation
> has no way to create multiple names for the same register bits. The
> meaning of the MSS field depends on other bits.
Reviewed-by: Mark Brown <broonie@kernel.org>
> +Sysreg PMSNEVFR_EL1 3 0 9 9 1
> +Field 63:0 E
> +EndSysreg
JFTR as noted last time this looks nothing like the spec but is clearly
a sensible interpretation.
I do note that one advantage of doing this register by register rather
than en masse is that it makes it a lot easier to avoid re-reviewing the
same register...
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WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie@kernel.org>
To: Rob Herring <robh@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>, Will Deacon <will@kernel.org>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Jiri Olsa <jolsa@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Mark Rutland <mark.rutland@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Ingo Molnar <mingo@redhat.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org,
linux-kernel@vger.kernel.org, James Clark <james.clark@arm.com>,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH v3 3/8] arm64/sysreg: Convert SPE registers to automatic generation
Date: Mon, 7 Nov 2022 15:11:07 +0000 [thread overview]
Message-ID: <Y2kgC9QlBwvXTLe6@sirena.org.uk> (raw)
In-Reply-To: <20220825-arm-spe-v8-7-v3-3-87682f78caac@kernel.org>
[-- Attachment #1.1: Type: text/plain, Size: 816 bytes --]
On Fri, Nov 04, 2022 at 10:55:03AM -0500, Rob Herring wrote:
> Convert all the SPE register defines to automatic generation. No
> functional changes.
>
> New registers and fields for SPEv1.2 are added with the conversion.
>
> Some of the PMBSR MSS field defines are kept as the automatic generation
> has no way to create multiple names for the same register bits. The
> meaning of the MSS field depends on other bits.
Reviewed-by: Mark Brown <broonie@kernel.org>
> +Sysreg PMSNEVFR_EL1 3 0 9 9 1
> +Field 63:0 E
> +EndSysreg
JFTR as noted last time this looks nothing like the spec but is clearly
a sensible interpretation.
I do note that one advantage of doing this register by register rather
than en masse is that it makes it a lot easier to avoid re-reviewing the
same register...
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[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-11-07 15:11 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-04 15:55 [PATCH v3 0/8] perf: Arm SPEv1.2 support Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` [PATCH v3 1/8] perf: arm_spe: Use feature numbering for PMSEVFR_EL1 defines Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` [PATCH v3 2/8] arm64: Drop SYS_ from SPE register defines Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` [PATCH v3 3/8] arm64/sysreg: Convert SPE registers to automatic generation Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-07 15:11 ` Mark Brown [this message]
2022-11-07 15:11 ` Mark Brown
2022-11-07 15:11 ` Mark Brown
2022-11-04 15:55 ` [PATCH v3 4/8] perf: arm_spe: Drop BIT() and use FIELD_GET/PREP accessors Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` [PATCH v3 5/8] perf: arm_spe: Use new PMSIDR_EL1 register enums Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` [PATCH v3 6/8] perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` [PATCH v3 7/8] perf: Add perf_event_attr::config3 Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-18 16:49 ` Will Deacon
2022-11-18 16:49 ` Will Deacon
2022-11-18 16:49 ` Will Deacon
2022-11-28 15:37 ` Rob Herring
2022-11-28 15:37 ` Rob Herring
2022-11-28 15:37 ` Rob Herring
2022-11-28 16:35 ` Alexander Shishkin
2022-11-28 16:35 ` Alexander Shishkin
2022-11-28 16:35 ` Alexander Shishkin
2022-11-28 17:15 ` Rob Herring
2022-11-28 17:15 ` Rob Herring
2022-11-28 17:15 ` Rob Herring
2022-12-06 16:28 ` Mark Rutland
2022-12-06 16:28 ` Mark Rutland
2022-12-06 16:28 ` Mark Rutland
2022-12-07 19:56 ` Rob Herring
2022-12-07 19:56 ` Rob Herring
2022-12-07 19:56 ` Rob Herring
2022-11-04 15:55 ` [PATCH v3 8/8] perf: arm_spe: Add support for SPEv1.2 inverted event filtering Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-04 15:55 ` Rob Herring
2022-11-07 19:48 ` Namhyung Kim
2022-11-07 19:48 ` Namhyung Kim
2022-11-07 19:48 ` Namhyung Kim
2022-11-08 13:12 ` Rob Herring
2022-11-08 13:12 ` Rob Herring
2022-11-08 13:12 ` Rob Herring
2022-11-17 14:43 ` [PATCH v3 0/8] perf: Arm SPEv1.2 support Rob Herring
2022-11-17 14:43 ` Rob Herring
2022-11-17 14:43 ` Rob Herring
2022-11-18 16:50 ` Will Deacon
2022-11-18 16:50 ` Will Deacon
2022-11-18 16:50 ` Will Deacon
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