* [PATCH v2 0/3] Add (more) missing PolarFire SoC io regions
@ 2022-11-12 13:34 Conor Dooley
2022-11-12 13:34 ` [PATCH v2 1/3] hw/misc/pfsoc: add fabric clocks to ioscb Conor Dooley
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Conor Dooley @ 2022-11-12 13:34 UTC (permalink / raw)
To: Bin Meng, Palmer Dabbelt, Alistair Francis
Cc: qemu-riscv, qemu-devel, Conor Dooley
From: Conor Dooley <conor.dooley@microchip.com>
Hey all,
But of a v2 of what I sent the other day [0]..
Apart from DDR (see [1]), these should be the last bits needed to get
recent Linux kernels booting again for Icicle/PolarFire SoC. Previously,
I had been disabling the hwrng and PCI but I keep forgetting that is
required and decided to fix that.
I'm not entirely sure if I have done some sort of no-no thing by
registering the same interrupt with both the IOSCB and SYSREG regions.
The interrupt is raised after the system controller handles a service
via the mailbox. The mailbox's status, control and mailbox registers
are all part of the IOSCB region. It's cleared by a write to a register
in the SYSREG region.
Since my goal here is to add the regions/peripherals without actually
implementing them so that Linux etc, I'm just raising an interrupt
once a guest requests a service & reporting a status indicating that the
service request failed.
Thanks,
Conor.
0 - https://lore.kernel.org/qemu-devel/20221109190849.1556711-1-conor@kernel.org/
1 - https://lore.kernel.org/all/Y2+dUCpd8OP52%2FDJ@spud/
Conor Dooley (3):
hw/misc/pfsoc: add fabric clocks to ioscb
hw/riscv: pfsoc: add missing FICs as unimplemented
hw/{misc,riscv}: pfsoc: add system controller as unimplemented
hw/misc/mchp_pfsoc_ioscb.c | 65 ++++++++++++++-
hw/misc/mchp_pfsoc_sysreg.c | 19 ++++-
hw/riscv/microchip_pfsoc.c | 121 ++++++++++++++++------------
include/hw/misc/mchp_pfsoc_ioscb.h | 4 +
include/hw/misc/mchp_pfsoc_sysreg.h | 1 +
include/hw/riscv/microchip_pfsoc.h | 3 +
6 files changed, 155 insertions(+), 58 deletions(-)
--
2.37.2
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v2 1/3] hw/misc/pfsoc: add fabric clocks to ioscb 2022-11-12 13:34 [PATCH v2 0/3] Add (more) missing PolarFire SoC io regions Conor Dooley @ 2022-11-12 13:34 ` Conor Dooley 2022-11-14 2:14 ` Alistair Francis 2022-11-12 13:34 ` [PATCH v2 2/3] hw/riscv: pfsoc: add missing FICs as unimplemented Conor Dooley 2022-11-12 13:34 ` [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller " Conor Dooley 2 siblings, 1 reply; 10+ messages in thread From: Conor Dooley @ 2022-11-12 13:34 UTC (permalink / raw) To: Bin Meng, Palmer Dabbelt, Alistair Francis Cc: qemu-riscv, qemu-devel, Conor Dooley From: Conor Dooley <conor.dooley@microchip.com> On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by "Clock Conditioning Circuitry" in the FPGA. The specific clock depends on the FPGA bitstream & can be locked to one particular {D,P}LL - in the Icicle Kit Reference Design v2022.09 or later this is/will be the case. Linux v6.1+ will have a driver for this peripheral and devicetrees that previously relied on "fixed-frequency" clock nodes have been switched over to clock-controller nodes. The IOSCB region is represented in QEMU, but the specific region of it that the CCCs occupy has not so v6.1-rcN kernels fail to boot in QEMU. Add the regions as unimplemented so that the status-quo in terms of boot is maintained. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- hw/misc/mchp_pfsoc_ioscb.c | 6 ++++++ include/hw/misc/mchp_pfsoc_ioscb.h | 1 + 2 files changed, 7 insertions(+) diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c index f4fd55a0e5..f976e42f72 100644 --- a/hw/misc/mchp_pfsoc_ioscb.c +++ b/hw/misc/mchp_pfsoc_ioscb.c @@ -33,6 +33,7 @@ */ #define IOSCB_WHOLE_REG_SIZE 0x10000000 #define IOSCB_SUBMOD_REG_SIZE 0x1000 +#define IOSCB_CCC_REG_SIZE 0x2000000 /* * There are many sub-modules in the IOSCB module. @@ -45,6 +46,7 @@ #define IOSCB_LANE23_BASE 0x06510000 #define IOSCB_CTRL_BASE 0x07020000 #define IOSCB_CFG_BASE 0x07080000 +#define IOSCB_CCC_BASE 0x08000000 #define IOSCB_PLL_MSS_BASE 0x0E001000 #define IOSCB_CFM_MSS_BASE 0x0E002000 #define IOSCB_PLL_DDR_BASE 0x0E010000 @@ -168,6 +170,10 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp) "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE); memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg); + memory_region_init_io(&s->ccc, OBJECT(s), &mchp_pfsoc_dummy_ops, s, + "mchp.pfsoc.ioscb.ccc", IOSCB_CCC_REG_SIZE); + memory_region_add_subregion(&s->container, IOSCB_CCC_BASE, &s->ccc); + memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s, "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE); memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss); diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h index 9235523e33..687b213742 100644 --- a/include/hw/misc/mchp_pfsoc_ioscb.h +++ b/include/hw/misc/mchp_pfsoc_ioscb.h @@ -30,6 +30,7 @@ typedef struct MchpPfSoCIoscbState { MemoryRegion lane23; MemoryRegion ctrl; MemoryRegion cfg; + MemoryRegion ccc; MemoryRegion pll_mss; MemoryRegion cfm_mss; MemoryRegion pll_ddr; -- 2.37.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/3] hw/misc/pfsoc: add fabric clocks to ioscb 2022-11-12 13:34 ` [PATCH v2 1/3] hw/misc/pfsoc: add fabric clocks to ioscb Conor Dooley @ 2022-11-14 2:14 ` Alistair Francis 0 siblings, 0 replies; 10+ messages in thread From: Alistair Francis @ 2022-11-14 2:14 UTC (permalink / raw) To: Conor Dooley Cc: Bin Meng, Palmer Dabbelt, Alistair Francis, qemu-riscv, qemu-devel, Conor Dooley On Sat, Nov 12, 2022 at 11:36 PM Conor Dooley <conor@kernel.org> wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > On PolarFire SoC, some peripherals (eg the PCI root port) are clocked by > "Clock Conditioning Circuitry" in the FPGA. The specific clock depends > on the FPGA bitstream & can be locked to one particular {D,P}LL - in the > Icicle Kit Reference Design v2022.09 or later this is/will be the case. > > Linux v6.1+ will have a driver for this peripheral and devicetrees that > previously relied on "fixed-frequency" clock nodes have been switched > over to clock-controller nodes. The IOSCB region is represented in QEMU, > but the specific region of it that the CCCs occupy has not so v6.1-rcN > kernels fail to boot in QEMU. > > Add the regions as unimplemented so that the status-quo in terms of boot > is maintained. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/misc/mchp_pfsoc_ioscb.c | 6 ++++++ > include/hw/misc/mchp_pfsoc_ioscb.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c > index f4fd55a0e5..f976e42f72 100644 > --- a/hw/misc/mchp_pfsoc_ioscb.c > +++ b/hw/misc/mchp_pfsoc_ioscb.c > @@ -33,6 +33,7 @@ > */ > #define IOSCB_WHOLE_REG_SIZE 0x10000000 > #define IOSCB_SUBMOD_REG_SIZE 0x1000 > +#define IOSCB_CCC_REG_SIZE 0x2000000 > > /* > * There are many sub-modules in the IOSCB module. > @@ -45,6 +46,7 @@ > #define IOSCB_LANE23_BASE 0x06510000 > #define IOSCB_CTRL_BASE 0x07020000 > #define IOSCB_CFG_BASE 0x07080000 > +#define IOSCB_CCC_BASE 0x08000000 > #define IOSCB_PLL_MSS_BASE 0x0E001000 > #define IOSCB_CFM_MSS_BASE 0x0E002000 > #define IOSCB_PLL_DDR_BASE 0x0E010000 > @@ -168,6 +170,10 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp) > "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE); > memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg); > > + memory_region_init_io(&s->ccc, OBJECT(s), &mchp_pfsoc_dummy_ops, s, > + "mchp.pfsoc.ioscb.ccc", IOSCB_CCC_REG_SIZE); > + memory_region_add_subregion(&s->container, IOSCB_CCC_BASE, &s->ccc); > + > memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s, > "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE); > memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss); > diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h > index 9235523e33..687b213742 100644 > --- a/include/hw/misc/mchp_pfsoc_ioscb.h > +++ b/include/hw/misc/mchp_pfsoc_ioscb.h > @@ -30,6 +30,7 @@ typedef struct MchpPfSoCIoscbState { > MemoryRegion lane23; > MemoryRegion ctrl; > MemoryRegion cfg; > + MemoryRegion ccc; > MemoryRegion pll_mss; > MemoryRegion cfm_mss; > MemoryRegion pll_ddr; > -- > 2.37.2 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/3] hw/riscv: pfsoc: add missing FICs as unimplemented 2022-11-12 13:34 [PATCH v2 0/3] Add (more) missing PolarFire SoC io regions Conor Dooley 2022-11-12 13:34 ` [PATCH v2 1/3] hw/misc/pfsoc: add fabric clocks to ioscb Conor Dooley @ 2022-11-12 13:34 ` Conor Dooley 2022-11-14 2:18 ` Alistair Francis 2022-11-12 13:34 ` [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller " Conor Dooley 2 siblings, 1 reply; 10+ messages in thread From: Conor Dooley @ 2022-11-12 13:34 UTC (permalink / raw) To: Bin Meng, Palmer Dabbelt, Alistair Francis Cc: qemu-riscv, qemu-devel, Conor Dooley From: Conor Dooley <conor.dooley@microchip.com> The Fabric Interconnect Controllers provide interfaces between the FPGA fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered 0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and does not show up on the MSS memory map. FIC4 is dedicated to the User Crypto Processor and does not show up on the MSS memory map either. FIC 0, 1 & 3 do show up in the MSS memory map and neither FICs 0 or 1 are represented in QEMU, leading to load access violations while booting Linux for Icicle if PCIe is enabled as the root port is connected via either FIC 0 or 1. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- hw/riscv/microchip_pfsoc.c | 115 ++++++++++++++++------------- include/hw/riscv/microchip_pfsoc.h | 2 + 2 files changed, 65 insertions(+), 52 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index a821263d4f..2a24e3437a 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -86,58 +86,61 @@ * describes the complete IOSCB modules memory maps */ static const MemMapEntry microchip_pfsoc_memmap[] = { - [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, - [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, - [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, - [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, - [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, - [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, - [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, - [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, - [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, - [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, - [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, - [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, - [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, - [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, - [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 }, - [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, - [MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 }, - [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, - [MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 }, - [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, - [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, - [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, - [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, - [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, - [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, - [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, - [MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 }, - [MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 }, - [MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 }, - [MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 }, - [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 }, - [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 }, - [MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 }, - [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, - [MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 }, - [MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 }, - [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, - [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, - [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, - [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, - [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, - [MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 }, - [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, - [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, - [MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 }, - [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, - [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, - [MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 }, - [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, - [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, - [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, - [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, + [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, + [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, + [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, + [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, + [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, + [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, + [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, + [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, + [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, + [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 }, + [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, + [MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 }, + [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, + [MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 }, + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, + [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, + [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, + [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, + [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, + [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, + [MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 }, + [MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 }, + [MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 }, + [MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 }, + [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 }, + [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 }, + [MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 }, + [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, + [MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 }, + [MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 }, + [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, + [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, + [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, + [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, + [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, + [MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 }, + [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, + [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, + [MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 }, + [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, + [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, + [MICROCHIP_PFSOC_FABRIC_FIC0] = { 0x2000000000, 0x1000000000 }, + [MICROCHIP_PFSOC_FABRIC_FIC1] = { 0x3000000000, 0x1000000000 }, + [MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 }, + [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, + [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, + [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, + [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, + }; static void microchip_pfsoc_soc_instance_init(Object *obj) @@ -461,6 +464,14 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) create_unimplemented_device("microchip.pfsoc.fabricfic3", memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base, memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size); + /* FPGA Fabric */ + create_unimplemented_device("microchip.pfsoc.fabricfic0", + memmap[MICROCHIP_PFSOC_FABRIC_FIC0].base, + memmap[MICROCHIP_PFSOC_FABRIC_FIC0].size); + /* FPGA Fabric */ + create_unimplemented_device("microchip.pfsoc.fabricfic1", + memmap[MICROCHIP_PFSOC_FABRIC_FIC1].base, + memmap[MICROCHIP_PFSOC_FABRIC_FIC1].size); /* QSPI Flash */ memory_region_init_rom(qspi_xip_mem, OBJECT(dev), diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index a757b240e0..7e7950dd36 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -121,6 +121,8 @@ enum { MICROCHIP_PFSOC_USB, MICROCHIP_PFSOC_QSPI_XIP, MICROCHIP_PFSOC_IOSCB, + MICROCHIP_PFSOC_FABRIC_FIC0, + MICROCHIP_PFSOC_FABRIC_FIC1, MICROCHIP_PFSOC_FABRIC_FIC3, MICROCHIP_PFSOC_DRAM_LO, MICROCHIP_PFSOC_DRAM_LO_ALIAS, -- 2.37.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] hw/riscv: pfsoc: add missing FICs as unimplemented 2022-11-12 13:34 ` [PATCH v2 2/3] hw/riscv: pfsoc: add missing FICs as unimplemented Conor Dooley @ 2022-11-14 2:18 ` Alistair Francis 0 siblings, 0 replies; 10+ messages in thread From: Alistair Francis @ 2022-11-14 2:18 UTC (permalink / raw) To: Conor Dooley Cc: Bin Meng, Palmer Dabbelt, Alistair Francis, qemu-riscv, qemu-devel, Conor Dooley On Sat, Nov 12, 2022 at 11:37 PM Conor Dooley <conor@kernel.org> wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > The Fabric Interconnect Controllers provide interfaces between the FPGA > fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered > 0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and > does not show up on the MSS memory map. FIC4 is dedicated to the User > Crypto Processor and does not show up on the MSS memory map either. > > FIC 0, 1 & 3 do show up in the MSS memory map and neither FICs 0 or 1 > are represented in QEMU, leading to load access violations while booting > Linux for Icicle if PCIe is enabled as the root port is connected via > either FIC 0 or 1. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/microchip_pfsoc.c | 115 ++++++++++++++++------------- > include/hw/riscv/microchip_pfsoc.h | 2 + > 2 files changed, 65 insertions(+), 52 deletions(-) > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index a821263d4f..2a24e3437a 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -86,58 +86,61 @@ > * describes the complete IOSCB modules memory maps > */ > static const MemMapEntry microchip_pfsoc_memmap[] = { > - [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, > - [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, > - [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, > - [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, > - [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, > - [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, > - [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, > - [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, > - [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, > - [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, > - [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, > - [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, > - [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, > - [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, > - [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 }, > - [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, > - [MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 }, > - [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, > - [MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 }, > - [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, > - [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, > - [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, > - [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, > - [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, > - [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, > - [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, > - [MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 }, > - [MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 }, > - [MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 }, > - [MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 }, > - [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 }, > - [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 }, > - [MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 }, > - [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, > - [MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 }, > - [MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 }, > - [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, > - [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, > - [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, > - [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, > - [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, > - [MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 }, > - [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, > - [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, > - [MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 }, > - [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, > - [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, > - [MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 }, > - [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, > - [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, > - [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, > - [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, > + [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, > + [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, > + [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, > + [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, > + [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, > + [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, > + [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, > + [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, > + [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, > + [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, > + [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, > + [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, > + [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, > + [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, > + [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 }, > + [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, > + [MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 }, > + [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, > + [MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 }, > + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, > + [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, > + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, > + [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, > + [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, > + [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, > + [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, > + [MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 }, > + [MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 }, > + [MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 }, > + [MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 }, > + [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 }, > + [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 }, > + [MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 }, > + [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, > + [MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 }, > + [MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 }, > + [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, > + [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, > + [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, > + [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, > + [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, > + [MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 }, > + [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, > + [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, > + [MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 }, > + [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, > + [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, > + [MICROCHIP_PFSOC_FABRIC_FIC0] = { 0x2000000000, 0x1000000000 }, > + [MICROCHIP_PFSOC_FABRIC_FIC1] = { 0x3000000000, 0x1000000000 }, > + [MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 }, > + [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, > + [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, > + [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, > + [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, > + > }; > > static void microchip_pfsoc_soc_instance_init(Object *obj) > @@ -461,6 +464,14 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) > create_unimplemented_device("microchip.pfsoc.fabricfic3", > memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base, > memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size); > + /* FPGA Fabric */ > + create_unimplemented_device("microchip.pfsoc.fabricfic0", > + memmap[MICROCHIP_PFSOC_FABRIC_FIC0].base, > + memmap[MICROCHIP_PFSOC_FABRIC_FIC0].size); > + /* FPGA Fabric */ > + create_unimplemented_device("microchip.pfsoc.fabricfic1", > + memmap[MICROCHIP_PFSOC_FABRIC_FIC1].base, > + memmap[MICROCHIP_PFSOC_FABRIC_FIC1].size); > > /* QSPI Flash */ > memory_region_init_rom(qspi_xip_mem, OBJECT(dev), > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h > index a757b240e0..7e7950dd36 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -121,6 +121,8 @@ enum { > MICROCHIP_PFSOC_USB, > MICROCHIP_PFSOC_QSPI_XIP, > MICROCHIP_PFSOC_IOSCB, > + MICROCHIP_PFSOC_FABRIC_FIC0, > + MICROCHIP_PFSOC_FABRIC_FIC1, > MICROCHIP_PFSOC_FABRIC_FIC3, > MICROCHIP_PFSOC_DRAM_LO, > MICROCHIP_PFSOC_DRAM_LO_ALIAS, > -- > 2.37.2 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller as unimplemented 2022-11-12 13:34 [PATCH v2 0/3] Add (more) missing PolarFire SoC io regions Conor Dooley 2022-11-12 13:34 ` [PATCH v2 1/3] hw/misc/pfsoc: add fabric clocks to ioscb Conor Dooley 2022-11-12 13:34 ` [PATCH v2 2/3] hw/riscv: pfsoc: add missing FICs as unimplemented Conor Dooley @ 2022-11-12 13:34 ` Conor Dooley 2022-11-13 19:30 ` Philippe Mathieu-Daudé 2022-11-17 17:00 ` Conor Dooley 2 siblings, 2 replies; 10+ messages in thread From: Conor Dooley @ 2022-11-12 13:34 UTC (permalink / raw) To: Bin Meng, Palmer Dabbelt, Alistair Francis Cc: qemu-riscv, qemu-devel, Conor Dooley From: Conor Dooley <conor.dooley@microchip.com> The system controller on PolarFire SoC is access via a mailbox. The control registers for this mailbox lie in the "IOSCB" region & the interrupt is cleared via write to the "SYSREG" region. It also has a QSPI controller, usually connected to a flash chip, that is used for storing FPGA bitstreams and used for In-Application Programming (IAP). Linux has an implementation of the system controller, through which the hwrng is accessed, leading to load/store access faults. Add the QSPI as unimplemented and a very basic (effectively unimplemented) version of the system controller's mailbox. Rather than purely marking the regions as unimplemented, service the mailbox requests by reporting failures and raising the interrupt so a guest can better handle the lack of support. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- hw/misc/mchp_pfsoc_ioscb.c | 59 ++++++++++++++++++++++++++++- hw/misc/mchp_pfsoc_sysreg.c | 19 ++++++++-- hw/riscv/microchip_pfsoc.c | 6 +++ include/hw/misc/mchp_pfsoc_ioscb.h | 3 ++ include/hw/misc/mchp_pfsoc_sysreg.h | 1 + include/hw/riscv/microchip_pfsoc.h | 1 + 6 files changed, 83 insertions(+), 6 deletions(-) diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c index f976e42f72..d7f27b4402 100644 --- a/hw/misc/mchp_pfsoc_ioscb.c +++ b/hw/misc/mchp_pfsoc_ioscb.c @@ -24,6 +24,7 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qapi/error.h" +#include "hw/irq.h" #include "hw/sysbus.h" #include "hw/misc/mchp_pfsoc_ioscb.h" @@ -34,6 +35,9 @@ #define IOSCB_WHOLE_REG_SIZE 0x10000000 #define IOSCB_SUBMOD_REG_SIZE 0x1000 #define IOSCB_CCC_REG_SIZE 0x2000000 +#define IOSCB_CTRL_REG_SIZE 0x800 +#define IOSCB_QSPIXIP_REG_SIZE 0x200 + /* * There are many sub-modules in the IOSCB module. @@ -45,6 +49,8 @@ #define IOSCB_LANE01_BASE 0x06500000 #define IOSCB_LANE23_BASE 0x06510000 #define IOSCB_CTRL_BASE 0x07020000 +#define IOSCB_QSPIXIP_BASE 0x07020100 +#define IOSCB_MAILBOX_BASE 0x07020800 #define IOSCB_CFG_BASE 0x07080000 #define IOSCB_CCC_BASE 0x08000000 #define IOSCB_PLL_MSS_BASE 0x0E001000 @@ -143,6 +149,45 @@ static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +#define SERVICES_SR 0x54 + +static uint64_t mchp_pfsoc_ctrl_read(void *opaque, hwaddr offset, + unsigned size) +{ + MchpPfSoCIoscbState *s = opaque; + uint32_t val = 0; + + switch (offset) { + case SERVICES_SR: + /* + * Although some services have no error codes, most do. All services + * that do implement errors, begin their error codes at 1. Treat all + * service requests as failures & return 1. + * See the "PolarFire® FPGA and PolarFire SoC FPGA System Services" + * user guide for more information on service error codes. + */ + val = 1; + qemu_irq_raise(s->irq); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " + "(size %d, offset 0x%" HWADDR_PRIx ")\n", + __func__, size, offset); + } + + return val; +} + +/* + * use the dummy write, since we are always going to report a failed message + * and therefore do not care what service is actually requested + */ +static const MemoryRegionOps mchp_pfsoc_ctrl_ops = { + .read = mchp_pfsoc_ctrl_read, + .write = mchp_pfsoc_dummy_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp) { MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev); @@ -162,10 +207,18 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp) "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE); memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23); - memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s, - "mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE); + memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_ctrl_ops, s, + "mchp.pfsoc.ioscb.ctrl", IOSCB_CTRL_REG_SIZE); memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl); + memory_region_init_io(&s->qspixip, OBJECT(s), &mchp_pfsoc_dummy_ops, s, + "mchp.pfsoc.ioscb.qspixip", IOSCB_QSPIXIP_REG_SIZE); + memory_region_add_subregion(&s->container, IOSCB_QSPIXIP_BASE, &s->qspixip); + + memory_region_init_io(&s->mailbox, OBJECT(s), &mchp_pfsoc_dummy_ops, s, + "mchp.pfsoc.ioscb.mailbox", IOSCB_SUBMOD_REG_SIZE); + memory_region_add_subregion(&s->container, IOSCB_MAILBOX_BASE, &s->mailbox); + memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s, "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE); memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg); @@ -222,6 +275,8 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp) IOSCB_SUBMOD_REG_SIZE); memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE, &s->io_calib_sgmii); + + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); } static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c index 89571eded5..9822fb05fd 100644 --- a/hw/misc/mchp_pfsoc_sysreg.c +++ b/hw/misc/mchp_pfsoc_sysreg.c @@ -24,10 +24,12 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qapi/error.h" +#include "hw/irq.h" #include "hw/sysbus.h" #include "hw/misc/mchp_pfsoc_sysreg.h" #define ENVM_CR 0xb8 +#define MESSAGE_INT 0x118c static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset, unsigned size) @@ -52,10 +54,18 @@ static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset, static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " - "(size %d, value 0x%" PRIx64 - ", offset 0x%" HWADDR_PRIx ")\n", - __func__, size, value, offset); + MchpPfSoCSysregState *s = opaque; + qemu_irq_lower(s->irq); + switch (offset) { + case MESSAGE_INT: + qemu_irq_lower(s->irq); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " + "(size %d, value 0x%" PRIx64 + ", offset 0x%" HWADDR_PRIx ")\n", + __func__, size, value, offset); + } } static const MemoryRegionOps mchp_pfsoc_sysreg_ops = { @@ -73,6 +83,7 @@ static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp) "mchp.pfsoc.sysreg", MCHP_PFSOC_SYSREG_REG_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg); + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); } static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 2a24e3437a..b10321b564 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -306,6 +306,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, memmap[MICROCHIP_PFSOC_SYSREG].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0, + qdev_get_gpio_in(DEVICE(s->plic), + MICROCHIP_PFSOC_MAILBOX_IRQ)); /* AXISW */ create_unimplemented_device("microchip.pfsoc.axisw", @@ -459,6 +462,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, memmap[MICROCHIP_PFSOC_IOSCB].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioscb), 0, + qdev_get_gpio_in(DEVICE(s->plic), + MICROCHIP_PFSOC_MAILBOX_IRQ)); /* FPGA Fabric */ create_unimplemented_device("microchip.pfsoc.fabricfic3", diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h index 687b213742..a1104862c8 100644 --- a/include/hw/misc/mchp_pfsoc_ioscb.h +++ b/include/hw/misc/mchp_pfsoc_ioscb.h @@ -29,6 +29,8 @@ typedef struct MchpPfSoCIoscbState { MemoryRegion lane01; MemoryRegion lane23; MemoryRegion ctrl; + MemoryRegion qspixip; + MemoryRegion mailbox; MemoryRegion cfg; MemoryRegion ccc; MemoryRegion pll_mss; @@ -41,6 +43,7 @@ typedef struct MchpPfSoCIoscbState { MemoryRegion cfm_sgmii; MemoryRegion bc_sgmii; MemoryRegion io_calib_sgmii; + qemu_irq irq; } MchpPfSoCIoscbState; #define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb" diff --git a/include/hw/misc/mchp_pfsoc_sysreg.h b/include/hw/misc/mchp_pfsoc_sysreg.h index 546ba68f6a..3cebe40ea9 100644 --- a/include/hw/misc/mchp_pfsoc_sysreg.h +++ b/include/hw/misc/mchp_pfsoc_sysreg.h @@ -28,6 +28,7 @@ typedef struct MchpPfSoCSysregState { SysBusDevice parent; MemoryRegion sysreg; + qemu_irq irq; } MchpPfSoCSysregState; #define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg" diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 7e7950dd36..69a686b54a 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -147,6 +147,7 @@ enum { MICROCHIP_PFSOC_MMUART2_IRQ = 92, MICROCHIP_PFSOC_MMUART3_IRQ = 93, MICROCHIP_PFSOC_MMUART4_IRQ = 94, + MICROCHIP_PFSOC_MAILBOX_IRQ = 96, }; #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 -- 2.37.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller as unimplemented 2022-11-12 13:34 ` [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller " Conor Dooley @ 2022-11-13 19:30 ` Philippe Mathieu-Daudé 2022-11-13 21:19 ` Conor Dooley 2022-11-17 17:00 ` Conor Dooley 1 sibling, 1 reply; 10+ messages in thread From: Philippe Mathieu-Daudé @ 2022-11-13 19:30 UTC (permalink / raw) To: Conor Dooley, Bin Meng, Palmer Dabbelt, Alistair Francis Cc: qemu-riscv, qemu-devel, Conor Dooley Hi Conor, On 12/11/22 14:34, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The system controller on PolarFire SoC is access via a mailbox. The > control registers for this mailbox lie in the "IOSCB" region & the > interrupt is cleared via write to the "SYSREG" region. It also has a > QSPI controller, usually connected to a flash chip, that is used for > storing FPGA bitstreams and used for In-Application Programming (IAP). > > Linux has an implementation of the system controller, through which the > hwrng is accessed, leading to load/store access faults. > > Add the QSPI as unimplemented and a very basic (effectively > unimplemented) version of the system controller's mailbox. Rather than > purely marking the regions as unimplemented, service the mailbox > requests by reporting failures and raising the interrupt so a guest can > better handle the lack of support. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > hw/misc/mchp_pfsoc_ioscb.c | 59 ++++++++++++++++++++++++++++- > hw/misc/mchp_pfsoc_sysreg.c | 19 ++++++++-- > hw/riscv/microchip_pfsoc.c | 6 +++ > include/hw/misc/mchp_pfsoc_ioscb.h | 3 ++ > include/hw/misc/mchp_pfsoc_sysreg.h | 1 + > include/hw/riscv/microchip_pfsoc.h | 1 + > 6 files changed, 83 insertions(+), 6 deletions(-) > @@ -52,10 +54,18 @@ static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset, > static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset, > uint64_t value, unsigned size) > { > - qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " > - "(size %d, value 0x%" PRIx64 > - ", offset 0x%" HWADDR_PRIx ")\n", > - __func__, size, value, offset); > + MchpPfSoCSysregState *s = opaque; > + qemu_irq_lower(s->irq); Is this always lowered IRQ line wanted? ... > + switch (offset) { > + case MESSAGE_INT: > + qemu_irq_lower(s->irq); ... since we do it here. > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " > + "(size %d, value 0x%" PRIx64 > + ", offset 0x%" HWADDR_PRIx ")\n", > + __func__, size, value, offset); > + } > } ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller as unimplemented 2022-11-13 19:30 ` Philippe Mathieu-Daudé @ 2022-11-13 21:19 ` Conor Dooley 0 siblings, 0 replies; 10+ messages in thread From: Conor Dooley @ 2022-11-13 21:19 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: Bin Meng, Palmer Dabbelt, Alistair Francis, qemu-riscv, qemu-devel, Conor Dooley On Sun, Nov 13, 2022 at 08:30:42PM +0100, Philippe Mathieu-Daudé wrote: > Hi Conor, > > On 12/11/22 14:34, Conor Dooley wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > > > The system controller on PolarFire SoC is access via a mailbox. The > > control registers for this mailbox lie in the "IOSCB" region & the > > interrupt is cleared via write to the "SYSREG" region. It also has a > > QSPI controller, usually connected to a flash chip, that is used for > > storing FPGA bitstreams and used for In-Application Programming (IAP). > > > > Linux has an implementation of the system controller, through which the > > hwrng is accessed, leading to load/store access faults. > > > > Add the QSPI as unimplemented and a very basic (effectively > > unimplemented) version of the system controller's mailbox. Rather than > > purely marking the regions as unimplemented, service the mailbox > > requests by reporting failures and raising the interrupt so a guest can > > better handle the lack of support. > > > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > --- > > hw/misc/mchp_pfsoc_ioscb.c | 59 ++++++++++++++++++++++++++++- > > hw/misc/mchp_pfsoc_sysreg.c | 19 ++++++++-- > > hw/riscv/microchip_pfsoc.c | 6 +++ > > include/hw/misc/mchp_pfsoc_ioscb.h | 3 ++ > > include/hw/misc/mchp_pfsoc_sysreg.h | 1 + > > include/hw/riscv/microchip_pfsoc.h | 1 + > > 6 files changed, 83 insertions(+), 6 deletions(-) > > > @@ -52,10 +54,18 @@ static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset, > > static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset, > > uint64_t value, unsigned size) > > { > > - qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " > > - "(size %d, value 0x%" PRIx64 > > - ", offset 0x%" HWADDR_PRIx ")\n", > > - __func__, size, value, offset); > > + MchpPfSoCSysregState *s = opaque; > > + qemu_irq_lower(s->irq); > > Is this always lowered IRQ line wanted? ... > > > + switch (offset) { > > + case MESSAGE_INT: > > + qemu_irq_lower(s->irq); > > ... since we do it here. Probably just me pressing the y key instead of the d one. I'll sort that out for v3, thanks! > > + break; > > + default: > > + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " > > + "(size %d, value 0x%" PRIx64 > > + ", offset 0x%" HWADDR_PRIx ")\n", > > + __func__, size, value, offset); > > + } > > } > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller as unimplemented 2022-11-12 13:34 ` [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller " Conor Dooley 2022-11-13 19:30 ` Philippe Mathieu-Daudé @ 2022-11-17 17:00 ` Conor Dooley 2022-11-18 7:04 ` Philippe Mathieu-Daudé 1 sibling, 1 reply; 10+ messages in thread From: Conor Dooley @ 2022-11-17 17:00 UTC (permalink / raw) To: Bin Meng, Palmer Dabbelt, Alistair Francis Cc: qemu-riscv, qemu-devel, Conor Dooley On Sat, Nov 12, 2022 at 01:34:15PM +0000, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The system controller on PolarFire SoC is access via a mailbox. The > control registers for this mailbox lie in the "IOSCB" region & the > interrupt is cleared via write to the "SYSREG" region. It also has a > QSPI controller, usually connected to a flash chip, that is used for > storing FPGA bitstreams and used for In-Application Programming (IAP). > > Linux has an implementation of the system controller, through which the > hwrng is accessed, leading to load/store access faults. > > Add the QSPI as unimplemented and a very basic (effectively > unimplemented) version of the system controller's mailbox. Rather than > purely marking the regions as unimplemented, service the mailbox > requests by reporting failures and raising the interrupt so a guest can > better handle the lack of support. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > hw/misc/mchp_pfsoc_ioscb.c | 59 ++++++++++++++++++++++++++++- > hw/misc/mchp_pfsoc_sysreg.c | 19 ++++++++-- > hw/riscv/microchip_pfsoc.c | 6 +++ > include/hw/misc/mchp_pfsoc_ioscb.h | 3 ++ > include/hw/misc/mchp_pfsoc_sysreg.h | 1 + > include/hw/riscv/microchip_pfsoc.h | 1 + > 6 files changed, 83 insertions(+), 6 deletions(-) > > diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c > index f976e42f72..d7f27b4402 100644 > --- a/hw/misc/mchp_pfsoc_ioscb.c > +++ b/hw/misc/mchp_pfsoc_ioscb.c > @@ -24,6 +24,7 @@ > #include "qemu/bitops.h" > #include "qemu/log.h" > #include "qapi/error.h" > +#include "hw/irq.h" > #include "hw/sysbus.h" > #include "hw/misc/mchp_pfsoc_ioscb.h" > > @@ -34,6 +35,9 @@ > #define IOSCB_WHOLE_REG_SIZE 0x10000000 > #define IOSCB_SUBMOD_REG_SIZE 0x1000 > #define IOSCB_CCC_REG_SIZE 0x2000000 > +#define IOSCB_CTRL_REG_SIZE 0x800 > +#define IOSCB_QSPIXIP_REG_SIZE 0x200 > + > > /* > * There are many sub-modules in the IOSCB module. > @@ -45,6 +49,8 @@ > #define IOSCB_LANE01_BASE 0x06500000 > #define IOSCB_LANE23_BASE 0x06510000 > #define IOSCB_CTRL_BASE 0x07020000 > +#define IOSCB_QSPIXIP_BASE 0x07020100 > +#define IOSCB_MAILBOX_BASE 0x07020800 > #define IOSCB_CFG_BASE 0x07080000 > #define IOSCB_CCC_BASE 0x08000000 > #define IOSCB_PLL_MSS_BASE 0x0E001000 > @@ -143,6 +149,45 @@ static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = { > .endianness = DEVICE_LITTLE_ENDIAN, > }; > > +#define SERVICES_SR 0x54 > + > +static uint64_t mchp_pfsoc_ctrl_read(void *opaque, hwaddr offset, > + unsigned size) > +{ > + MchpPfSoCIoscbState *s = opaque; > + uint32_t val = 0; > + > + switch (offset) { > + case SERVICES_SR: > + /* > + * Although some services have no error codes, most do. All services > + * that do implement errors, begin their error codes at 1. Treat all > + * service requests as failures & return 1. > + * See the "PolarFire® FPGA and PolarFire SoC FPGA System Services" > + * user guide for more information on service error codes. > + */ > + val = 1; Another issue I just spotted here, this should not be returning 1, but rather 1 << 16. The status bits are 31:16 & I was just getting lucky b/c of something wrong with the Linux driver exercising it! > + qemu_irq_raise(s->irq); > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " > + "(size %d, offset 0x%" HWADDR_PRIx ")\n", > + __func__, size, offset); > + } > + > + return val; > +} > + > +/* > + * use the dummy write, since we are always going to report a failed message > + * and therefore do not care what service is actually requested > + */ > +static const MemoryRegionOps mchp_pfsoc_ctrl_ops = { > + .read = mchp_pfsoc_ctrl_read, > + .write = mchp_pfsoc_dummy_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > +}; > + > static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp) > { > MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev); > @@ -162,10 +207,18 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp) > "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE); > memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23); > > - memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s, > - "mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE); > + memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_ctrl_ops, s, > + "mchp.pfsoc.ioscb.ctrl", IOSCB_CTRL_REG_SIZE); > memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl); > > + memory_region_init_io(&s->qspixip, OBJECT(s), &mchp_pfsoc_dummy_ops, s, > + "mchp.pfsoc.ioscb.qspixip", IOSCB_QSPIXIP_REG_SIZE); > + memory_region_add_subregion(&s->container, IOSCB_QSPIXIP_BASE, &s->qspixip); > + > + memory_region_init_io(&s->mailbox, OBJECT(s), &mchp_pfsoc_dummy_ops, s, > + "mchp.pfsoc.ioscb.mailbox", IOSCB_SUBMOD_REG_SIZE); > + memory_region_add_subregion(&s->container, IOSCB_MAILBOX_BASE, &s->mailbox); > + > memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s, > "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE); > memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg); > @@ -222,6 +275,8 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp) > IOSCB_SUBMOD_REG_SIZE); > memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE, > &s->io_calib_sgmii); > + > + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); > } > > static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data) > diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c > index 89571eded5..9822fb05fd 100644 > --- a/hw/misc/mchp_pfsoc_sysreg.c > +++ b/hw/misc/mchp_pfsoc_sysreg.c > @@ -24,10 +24,12 @@ > #include "qemu/bitops.h" > #include "qemu/log.h" > #include "qapi/error.h" > +#include "hw/irq.h" > #include "hw/sysbus.h" > #include "hw/misc/mchp_pfsoc_sysreg.h" > > #define ENVM_CR 0xb8 > +#define MESSAGE_INT 0x118c > > static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset, > unsigned size) > @@ -52,10 +54,18 @@ static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset, > static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset, > uint64_t value, unsigned size) > { > - qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " > - "(size %d, value 0x%" PRIx64 > - ", offset 0x%" HWADDR_PRIx ")\n", > - __func__, size, value, offset); > + MchpPfSoCSysregState *s = opaque; > + qemu_irq_lower(s->irq); > + switch (offset) { > + case MESSAGE_INT: > + qemu_irq_lower(s->irq); > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " > + "(size %d, value 0x%" PRIx64 > + ", offset 0x%" HWADDR_PRIx ")\n", > + __func__, size, value, offset); > + } > } > > static const MemoryRegionOps mchp_pfsoc_sysreg_ops = { > @@ -73,6 +83,7 @@ static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp) > "mchp.pfsoc.sysreg", > MCHP_PFSOC_SYSREG_REG_SIZE); > sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg); > + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); > } > > static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data) > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 2a24e3437a..b10321b564 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -306,6 +306,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) > sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); > sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, > memmap[MICROCHIP_PFSOC_SYSREG].base); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0, > + qdev_get_gpio_in(DEVICE(s->plic), > + MICROCHIP_PFSOC_MAILBOX_IRQ)); > > /* AXISW */ > create_unimplemented_device("microchip.pfsoc.axisw", > @@ -459,6 +462,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) > sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); > sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, > memmap[MICROCHIP_PFSOC_IOSCB].base); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioscb), 0, > + qdev_get_gpio_in(DEVICE(s->plic), > + MICROCHIP_PFSOC_MAILBOX_IRQ)); > > /* FPGA Fabric */ > create_unimplemented_device("microchip.pfsoc.fabricfic3", > diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h > index 687b213742..a1104862c8 100644 > --- a/include/hw/misc/mchp_pfsoc_ioscb.h > +++ b/include/hw/misc/mchp_pfsoc_ioscb.h > @@ -29,6 +29,8 @@ typedef struct MchpPfSoCIoscbState { > MemoryRegion lane01; > MemoryRegion lane23; > MemoryRegion ctrl; > + MemoryRegion qspixip; > + MemoryRegion mailbox; > MemoryRegion cfg; > MemoryRegion ccc; > MemoryRegion pll_mss; > @@ -41,6 +43,7 @@ typedef struct MchpPfSoCIoscbState { > MemoryRegion cfm_sgmii; > MemoryRegion bc_sgmii; > MemoryRegion io_calib_sgmii; > + qemu_irq irq; > } MchpPfSoCIoscbState; > > #define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb" > diff --git a/include/hw/misc/mchp_pfsoc_sysreg.h b/include/hw/misc/mchp_pfsoc_sysreg.h > index 546ba68f6a..3cebe40ea9 100644 > --- a/include/hw/misc/mchp_pfsoc_sysreg.h > +++ b/include/hw/misc/mchp_pfsoc_sysreg.h > @@ -28,6 +28,7 @@ > typedef struct MchpPfSoCSysregState { > SysBusDevice parent; > MemoryRegion sysreg; > + qemu_irq irq; > } MchpPfSoCSysregState; > > #define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg" > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h > index 7e7950dd36..69a686b54a 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -147,6 +147,7 @@ enum { > MICROCHIP_PFSOC_MMUART2_IRQ = 92, > MICROCHIP_PFSOC_MMUART3_IRQ = 93, > MICROCHIP_PFSOC_MMUART4_IRQ = 94, > + MICROCHIP_PFSOC_MAILBOX_IRQ = 96, > }; > > #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 > -- > 2.37.2 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller as unimplemented 2022-11-17 17:00 ` Conor Dooley @ 2022-11-18 7:04 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 10+ messages in thread From: Philippe Mathieu-Daudé @ 2022-11-18 7:04 UTC (permalink / raw) To: Conor Dooley, Bin Meng, Palmer Dabbelt, Alistair Francis Cc: qemu-riscv, qemu-devel, Conor Dooley On 17/11/22 18:00, Conor Dooley wrote: > On Sat, Nov 12, 2022 at 01:34:15PM +0000, Conor Dooley wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> The system controller on PolarFire SoC is access via a mailbox. The >> control registers for this mailbox lie in the "IOSCB" region & the >> interrupt is cleared via write to the "SYSREG" region. It also has a >> QSPI controller, usually connected to a flash chip, that is used for >> storing FPGA bitstreams and used for In-Application Programming (IAP). >> >> Linux has an implementation of the system controller, through which the >> hwrng is accessed, leading to load/store access faults. >> >> Add the QSPI as unimplemented and a very basic (effectively >> unimplemented) version of the system controller's mailbox. Rather than >> purely marking the regions as unimplemented, service the mailbox >> requests by reporting failures and raising the interrupt so a guest can >> better handle the lack of support. >> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> hw/misc/mchp_pfsoc_ioscb.c | 59 ++++++++++++++++++++++++++++- >> hw/misc/mchp_pfsoc_sysreg.c | 19 ++++++++-- >> hw/riscv/microchip_pfsoc.c | 6 +++ >> include/hw/misc/mchp_pfsoc_ioscb.h | 3 ++ >> include/hw/misc/mchp_pfsoc_sysreg.h | 1 + >> include/hw/riscv/microchip_pfsoc.h | 1 + >> 6 files changed, 83 insertions(+), 6 deletions(-) >> @@ -143,6 +149,45 @@ static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = { >> .endianness = DEVICE_LITTLE_ENDIAN, >> }; >> >> +#define SERVICES_SR 0x54 >> + >> +static uint64_t mchp_pfsoc_ctrl_read(void *opaque, hwaddr offset, >> + unsigned size) >> +{ >> + MchpPfSoCIoscbState *s = opaque; >> + uint32_t val = 0; >> + >> + switch (offset) { >> + case SERVICES_SR: >> + /* >> + * Although some services have no error codes, most do. All services >> + * that do implement errors, begin their error codes at 1. Treat all >> + * service requests as failures & return 1. >> + * See the "PolarFire® FPGA and PolarFire SoC FPGA System Services" >> + * user guide for more information on service error codes. >> + */ >> + val = 1; > > Another issue I just spotted here, this should not be returning 1, but > rather 1 << 16. The status bits are 31:16 & I was just getting lucky > b/c of something wrong with the Linux driver exercising it! So your implementation expects 32-bit accesses, thus ... >> + qemu_irq_raise(s->irq); >> + break; >> + default: >> + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " >> + "(size %d, offset 0x%" HWADDR_PRIx ")\n", >> + __func__, size, offset); >> + } >> + >> + return val; >> +} >> + >> +/* >> + * use the dummy write, since we are always going to report a failed message >> + * and therefore do not care what service is actually requested >> + */ >> +static const MemoryRegionOps mchp_pfsoc_ctrl_ops = { >> + .read = mchp_pfsoc_ctrl_read, >> + .write = mchp_pfsoc_dummy_write, >> + .endianness = DEVICE_LITTLE_ENDIAN, ... you might want to complete this with (at least): .impl.min_access_size = 4, And eventually if this region is only accessible as 32-bit: .valid.min_access_size = 4, >> +}; ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-11-18 7:05 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-12 13:34 [PATCH v2 0/3] Add (more) missing PolarFire SoC io regions Conor Dooley
2022-11-12 13:34 ` [PATCH v2 1/3] hw/misc/pfsoc: add fabric clocks to ioscb Conor Dooley
2022-11-14 2:14 ` Alistair Francis
2022-11-12 13:34 ` [PATCH v2 2/3] hw/riscv: pfsoc: add missing FICs as unimplemented Conor Dooley
2022-11-14 2:18 ` Alistair Francis
2022-11-12 13:34 ` [PATCH v2 3/3] hw/{misc, riscv}: pfsoc: add system controller " Conor Dooley
2022-11-13 19:30 ` Philippe Mathieu-Daudé
2022-11-13 21:19 ` Conor Dooley
2022-11-17 17:00 ` Conor Dooley
2022-11-18 7:04 ` Philippe Mathieu-Daudé
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