[PATCH v3 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add sm6350 compatible

[PATCH v3 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add sm6350 compatible

[Luca Weiss]

Add the compatible describing the combo phy found on SM6350.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes since v2:
* Drop misc schema changes again since same schema applies to sm6350

 .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
index 6f31693d9868..0764cd977e76 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
@@ -17,6 +17,7 @@ properties:
   compatible:
     enum:
       - qcom,sc8280xp-qmp-usb43dp-phy
+      - qcom,sm6350-qmp-usb3-dp-phy
 
   reg:
     maxItems: 1
-- 
2.38.1

[PATCH v3 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add sm6350 compatible

[Luca Weiss]

Add the compatible describing the combo phy found on SM6350.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes since v2:
* Drop misc schema changes again since same schema applies to sm6350

 .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
index 6f31693d9868..0764cd977e76 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
@@ -17,6 +17,7 @@ properties:
   compatible:
     enum:
       - qcom,sc8280xp-qmp-usb43dp-phy
+      - qcom,sm6350-qmp-usb3-dp-phy
 
   reg:
     maxItems: 1
-- 
2.38.1


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[PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Luca Weiss]

Add the tables and config for the combo phy found on SM6350.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes since v2:
* Drop dp_txa/dp_txb changes, not required
* Fix dp_dp_phy offset

 drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
 1 file changed, 126 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 77052c66cf70..6ac0c68269dc 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -311,6 +311,70 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 };
 
+static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
+};
+
+static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = {
+	/* FLL settings */
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+
+	/* Lock Det settings */
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
+
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04),
+
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
+};
+
 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
@@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
 	"phy",
 };
 
+static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
+	.com		= 0x0000,
+	.txa		= 0x1200,
+	.rxa		= 0x1400,
+	.txb		= 0x1600,
+	.rxb		= 0x1800,
+	.usb3_serdes	= 0x1000,
+	.usb3_pcs_misc	= 0x1a00,
+	.usb3_pcs	= 0x1c00,
+	.dp_serdes	= 0x1000,
+	.dp_dp_phy	= 0x2a00,
+};
+
 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
 	.com		= 0x0000,
 	.txa		= 0x0400,
@@ -1172,6 +1249,51 @@ static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = {
 	.regs			= qmp_v4_usb3phy_regs_layout,
 };
 
+static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
+	.offsets		= &qmp_combo_offsets_v3,
+
+	.serdes_tbl		= qmp_v3_usb3_serdes_tbl,
+	.serdes_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
+	.tx_tbl			= qmp_v3_usb3_tx_tbl,
+	.tx_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
+	.rx_tbl			= sm6350_usb3_rx_tbl,
+	.rx_tbl_num		= ARRAY_SIZE(sm6350_usb3_rx_tbl),
+	.pcs_tbl		= sm6350_usb3_pcs_tbl,
+	.pcs_tbl_num		= ARRAY_SIZE(sm6350_usb3_pcs_tbl),
+
+	.dp_serdes_tbl		= qmp_v3_dp_serdes_tbl,
+	.dp_serdes_tbl_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
+	.dp_tx_tbl		= qmp_v3_dp_tx_tbl,
+	.dp_tx_tbl_num		= ARRAY_SIZE(qmp_v3_dp_tx_tbl),
+
+	.serdes_tbl_rbr		= qmp_v3_dp_serdes_tbl_rbr,
+	.serdes_tbl_rbr_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
+	.serdes_tbl_hbr		= qmp_v3_dp_serdes_tbl_hbr,
+	.serdes_tbl_hbr_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
+	.serdes_tbl_hbr2	= qmp_v3_dp_serdes_tbl_hbr2,
+	.serdes_tbl_hbr2_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
+	.serdes_tbl_hbr3	= qmp_v3_dp_serdes_tbl_hbr3,
+	.serdes_tbl_hbr3_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
+
+	.swing_hbr_rbr		= &qmp_dp_v3_voltage_swing_hbr_rbr,
+	.pre_emphasis_hbr_rbr	= &qmp_dp_v3_pre_emphasis_hbr_rbr,
+	.swing_hbr3_hbr2	= &qmp_dp_v3_voltage_swing_hbr3_hbr2,
+	.pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
+
+	.dp_aux_init		= qmp_v3_dp_aux_init,
+	.configure_dp_tx	= qmp_v3_configure_dp_tx,
+	.configure_dp_phy	= qmp_v3_configure_dp_phy,
+	.calibrate_dp_phy	= qmp_v3_calibrate_dp_phy,
+
+	.clk_list		= qmp_v4_phy_clk_l,
+	.num_clks		= ARRAY_SIZE(qmp_v4_phy_clk_l),
+	.reset_list		= msm8996_usb3phy_reset_l,
+	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
+	.vreg_list		= qmp_phy_vreg_l,
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
+	.regs			= qmp_v3_usb3phy_regs_layout,
+};
+
 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
 	.serdes_tbl		= sm8150_usb3_serdes_tbl,
 	.serdes_tbl_num		= ARRAY_SIZE(sm8150_usb3_serdes_tbl),
@@ -2789,6 +2911,10 @@ static const struct of_device_id qmp_combo_of_match_table[] = {
 		.compatible = "qcom,sdm845-qmp-usb3-dp-phy",
 		.data = &sdm845_usb3dpphy_cfg,
 	},
+	{
+		.compatible = "qcom,sm6350-qmp-usb3-dp-phy",
+		.data = &sm6350_usb3dpphy_cfg,
+	},
 	{
 		.compatible = "qcom,sm8250-qmp-usb3-dp-phy",
 		.data = &sm8250_usb3dpphy_cfg,
-- 
2.38.1

[PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Luca Weiss]

Add the tables and config for the combo phy found on SM6350.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes since v2:
* Drop dp_txa/dp_txb changes, not required
* Fix dp_dp_phy offset

 drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
 1 file changed, 126 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 77052c66cf70..6ac0c68269dc 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -311,6 +311,70 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 };
 
+static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
+	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
+};
+
+static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = {
+	/* FLL settings */
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+
+	/* Lock Det settings */
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
+
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04),
+
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
+	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
+};
+
 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
@@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
 	"phy",
 };
 
+static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
+	.com		= 0x0000,
+	.txa		= 0x1200,
+	.rxa		= 0x1400,
+	.txb		= 0x1600,
+	.rxb		= 0x1800,
+	.usb3_serdes	= 0x1000,
+	.usb3_pcs_misc	= 0x1a00,
+	.usb3_pcs	= 0x1c00,
+	.dp_serdes	= 0x1000,
+	.dp_dp_phy	= 0x2a00,
+};
+
 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
 	.com		= 0x0000,
 	.txa		= 0x0400,
@@ -1172,6 +1249,51 @@ static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = {
 	.regs			= qmp_v4_usb3phy_regs_layout,
 };
 
+static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
+	.offsets		= &qmp_combo_offsets_v3,
+
+	.serdes_tbl		= qmp_v3_usb3_serdes_tbl,
+	.serdes_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
+	.tx_tbl			= qmp_v3_usb3_tx_tbl,
+	.tx_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
+	.rx_tbl			= sm6350_usb3_rx_tbl,
+	.rx_tbl_num		= ARRAY_SIZE(sm6350_usb3_rx_tbl),
+	.pcs_tbl		= sm6350_usb3_pcs_tbl,
+	.pcs_tbl_num		= ARRAY_SIZE(sm6350_usb3_pcs_tbl),
+
+	.dp_serdes_tbl		= qmp_v3_dp_serdes_tbl,
+	.dp_serdes_tbl_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
+	.dp_tx_tbl		= qmp_v3_dp_tx_tbl,
+	.dp_tx_tbl_num		= ARRAY_SIZE(qmp_v3_dp_tx_tbl),
+
+	.serdes_tbl_rbr		= qmp_v3_dp_serdes_tbl_rbr,
+	.serdes_tbl_rbr_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
+	.serdes_tbl_hbr		= qmp_v3_dp_serdes_tbl_hbr,
+	.serdes_tbl_hbr_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
+	.serdes_tbl_hbr2	= qmp_v3_dp_serdes_tbl_hbr2,
+	.serdes_tbl_hbr2_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
+	.serdes_tbl_hbr3	= qmp_v3_dp_serdes_tbl_hbr3,
+	.serdes_tbl_hbr3_num	= ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
+
+	.swing_hbr_rbr		= &qmp_dp_v3_voltage_swing_hbr_rbr,
+	.pre_emphasis_hbr_rbr	= &qmp_dp_v3_pre_emphasis_hbr_rbr,
+	.swing_hbr3_hbr2	= &qmp_dp_v3_voltage_swing_hbr3_hbr2,
+	.pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
+
+	.dp_aux_init		= qmp_v3_dp_aux_init,
+	.configure_dp_tx	= qmp_v3_configure_dp_tx,
+	.configure_dp_phy	= qmp_v3_configure_dp_phy,
+	.calibrate_dp_phy	= qmp_v3_calibrate_dp_phy,
+
+	.clk_list		= qmp_v4_phy_clk_l,
+	.num_clks		= ARRAY_SIZE(qmp_v4_phy_clk_l),
+	.reset_list		= msm8996_usb3phy_reset_l,
+	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
+	.vreg_list		= qmp_phy_vreg_l,
+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
+	.regs			= qmp_v3_usb3phy_regs_layout,
+};
+
 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
 	.serdes_tbl		= sm8150_usb3_serdes_tbl,
 	.serdes_tbl_num		= ARRAY_SIZE(sm8150_usb3_serdes_tbl),
@@ -2789,6 +2911,10 @@ static const struct of_device_id qmp_combo_of_match_table[] = {
 		.compatible = "qcom,sdm845-qmp-usb3-dp-phy",
 		.data = &sdm845_usb3dpphy_cfg,
 	},
+	{
+		.compatible = "qcom,sm6350-qmp-usb3-dp-phy",
+		.data = &sm6350_usb3dpphy_cfg,
+	},
 	{
 		.compatible = "qcom,sm8250-qmp-usb3-dp-phy",
 		.data = &sm8250_usb3dpphy_cfg,
-- 
2.38.1


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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Johan Hovold]

Luca, Vinod,

On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> Add the tables and config for the combo phy found on SM6350.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Changes since v2:
> * Drop dp_txa/dp_txb changes, not required
> * Fix dp_dp_phy offset
> 
>  drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
>  1 file changed, 126 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index 77052c66cf70..6ac0c68269dc 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c

> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
>  	"phy",
>  };
>  
> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> +	.com		= 0x0000,
> +	.txa		= 0x1200,
> +	.rxa		= 0x1400,
> +	.txb		= 0x1600,
> +	.rxb		= 0x1800,
> +	.usb3_serdes	= 0x1000,
> +	.usb3_pcs_misc	= 0x1a00,
> +	.usb3_pcs	= 0x1c00,
> +	.dp_serdes	= 0x1000,

I would have expected this to be 0x2000 as that's what the older
platforms have been using for the dp serdes table so far. Without access
to any documentation it's hard to tell whether everyone's just been
cargo-culting all along or if there's actually something there at offset
0x2000.

Vinod, could you shed some light on this as presumably you have access
to some documentation?

> +	.dp_dp_phy	= 0x2a00,
> +};

Johan

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Johan Hovold]

Luca, Vinod,

On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> Add the tables and config for the combo phy found on SM6350.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Changes since v2:
> * Drop dp_txa/dp_txb changes, not required
> * Fix dp_dp_phy offset
> 
>  drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
>  1 file changed, 126 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index 77052c66cf70..6ac0c68269dc 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c

> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
>  	"phy",
>  };
>  
> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> +	.com		= 0x0000,
> +	.txa		= 0x1200,
> +	.rxa		= 0x1400,
> +	.txb		= 0x1600,
> +	.rxb		= 0x1800,
> +	.usb3_serdes	= 0x1000,
> +	.usb3_pcs_misc	= 0x1a00,
> +	.usb3_pcs	= 0x1c00,
> +	.dp_serdes	= 0x1000,

I would have expected this to be 0x2000 as that's what the older
platforms have been using for the dp serdes table so far. Without access
to any documentation it's hard to tell whether everyone's just been
cargo-culting all along or if there's actually something there at offset
0x2000.

Vinod, could you shed some light on this as presumably you have access
to some documentation?

> +	.dp_dp_phy	= 0x2a00,
> +};

Johan

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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Luca Weiss]

Hi Johan,

On Wed Dec 28, 2022 at 3:17 PM CET, Johan Hovold wrote:
> Luca, Vinod,
>
> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> > Add the tables and config for the combo phy found on SM6350.
> > 
> > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > ---
> > Changes since v2:
> > * Drop dp_txa/dp_txb changes, not required
> > * Fix dp_dp_phy offset
> > 
> >  drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> >  1 file changed, 126 insertions(+)
> > 
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > index 77052c66cf70..6ac0c68269dc 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>
> > @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> >  	"phy",
> >  };
> >  
> > +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> > +	.com		= 0x0000,
> > +	.txa		= 0x1200,
> > +	.rxa		= 0x1400,
> > +	.txb		= 0x1600,
> > +	.rxb		= 0x1800,
> > +	.usb3_serdes	= 0x1000,
> > +	.usb3_pcs_misc	= 0x1a00,
> > +	.usb3_pcs	= 0x1c00,
> > +	.dp_serdes	= 0x1000,
>
> I would have expected this to be 0x2000 as that's what the older
> platforms have been using for the dp serdes table so far. Without access
> to any documentation it's hard to tell whether everyone's just been
> cargo-culting all along or if there's actually something there at offset
> 0x2000.

From what I saw comparing downstream code vs mainline 0x1000 should be
correct.

From https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-4.19/+/refs/heads/kernel/11/fp4/include/dt-bindings/phy/qcom,lagoon-qmp-usb3.h#38

USB3_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN (downstream 0x1034) =
  QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN (mainline 0x034)

USB3_DP_QSERDES_COM_CP_CTRL_MODE0 (downstream 0x1060) =
  QSERDES_V3_COM_CP_CTRL_MODE0 (mainline 0x060)

These defines downstream are used in qcom,qmp-phy-init-seq
(lagoon-usb.dtsi) which super abbreviated gets used like this:

lagoon-usb.dtsi:
    reg = <0x88e8000 0x3000>;
    reg-names = "qmp_phy_base";
    qcom,qmp-phy-init-seq = <...>;

drivers/usb/phy/phy-msm-ssusb-qmp.c
    res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
                        "qmp_phy_base");
    phy->base = devm_ioremap_nocache(dev, res->start, resource_size(res));

    of_property_read_u32_array(dev->of_node,
            "qcom,qmp-phy-init-seq",
            phy->qmp_phy_init_seq,
            phy->init_seq_len);

    reg = (struct qmp_reg_val *)phy->qmp_phy_init_seq;

    while (reg->offset != -1) {
        writel_relaxed(reg->val, phy->base + reg->offset);

I don't see anywhere where an extra 0x1000 should come from. But perhaps
I'm missing something. The reg address is the same downstream and
mainline also.

>
> Vinod, could you shed some light on this as presumably you have access
> to some documentation?

That would be useful :)

Regards
Luca

>
> > +	.dp_dp_phy	= 0x2a00,
> > +};
>
> Johan

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Luca Weiss]

Hi Johan,

On Wed Dec 28, 2022 at 3:17 PM CET, Johan Hovold wrote:
> Luca, Vinod,
>
> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> > Add the tables and config for the combo phy found on SM6350.
> > 
> > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > ---
> > Changes since v2:
> > * Drop dp_txa/dp_txb changes, not required
> > * Fix dp_dp_phy offset
> > 
> >  drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> >  1 file changed, 126 insertions(+)
> > 
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > index 77052c66cf70..6ac0c68269dc 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>
> > @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> >  	"phy",
> >  };
> >  
> > +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> > +	.com		= 0x0000,
> > +	.txa		= 0x1200,
> > +	.rxa		= 0x1400,
> > +	.txb		= 0x1600,
> > +	.rxb		= 0x1800,
> > +	.usb3_serdes	= 0x1000,
> > +	.usb3_pcs_misc	= 0x1a00,
> > +	.usb3_pcs	= 0x1c00,
> > +	.dp_serdes	= 0x1000,
>
> I would have expected this to be 0x2000 as that's what the older
> platforms have been using for the dp serdes table so far. Without access
> to any documentation it's hard to tell whether everyone's just been
> cargo-culting all along or if there's actually something there at offset
> 0x2000.

From what I saw comparing downstream code vs mainline 0x1000 should be
correct.

From https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-4.19/+/refs/heads/kernel/11/fp4/include/dt-bindings/phy/qcom,lagoon-qmp-usb3.h#38

USB3_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN (downstream 0x1034) =
  QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN (mainline 0x034)

USB3_DP_QSERDES_COM_CP_CTRL_MODE0 (downstream 0x1060) =
  QSERDES_V3_COM_CP_CTRL_MODE0 (mainline 0x060)

These defines downstream are used in qcom,qmp-phy-init-seq
(lagoon-usb.dtsi) which super abbreviated gets used like this:

lagoon-usb.dtsi:
    reg = <0x88e8000 0x3000>;
    reg-names = "qmp_phy_base";
    qcom,qmp-phy-init-seq = <...>;

drivers/usb/phy/phy-msm-ssusb-qmp.c
    res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
                        "qmp_phy_base");
    phy->base = devm_ioremap_nocache(dev, res->start, resource_size(res));

    of_property_read_u32_array(dev->of_node,
            "qcom,qmp-phy-init-seq",
            phy->qmp_phy_init_seq,
            phy->init_seq_len);

    reg = (struct qmp_reg_val *)phy->qmp_phy_init_seq;

    while (reg->offset != -1) {
        writel_relaxed(reg->val, phy->base + reg->offset);

I don't see anywhere where an extra 0x1000 should come from. But perhaps
I'm missing something. The reg address is the same downstream and
mainline also.

>
> Vinod, could you shed some light on this as presumably you have access
> to some documentation?

That would be useful :)

Regards
Luca

>
> > +	.dp_dp_phy	= 0x2a00,
> > +};
>
> Johan


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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Vinod Koul]

On 28-12-22, 15:17, Johan Hovold wrote:
> Luca, Vinod,
> 
> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> > Add the tables and config for the combo phy found on SM6350.
> > 
> > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > ---
> > Changes since v2:
> > * Drop dp_txa/dp_txb changes, not required
> > * Fix dp_dp_phy offset
> > 
> >  drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> >  1 file changed, 126 insertions(+)
> > 
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > index 77052c66cf70..6ac0c68269dc 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> 
> > @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> >  	"phy",
> >  };
> >  
> > +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> > +	.com		= 0x0000,
> > +	.txa		= 0x1200,
> > +	.rxa		= 0x1400,
> > +	.txb		= 0x1600,
> > +	.rxb		= 0x1800,
> > +	.usb3_serdes	= 0x1000,
> > +	.usb3_pcs_misc	= 0x1a00,
> > +	.usb3_pcs	= 0x1c00,
> > +	.dp_serdes	= 0x1000,
> 
> I would have expected this to be 0x2000 as that's what the older
> platforms have been using for the dp serdes table so far. Without access
> to any documentation it's hard to tell whether everyone's just been
> cargo-culting all along or if there's actually something there at offset
> 0x2000.
> 
> Vinod, could you shed some light on this as presumably you have access
> to some documentation?
> 
> > +	.dp_dp_phy	= 0x2a00,

No sorry, I dont have access to this version...

-- 
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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Vinod Koul]

On 28-12-22, 15:17, Johan Hovold wrote:
> Luca, Vinod,
> 
> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> > Add the tables and config for the combo phy found on SM6350.
> > 
> > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > ---
> > Changes since v2:
> > * Drop dp_txa/dp_txb changes, not required
> > * Fix dp_dp_phy offset
> > 
> >  drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> >  1 file changed, 126 insertions(+)
> > 
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > index 77052c66cf70..6ac0c68269dc 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> 
> > @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> >  	"phy",
> >  };
> >  
> > +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> > +	.com		= 0x0000,
> > +	.txa		= 0x1200,
> > +	.rxa		= 0x1400,
> > +	.txb		= 0x1600,
> > +	.rxb		= 0x1800,
> > +	.usb3_serdes	= 0x1000,
> > +	.usb3_pcs_misc	= 0x1a00,
> > +	.usb3_pcs	= 0x1c00,
> > +	.dp_serdes	= 0x1000,
> 
> I would have expected this to be 0x2000 as that's what the older
> platforms have been using for the dp serdes table so far. Without access
> to any documentation it's hard to tell whether everyone's just been
> cargo-culting all along or if there's actually something there at offset
> 0x2000.
> 
> Vinod, could you shed some light on this as presumably you have access
> to some documentation?
> 
> > +	.dp_dp_phy	= 0x2a00,

No sorry, I dont have access to this version...

-- 
~Vinod

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Dmitry Baryshkov]

On 12/01/2023 19:50, Vinod Koul wrote:
> On 28-12-22, 15:17, Johan Hovold wrote:
>> Luca, Vinod,
>>
>> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
>>> Add the tables and config for the combo phy found on SM6350.
>>>
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>> Changes since v2:
>>> * Drop dp_txa/dp_txb changes, not required
>>> * Fix dp_dp_phy offset
>>>
>>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
>>>   1 file changed, 126 insertions(+)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>> index 77052c66cf70..6ac0c68269dc 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>
>>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
>>>   	"phy",
>>>   };
>>>   
>>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
>>> +	.com		= 0x0000,
>>> +	.txa		= 0x1200,
>>> +	.rxa		= 0x1400,
>>> +	.txb		= 0x1600,
>>> +	.rxb		= 0x1800,
>>> +	.usb3_serdes	= 0x1000,
>>> +	.usb3_pcs_misc	= 0x1a00,
>>> +	.usb3_pcs	= 0x1c00,
>>> +	.dp_serdes	= 0x1000,
>>
>> I would have expected this to be 0x2000 as that's what the older
>> platforms have been using for the dp serdes table so far. Without access
>> to any documentation it's hard to tell whether everyone's just been
>> cargo-culting all along or if there's actually something there at offset
>> 0x2000.

usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.

Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So 
dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 = 
0x2600.

>>
>> Vinod, could you shed some light on this as presumably you have access
>> to some documentation?
>>
>>> +	.dp_dp_phy	= 0x2a00,
> 
> No sorry, I dont have access to this version...
> 

-- 
With best wishes
Dmitry

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Dmitry Baryshkov]

On 12/01/2023 19:50, Vinod Koul wrote:
> On 28-12-22, 15:17, Johan Hovold wrote:
>> Luca, Vinod,
>>
>> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
>>> Add the tables and config for the combo phy found on SM6350.
>>>
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>> Changes since v2:
>>> * Drop dp_txa/dp_txb changes, not required
>>> * Fix dp_dp_phy offset
>>>
>>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
>>>   1 file changed, 126 insertions(+)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>> index 77052c66cf70..6ac0c68269dc 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>
>>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
>>>   	"phy",
>>>   };
>>>   
>>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
>>> +	.com		= 0x0000,
>>> +	.txa		= 0x1200,
>>> +	.rxa		= 0x1400,
>>> +	.txb		= 0x1600,
>>> +	.rxb		= 0x1800,
>>> +	.usb3_serdes	= 0x1000,
>>> +	.usb3_pcs_misc	= 0x1a00,
>>> +	.usb3_pcs	= 0x1c00,
>>> +	.dp_serdes	= 0x1000,
>>
>> I would have expected this to be 0x2000 as that's what the older
>> platforms have been using for the dp serdes table so far. Without access
>> to any documentation it's hard to tell whether everyone's just been
>> cargo-culting all along or if there's actually something there at offset
>> 0x2000.

usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.

Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So 
dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 = 
0x2600.

>>
>> Vinod, could you shed some light on this as presumably you have access
>> to some documentation?
>>
>>> +	.dp_dp_phy	= 0x2a00,
> 
> No sorry, I dont have access to this version...
> 

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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Luca Weiss]

Hi Dmitry,

On Thu Jan 12, 2023 at 8:33 PM CET, Dmitry Baryshkov wrote:
> On 12/01/2023 19:50, Vinod Koul wrote:
> > On 28-12-22, 15:17, Johan Hovold wrote:
> >> Luca, Vinod,
> >>
> >> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> >>> Add the tables and config for the combo phy found on SM6350.
> >>>
> >>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> >>> ---
> >>> Changes since v2:
> >>> * Drop dp_txa/dp_txb changes, not required
> >>> * Fix dp_dp_phy offset
> >>>
> >>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> >>>   1 file changed, 126 insertions(+)
> >>>
> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> >>> index 77052c66cf70..6ac0c68269dc 100644
> >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> >>
> >>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> >>>   	"phy",
> >>>   };
> >>>   
> >>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> >>> +	.com		= 0x0000,
> >>> +	.txa		= 0x1200,
> >>> +	.rxa		= 0x1400,
> >>> +	.txb		= 0x1600,
> >>> +	.rxb		= 0x1800,
> >>> +	.usb3_serdes	= 0x1000,
> >>> +	.usb3_pcs_misc	= 0x1a00,
> >>> +	.usb3_pcs	= 0x1c00,
> >>> +	.dp_serdes	= 0x1000,
> >>
> >> I would have expected this to be 0x2000 as that's what the older
> >> platforms have been using for the dp serdes table so far. Without access
> >> to any documentation it's hard to tell whether everyone's just been
> >> cargo-culting all along or if there's actually something there at offset
> >> 0x2000.
>
> usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.
>
> Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So 
> dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 = 
> 0x2600.

Can you share how you got to the 0x2000 offset? You can see my
(potentially wrong) reasoning for 0x1000 a few messages ago[0].

The only 0x2000-something I could find now while looking at it again is
"#define USB3_DP_PHY_DP_DP_PHY_PD_CTL 0x2a18" which becomes
USB3_DP_DP_PHY_PD_CTL in the driver but this is seemingly not used at
all in my msm-4.19 tree.

Also if you have any idea on how to test it at runtime without actually
having to get all the type-C functionality up I'd be happy to try that.
Unfortunately I believe there's still quite some bits missing to
actually get DP out via the USB-C port - which I imagine would trigger
the PHY setup.

[0] https://lore.kernel.org/linux-arm-msm/CPDIYQ3SSY3E.I0Y0NMIED0WO@otso/

Regards
Luca

>
> >>
> >> Vinod, could you shed some light on this as presumably you have access
> >> to some documentation?
> >>
> >>> +	.dp_dp_phy	= 0x2a00,
> > 
> > No sorry, I dont have access to this version...
> > 
>
> -- 
> With best wishes
> Dmitry


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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Luca Weiss]

Hi Dmitry,

On Thu Jan 12, 2023 at 8:33 PM CET, Dmitry Baryshkov wrote:
> On 12/01/2023 19:50, Vinod Koul wrote:
> > On 28-12-22, 15:17, Johan Hovold wrote:
> >> Luca, Vinod,
> >>
> >> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> >>> Add the tables and config for the combo phy found on SM6350.
> >>>
> >>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> >>> ---
> >>> Changes since v2:
> >>> * Drop dp_txa/dp_txb changes, not required
> >>> * Fix dp_dp_phy offset
> >>>
> >>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> >>>   1 file changed, 126 insertions(+)
> >>>
> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> >>> index 77052c66cf70..6ac0c68269dc 100644
> >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> >>
> >>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> >>>   	"phy",
> >>>   };
> >>>   
> >>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> >>> +	.com		= 0x0000,
> >>> +	.txa		= 0x1200,
> >>> +	.rxa		= 0x1400,
> >>> +	.txb		= 0x1600,
> >>> +	.rxb		= 0x1800,
> >>> +	.usb3_serdes	= 0x1000,
> >>> +	.usb3_pcs_misc	= 0x1a00,
> >>> +	.usb3_pcs	= 0x1c00,
> >>> +	.dp_serdes	= 0x1000,
> >>
> >> I would have expected this to be 0x2000 as that's what the older
> >> platforms have been using for the dp serdes table so far. Without access
> >> to any documentation it's hard to tell whether everyone's just been
> >> cargo-culting all along or if there's actually something there at offset
> >> 0x2000.
>
> usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.
>
> Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So 
> dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 = 
> 0x2600.

Can you share how you got to the 0x2000 offset? You can see my
(potentially wrong) reasoning for 0x1000 a few messages ago[0].

The only 0x2000-something I could find now while looking at it again is
"#define USB3_DP_PHY_DP_DP_PHY_PD_CTL 0x2a18" which becomes
USB3_DP_DP_PHY_PD_CTL in the driver but this is seemingly not used at
all in my msm-4.19 tree.

Also if you have any idea on how to test it at runtime without actually
having to get all the type-C functionality up I'd be happy to try that.
Unfortunately I believe there's still quite some bits missing to
actually get DP out via the USB-C port - which I imagine would trigger
the PHY setup.

[0] https://lore.kernel.org/linux-arm-msm/CPDIYQ3SSY3E.I0Y0NMIED0WO@otso/

Regards
Luca

>
> >>
> >> Vinod, could you shed some light on this as presumably you have access
> >> to some documentation?
> >>
> >>> +	.dp_dp_phy	= 0x2a00,
> > 
> > No sorry, I dont have access to this version...
> > 
>
> -- 
> With best wishes
> Dmitry

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Dmitry Baryshkov]

On Fri, 13 Jan 2023 at 14:44, Luca Weiss <luca.weiss@fairphone.com> wrote:
>
> Hi Dmitry,
>
> On Thu Jan 12, 2023 at 8:33 PM CET, Dmitry Baryshkov wrote:
> > On 12/01/2023 19:50, Vinod Koul wrote:
> > > On 28-12-22, 15:17, Johan Hovold wrote:
> > >> Luca, Vinod,
> > >>
> > >> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> > >>> Add the tables and config for the combo phy found on SM6350.
> > >>>
> > >>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > >>> ---
> > >>> Changes since v2:
> > >>> * Drop dp_txa/dp_txb changes, not required
> > >>> * Fix dp_dp_phy offset
> > >>>
> > >>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> > >>>   1 file changed, 126 insertions(+)
> > >>>
> > >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > >>> index 77052c66cf70..6ac0c68269dc 100644
> > >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > >>
> > >>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> > >>>           "phy",
> > >>>   };
> > >>>
> > >>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> > >>> + .com            = 0x0000,
> > >>> + .txa            = 0x1200,
> > >>> + .rxa            = 0x1400,
> > >>> + .txb            = 0x1600,
> > >>> + .rxb            = 0x1800,
> > >>> + .usb3_serdes    = 0x1000,
> > >>> + .usb3_pcs_misc  = 0x1a00,
> > >>> + .usb3_pcs       = 0x1c00,
> > >>> + .dp_serdes      = 0x1000,
> > >>
> > >> I would have expected this to be 0x2000 as that's what the older
> > >> platforms have been using for the dp serdes table so far. Without access
> > >> to any documentation it's hard to tell whether everyone's just been
> > >> cargo-culting all along or if there's actually something there at offset
> > >> 0x2000.
> >
> > usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.
> >
> > Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So
> > dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 =
> > 0x2600.
>
> Can you share how you got to the 0x2000 offset? You can see my
> (potentially wrong) reasoning for 0x1000 a few messages ago[0].
>
> The only 0x2000-something I could find now while looking at it again is
> "#define USB3_DP_PHY_DP_DP_PHY_PD_CTL 0x2a18" which becomes
> USB3_DP_DP_PHY_PD_CTL in the driver but this is seemingly not used at
> all in my msm-4.19 tree.

Quite simple: see [1]. DP_PLL is at +0x2000

[1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/lagoon-sde-pll.dtsi#27

Anyway, having DP serdes at the space as USB3 serdes would mean that
one would be setting USB3 PLL when trying to enable DP. So I could
have said even w/o looking at the dtsi that dp serdes can _not_ be at
0x1000.

>
> Also if you have any idea on how to test it at runtime without actually
> having to get all the type-C functionality up I'd be happy to try that.
> Unfortunately I believe there's still quite some bits missing to
> actually get DP out via the USB-C port - which I imagine would trigger
> the PHY setup.

Unfortunately, I don't have a recipe to test this.

>
> [0] https://lore.kernel.org/linux-arm-msm/CPDIYQ3SSY3E.I0Y0NMIED0WO@otso/
>
> Regards
> Luca


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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Dmitry Baryshkov]

On Fri, 13 Jan 2023 at 14:44, Luca Weiss <luca.weiss@fairphone.com> wrote:
>
> Hi Dmitry,
>
> On Thu Jan 12, 2023 at 8:33 PM CET, Dmitry Baryshkov wrote:
> > On 12/01/2023 19:50, Vinod Koul wrote:
> > > On 28-12-22, 15:17, Johan Hovold wrote:
> > >> Luca, Vinod,
> > >>
> > >> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> > >>> Add the tables and config for the combo phy found on SM6350.
> > >>>
> > >>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > >>> ---
> > >>> Changes since v2:
> > >>> * Drop dp_txa/dp_txb changes, not required
> > >>> * Fix dp_dp_phy offset
> > >>>
> > >>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> > >>>   1 file changed, 126 insertions(+)
> > >>>
> > >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > >>> index 77052c66cf70..6ac0c68269dc 100644
> > >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > >>
> > >>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> > >>>           "phy",
> > >>>   };
> > >>>
> > >>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> > >>> + .com            = 0x0000,
> > >>> + .txa            = 0x1200,
> > >>> + .rxa            = 0x1400,
> > >>> + .txb            = 0x1600,
> > >>> + .rxb            = 0x1800,
> > >>> + .usb3_serdes    = 0x1000,
> > >>> + .usb3_pcs_misc  = 0x1a00,
> > >>> + .usb3_pcs       = 0x1c00,
> > >>> + .dp_serdes      = 0x1000,
> > >>
> > >> I would have expected this to be 0x2000 as that's what the older
> > >> platforms have been using for the dp serdes table so far. Without access
> > >> to any documentation it's hard to tell whether everyone's just been
> > >> cargo-culting all along or if there's actually something there at offset
> > >> 0x2000.
> >
> > usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.
> >
> > Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So
> > dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 =
> > 0x2600.
>
> Can you share how you got to the 0x2000 offset? You can see my
> (potentially wrong) reasoning for 0x1000 a few messages ago[0].
>
> The only 0x2000-something I could find now while looking at it again is
> "#define USB3_DP_PHY_DP_DP_PHY_PD_CTL 0x2a18" which becomes
> USB3_DP_DP_PHY_PD_CTL in the driver but this is seemingly not used at
> all in my msm-4.19 tree.

Quite simple: see [1]. DP_PLL is at +0x2000

[1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/lagoon-sde-pll.dtsi#27

Anyway, having DP serdes at the space as USB3 serdes would mean that
one would be setting USB3 PLL when trying to enable DP. So I could
have said even w/o looking at the dtsi that dp serdes can _not_ be at
0x1000.

>
> Also if you have any idea on how to test it at runtime without actually
> having to get all the type-C functionality up I'd be happy to try that.
> Unfortunately I believe there's still quite some bits missing to
> actually get DP out via the USB-C port - which I imagine would trigger
> the PHY setup.

Unfortunately, I don't have a recipe to test this.

>
> [0] https://lore.kernel.org/linux-arm-msm/CPDIYQ3SSY3E.I0Y0NMIED0WO@otso/
>
> Regards
> Luca


-- 
With best wishes
Dmitry

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Luca Weiss]

On Fri Jan 13, 2023 at 2:01 PM CET, Dmitry Baryshkov wrote:
> On Fri, 13 Jan 2023 at 14:44, Luca Weiss <luca.weiss@fairphone.com> wrote:
> >
> > Hi Dmitry,
> >
> > On Thu Jan 12, 2023 at 8:33 PM CET, Dmitry Baryshkov wrote:
> > > On 12/01/2023 19:50, Vinod Koul wrote:
> > > > On 28-12-22, 15:17, Johan Hovold wrote:
> > > >> Luca, Vinod,
> > > >>
> > > >> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> > > >>> Add the tables and config for the combo phy found on SM6350.
> > > >>>
> > > >>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > > >>> ---
> > > >>> Changes since v2:
> > > >>> * Drop dp_txa/dp_txb changes, not required
> > > >>> * Fix dp_dp_phy offset
> > > >>>
> > > >>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> > > >>>   1 file changed, 126 insertions(+)
> > > >>>
> > > >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > > >>> index 77052c66cf70..6ac0c68269dc 100644
> > > >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > > >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > > >>
> > > >>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> > > >>>           "phy",
> > > >>>   };
> > > >>>
> > > >>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> > > >>> + .com            = 0x0000,
> > > >>> + .txa            = 0x1200,
> > > >>> + .rxa            = 0x1400,
> > > >>> + .txb            = 0x1600,
> > > >>> + .rxb            = 0x1800,
> > > >>> + .usb3_serdes    = 0x1000,
> > > >>> + .usb3_pcs_misc  = 0x1a00,
> > > >>> + .usb3_pcs       = 0x1c00,
> > > >>> + .dp_serdes      = 0x1000,
> > > >>
> > > >> I would have expected this to be 0x2000 as that's what the older
> > > >> platforms have been using for the dp serdes table so far. Without access
> > > >> to any documentation it's hard to tell whether everyone's just been
> > > >> cargo-culting all along or if there's actually something there at offset
> > > >> 0x2000.
> > >
> > > usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.
> > >
> > > Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So
> > > dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 =
> > > 0x2600.
> >
> > Can you share how you got to the 0x2000 offset? You can see my
> > (potentially wrong) reasoning for 0x1000 a few messages ago[0].
> >
> > The only 0x2000-something I could find now while looking at it again is
> > "#define USB3_DP_PHY_DP_DP_PHY_PD_CTL 0x2a18" which becomes
> > USB3_DP_DP_PHY_PD_CTL in the driver but this is seemingly not used at
> > all in my msm-4.19 tree.
>
> Quite simple: see [1]. DP_PLL is at +0x2000
>
> [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/lagoon-sde-pll.dtsi#27

I still disagree from what I see.

E.g. this part of the dp_serdes init table in mainline:

static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),

With this one:
#define QSERDES_V3_COM_HSCLK_SEL                     0x13c

To write this config qmp->dp_serdes gets used which is set at:
	qmp->dp_serdes = base + offs->dp_serdes;

So if offs->dp_serdes is 0x2000, this write will go to 0x213c.

If we go back to msm-4.19 downstream the equivalent define is
#define USB3_DP_QSERDES_COM_HSCLK_SEL				0x113c

So there we are at offset 0x1000. And this define is used in
qcom,qmp-phy-init-seq which I already went to in detail in a previous
email in this thread.

>
> Anyway, having DP serdes at the space as USB3 serdes would mean that
> one would be setting USB3 PLL when trying to enable DP. So I could
> have said even w/o looking at the dtsi that dp serdes can _not_ be at
> 0x1000.

I don't know enough about these PHY/DP/etc blocks to say anything there.

>
> >
> > Also if you have any idea on how to test it at runtime without actually
> > having to get all the type-C functionality up I'd be happy to try that.
> > Unfortunately I believe there's still quite some bits missing to
> > actually get DP out via the USB-C port - which I imagine would trigger
> > the PHY setup.
>
> Unfortunately, I don't have a recipe to test this.

No worries :)

Regards
Luca

>
> >
> > [0] https://lore.kernel.org/linux-arm-msm/CPDIYQ3SSY3E.I0Y0NMIED0WO@otso/
> >
> > Regards
> > Luca
>
>
> -- 
> With best wishes
> Dmitry


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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Luca Weiss]

On Fri Jan 13, 2023 at 2:01 PM CET, Dmitry Baryshkov wrote:
> On Fri, 13 Jan 2023 at 14:44, Luca Weiss <luca.weiss@fairphone.com> wrote:
> >
> > Hi Dmitry,
> >
> > On Thu Jan 12, 2023 at 8:33 PM CET, Dmitry Baryshkov wrote:
> > > On 12/01/2023 19:50, Vinod Koul wrote:
> > > > On 28-12-22, 15:17, Johan Hovold wrote:
> > > >> Luca, Vinod,
> > > >>
> > > >> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> > > >>> Add the tables and config for the combo phy found on SM6350.
> > > >>>
> > > >>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > > >>> ---
> > > >>> Changes since v2:
> > > >>> * Drop dp_txa/dp_txb changes, not required
> > > >>> * Fix dp_dp_phy offset
> > > >>>
> > > >>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> > > >>>   1 file changed, 126 insertions(+)
> > > >>>
> > > >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > > >>> index 77052c66cf70..6ac0c68269dc 100644
> > > >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > > >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > > >>
> > > >>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> > > >>>           "phy",
> > > >>>   };
> > > >>>
> > > >>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> > > >>> + .com            = 0x0000,
> > > >>> + .txa            = 0x1200,
> > > >>> + .rxa            = 0x1400,
> > > >>> + .txb            = 0x1600,
> > > >>> + .rxb            = 0x1800,
> > > >>> + .usb3_serdes    = 0x1000,
> > > >>> + .usb3_pcs_misc  = 0x1a00,
> > > >>> + .usb3_pcs       = 0x1c00,
> > > >>> + .dp_serdes      = 0x1000,
> > > >>
> > > >> I would have expected this to be 0x2000 as that's what the older
> > > >> platforms have been using for the dp serdes table so far. Without access
> > > >> to any documentation it's hard to tell whether everyone's just been
> > > >> cargo-culting all along or if there's actually something there at offset
> > > >> 0x2000.
> > >
> > > usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.
> > >
> > > Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So
> > > dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 =
> > > 0x2600.
> >
> > Can you share how you got to the 0x2000 offset? You can see my
> > (potentially wrong) reasoning for 0x1000 a few messages ago[0].
> >
> > The only 0x2000-something I could find now while looking at it again is
> > "#define USB3_DP_PHY_DP_DP_PHY_PD_CTL 0x2a18" which becomes
> > USB3_DP_DP_PHY_PD_CTL in the driver but this is seemingly not used at
> > all in my msm-4.19 tree.
>
> Quite simple: see [1]. DP_PLL is at +0x2000
>
> [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/lagoon-sde-pll.dtsi#27

I still disagree from what I see.

E.g. this part of the dp_serdes init table in mainline:

static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),

With this one:
#define QSERDES_V3_COM_HSCLK_SEL                     0x13c

To write this config qmp->dp_serdes gets used which is set at:
	qmp->dp_serdes = base + offs->dp_serdes;

So if offs->dp_serdes is 0x2000, this write will go to 0x213c.

If we go back to msm-4.19 downstream the equivalent define is
#define USB3_DP_QSERDES_COM_HSCLK_SEL				0x113c

So there we are at offset 0x1000. And this define is used in
qcom,qmp-phy-init-seq which I already went to in detail in a previous
email in this thread.

>
> Anyway, having DP serdes at the space as USB3 serdes would mean that
> one would be setting USB3 PLL when trying to enable DP. So I could
> have said even w/o looking at the dtsi that dp serdes can _not_ be at
> 0x1000.

I don't know enough about these PHY/DP/etc blocks to say anything there.

>
> >
> > Also if you have any idea on how to test it at runtime without actually
> > having to get all the type-C functionality up I'd be happy to try that.
> > Unfortunately I believe there's still quite some bits missing to
> > actually get DP out via the USB-C port - which I imagine would trigger
> > the PHY setup.
>
> Unfortunately, I don't have a recipe to test this.

No worries :)

Regards
Luca

>
> >
> > [0] https://lore.kernel.org/linux-arm-msm/CPDIYQ3SSY3E.I0Y0NMIED0WO@otso/
> >
> > Regards
> > Luca
>
>
> -- 
> With best wishes
> Dmitry

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Johan Hovold]

On Fri, Jan 20, 2023 at 03:13:46PM +0100, Luca Weiss wrote:
> On Fri Jan 13, 2023 at 2:01 PM CET, Dmitry Baryshkov wrote:
> > On Fri, 13 Jan 2023 at 14:44, Luca Weiss <luca.weiss@fairphone.com> wrote:
> > >
> > > Hi Dmitry,
> > >
> > > On Thu Jan 12, 2023 at 8:33 PM CET, Dmitry Baryshkov wrote:
> > > > On 12/01/2023 19:50, Vinod Koul wrote:
> > > > > On 28-12-22, 15:17, Johan Hovold wrote:
> > > > >> Luca, Vinod,
> > > > >>
> > > > >> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> > > > >>> Add the tables and config for the combo phy found on SM6350.
> > > > >>>
> > > > >>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > > > >>> ---
> > > > >>> Changes since v2:
> > > > >>> * Drop dp_txa/dp_txb changes, not required
> > > > >>> * Fix dp_dp_phy offset
> > > > >>>
> > > > >>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> > > > >>>   1 file changed, 126 insertions(+)
> > > > >>>
> > > > >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > > > >>> index 77052c66cf70..6ac0c68269dc 100644
> > > > >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > > > >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > > > >>
> > > > >>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> > > > >>>           "phy",
> > > > >>>   };
> > > > >>>
> > > > >>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> > > > >>> + .com            = 0x0000,
> > > > >>> + .txa            = 0x1200,
> > > > >>> + .rxa            = 0x1400,
> > > > >>> + .txb            = 0x1600,
> > > > >>> + .rxb            = 0x1800,
> > > > >>> + .usb3_serdes    = 0x1000,
> > > > >>> + .usb3_pcs_misc  = 0x1a00,
> > > > >>> + .usb3_pcs       = 0x1c00,
> > > > >>> + .dp_serdes      = 0x1000,
> > > > >>
> > > > >> I would have expected this to be 0x2000 as that's what the older
> > > > >> platforms have been using for the dp serdes table so far. Without access
> > > > >> to any documentation it's hard to tell whether everyone's just been
> > > > >> cargo-culting all along or if there's actually something there at offset
> > > > >> 0x2000.
> > > >
> > > > usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.
> > > >
> > > > Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So
> > > > dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 =
> > > > 0x2600.
> > >
> > > Can you share how you got to the 0x2000 offset? You can see my
> > > (potentially wrong) reasoning for 0x1000 a few messages ago[0].
> > >
> > > The only 0x2000-something I could find now while looking at it again is
> > > "#define USB3_DP_PHY_DP_DP_PHY_PD_CTL 0x2a18" which becomes
> > > USB3_DP_DP_PHY_PD_CTL in the driver but this is seemingly not used at
> > > all in my msm-4.19 tree.
> >
> > Quite simple: see [1]. DP_PLL is at +0x2000
> >
> > [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/lagoon-sde-pll.dtsi#27
> 
> I still disagree from what I see.
> 
> E.g. this part of the dp_serdes init table in mainline:
> 
> static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
> 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
> 
> With this one:
> #define QSERDES_V3_COM_HSCLK_SEL                     0x13c
> 
> To write this config qmp->dp_serdes gets used which is set at:
> 	qmp->dp_serdes = base + offs->dp_serdes;
> 
> So if offs->dp_serdes is 0x2000, this write will go to 0x213c.
> 
> If we go back to msm-4.19 downstream the equivalent define is
> #define USB3_DP_QSERDES_COM_HSCLK_SEL				0x113c
> 
> So there we are at offset 0x1000. And this define is used in
> qcom,qmp-phy-init-seq which I already went to in detail in a previous
> email in this thread.

From what I've heard, the PHY driver in the vendor kernel only deals
with the USB part of the PHY, while some display driver accesses the DP
part directly. So the fact that the Qualcomm USB PHY driver init
sequences don't seem to use the DP regions (apart from that
USB3_DP_PHY_DP_DP_PHY_PD_CTL register) is to be expected.

IIRC the v3 layout was also used by the SoC for which DP support was
first implemented. Presumably, the separate USB and DP regions do exist
and you should include them also for SM6350 even if you can't test it
currently.

We'll convert the older platforms over to use the new binding scheme
soon and then we'd need this anyway. And if it turns out later that this
was all bogus, at least we only need to fix the driver (and not worry
about dts backward compatibility as we had to with the old style
bindings).

Johan

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Johan Hovold]

On Fri, Jan 20, 2023 at 03:13:46PM +0100, Luca Weiss wrote:
> On Fri Jan 13, 2023 at 2:01 PM CET, Dmitry Baryshkov wrote:
> > On Fri, 13 Jan 2023 at 14:44, Luca Weiss <luca.weiss@fairphone.com> wrote:
> > >
> > > Hi Dmitry,
> > >
> > > On Thu Jan 12, 2023 at 8:33 PM CET, Dmitry Baryshkov wrote:
> > > > On 12/01/2023 19:50, Vinod Koul wrote:
> > > > > On 28-12-22, 15:17, Johan Hovold wrote:
> > > > >> Luca, Vinod,
> > > > >>
> > > > >> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> > > > >>> Add the tables and config for the combo phy found on SM6350.
> > > > >>>
> > > > >>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > > > >>> ---
> > > > >>> Changes since v2:
> > > > >>> * Drop dp_txa/dp_txb changes, not required
> > > > >>> * Fix dp_dp_phy offset
> > > > >>>
> > > > >>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> > > > >>>   1 file changed, 126 insertions(+)
> > > > >>>
> > > > >>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > > > >>> index 77052c66cf70..6ac0c68269dc 100644
> > > > >>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > > > >>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> > > > >>
> > > > >>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> > > > >>>           "phy",
> > > > >>>   };
> > > > >>>
> > > > >>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> > > > >>> + .com            = 0x0000,
> > > > >>> + .txa            = 0x1200,
> > > > >>> + .rxa            = 0x1400,
> > > > >>> + .txb            = 0x1600,
> > > > >>> + .rxb            = 0x1800,
> > > > >>> + .usb3_serdes    = 0x1000,
> > > > >>> + .usb3_pcs_misc  = 0x1a00,
> > > > >>> + .usb3_pcs       = 0x1c00,
> > > > >>> + .dp_serdes      = 0x1000,
> > > > >>
> > > > >> I would have expected this to be 0x2000 as that's what the older
> > > > >> platforms have been using for the dp serdes table so far. Without access
> > > > >> to any documentation it's hard to tell whether everyone's just been
> > > > >> cargo-culting all along or if there's actually something there at offset
> > > > >> 0x2000.
> > > >
> > > > usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.
> > > >
> > > > Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So
> > > > dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 =
> > > > 0x2600.
> > >
> > > Can you share how you got to the 0x2000 offset? You can see my
> > > (potentially wrong) reasoning for 0x1000 a few messages ago[0].
> > >
> > > The only 0x2000-something I could find now while looking at it again is
> > > "#define USB3_DP_PHY_DP_DP_PHY_PD_CTL 0x2a18" which becomes
> > > USB3_DP_DP_PHY_PD_CTL in the driver but this is seemingly not used at
> > > all in my msm-4.19 tree.
> >
> > Quite simple: see [1]. DP_PLL is at +0x2000
> >
> > [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/lagoon-sde-pll.dtsi#27
> 
> I still disagree from what I see.
> 
> E.g. this part of the dp_serdes init table in mainline:
> 
> static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
> 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
> 
> With this one:
> #define QSERDES_V3_COM_HSCLK_SEL                     0x13c
> 
> To write this config qmp->dp_serdes gets used which is set at:
> 	qmp->dp_serdes = base + offs->dp_serdes;
> 
> So if offs->dp_serdes is 0x2000, this write will go to 0x213c.
> 
> If we go back to msm-4.19 downstream the equivalent define is
> #define USB3_DP_QSERDES_COM_HSCLK_SEL				0x113c
> 
> So there we are at offset 0x1000. And this define is used in
> qcom,qmp-phy-init-seq which I already went to in detail in a previous
> email in this thread.

From what I've heard, the PHY driver in the vendor kernel only deals
with the USB part of the PHY, while some display driver accesses the DP
part directly. So the fact that the Qualcomm USB PHY driver init
sequences don't seem to use the DP regions (apart from that
USB3_DP_PHY_DP_DP_PHY_PD_CTL register) is to be expected.

IIRC the v3 layout was also used by the SoC for which DP support was
first implemented. Presumably, the separate USB and DP regions do exist
and you should include them also for SM6350 even if you can't test it
currently.

We'll convert the older platforms over to use the new binding scheme
soon and then we'd need this anyway. And if it turns out later that this
was all bogus, at least we only need to fix the driver (and not worry
about dts backward compatibility as we had to with the old style
bindings).

Johan

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Dmitry Baryshkov]

On 23/01/2023 11:43, Johan Hovold wrote:
> On Fri, Jan 20, 2023 at 03:13:46PM +0100, Luca Weiss wrote:
>> On Fri Jan 13, 2023 at 2:01 PM CET, Dmitry Baryshkov wrote:
>>> On Fri, 13 Jan 2023 at 14:44, Luca Weiss <luca.weiss@fairphone.com> wrote:
>>>>
>>>> Hi Dmitry,
>>>>
>>>> On Thu Jan 12, 2023 at 8:33 PM CET, Dmitry Baryshkov wrote:
>>>>> On 12/01/2023 19:50, Vinod Koul wrote:
>>>>>> On 28-12-22, 15:17, Johan Hovold wrote:
>>>>>>> Luca, Vinod,
>>>>>>>
>>>>>>> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
>>>>>>>> Add the tables and config for the combo phy found on SM6350.
>>>>>>>>
>>>>>>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>>>>>>> ---
>>>>>>>> Changes since v2:
>>>>>>>> * Drop dp_txa/dp_txb changes, not required
>>>>>>>> * Fix dp_dp_phy offset
>>>>>>>>
>>>>>>>>    drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
>>>>>>>>    1 file changed, 126 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>>>>>>> index 77052c66cf70..6ac0c68269dc 100644
>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>>>>>>
>>>>>>>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
>>>>>>>>            "phy",
>>>>>>>>    };
>>>>>>>>
>>>>>>>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
>>>>>>>> + .com            = 0x0000,
>>>>>>>> + .txa            = 0x1200,
>>>>>>>> + .rxa            = 0x1400,
>>>>>>>> + .txb            = 0x1600,
>>>>>>>> + .rxb            = 0x1800,
>>>>>>>> + .usb3_serdes    = 0x1000,
>>>>>>>> + .usb3_pcs_misc  = 0x1a00,
>>>>>>>> + .usb3_pcs       = 0x1c00,
>>>>>>>> + .dp_serdes      = 0x1000,
>>>>>>>
>>>>>>> I would have expected this to be 0x2000 as that's what the older
>>>>>>> platforms have been using for the dp serdes table so far. Without access
>>>>>>> to any documentation it's hard to tell whether everyone's just been
>>>>>>> cargo-culting all along or if there's actually something there at offset
>>>>>>> 0x2000.
>>>>>
>>>>> usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.
>>>>>
>>>>> Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So
>>>>> dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 =
>>>>> 0x2600.
>>>>
>>>> Can you share how you got to the 0x2000 offset? You can see my
>>>> (potentially wrong) reasoning for 0x1000 a few messages ago[0].
>>>>
>>>> The only 0x2000-something I could find now while looking at it again is
>>>> "#define USB3_DP_PHY_DP_DP_PHY_PD_CTL 0x2a18" which becomes
>>>> USB3_DP_DP_PHY_PD_CTL in the driver but this is seemingly not used at
>>>> all in my msm-4.19 tree.
>>>
>>> Quite simple: see [1]. DP_PLL is at +0x2000
>>>
>>> [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/lagoon-sde-pll.dtsi#27
>>
>> I still disagree from what I see.
>>
>> E.g. this part of the dp_serdes init table in mainline:
>>
>> static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
>> 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
>>
>> With this one:
>> #define QSERDES_V3_COM_HSCLK_SEL                     0x13c
>>
>> To write this config qmp->dp_serdes gets used which is set at:
>> 	qmp->dp_serdes = base + offs->dp_serdes;
>>
>> So if offs->dp_serdes is 0x2000, this write will go to 0x213c.
>>
>> If we go back to msm-4.19 downstream the equivalent define is
>> #define USB3_DP_QSERDES_COM_HSCLK_SEL				0x113c

There are two SERDES regions. One used by USB part of the PHY (at 
0x1000) and another SERDES region used for DP (at 0x2000). As Johan 
described below, vendor kernel handles the DP regions in the DP driver. 
Possibly this caused a confusion on your side.

>>
>> So there we are at offset 0x1000. And this define is used in
>> qcom,qmp-phy-init-seq which I already went to in detail in a previous
>> email in this thread.
> 
>  From what I've heard, the PHY driver in the vendor kernel only deals
> with the USB part of the PHY, while some display driver accesses the DP
> part directly. So the fact that the Qualcomm USB PHY driver init
> sequences don't seem to use the DP regions (apart from that
> USB3_DP_PHY_DP_DP_PHY_PD_CTL register) is to be expected.

Correct.

> 
> IIRC the v3 layout was also used by the SoC for which DP support was
> first implemented. Presumably, the separate USB and DP regions do exist
> and you should include them also for SM6350 even if you can't test it
> currently.

Correct. sdm845 and sc7180 are v3 and they handle DP and USB3 regions 
separately inside a single Combo driver.

> We'll convert the older platforms over to use the new binding scheme
> soon and then we'd need this anyway. And if it turns out later that this
> was all bogus, at least we only need to fix the driver (and not worry
> about dts backward compatibility as we had to with the old style
> bindings).

As you mentioned this. Do you have plans to work on this conversion? If 
not, I'll probably take a look during next development window.
-- 
With best wishes
Dmitry

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Dmitry Baryshkov]

On 23/01/2023 11:43, Johan Hovold wrote:
> On Fri, Jan 20, 2023 at 03:13:46PM +0100, Luca Weiss wrote:
>> On Fri Jan 13, 2023 at 2:01 PM CET, Dmitry Baryshkov wrote:
>>> On Fri, 13 Jan 2023 at 14:44, Luca Weiss <luca.weiss@fairphone.com> wrote:
>>>>
>>>> Hi Dmitry,
>>>>
>>>> On Thu Jan 12, 2023 at 8:33 PM CET, Dmitry Baryshkov wrote:
>>>>> On 12/01/2023 19:50, Vinod Koul wrote:
>>>>>> On 28-12-22, 15:17, Johan Hovold wrote:
>>>>>>> Luca, Vinod,
>>>>>>>
>>>>>>> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
>>>>>>>> Add the tables and config for the combo phy found on SM6350.
>>>>>>>>
>>>>>>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>>>>>>> ---
>>>>>>>> Changes since v2:
>>>>>>>> * Drop dp_txa/dp_txb changes, not required
>>>>>>>> * Fix dp_dp_phy offset
>>>>>>>>
>>>>>>>>    drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
>>>>>>>>    1 file changed, 126 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>>>>>>> index 77052c66cf70..6ac0c68269dc 100644
>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>>>>>>
>>>>>>>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
>>>>>>>>            "phy",
>>>>>>>>    };
>>>>>>>>
>>>>>>>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
>>>>>>>> + .com            = 0x0000,
>>>>>>>> + .txa            = 0x1200,
>>>>>>>> + .rxa            = 0x1400,
>>>>>>>> + .txb            = 0x1600,
>>>>>>>> + .rxb            = 0x1800,
>>>>>>>> + .usb3_serdes    = 0x1000,
>>>>>>>> + .usb3_pcs_misc  = 0x1a00,
>>>>>>>> + .usb3_pcs       = 0x1c00,
>>>>>>>> + .dp_serdes      = 0x1000,
>>>>>>>
>>>>>>> I would have expected this to be 0x2000 as that's what the older
>>>>>>> platforms have been using for the dp serdes table so far. Without access
>>>>>>> to any documentation it's hard to tell whether everyone's just been
>>>>>>> cargo-culting all along or if there's actually something there at offset
>>>>>>> 0x2000.
>>>>>
>>>>> usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.
>>>>>
>>>>> Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So
>>>>> dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 =
>>>>> 0x2600.
>>>>
>>>> Can you share how you got to the 0x2000 offset? You can see my
>>>> (potentially wrong) reasoning for 0x1000 a few messages ago[0].
>>>>
>>>> The only 0x2000-something I could find now while looking at it again is
>>>> "#define USB3_DP_PHY_DP_DP_PHY_PD_CTL 0x2a18" which becomes
>>>> USB3_DP_DP_PHY_PD_CTL in the driver but this is seemingly not used at
>>>> all in my msm-4.19 tree.
>>>
>>> Quite simple: see [1]. DP_PLL is at +0x2000
>>>
>>> [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/lagoon-sde-pll.dtsi#27
>>
>> I still disagree from what I see.
>>
>> E.g. this part of the dp_serdes init table in mainline:
>>
>> static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
>> 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
>>
>> With this one:
>> #define QSERDES_V3_COM_HSCLK_SEL                     0x13c
>>
>> To write this config qmp->dp_serdes gets used which is set at:
>> 	qmp->dp_serdes = base + offs->dp_serdes;
>>
>> So if offs->dp_serdes is 0x2000, this write will go to 0x213c.
>>
>> If we go back to msm-4.19 downstream the equivalent define is
>> #define USB3_DP_QSERDES_COM_HSCLK_SEL				0x113c

There are two SERDES regions. One used by USB part of the PHY (at 
0x1000) and another SERDES region used for DP (at 0x2000). As Johan 
described below, vendor kernel handles the DP regions in the DP driver. 
Possibly this caused a confusion on your side.

>>
>> So there we are at offset 0x1000. And this define is used in
>> qcom,qmp-phy-init-seq which I already went to in detail in a previous
>> email in this thread.
> 
>  From what I've heard, the PHY driver in the vendor kernel only deals
> with the USB part of the PHY, while some display driver accesses the DP
> part directly. So the fact that the Qualcomm USB PHY driver init
> sequences don't seem to use the DP regions (apart from that
> USB3_DP_PHY_DP_DP_PHY_PD_CTL register) is to be expected.

Correct.

> 
> IIRC the v3 layout was also used by the SoC for which DP support was
> first implemented. Presumably, the separate USB and DP regions do exist
> and you should include them also for SM6350 even if you can't test it
> currently.

Correct. sdm845 and sc7180 are v3 and they handle DP and USB3 regions 
separately inside a single Combo driver.

> We'll convert the older platforms over to use the new binding scheme
> soon and then we'd need this anyway. And if it turns out later that this
> was all bogus, at least we only need to fix the driver (and not worry
> about dts backward compatibility as we had to with the old style
> bindings).

As you mentioned this. Do you have plans to work on this conversion? If 
not, I'll probably take a look during next development window.
-- 
With best wishes
Dmitry


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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Luca Weiss]

On Mon Jan 23, 2023 at 12:15 PM CET, Dmitry Baryshkov wrote:
> On 23/01/2023 11:43, Johan Hovold wrote:
> > On Fri, Jan 20, 2023 at 03:13:46PM +0100, Luca Weiss wrote:
> >> On Fri Jan 13, 2023 at 2:01 PM CET, Dmitry Baryshkov wrote:
> >>> On Fri, 13 Jan 2023 at 14:44, Luca Weiss <luca.weiss@fairphone.com> wrote:
> >>>>
> >>>> Hi Dmitry,
> >>>>
> >>>> On Thu Jan 12, 2023 at 8:33 PM CET, Dmitry Baryshkov wrote:
> >>>>> On 12/01/2023 19:50, Vinod Koul wrote:
> >>>>>> On 28-12-22, 15:17, Johan Hovold wrote:
> >>>>>>> Luca, Vinod,
> >>>>>>>
> >>>>>>> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> >>>>>>>> Add the tables and config for the combo phy found on SM6350.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> >>>>>>>> ---
> >>>>>>>> Changes since v2:
> >>>>>>>> * Drop dp_txa/dp_txb changes, not required
> >>>>>>>> * Fix dp_dp_phy offset
> >>>>>>>>
> >>>>>>>>    drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> >>>>>>>>    1 file changed, 126 insertions(+)
> >>>>>>>>
> >>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> >>>>>>>> index 77052c66cf70..6ac0c68269dc 100644
> >>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> >>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> >>>>>>>
> >>>>>>>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> >>>>>>>>            "phy",
> >>>>>>>>    };
> >>>>>>>>
> >>>>>>>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> >>>>>>>> + .com            = 0x0000,
> >>>>>>>> + .txa            = 0x1200,
> >>>>>>>> + .rxa            = 0x1400,
> >>>>>>>> + .txb            = 0x1600,
> >>>>>>>> + .rxb            = 0x1800,
> >>>>>>>> + .usb3_serdes    = 0x1000,
> >>>>>>>> + .usb3_pcs_misc  = 0x1a00,
> >>>>>>>> + .usb3_pcs       = 0x1c00,
> >>>>>>>> + .dp_serdes      = 0x1000,
> >>>>>>>
> >>>>>>> I would have expected this to be 0x2000 as that's what the older
> >>>>>>> platforms have been using for the dp serdes table so far. Without access
> >>>>>>> to any documentation it's hard to tell whether everyone's just been
> >>>>>>> cargo-culting all along or if there's actually something there at offset
> >>>>>>> 0x2000.
> >>>>>
> >>>>> usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.
> >>>>>
> >>>>> Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So
> >>>>> dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 =
> >>>>> 0x2600.
> >>>>
> >>>> Can you share how you got to the 0x2000 offset? You can see my
> >>>> (potentially wrong) reasoning for 0x1000 a few messages ago[0].
> >>>>
> >>>> The only 0x2000-something I could find now while looking at it again is
> >>>> "#define USB3_DP_PHY_DP_DP_PHY_PD_CTL 0x2a18" which becomes
> >>>> USB3_DP_DP_PHY_PD_CTL in the driver but this is seemingly not used at
> >>>> all in my msm-4.19 tree.
> >>>
> >>> Quite simple: see [1]. DP_PLL is at +0x2000
> >>>
> >>> [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/lagoon-sde-pll.dtsi#27
> >>
> >> I still disagree from what I see.
> >>
> >> E.g. this part of the dp_serdes init table in mainline:
> >>
> >> static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
> >> 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
> >>
> >> With this one:
> >> #define QSERDES_V3_COM_HSCLK_SEL                     0x13c
> >>
> >> To write this config qmp->dp_serdes gets used which is set at:
> >> 	qmp->dp_serdes = base + offs->dp_serdes;
> >>
> >> So if offs->dp_serdes is 0x2000, this write will go to 0x213c.
> >>
> >> If we go back to msm-4.19 downstream the equivalent define is
> >> #define USB3_DP_QSERDES_COM_HSCLK_SEL				0x113c
>
> There are two SERDES regions. One used by USB part of the PHY (at 
> 0x1000) and another SERDES region used for DP (at 0x2000). As Johan 
> described below, vendor kernel handles the DP regions in the DP driver. 
> Possibly this caused a confusion on your side.

Ack, I think I got it now. I also see the registers used downstream
now, e.g.:

techpack/display/pll/dp_pll_10nm_util.c:#define QSERDES_COM_LOCK_CMP2_MODE0             0x009C

So now .dp_serdes should be 0x2000. Do I need to change anything else
also? I think not?

Regards
Luca

>
> >>
> >> So there we are at offset 0x1000. And this define is used in
> >> qcom,qmp-phy-init-seq which I already went to in detail in a previous
> >> email in this thread.
> > 
> >  From what I've heard, the PHY driver in the vendor kernel only deals
> > with the USB part of the PHY, while some display driver accesses the DP
> > part directly. So the fact that the Qualcomm USB PHY driver init
> > sequences don't seem to use the DP regions (apart from that
> > USB3_DP_PHY_DP_DP_PHY_PD_CTL register) is to be expected.
>
> Correct.
>
> > 
> > IIRC the v3 layout was also used by the SoC for which DP support was
> > first implemented. Presumably, the separate USB and DP regions do exist
> > and you should include them also for SM6350 even if you can't test it
> > currently.
>
> Correct. sdm845 and sc7180 are v3 and they handle DP and USB3 regions 
> separately inside a single Combo driver.
>
> > We'll convert the older platforms over to use the new binding scheme
> > soon and then we'd need this anyway. And if it turns out later that this
> > was all bogus, at least we only need to fix the driver (and not worry
> > about dts backward compatibility as we had to with the old style
> > bindings).
>
> As you mentioned this. Do you have plans to work on this conversion? If 
> not, I'll probably take a look during next development window.
> -- 
> With best wishes
> Dmitry

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Luca Weiss]

On Mon Jan 23, 2023 at 12:15 PM CET, Dmitry Baryshkov wrote:
> On 23/01/2023 11:43, Johan Hovold wrote:
> > On Fri, Jan 20, 2023 at 03:13:46PM +0100, Luca Weiss wrote:
> >> On Fri Jan 13, 2023 at 2:01 PM CET, Dmitry Baryshkov wrote:
> >>> On Fri, 13 Jan 2023 at 14:44, Luca Weiss <luca.weiss@fairphone.com> wrote:
> >>>>
> >>>> Hi Dmitry,
> >>>>
> >>>> On Thu Jan 12, 2023 at 8:33 PM CET, Dmitry Baryshkov wrote:
> >>>>> On 12/01/2023 19:50, Vinod Koul wrote:
> >>>>>> On 28-12-22, 15:17, Johan Hovold wrote:
> >>>>>>> Luca, Vinod,
> >>>>>>>
> >>>>>>> On Wed, Nov 30, 2022 at 09:14:28AM +0100, Luca Weiss wrote:
> >>>>>>>> Add the tables and config for the combo phy found on SM6350.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> >>>>>>>> ---
> >>>>>>>> Changes since v2:
> >>>>>>>> * Drop dp_txa/dp_txb changes, not required
> >>>>>>>> * Fix dp_dp_phy offset
> >>>>>>>>
> >>>>>>>>    drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 126 ++++++++++++++++++++++
> >>>>>>>>    1 file changed, 126 insertions(+)
> >>>>>>>>
> >>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> >>>>>>>> index 77052c66cf70..6ac0c68269dc 100644
> >>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> >>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> >>>>>>>
> >>>>>>>> @@ -975,6 +1039,19 @@ static const char * const sc7180_usb3phy_reset_l[] = {
> >>>>>>>>            "phy",
> >>>>>>>>    };
> >>>>>>>>
> >>>>>>>> +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
> >>>>>>>> + .com            = 0x0000,
> >>>>>>>> + .txa            = 0x1200,
> >>>>>>>> + .rxa            = 0x1400,
> >>>>>>>> + .txb            = 0x1600,
> >>>>>>>> + .rxb            = 0x1800,
> >>>>>>>> + .usb3_serdes    = 0x1000,
> >>>>>>>> + .usb3_pcs_misc  = 0x1a00,
> >>>>>>>> + .usb3_pcs       = 0x1c00,
> >>>>>>>> + .dp_serdes      = 0x1000,
> >>>>>>>
> >>>>>>> I would have expected this to be 0x2000 as that's what the older
> >>>>>>> platforms have been using for the dp serdes table so far. Without access
> >>>>>>> to any documentation it's hard to tell whether everyone's just been
> >>>>>>> cargo-culting all along or if there's actually something there at offset
> >>>>>>> 0x2000.
> >>>>>
> >>>>> usb3_serdes is 0x1000, so dp_serdes equal to 0x1000 is definitely an typo.
> >>>>>
> >>>>> Judging from the downstream dtsi, the DP PHY starts at offset 0x2000. So
> >>>>> dp_serdes is equal to 0x2000, dp_phy = 0x2a00, ln_tx1 = 0x2200, ln_tx2 =
> >>>>> 0x2600.
> >>>>
> >>>> Can you share how you got to the 0x2000 offset? You can see my
> >>>> (potentially wrong) reasoning for 0x1000 a few messages ago[0].
> >>>>
> >>>> The only 0x2000-something I could find now while looking at it again is
> >>>> "#define USB3_DP_PHY_DP_DP_PHY_PD_CTL 0x2a18" which becomes
> >>>> USB3_DP_DP_PHY_PD_CTL in the driver but this is seemingly not used at
> >>>> all in my msm-4.19 tree.
> >>>
> >>> Quite simple: see [1]. DP_PLL is at +0x2000
> >>>
> >>> [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/lagoon-sde-pll.dtsi#27
> >>
> >> I still disagree from what I see.
> >>
> >> E.g. this part of the dp_serdes init table in mainline:
> >>
> >> static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
> >> 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
> >>
> >> With this one:
> >> #define QSERDES_V3_COM_HSCLK_SEL                     0x13c
> >>
> >> To write this config qmp->dp_serdes gets used which is set at:
> >> 	qmp->dp_serdes = base + offs->dp_serdes;
> >>
> >> So if offs->dp_serdes is 0x2000, this write will go to 0x213c.
> >>
> >> If we go back to msm-4.19 downstream the equivalent define is
> >> #define USB3_DP_QSERDES_COM_HSCLK_SEL				0x113c
>
> There are two SERDES regions. One used by USB part of the PHY (at 
> 0x1000) and another SERDES region used for DP (at 0x2000). As Johan 
> described below, vendor kernel handles the DP regions in the DP driver. 
> Possibly this caused a confusion on your side.

Ack, I think I got it now. I also see the registers used downstream
now, e.g.:

techpack/display/pll/dp_pll_10nm_util.c:#define QSERDES_COM_LOCK_CMP2_MODE0             0x009C

So now .dp_serdes should be 0x2000. Do I need to change anything else
also? I think not?

Regards
Luca

>
> >>
> >> So there we are at offset 0x1000. And this define is used in
> >> qcom,qmp-phy-init-seq which I already went to in detail in a previous
> >> email in this thread.
> > 
> >  From what I've heard, the PHY driver in the vendor kernel only deals
> > with the USB part of the PHY, while some display driver accesses the DP
> > part directly. So the fact that the Qualcomm USB PHY driver init
> > sequences don't seem to use the DP regions (apart from that
> > USB3_DP_PHY_DP_DP_PHY_PD_CTL register) is to be expected.
>
> Correct.
>
> > 
> > IIRC the v3 layout was also used by the SoC for which DP support was
> > first implemented. Presumably, the separate USB and DP regions do exist
> > and you should include them also for SM6350 even if you can't test it
> > currently.
>
> Correct. sdm845 and sc7180 are v3 and they handle DP and USB3 regions 
> separately inside a single Combo driver.
>
> > We'll convert the older platforms over to use the new binding scheme
> > soon and then we'd need this anyway. And if it turns out later that this
> > was all bogus, at least we only need to fix the driver (and not worry
> > about dts backward compatibility as we had to with the old style
> > bindings).
>
> As you mentioned this. Do you have plans to work on this conversion? If 
> not, I'll probably take a look during next development window.
> -- 
> With best wishes
> Dmitry


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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Johan Hovold]

On Mon, Jan 23, 2023 at 12:22:32PM +0100, Luca Weiss wrote:
> On Mon Jan 23, 2023 at 12:15 PM CET, Dmitry Baryshkov wrote:

> > There are two SERDES regions. One used by USB part of the PHY (at 
> > 0x1000) and another SERDES region used for DP (at 0x2000). As Johan 
> > described below, vendor kernel handles the DP regions in the DP driver. 
> > Possibly this caused a confusion on your side.
> 
> Ack, I think I got it now. I also see the registers used downstream
> now, e.g.:
> 
> techpack/display/pll/dp_pll_10nm_util.c:#define QSERDES_COM_LOCK_CMP2_MODE0             0x009C
> 
> So now .dp_serdes should be 0x2000. Do I need to change anything else
> also? I think not?

You also need to add new dp_tx/rx pointers to the offset struct and use
those in favour of the current ones if set. I think we hashed that bit
out in one of the previous versions of this patch.

Johan

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Johan Hovold]

On Mon, Jan 23, 2023 at 12:22:32PM +0100, Luca Weiss wrote:
> On Mon Jan 23, 2023 at 12:15 PM CET, Dmitry Baryshkov wrote:

> > There are two SERDES regions. One used by USB part of the PHY (at 
> > 0x1000) and another SERDES region used for DP (at 0x2000). As Johan 
> > described below, vendor kernel handles the DP regions in the DP driver. 
> > Possibly this caused a confusion on your side.
> 
> Ack, I think I got it now. I also see the registers used downstream
> now, e.g.:
> 
> techpack/display/pll/dp_pll_10nm_util.c:#define QSERDES_COM_LOCK_CMP2_MODE0             0x009C
> 
> So now .dp_serdes should be 0x2000. Do I need to change anything else
> also? I think not?

You also need to add new dp_tx/rx pointers to the offset struct and use
those in favour of the current ones if set. I think we hashed that bit
out in one of the previous versions of this patch.

Johan

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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Luca Weiss]

On Mon Jan 23, 2023 at 1:03 PM CET, Johan Hovold wrote:
> On Mon, Jan 23, 2023 at 12:22:32PM +0100, Luca Weiss wrote:
> > On Mon Jan 23, 2023 at 12:15 PM CET, Dmitry Baryshkov wrote:
>
> > > There are two SERDES regions. One used by USB part of the PHY (at 
> > > 0x1000) and another SERDES region used for DP (at 0x2000). As Johan 
> > > described below, vendor kernel handles the DP regions in the DP driver. 
> > > Possibly this caused a confusion on your side.
> > 
> > Ack, I think I got it now. I also see the registers used downstream
> > now, e.g.:
> > 
> > techpack/display/pll/dp_pll_10nm_util.c:#define QSERDES_COM_LOCK_CMP2_MODE0             0x009C
> > 
> > So now .dp_serdes should be 0x2000. Do I need to change anything else
> > also? I think not?
>
> You also need to add new dp_tx/rx pointers to the offset struct and use
> those in favour of the current ones if set. I think we hashed that bit
> out in one of the previous versions of this patch.

Thanks for the persistent help, I've sent out v4 now, I hope that's good
now and we can get this into v6.3 :)

>
> Johan

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Luca Weiss]

On Mon Jan 23, 2023 at 1:03 PM CET, Johan Hovold wrote:
> On Mon, Jan 23, 2023 at 12:22:32PM +0100, Luca Weiss wrote:
> > On Mon Jan 23, 2023 at 12:15 PM CET, Dmitry Baryshkov wrote:
>
> > > There are two SERDES regions. One used by USB part of the PHY (at 
> > > 0x1000) and another SERDES region used for DP (at 0x2000). As Johan 
> > > described below, vendor kernel handles the DP regions in the DP driver. 
> > > Possibly this caused a confusion on your side.
> > 
> > Ack, I think I got it now. I also see the registers used downstream
> > now, e.g.:
> > 
> > techpack/display/pll/dp_pll_10nm_util.c:#define QSERDES_COM_LOCK_CMP2_MODE0             0x009C
> > 
> > So now .dp_serdes should be 0x2000. Do I need to change anything else
> > also? I think not?
>
> You also need to add new dp_tx/rx pointers to the offset struct and use
> those in favour of the current ones if set. I think we hashed that bit
> out in one of the previous versions of this patch.

Thanks for the persistent help, I've sent out v4 now, I hope that's good
now and we can get this into v6.3 :)

>
> Johan


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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Johan Hovold]

On Mon, Jan 23, 2023 at 01:15:52PM +0200, Dmitry Baryshkov wrote:
> On 23/01/2023 11:43, Johan Hovold wrote:

> > We'll convert the older platforms over to use the new binding scheme
> > soon and then we'd need this anyway. And if it turns out later that this
> > was all bogus, at least we only need to fix the driver (and not worry
> > about dts backward compatibility as we had to with the old style
> > bindings).
> 
> As you mentioned this. Do you have plans to work on this conversion? If 
> not, I'll probably take a look during next development window.

Yes, I was planning on looking at this after Luca's series is merged. I
have some higher prio stuff to get out the door these next couple of
weeks first, though.

Johan

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Johan Hovold]

On Mon, Jan 23, 2023 at 01:15:52PM +0200, Dmitry Baryshkov wrote:
> On 23/01/2023 11:43, Johan Hovold wrote:

> > We'll convert the older platforms over to use the new binding scheme
> > soon and then we'd need this anyway. And if it turns out later that this
> > was all bogus, at least we only need to fix the driver (and not worry
> > about dts backward compatibility as we had to with the old style
> > bindings).
> 
> As you mentioned this. Do you have plans to work on this conversion? If 
> not, I'll probably take a look during next development window.

Yes, I was planning on looking at this after Luca's series is merged. I
have some higher prio stuff to get out the door these next couple of
weeks first, though.

Johan

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Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Dmitry Baryshkov]

On 23/01/2023 14:05, Johan Hovold wrote:
> On Mon, Jan 23, 2023 at 01:15:52PM +0200, Dmitry Baryshkov wrote:
>> On 23/01/2023 11:43, Johan Hovold wrote:
> 
>>> We'll convert the older platforms over to use the new binding scheme
>>> soon and then we'd need this anyway. And if it turns out later that this
>>> was all bogus, at least we only need to fix the driver (and not worry
>>> about dts backward compatibility as we had to with the old style
>>> bindings).
>>
>> As you mentioned this. Do you have plans to work on this conversion? If
>> not, I'll probably take a look during next development window.
> 
> Yes, I was planning on looking at this after Luca's series is merged. I
> have some higher prio stuff to get out the door these next couple of
> weeks first, though.

Ack, I'll sync with you then, let's see who has spare time for that.

-- 
With best wishes
Dmitry

Re: [PATCH v3 2/3] phy: qcom-qmp-combo: Add config for SM6350

[Dmitry Baryshkov]

On 23/01/2023 14:05, Johan Hovold wrote:
> On Mon, Jan 23, 2023 at 01:15:52PM +0200, Dmitry Baryshkov wrote:
>> On 23/01/2023 11:43, Johan Hovold wrote:
> 
>>> We'll convert the older platforms over to use the new binding scheme
>>> soon and then we'd need this anyway. And if it turns out later that this
>>> was all bogus, at least we only need to fix the driver (and not worry
>>> about dts backward compatibility as we had to with the old style
>>> bindings).
>>
>> As you mentioned this. Do you have plans to work on this conversion? If
>> not, I'll probably take a look during next development window.
> 
> Yes, I was planning on looking at this after Luca's series is merged. I
> have some higher prio stuff to get out the door these next couple of
> weeks first, though.

Ack, I'll sync with you then, let's see who has spare time for that.

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[PATCH v3 3/3] arm64: dts: qcom: sm6350: Use specific qmpphy compatible

[Luca Weiss]

The sc7180 phy compatible works fine for some cases, but it turns out
sm6350 does need proper phy configuration in the driver, so use the
newly added sm6350 compatible.

Because the sm6350 compatible is using the new binding, we need to
change the node quite a bit to match it.

This fixes qmpphy init when no USB cable is plugged in during bootloader
stage.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes since v2:
* Rebase on https://lore.kernel.org/all/20221111094729.11842-2-johan+linaro@kernel.org/
  While this commit deletes the changes there it's still good to get it
  in for completeness
* Fix clocks, add power-domain

 arch/arm64/boot/dts/qcom/sm6350.dtsi | 50 ++++++++--------------------
 1 file changed, 14 insertions(+), 36 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 43324bf291c3..cb48f03a6cc9 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/interconnect/qcom,sm6350.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
@@ -1119,49 +1120,26 @@ usb_1_hsphy: phy@88e3000 {
 			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 		};
 
-		usb_1_qmpphy: phy@88e9000 {
-			compatible = "qcom,sc7180-qmp-usb3-dp-phy";
-			reg = <0 0x088e9000 0 0x200>,
-			      <0 0x088e8000 0 0x40>,
-			      <0 0x088ea000 0 0x200>;
-			status = "disabled";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
+		usb_1_qmpphy: phy@88e8000 {
+			compatible = "qcom,sm6350-qmp-usb3-dp-phy";
+			reg = <0 0x088e8000 0 0x3000>;
 
 			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
-				 <&xo_board>,
-				 <&rpmhcc RPMH_QLINK_CLK>,
-				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
-			clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+			clock-names = "aux", "ref", "com_aux", "usb3_pipe";
+
+			power-domains = <&gcc USB30_PRIM_GDSC>;
 
 			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
 				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
 			reset-names = "phy", "common";
 
-			usb_1_ssphy: usb3-phy@88e9200 {
-				reg = <0 0x088e9200 0 0x200>,
-				      <0 0x088e9400 0 0x200>,
-				      <0 0x088e9c00 0 0x400>,
-				      <0 0x088e9600 0 0x200>,
-				      <0 0x088e9800 0 0x200>,
-				      <0 0x088e9a00 0 0x100>;
-				#clock-cells = <0>;
-				#phy-cells = <0>;
-				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
-				clock-names = "pipe0";
-				clock-output-names = "usb3_phy_pipe_clk_src";
-			};
+			#clock-cells = <1>;
+			#phy-cells = <1>;
 
-			dp_phy: dp-phy@88ea200 {
-				reg = <0 0x088ea200 0 0x200>,
-				      <0 0x088ea400 0 0x200>,
-				      <0 0x088eaa00 0 0x200>,
-				      <0 0x088ea600 0 0x200>,
-				      <0 0x088ea800 0 0x200>;
-				#phy-cells = <0>;
-				#clock-cells = <1>;
-			};
+			status = "disabled";
 		};
 
 		dc_noc: interconnect@9160000 {
@@ -1235,7 +1213,7 @@ usb_1_dwc3: usb@a600000 {
 				snps,dis_enblslpm_quirk;
 				snps,has-lpm-erratum;
 				snps,hird-threshold = /bits/ 8 <0x10>;
-				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
 		};
-- 
2.38.1

Re: [PATCH v3 3/3] arm64: dts: qcom: sm6350: Use specific qmpphy compatible

[Johan Hovold]

On Wed, Nov 30, 2022 at 09:14:29AM +0100, Luca Weiss wrote:
> The sc7180 phy compatible works fine for some cases, but it turns out
> sm6350 does need proper phy configuration in the driver, so use the
> newly added sm6350 compatible.
> 
> Because the sm6350 compatible is using the new binding, we need to
> change the node quite a bit to match it.
> 
> This fixes qmpphy init when no USB cable is plugged in during bootloader
> stage.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Changes since v2:
> * Rebase on https://lore.kernel.org/all/20221111094729.11842-2-johan+linaro@kernel.org/
>   While this commit deletes the changes there it's still good to get it
>   in for completeness
> * Fix clocks, add power-domain
> 
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 50 ++++++++--------------------
>  1 file changed, 14 insertions(+), 36 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 43324bf291c3..cb48f03a6cc9 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -11,6 +11,7 @@
>  #include <dt-bindings/interconnect/qcom,sm6350.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
>  #include <dt-bindings/power/qcom-rpmpd.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>  
> @@ -1119,49 +1120,26 @@ usb_1_hsphy: phy@88e3000 {
>  			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
>  		};
>  
> -		usb_1_qmpphy: phy@88e9000 {
> -			compatible = "qcom,sc7180-qmp-usb3-dp-phy";
> -			reg = <0 0x088e9000 0 0x200>,
> -			      <0 0x088e8000 0 0x40>,
> -			      <0 0x088ea000 0 0x200>;
> -			status = "disabled";
> -			#address-cells = <2>;
> -			#size-cells = <2>;
> -			ranges;
> +		usb_1_qmpphy: phy@88e8000 {
> +			compatible = "qcom,sm6350-qmp-usb3-dp-phy";
> +			reg = <0 0x088e8000 0 0x3000>;
>  
>  			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> -				 <&xo_board>,
> -				 <&rpmhcc RPMH_QLINK_CLK>,
> -				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> -			clock-names = "aux", "cfg_ahb", "ref", "com_aux";
> +				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> +				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> +				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> +			clock-names = "aux", "ref", "com_aux", "usb3_pipe";
> +
> +			power-domains = <&gcc USB30_PRIM_GDSC>;
>  
>  			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
>  				 <&gcc GCC_USB3_PHY_PRIM_BCR>;

These have been switched too.

>  			reset-names = "phy", "common";
>  
> -			usb_1_ssphy: usb3-phy@88e9200 {
> -				reg = <0 0x088e9200 0 0x200>,
> -				      <0 0x088e9400 0 0x200>,
> -				      <0 0x088e9c00 0 0x400>,
> -				      <0 0x088e9600 0 0x200>,
> -				      <0 0x088e9800 0 0x200>,
> -				      <0 0x088e9a00 0 0x100>;
> -				#clock-cells = <0>;
> -				#phy-cells = <0>;
> -				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> -				clock-names = "pipe0";
> -				clock-output-names = "usb3_phy_pipe_clk_src";
> -			};
> +			#clock-cells = <1>;
> +			#phy-cells = <1>;
>  
> -			dp_phy: dp-phy@88ea200 {
> -				reg = <0 0x088ea200 0 0x200>,
> -				      <0 0x088ea400 0 0x200>,
> -				      <0 0x088eaa00 0 0x200>,
> -				      <0 0x088ea600 0 0x200>,
> -				      <0 0x088ea800 0 0x200>;
> -				#phy-cells = <0>;
> -				#clock-cells = <1>;
> -			};
> +			status = "disabled";
>  		};
>  
>  		dc_noc: interconnect@9160000 {
> @@ -1235,7 +1213,7 @@ usb_1_dwc3: usb@a600000 {
>  				snps,dis_enblslpm_quirk;
>  				snps,has-lpm-erratum;
>  				snps,hird-threshold = /bits/ 8 <0x10>;
> -				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> +				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
>  				phy-names = "usb2-phy", "usb3-phy";
>  			};
>  		};

Looks good otherwise. With the resets fixed you can add my:

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>

Johan

Re: [PATCH v3 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add sm6350 compatible

[Krzysztof Kozlowski]

On 30/11/2022 09:14, Luca Weiss wrote:
> Add the compatible describing the combo phy found on SM6350.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Changes since v2:
> * Drop misc schema changes again since same schema applies to sm6350


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add sm6350 compatible

[Krzysztof Kozlowski]

On 30/11/2022 09:14, Luca Weiss wrote:
> Add the compatible describing the combo phy found on SM6350.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Changes since v2:
> * Drop misc schema changes again since same schema applies to sm6350


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


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Re: [PATCH v3 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add sm6350 compatible

[Johan Hovold]

On Wed, Nov 30, 2022 at 09:14:27AM +0100, Luca Weiss wrote:
> Add the compatible describing the combo phy found on SM6350.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Changes since v2:
> * Drop misc schema changes again since same schema applies to sm6350
> 
>  .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml   | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> index 6f31693d9868..0764cd977e76 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> @@ -17,6 +17,7 @@ properties:
>    compatible:
>      enum:
>        - qcom,sc8280xp-qmp-usb43dp-phy
> +      - qcom,sm6350-qmp-usb3-dp-phy
>  
>    reg:
>      maxItems: 1

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>

Re: [PATCH v3 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add sm6350 compatible

[Johan Hovold]

On Wed, Nov 30, 2022 at 09:14:27AM +0100, Luca Weiss wrote:
> Add the compatible describing the combo phy found on SM6350.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Changes since v2:
> * Drop misc schema changes again since same schema applies to sm6350
> 
>  .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml   | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> index 6f31693d9868..0764cd977e76 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
> @@ -17,6 +17,7 @@ properties:
>    compatible:
>      enum:
>        - qcom,sc8280xp-qmp-usb43dp-phy
> +      - qcom,sm6350-qmp-usb3-dp-phy
>  
>    reg:
>      maxItems: 1

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>

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