From: Conor Dooley <conor@kernel.org> To: Anup Patel <apatel@ventanamicro.com> Cc: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Atish Patra <atishp@atishpatra.org>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 1/9] RISC-V: Add AIA related CSR defines Date: Wed, 4 Jan 2023 23:07:19 +0000 [thread overview] Message-ID: <Y7YGp/7ufyRPhkwg@spud> (raw) In-Reply-To: <20230103141409.772298-2-apatel@ventanamicro.com> [-- Attachment #1: Type: text/plain, Size: 2114 bytes --] Hey Anup! On Tue, Jan 03, 2023 at 07:44:01PM +0530, Anup Patel wrote: > The RISC-V AIA specification improves handling per-HART local interrupts > in a backward compatible manner. This patch adds defines for new RISC-V > AIA CSRs. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/include/asm/csr.h | 92 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 92 insertions(+) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 0e571f6483d9..4e1356bad7b2 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -73,7 +73,10 @@ > #define IRQ_S_EXT 9 > #define IRQ_VS_EXT 10 > #define IRQ_M_EXT 11 > +#define IRQ_S_GEXT 12 > #define IRQ_PMU_OVF 13 > +#define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) > +#define IRQ_LOCAL_MASK ((_AC(1, UL) << IRQ_LOCAL_MAX) - 1) > > /* Exception causes */ > #define EXC_INST_MISALIGNED 0 > @@ -156,6 +159,26 @@ > (_AC(1, UL) << IRQ_S_TIMER) | \ > (_AC(1, UL) << IRQ_S_EXT)) > > +/* AIA CSR bits */ > +#define TOPI_IID_SHIFT 16 > +#define TOPI_IID_MASK 0xfff > +#define TOPI_IPRIO_MASK 0xff > +#define TOPI_IPRIO_BITS 8 > + > +#define TOPEI_ID_SHIFT 16 > +#define TOPEI_ID_MASK 0x7ff > +#define TOPEI_PRIO_MASK 0x7ff > + > +#define ISELECT_IPRIO0 0x30 > +#define ISELECT_IPRIO15 0x3f > +#define ISELECT_MASK 0x1ff > + > +#define HVICTL_VTI 0x40000000 > +#define HVICTL_IID 0x0fff0000 > +#define HVICTL_IID_SHIFT 16 > +#define HVICTL_IPRIOM 0x00000100 > +#define HVICTL_IPRIO 0x000000ff Why not name these as masks, like you did for the other masks? Also, the mask/shift defines appear inconsistent. TOPI_IID_MASK is intended to be used post-shift AFAICT, but HVICTL_IID_SHIFT is intended to be used *pre*-shift. Some consistency in naming and function would be great. > +/* Machine-Level High-Half CSRs (AIA) */ > +#define CSR_MIDELEGH 0x313 I feel like I could find Midelegh in an Irish dictionary lol Anyways, I went through the CSRs and they do all seem correct. Thanks, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --]
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From: Conor Dooley <conor@kernel.org> To: Anup Patel <apatel@ventanamicro.com> Cc: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Atish Patra <atishp@atishpatra.org>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 1/9] RISC-V: Add AIA related CSR defines Date: Wed, 4 Jan 2023 23:07:19 +0000 [thread overview] Message-ID: <Y7YGp/7ufyRPhkwg@spud> (raw) In-Reply-To: <20230103141409.772298-2-apatel@ventanamicro.com> [-- Attachment #1.1: Type: text/plain, Size: 2114 bytes --] Hey Anup! On Tue, Jan 03, 2023 at 07:44:01PM +0530, Anup Patel wrote: > The RISC-V AIA specification improves handling per-HART local interrupts > in a backward compatible manner. This patch adds defines for new RISC-V > AIA CSRs. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/include/asm/csr.h | 92 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 92 insertions(+) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 0e571f6483d9..4e1356bad7b2 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -73,7 +73,10 @@ > #define IRQ_S_EXT 9 > #define IRQ_VS_EXT 10 > #define IRQ_M_EXT 11 > +#define IRQ_S_GEXT 12 > #define IRQ_PMU_OVF 13 > +#define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) > +#define IRQ_LOCAL_MASK ((_AC(1, UL) << IRQ_LOCAL_MAX) - 1) > > /* Exception causes */ > #define EXC_INST_MISALIGNED 0 > @@ -156,6 +159,26 @@ > (_AC(1, UL) << IRQ_S_TIMER) | \ > (_AC(1, UL) << IRQ_S_EXT)) > > +/* AIA CSR bits */ > +#define TOPI_IID_SHIFT 16 > +#define TOPI_IID_MASK 0xfff > +#define TOPI_IPRIO_MASK 0xff > +#define TOPI_IPRIO_BITS 8 > + > +#define TOPEI_ID_SHIFT 16 > +#define TOPEI_ID_MASK 0x7ff > +#define TOPEI_PRIO_MASK 0x7ff > + > +#define ISELECT_IPRIO0 0x30 > +#define ISELECT_IPRIO15 0x3f > +#define ISELECT_MASK 0x1ff > + > +#define HVICTL_VTI 0x40000000 > +#define HVICTL_IID 0x0fff0000 > +#define HVICTL_IID_SHIFT 16 > +#define HVICTL_IPRIOM 0x00000100 > +#define HVICTL_IPRIO 0x000000ff Why not name these as masks, like you did for the other masks? Also, the mask/shift defines appear inconsistent. TOPI_IID_MASK is intended to be used post-shift AFAICT, but HVICTL_IID_SHIFT is intended to be used *pre*-shift. Some consistency in naming and function would be great. > +/* Machine-Level High-Half CSRs (AIA) */ > +#define CSR_MIDELEGH 0x313 I feel like I could find Midelegh in an Irish dictionary lol Anyways, I went through the CSRs and they do all seem correct. Thanks, Conor. [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 161 bytes --] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-04 23:07 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-03 14:14 [PATCH v2 0/9] Linux RISC-V AIA Support Anup Patel 2023-01-03 14:14 ` Anup Patel 2023-01-03 14:14 ` [PATCH v2 1/9] RISC-V: Add AIA related CSR defines Anup Patel 2023-01-03 14:14 ` Anup Patel 2023-01-04 23:07 ` Conor Dooley [this message] 2023-01-04 23:07 ` Conor Dooley 2023-01-09 5:09 ` Anup Patel 2023-01-09 5:09 ` Anup Patel 2023-01-17 20:42 ` Conor Dooley 2023-01-17 20:42 ` Conor Dooley 2023-01-27 11:58 ` Anup Patel 2023-01-27 11:58 ` Anup Patel 2023-01-27 14:20 ` Conor Dooley 2023-01-27 14:20 ` Conor Dooley 2023-01-03 14:14 ` [PATCH v2 2/9] RISC-V: Detect AIA CSRs from ISA string Anup Patel 2023-01-03 14:14 ` Anup Patel 2023-01-03 14:14 ` [PATCH v2 3/9] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel 2023-01-03 14:14 ` Anup Patel 2023-01-13 9:39 ` Marc Zyngier 2023-01-13 9:39 ` Marc Zyngier 2023-01-03 14:14 ` [PATCH v2 4/9] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel 2023-01-03 14:14 ` Anup Patel 2023-01-04 23:21 ` Conor Dooley 2023-01-04 23:21 ` Conor Dooley 2023-02-20 3:15 ` Anup Patel 2023-02-20 3:15 ` Anup Patel 2023-01-12 20:49 ` Rob Herring 2023-01-12 20:49 ` Rob Herring 2023-02-20 3:20 ` Anup Patel 2023-02-20 3:20 ` Anup Patel 2023-02-19 11:17 ` Vivian Wang 2023-02-19 11:17 ` Vivian Wang 2023-02-20 3:31 ` Anup Patel 2023-02-20 3:31 ` Anup Patel 2023-01-03 14:14 ` [PATCH v2 5/9] irqchip: Add RISC-V incoming MSI controller driver Anup Patel 2023-01-03 14:14 ` Anup Patel 2023-01-13 10:10 ` Marc Zyngier 2023-01-13 10:10 ` Marc Zyngier 2023-05-01 8:28 ` Anup Patel 2023-05-01 8:28 ` Anup Patel 2023-05-01 8:44 ` Marc Zyngier 2023-05-01 8:44 ` Marc Zyngier [not found] ` <CAPqJEFqhd-=-RYepKqnco7HySoxk7AhEctL+vzNozMSWe0mv7A@mail.gmail.com> [not found] ` <CABvJ_xhcuC92A_oo1mWQoRvtRzE8XXx9bbXKs7N7wKm0=Z3_Cw@mail.gmail.com> 2023-01-18 3:49 ` Fwd: " Vincent Chen 2023-01-18 3:49 ` Vincent Chen 2023-01-18 4:20 ` Anup Patel 2023-01-18 4:20 ` Anup Patel 2023-01-03 14:14 ` [PATCH v2 6/9] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel 2023-01-03 14:14 ` Anup Patel 2023-01-04 22:16 ` Conor Dooley 2023-01-04 22:16 ` Conor Dooley 2023-02-20 4:36 ` Anup Patel 2023-02-20 4:36 ` Anup Patel 2023-02-20 10:32 ` Conor Dooley 2023-02-20 10:32 ` Conor Dooley 2023-02-20 10:56 ` Conor Dooley 2023-02-20 10:56 ` Conor Dooley 2023-01-12 21:02 ` Rob Herring 2023-01-12 21:02 ` Rob Herring 2023-02-19 11:48 ` Vivian Wang 2023-02-19 11:48 ` Vivian Wang 2023-02-20 5:09 ` Anup Patel 2023-02-20 5:09 ` Anup Patel 2023-01-03 14:14 ` [PATCH v2 7/9] irqchip: Add RISC-V advanced PLIC driver Anup Patel 2023-01-03 14:14 ` Anup Patel [not found] ` <CAPqJEFpmAvWiOdackxYwSPBfjo4DnTHXrXVSCC4snMn8tnZXPw@mail.gmail.com> [not found] ` <CABvJ_xhjMa8xTsO-Qa23TOqxPpYxyBYSfV6TmKney-Gp3oi8cA@mail.gmail.com> 2023-01-17 7:09 ` Fwd: " Vincent Chen 2023-01-17 7:09 ` Vincent Chen 2023-01-18 4:37 ` Anup Patel 2023-01-18 4:37 ` Anup Patel 2023-01-03 14:14 ` [PATCH v2 8/9] RISC-V: Select APLIC and IMSIC drivers Anup Patel 2023-01-03 14:14 ` Anup Patel 2023-01-03 14:14 ` [PATCH v2 9/9] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel 2023-01-03 14:14 ` Anup Patel
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