[Intel-xe] [PATCH 00/37] Catching up since we went public

[Intel-xe] [PATCH 00/37] Catching up since we went public

[Rodrigo Vivi]

Hi Folks,

For those yet not subsribed to the mailing list, please do so:
https://lists.freedesktop.org/mailman/listinfo/intel-xe

This is the catch up since we went live.
The goal is to merge this patches on top of cgit/drm-xe-next and
then use this mailing list here to continue the public development.

gitlab will be used only for issues handling, but not as git
repository and not for merge requests.

We need to move towards the open source upstream development aligned
with the drm community methods and processes. What is using the cgit
and patches over email. In this way we don't create some strange
fragmentation with the rest of the community and ensure a better
care of the individual commits with proper history, log and recorded
reviewed-bys.

Please notice that I have added some 'Cc:' in most of the patches.
Those are the folks who approved the merge request containing that
commit in gitlab. I cannot forge any reviewed-by tag, but please
respond if that's okay to convert that cc to the reviewed-by.

Also, please notice that there are many commits without any message.
By the kernel rules this is not acceptable. We need to get a message
to the commits. Please respond the email with a message that I can
update the commit myself.

Once everything is in place I will push them to drm-xe-next.

I believe a few rounds will be needed before we can convert the flow.
So I will for now port the patches over. But please ensure that
the new commits in gitlab has the proper commit messages and style.

Thanks,
Rodrigo.

Maarten Lankhorst (13):
  drm/xe: Add intel_pps support too
  drm/xe: Rework initialisation ordering slightly so we can inherit fb
  drm/xe: Implement stolen memory.
  drm/xe: Allow fbdev to allocate stolen memory
  drm/xe: Implement initial hw readout for framebuffer
  drm/xe: Put DPT into stolen memory, if available
  drm/xe: Implement FBC support
  drm/i915: Remove i915_drm_suspend_mode
  drm/xe: Fix dumb bo create
  drm/xe: Make FBC check stolen at use time.
  drm/xe: Move xe_ttm_stolen_mgr_init back
  drm/xe: Fix hidden gotcha regression with bo create
  drm/xe: Fix xe_mmio_wait32 timeouts.

Matthew Brost (9):
  drm/msm: Fix compile error
  drm/xe: Take memory ref on kernel job creation
  Revert "drm/xe: Validate BO on CPU fault"
  drm/xe: Ensure VMA not userptr before calling xe_bo_is_stolen
  drm/xe: Don't use engine_mask until after hwconfig parse
  drm/xe: Fake pulling gt->info.engine_mask from hwconfig blob
  drm/xe/guc: Report submission version of GuC firmware
  drm/xe/guc: s/xe_guc_send_mmio/xe_guc_mmio_send
  drm/xe/guc: Add support GuC MMIO send / recv

Mauro Carvalho Chehab (1):
  drm/xe: Fix compilation when Xe driver is builtin

Philippe Lecluse (1):
  drm/xe: enforce GSMBASE for DG1 instead of BAR2

Rodrigo Vivi (12):
  drm/xe: Implement a local xe_mmio_wait32
  drm/xe: Stop using i915's range_overflows_t macro.
  drm/xe: Let's return last value read on xe_mmio_wait32.
  drm/xe: Convert guc_ready to regular xe_mmio_wait32
  drm/xe: Wait for success on guc done.
  drm/xe: Remove i915_utils dependency from xe_guc_pc.
  drm/xe: Stop using i915_utils in xe_wopcm.
  drm/xe: Let's avoid i915_utils in the xe_force_wake.
  drm/xe: Convert xe_mmio_wait32 to us so we can stop using wait_for_us.
  drm/xe: Remove i915_utils dependency from xe_pcode.
  drm/i915: Expand force_probe to block probe of devices as well.
  drm/xe: Introduce force_probe parameter.

Thomas Hellström (1):
  drm/xe/migrate: Add kerneldoc for the migrate subsystem

 drivers/gpu/drm/i915/Kconfig                  |  15 +-
 .../drm/i915/display/intel_display_power.c    |   8 +-
 .../drm/i915/display/intel_display_power.h    |   3 +-
 drivers/gpu/drm/i915/display/intel_fb.c       |   9 +
 drivers/gpu/drm/i915/display/intel_fbc.c      |  94 +++++--
 drivers/gpu/drm/i915/display/intel_fbdev.c    |  66 +++--
 drivers/gpu/drm/i915/display/intel_pps.c      |  14 +-
 drivers/gpu/drm/i915/i915_driver.c            |  16 +-
 drivers/gpu/drm/i915/i915_params.c            |   2 +-
 drivers/gpu/drm/i915/i915_pci.c               |  33 ++-
 drivers/gpu/drm/i915/intel_runtime_pm.h       |   6 -
 drivers/gpu/drm/msm/adreno/adreno_device.c    |   4 +-
 drivers/gpu/drm/xe/Kconfig                    |  29 +++
 drivers/gpu/drm/xe/Makefile                   |   3 +-
 drivers/gpu/drm/xe/display/intel_de.h         |   6 +-
 drivers/gpu/drm/xe/display/intel_pps.c        |   1 +
 drivers/gpu/drm/xe/display/intel_pps_stub.c   |  43 ----
 drivers/gpu/drm/xe/display/xe_fb_pin.c        |  40 +--
 drivers/gpu/drm/xe/display/xe_plane_initial.c | 224 ++++++----------
 drivers/gpu/drm/xe/xe_bo.c                    | 194 +++++++++++---
 drivers/gpu/drm/xe/xe_bo.h                    |  22 +-
 drivers/gpu/drm/xe/xe_debugfs.c               |   4 +
 drivers/gpu/drm/xe/xe_device.c                |  32 ++-
 drivers/gpu/drm/xe/xe_force_wake.c            |  11 +-
 drivers/gpu/drm/xe/xe_ggtt.c                  |  72 ++++--
 drivers/gpu/drm/xe/xe_ggtt.h                  |   1 +
 drivers/gpu/drm/xe/xe_gt.c                    |  54 +++-
 drivers/gpu/drm/xe/xe_gt.h                    |   1 +
 drivers/gpu/drm/xe/xe_gt_mcr.c                |   3 +-
 drivers/gpu/drm/xe/xe_gt_types.h              |   6 +
 drivers/gpu/drm/xe/xe_guc.c                   |  82 +++---
 drivers/gpu/drm/xe/xe_guc.h                   |   4 +-
 drivers/gpu/drm/xe/xe_guc_ct.c                |   2 +-
 drivers/gpu/drm/xe/xe_guc_hwconfig.c          |   2 +-
 drivers/gpu/drm/xe/xe_guc_pc.c                |  30 ++-
 drivers/gpu/drm/xe/xe_guc_types.h             |   9 +
 drivers/gpu/drm/xe/xe_huc.c                   |   2 +-
 drivers/gpu/drm/xe/xe_irq.c                   |  34 +--
 drivers/gpu/drm/xe/xe_irq.h                   |   2 +
 drivers/gpu/drm/xe/xe_migrate.c               | 108 +++++++-
 drivers/gpu/drm/xe/xe_migrate.h               |  16 +-
 drivers/gpu/drm/xe/xe_mmio.c                  |  66 +++--
 drivers/gpu/drm/xe/xe_mmio.h                  |  49 +++-
 drivers/gpu/drm/xe/xe_pci.c                   |  83 +++++-
 drivers/gpu/drm/xe/xe_pcode.c                 |  91 +++----
 drivers/gpu/drm/xe/xe_pt.c                    |   5 +-
 drivers/gpu/drm/xe/xe_res_cursor.h            |  47 +++-
 drivers/gpu/drm/xe/xe_sched_job.c             |  14 +-
 drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c        | 243 ++++++++++++++++++
 drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h        |  21 ++
 drivers/gpu/drm/xe/xe_ttm_vram_mgr.c          |  91 +++----
 drivers/gpu/drm/xe/xe_ttm_vram_mgr.h          |  18 +-
 drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h    |   2 +
 drivers/gpu/drm/xe/xe_uc_fw.c                 |  54 +++-
 drivers/gpu/drm/xe/xe_uc_fw_abi.h             |   6 +-
 drivers/gpu/drm/xe/xe_wopcm.c                 |   5 +-
 56 files changed, 1465 insertions(+), 637 deletions(-)
 create mode 120000 drivers/gpu/drm/xe/display/intel_pps.c
 delete mode 100644 drivers/gpu/drm/xe/display/intel_pps_stub.c
 create mode 100644 drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
 create mode 100644 drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h

-- 
2.38.1

[Intel-xe] [PATCH 01/37] drm/msm: Fix compile error

[Rodrigo Vivi]

From: Matthew Brost <matthew.brost@intel.com>

When changing the DRM scheduler from a kthread to a work queue the MSM
driver was not updated to reflect this change. Fix this.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 628806423f7d..37cf74a2cbc3 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -660,7 +660,7 @@ static void suspend_scheduler(struct msm_gpu *gpu)
 	 */
 	for (i = 0; i < gpu->nr_rings; i++) {
 		struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;
-		kthread_park(sched->thread);
+		drm_sched_run_wq_stop(sched);
 	}
 }
 
@@ -670,7 +670,7 @@ static void resume_scheduler(struct msm_gpu *gpu)
 
 	for (i = 0; i < gpu->nr_rings; i++) {
 		struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;
-		kthread_unpark(sched->thread);
+		drm_sched_run_wq_start(sched);
 	}
 }
 
-- 
2.38.1

[Intel-xe] [PATCH 02/37] drm/xe: Implement a local xe_mmio_wait32

[Rodrigo Vivi]

Then, move the i915_utils.h include to its user.

The overall goal is to kill all the usages of the i915_utils
stuff.

Yes, wait_for also depends on <linux/delay.h>, so they go
together to where it is needed. It will be likely needed
anyway directly for udelay or usleep_range.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_force_wake.c |  6 ++++++
 drivers/gpu/drm/xe/xe_gt_mcr.c     |  7 +++++++
 drivers/gpu/drm/xe/xe_guc.c        |  7 +++++++
 drivers/gpu/drm/xe/xe_guc_pc.c     |  7 +++++++
 drivers/gpu/drm/xe/xe_mmio.h       | 29 ++++++++++++++++++++---------
 drivers/gpu/drm/xe/xe_pcode.c      |  7 +++++++
 6 files changed, 54 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
index 5a5b6e3e715d..04b22eeb8ab5 100644
--- a/drivers/gpu/drm/xe/xe_force_wake.c
+++ b/drivers/gpu/drm/xe/xe_force_wake.c
@@ -10,6 +10,12 @@
 #include "xe_mmio.h"
 #include "../i915/gt/intel_gt_regs.h"
 
+/*
+ * FIXME: This header has been deemed evil and we need to kill it. Temporarily
+ * including so we can use '__mask_next_bit'.
+ */
+#include "i915_utils.h"
+
 #define XE_FORCE_WAKE_ACK_TIMEOUT_MS	50
 
 static struct xe_gt *
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 63829d8c8b54..ce776b260750 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -11,6 +11,13 @@
 
 #include "../i915/gt/intel_gt_regs.h"
 
+#include <linux/delay.h>
+/*
+ * FIXME: This header has been deemed evil and we need to kill it. Temporar
+ * including so we can use 'wait_for'.
+ */
+#include "i915_utils.h"
+
 /**
  * DOC: GT Multicast/Replicated (MCR) Register Support
  *
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index b5557375804f..373c94230fc3 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -22,6 +22,13 @@
 #include "i915_reg_defs.h"
 #include "../i915/gt/intel_gt_regs.h"
 
+#include <linux/delay.h>
+/*
+ * FIXME: This header has been deemed evil and we need to kill it. Temporarily
+ * including so we can use 'wait_for' and range_overflow_t.
+ */
+#include "i915_utils.h"
+
 /* TODO: move to common file */
 #define GUC_PVC_MOCS_INDEX_MASK		REG_GENMASK(25, 24)
 #define PVC_MOCS_UC_INDEX		1
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 38b1275ea655..515b7aab03c3 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -16,6 +16,13 @@
 #include "i915_reg_defs.h"
 #include "../i915/i915_reg.h"
 
+#include <linux/delay.h>
+/*
+ * FIXME: This header has been deemed evil and we need to kill it. Temporarily
+ * including so we can use 'wait_for'.
+ */
+#include "i915_utils.h"
+
 #include "../i915/intel_mchbar_regs.h"
 /* For GEN6_RP_STATE_CAP.reg to be merged when the definition moves to Xe */
 #define   RP0_MASK	REG_GENMASK(7, 0)
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index e7cca6d2f81f..d3bc0989ce2e 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -10,13 +10,6 @@
 
 #include "xe_gt_types.h"
 
-/*
- * FIXME: This header has been deemed evil and we need to kill it. Temporarily
- * including so we can use 'wait_for' and unblock initial development. A follow
- * should replace 'wait_for' with a sane version and drop including this header.
- */
-#include "i915_utils.h"
-
 struct drm_device;
 struct drm_file;
 struct xe_device;
@@ -84,8 +77,26 @@ static inline int xe_mmio_wait32(struct xe_gt *gt,
 				 u32 reg, u32 val,
 				 u32 mask, u32 timeout_ms)
 {
-	return wait_for((xe_mmio_read32(gt, reg) & mask) == val,
-			timeout_ms);
+	ktime_t cur = ktime_get_raw();
+	const ktime_t end = ktime_add_ms(cur, timeout_ms);
+	s64 wait = 10;
+
+	for (;;) {
+		if ((xe_mmio_read32(gt, reg) & mask) == val)
+			return 0;
+
+		cur = ktime_get_raw();
+		if (!ktime_before(cur, end))
+			return -ETIMEDOUT;
+
+		if (ktime_after(ktime_add_us(cur, wait), end))
+			wait = ktime_us_delta(end, cur);
+
+		usleep_range(wait, wait << 1);
+		wait <<= 1;
+	}
+
+	return -ETIMEDOUT;
 }
 
 int xe_mmio_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
index 236159c8a6c0..313ccd70d1a9 100644
--- a/drivers/gpu/drm/xe/xe_pcode.c
+++ b/drivers/gpu/drm/xe/xe_pcode.c
@@ -11,6 +11,13 @@
 
 #include <linux/errno.h>
 
+#include <linux/delay.h>
+/*
+ * FIXME: This header has been deemed evil and we need to kill it. Temporarily
+ * including so we can use 'wait_for'.
+ */
+#include "i915_utils.h"
+
 /**
  * DOC: PCODE
  *
-- 
2.38.1

[Intel-xe] [PATCH 03/37] drm/xe: Stop using i915's range_overflows_t macro.

[Rodrigo Vivi]

Let's do it directly.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 373c94230fc3..f3cb52b99d29 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -25,7 +25,7 @@
 #include <linux/delay.h>
 /*
  * FIXME: This header has been deemed evil and we need to kill it. Temporarily
- * including so we can use 'wait_for' and range_overflow_t.
+ * including so we can use 'wait_for'.
  */
 #include "i915_utils.h"
 
@@ -55,7 +55,8 @@ static u32 guc_bo_ggtt_addr(struct xe_guc *guc,
 	u32 addr = xe_bo_ggtt_addr(bo);
 
 	XE_BUG_ON(addr < xe_wopcm_size(guc_to_xe(guc)));
-	XE_BUG_ON(range_overflows_t(u32, addr, bo->size, GUC_GGTT_TOP));
+	XE_BUG_ON(addr >= GUC_GGTT_TOP);
+	XE_BUG_ON(bo->size > GUC_GGTT_TOP - addr);
 
 	return addr;
 }
-- 
2.38.1

[Intel-xe] [PATCH 04/37] drm/xe: Let's return last value read on xe_mmio_wait32.

[Rodrigo Vivi]

This is already useful because it avoids some extra reads
where registers might have changed after the timeout decision.

But also, it will be important to end the kill of i915's wait_for.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/display/intel_de.h |  4 ++--
 drivers/gpu/drm/xe/xe_force_wake.c    |  4 ++--
 drivers/gpu/drm/xe/xe_gt.c            |  2 +-
 drivers/gpu/drm/xe/xe_guc.c           | 13 ++++++-------
 drivers/gpu/drm/xe/xe_huc.c           |  2 +-
 drivers/gpu/drm/xe/xe_mmio.h          | 20 +++++++++++++++-----
 drivers/gpu/drm/xe/xe_uc_fw.c         |  7 +++----
 7 files changed, 30 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/intel_de.h b/drivers/gpu/drm/xe/display/intel_de.h
index 974aadada45a..80cc8c9e48b8 100644
--- a/drivers/gpu/drm/xe/display/intel_de.h
+++ b/drivers/gpu/drm/xe/display/intel_de.h
@@ -41,14 +41,14 @@ static inline int
 intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
 			   u32 mask, u32 value, unsigned int timeout)
 {
-	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout);
+	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout, NULL);
 }
 
 static inline int
 intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,
 			      u32 mask, u32 value, unsigned int timeout)
 {
-	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout);
+	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout, NULL);
 }
 
 static inline int
diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
index 04b22eeb8ab5..6c137d208a4a 100644
--- a/drivers/gpu/drm/xe/xe_force_wake.c
+++ b/drivers/gpu/drm/xe/xe_force_wake.c
@@ -129,7 +129,7 @@ static int domain_wake_wait(struct xe_gt *gt,
 			    struct xe_force_wake_domain *domain)
 {
 	return xe_mmio_wait32(gt, domain->reg_ack, domain->val, domain->val,
-			      XE_FORCE_WAKE_ACK_TIMEOUT_MS);
+			      XE_FORCE_WAKE_ACK_TIMEOUT_MS, NULL);
 }
 
 static void domain_sleep(struct xe_gt *gt, struct xe_force_wake_domain *domain)
@@ -141,7 +141,7 @@ static int domain_sleep_wait(struct xe_gt *gt,
 			     struct xe_force_wake_domain *domain)
 {
 	return xe_mmio_wait32(gt, domain->reg_ack, 0, domain->val,
-			      XE_FORCE_WAKE_ACK_TIMEOUT_MS);
+			      XE_FORCE_WAKE_ACK_TIMEOUT_MS, NULL);
 }
 
 #define for_each_fw_domain_masked(domain__, mask__, fw__, tmp__) \
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 7f2213b7f6c7..71d255e72234 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -559,7 +559,7 @@ int do_gt_reset(struct xe_gt *gt)
 	int err;
 
 	xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_FULL);
-	err = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_FULL, 5);
+	err = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_FULL, 5, NULL);
 	if (err)
 		drm_err(&xe->drm,
 			"GT reset failed to clear GEN11_GRDOM_FULL\n");
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index f3cb52b99d29..d7fdb0acc8ab 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -324,17 +324,17 @@ int xe_guc_reset(struct xe_guc *guc)
 {
 	struct xe_device *xe = guc_to_xe(guc);
 	struct xe_gt *gt = guc_to_gt(guc);
-	u32 guc_status;
+	u32 guc_status, gdrst;
 	int ret;
 
 	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
 
 	xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_GUC);
 
-	ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5);
+	ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5, &gdrst);
 	if (ret) {
 		drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n",
-			xe_mmio_read32(gt, GEN6_GDRST.reg));
+			gdrst);
 		goto err_out;
 	}
 
@@ -654,7 +654,7 @@ int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len)
 {
 	struct xe_device *xe = guc_to_xe(guc);
 	struct xe_gt *gt = guc_to_gt(guc);
-	u32 header;
+	u32 header, reply;
 	u32 reply_reg = xe_gt_is_media_type(gt) ?
 		MEDIA_SOFT_SCRATCH(0).reg : GEN11_SOFT_SCRATCH(0).reg;
 	int ret;
@@ -691,12 +691,11 @@ int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len)
 	ret = xe_mmio_wait32(gt, reply_reg,
 			     FIELD_PREP(GUC_HXG_MSG_0_ORIGIN,
 					GUC_HXG_ORIGIN_GUC),
-			     GUC_HXG_MSG_0_ORIGIN,
-			     50);
+			     GUC_HXG_MSG_0_ORIGIN, 50, &reply);
 	if (ret) {
 timeout:
 		drm_err(&xe->drm, "mmio request 0x%08x: no reply 0x%08x\n",
-			request[0], xe_mmio_read32(gt, reply_reg));
+			request[0], reply);
 		return ret;
 	}
 
diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
index 93b22fac6e14..c8c93bdf4760 100644
--- a/drivers/gpu/drm/xe/xe_huc.c
+++ b/drivers/gpu/drm/xe/xe_huc.c
@@ -85,7 +85,7 @@ int xe_huc_auth(struct xe_huc *huc)
 
 	ret = xe_mmio_wait32(gt, GEN11_HUC_KERNEL_LOAD_INFO.reg,
 			     HUC_LOAD_SUCCESSFUL,
-			     HUC_LOAD_SUCCESSFUL, 100);
+			     HUC_LOAD_SUCCESSFUL, 100, NULL);
 	if (ret) {
 		drm_err(&xe->drm, "HuC: Firmware not verified %d\n", ret);
 		goto fail;
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index d3bc0989ce2e..faba1694eeba 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -73,21 +73,28 @@ static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
 	return (reg_val & mask) != eval ? -EINVAL : 0;
 }
 
-static inline int xe_mmio_wait32(struct xe_gt *gt,
-				 u32 reg, u32 val,
-				 u32 mask, u32 timeout_ms)
+static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val,
+				 u32 mask, u32 timeout_ms, u32 *out_val)
 {
 	ktime_t cur = ktime_get_raw();
 	const ktime_t end = ktime_add_ms(cur, timeout_ms);
+	int ret = -ETIMEDOUT;
 	s64 wait = 10;
+	u32 read;
 
 	for (;;) {
 		if ((xe_mmio_read32(gt, reg) & mask) == val)
 			return 0;
 
+		read = xe_mmio_read32(gt, reg);
+		if ((read & mask) == val) {
+			ret = 0;
+			break;
+		}
+
 		cur = ktime_get_raw();
 		if (!ktime_before(cur, end))
-			return -ETIMEDOUT;
+			break;
 
 		if (ktime_after(ktime_add_us(cur, wait), end))
 			wait = ktime_us_delta(end, cur);
@@ -96,7 +103,10 @@ static inline int xe_mmio_wait32(struct xe_gt *gt,
 		wait <<= 1;
 	}
 
-	return -ETIMEDOUT;
+	if (out_val)
+		*out_val = read;
+
+	return ret;
 }
 
 int xe_mmio_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 86c47b7f0901..edd6a5d2db34 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -326,7 +326,7 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
 {
 	struct xe_device *xe = uc_fw_to_xe(uc_fw);
 	struct xe_gt *gt = uc_fw_to_gt(uc_fw);
-	u32 src_offset;
+	u32 src_offset, dma_ctrl;
 	int ret;
 
 	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
@@ -352,11 +352,10 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
 			_MASKED_BIT_ENABLE(dma_flags | START_DMA));
 
 	/* Wait for DMA to finish */
-	ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100);
+	ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100, &dma_ctrl);
 	if (ret)
 		drm_err(&xe->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
-			xe_uc_fw_type_repr(uc_fw->type),
-			xe_mmio_read32(gt, DMA_CTRL.reg));
+			xe_uc_fw_type_repr(uc_fw->type), dma_ctrl);
 
 	/* Disable the bits once DMA is over */
 	xe_mmio_write32(gt, DMA_CTRL.reg, _MASKED_BIT_DISABLE(dma_flags));
-- 
2.38.1

[Intel-xe] [PATCH 05/37] drm/xe: Convert guc_ready to regular xe_mmio_wait32

[Rodrigo Vivi]

Possible now that the wait function returns the last read value.

So we can remove the users of i915's wait_for one by one...

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc.c | 24 +++++-------------------
 1 file changed, 5 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index d7fdb0acc8ab..966cac79625f 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -403,24 +403,6 @@ static int guc_xfer_rsa(struct xe_guc *guc)
 	return 0;
 }
 
-/*
- * Read the GuC status register (GUC_STATUS) and store it in the
- * specified location; then return a boolean indicating whether
- * the value matches either of two values representing completion
- * of the GuC boot process.
- *
- * This is used for polling the GuC status in a wait_for()
- * loop below.
- */
-static bool guc_ready(struct xe_guc *guc, u32 *status)
-{
-	u32 val = xe_mmio_read32(guc_to_gt(guc), GUC_STATUS.reg);
-	u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, val);
-
-	*status = val;
-	return uk_val == XE_GUC_LOAD_STATUS_READY;
-}
-
 static int guc_wait_ucode(struct xe_guc *guc)
 {
 	struct xe_device *xe = guc_to_xe(guc);
@@ -444,7 +426,11 @@ static int guc_wait_ucode(struct xe_guc *guc)
 	 * 200ms. Even at slowest clock, this should be sufficient. And
 	 * in the working case, a larger timeout makes no difference.
 	 */
-	ret = wait_for(guc_ready(guc, &status), 200);
+	ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS.reg,
+			     FIELD_PREP(GS_UKERNEL_MASK,
+					XE_GUC_LOAD_STATUS_READY),
+			     GS_UKERNEL_MASK, 200, &status);
+
 	if (ret) {
 		struct drm_device *drm = &xe->drm;
 		struct drm_printer p = drm_info_printer(drm->dev);
-- 
2.38.1

[Intel-xe] [PATCH 06/37] drm/xe: Wait for success on guc done.

[Rodrigo Vivi]

Rather than a constant check on proto and wait not busy,
let's wait for the expected success and then check the
protocol afterwards.

With this, we can now use the regular xe_mmio_wait32
and kill this local need for the wait_for.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc.c | 25 ++++++++-----------------
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 966cac79625f..39a6d8f1cf68 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -22,13 +22,6 @@
 #include "i915_reg_defs.h"
 #include "../i915/gt/intel_gt_regs.h"
 
-#include <linux/delay.h>
-/*
- * FIXME: This header has been deemed evil and we need to kill it. Temporarily
- * including so we can use 'wait_for'.
- */
-#include "i915_utils.h"
-
 /* TODO: move to common file */
 #define GUC_PVC_MOCS_INDEX_MASK		REG_GENMASK(25, 24)
 #define PVC_MOCS_UC_INDEX		1
@@ -688,19 +681,17 @@ int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len)
 	header = xe_mmio_read32(gt, reply_reg);
 	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==
 	    GUC_HXG_TYPE_NO_RESPONSE_BUSY) {
-#define done ({ header = xe_mmio_read32(gt, reply_reg); \
-		FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != \
-		GUC_HXG_ORIGIN_GUC || \
-		FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != \
-		GUC_HXG_TYPE_NO_RESPONSE_BUSY; })
 
-		ret = wait_for(done, 1000);
-		if (unlikely(ret))
-			goto timeout;
+		ret = xe_mmio_wait32(gt, reply_reg,
+				     FIELD_PREP(GUC_HXG_MSG_0_TYPE,
+						GUC_HXG_TYPE_RESPONSE_SUCCESS),
+				     GUC_HXG_MSG_0_TYPE, 1000, &header);
+
 		if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=
-				       GUC_HXG_ORIGIN_GUC))
+			     GUC_HXG_ORIGIN_GUC))
 			goto proto;
-#undef done
+		if (unlikely(ret))
+			goto timeout;
 	}
 
 	if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==
-- 
2.38.1

[Intel-xe] [PATCH 07/37] drm/xe: Remove i915_utils dependency from xe_guc_pc.

[Rodrigo Vivi]

To make it simpler, all of the status checks also waits and
times out.

Also, no ktime precision is needed in this case, and we
can use usleep_range because we are not in atomic paths here.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_pc.c | 33 ++++++++++++++++++++++-----------
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 515b7aab03c3..506b9cb3f14c 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -17,11 +17,6 @@
 #include "../i915/i915_reg.h"
 
 #include <linux/delay.h>
-/*
- * FIXME: This header has been deemed evil and we need to kill it. Temporarily
- * including so we can use 'wait_for'.
- */
-#include "i915_utils.h"
 
 #include "../i915/intel_mchbar_regs.h"
 /* For GEN6_RP_STATE_CAP.reg to be merged when the definition moves to Xe */
@@ -134,10 +129,26 @@ pc_to_maps(struct xe_guc_pc *pc)
 	(FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \
 	 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, count))
 
-static bool pc_is_in_state(struct xe_guc_pc *pc, enum slpc_global_state state)
+static int wait_for_pc_state(struct xe_guc_pc *pc,
+			     enum slpc_global_state state)
 {
+	int timeout_us = 5000; /* rought 5ms, but no need for precision */
+	int slept, wait = 10;
+
 	xe_device_assert_mem_access(pc_to_xe(pc));
-	return slpc_shared_data_read(pc, header.global_state) == state;
+
+	for (slept = 0; slept < timeout_us;) {
+		if (slpc_shared_data_read(pc, header.global_state) == state)
+			return 0;
+
+		usleep_range(wait, wait << 1);
+		slept += wait;
+		wait <<= 1;
+		if (slept + wait > timeout_us)
+			wait = timeout_us - slept;
+	}
+
+	return -ETIMEDOUT;
 }
 
 static int pc_action_reset(struct xe_guc_pc *pc)
@@ -188,7 +199,7 @@ static int pc_action_query_task_state(struct xe_guc_pc *pc)
 		0,
 	};
 
-	if (!pc_is_in_state(pc, SLPC_GLOBAL_STATE_RUNNING))
+	if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING))
 		return -EAGAIN;
 
 	/* Blocking here to ensure the results are ready before reading them */
@@ -211,7 +222,7 @@ static int pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value)
 		value,
 	};
 
-	if (!pc_is_in_state(pc, SLPC_GLOBAL_STATE_RUNNING))
+	if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING))
 		return -EAGAIN;
 
 	ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0);
@@ -746,7 +757,7 @@ int xe_guc_pc_start(struct xe_guc_pc *pc)
 	if (ret)
 		goto out;
 
-	if (wait_for(pc_is_in_state(pc, SLPC_GLOBAL_STATE_RUNNING), 5)) {
+	if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING)) {
 		drm_err(&pc_to_xe(pc)->drm, "GuC PC Start failed\n");
 		ret = -EIO;
 		goto out;
@@ -792,7 +803,7 @@ int xe_guc_pc_stop(struct xe_guc_pc *pc)
 	if (ret)
 		goto out;
 
-	if (wait_for(pc_is_in_state(pc, SLPC_GLOBAL_STATE_NOT_RUNNING), 5)) {
+	if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_NOT_RUNNING)) {
 		drm_err(&pc_to_xe(pc)->drm, "GuC PC Shutdown failed\n");
 		ret = -EIO;
 	}
-- 
2.38.1

[Intel-xe] [PATCH 08/37] drm/xe: Stop using i915_utils in xe_wopcm.

[Rodrigo Vivi]

We don't need any macro for a simple check we can do explicitly
and clear.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_wopcm.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
index e4a8d4a1899e..8fe182afa06c 100644
--- a/drivers/gpu/drm/xe/xe_wopcm.c
+++ b/drivers/gpu/drm/xe/xe_wopcm.c
@@ -11,8 +11,6 @@
 #include "xe_uc_fw.h"
 #include "xe_wopcm.h"
 
-#include "i915_utils.h"
-
 /**
  * DOC: Write Once Protected Content Memory (WOPCM) Layout
  *
@@ -92,7 +90,8 @@ static bool __check_layout(struct xe_device *xe, u32 wopcm_size,
 	u32 size;
 
 	size = wopcm_size - ctx_rsvd;
-	if (unlikely(range_overflows(guc_wopcm_base, guc_wopcm_size, size))) {
+	if (unlikely(guc_wopcm_base >= size ||
+		     guc_wopcm_size > size - guc_wopcm_base)) {
 		drm_err(&xe->drm,
 			"WOPCM: invalid GuC region layout: %uK + %uK > %uK\n",
 			guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K,
-- 
2.38.1

[Intel-xe] [PATCH 09/37] drm/xe: Let's avoid i915_utils in the xe_force_wake.

[Rodrigo Vivi]

We can run the bit operation locally without yet another macro.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_force_wake.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
index 6c137d208a4a..9e2abddefb8a 100644
--- a/drivers/gpu/drm/xe/xe_force_wake.c
+++ b/drivers/gpu/drm/xe/xe_force_wake.c
@@ -10,11 +10,6 @@
 #include "xe_mmio.h"
 #include "../i915/gt/intel_gt_regs.h"
 
-/*
- * FIXME: This header has been deemed evil and we need to kill it. Temporarily
- * including so we can use '__mask_next_bit'.
- */
-#include "i915_utils.h"
 
 #define XE_FORCE_WAKE_ACK_TIMEOUT_MS	50
 
@@ -145,9 +140,9 @@ static int domain_sleep_wait(struct xe_gt *gt,
 }
 
 #define for_each_fw_domain_masked(domain__, mask__, fw__, tmp__) \
-	for (tmp__ = (mask__); tmp__ ;) \
+	for (tmp__ = (mask__); tmp__; tmp__ &= ~BIT(ffs(tmp__) - 1)) \
 		for_each_if((domain__ = ((fw__)->domains + \
-					 __mask_next_bit(tmp__))) && \
+					 (ffs(tmp__) - 1))) && \
 					 domain__->reg_ctl)
 
 int xe_force_wake_get(struct xe_force_wake *fw,
-- 
2.38.1

[Intel-xe] [PATCH 10/37] drm/xe: Convert xe_mmio_wait32 to us so we can stop using wait_for_us.

[Rodrigo Vivi]

Another clean-up towards killing the usage of i915_utils.h

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_force_wake.c | 6 ++++--
 drivers/gpu/drm/xe/xe_gt.c         | 3 ++-
 drivers/gpu/drm/xe/xe_gt_mcr.c     | 9 +--------
 drivers/gpu/drm/xe/xe_guc.c        | 9 +++++----
 drivers/gpu/drm/xe/xe_huc.c        | 2 +-
 drivers/gpu/drm/xe/xe_mmio.h       | 4 ++--
 drivers/gpu/drm/xe/xe_uc_fw.c      | 2 +-
 7 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
index 9e2abddefb8a..9c613a68b8d5 100644
--- a/drivers/gpu/drm/xe/xe_force_wake.c
+++ b/drivers/gpu/drm/xe/xe_force_wake.c
@@ -124,7 +124,8 @@ static int domain_wake_wait(struct xe_gt *gt,
 			    struct xe_force_wake_domain *domain)
 {
 	return xe_mmio_wait32(gt, domain->reg_ack, domain->val, domain->val,
-			      XE_FORCE_WAKE_ACK_TIMEOUT_MS, NULL);
+			      XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,
+			      NULL);
 }
 
 static void domain_sleep(struct xe_gt *gt, struct xe_force_wake_domain *domain)
@@ -136,7 +137,8 @@ static int domain_sleep_wait(struct xe_gt *gt,
 			     struct xe_force_wake_domain *domain)
 {
 	return xe_mmio_wait32(gt, domain->reg_ack, 0, domain->val,
-			      XE_FORCE_WAKE_ACK_TIMEOUT_MS, NULL);
+			      XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,
+			      NULL);
 }
 
 #define for_each_fw_domain_masked(domain__, mask__, fw__, tmp__) \
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 71d255e72234..bf173f374e73 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -559,7 +559,8 @@ int do_gt_reset(struct xe_gt *gt)
 	int err;
 
 	xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_FULL);
-	err = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_FULL, 5, NULL);
+	err = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_FULL, 5000,
+			     NULL);
 	if (err)
 		drm_err(&xe->drm,
 			"GT reset failed to clear GEN11_GRDOM_FULL\n");
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index ce776b260750..51badd3d6e90 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -11,13 +11,6 @@
 
 #include "../i915/gt/intel_gt_regs.h"
 
-#include <linux/delay.h>
-/*
- * FIXME: This header has been deemed evil and we need to kill it. Temporar
- * including so we can use 'wait_for'.
- */
-#include "i915_utils.h"
-
 /**
  * DOC: GT Multicast/Replicated (MCR) Register Support
  *
@@ -383,7 +376,7 @@ static void mcr_lock(struct xe_gt *gt)
 	 * shares the same steering control register.
 	 */
 	if (GRAPHICS_VERx100(xe) >= 1270)
-		ret = wait_for_us(xe_mmio_read32(gt, STEER_SEMAPHORE) == 0x1, 10);
+		ret = xe_mmio_wait32(gt, STEER_SEMAPHORE, 0, 0x1, 10, NULL);
 
 	drm_WARN_ON_ONCE(&xe->drm, ret == -ETIMEDOUT);
 }
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 39a6d8f1cf68..de24d289c635 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -324,7 +324,8 @@ int xe_guc_reset(struct xe_guc *guc)
 
 	xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_GUC);
 
-	ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5, &gdrst);
+	ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5000,
+			     &gdrst);
 	if (ret) {
 		drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n",
 			gdrst);
@@ -422,7 +423,7 @@ static int guc_wait_ucode(struct xe_guc *guc)
 	ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS.reg,
 			     FIELD_PREP(GS_UKERNEL_MASK,
 					XE_GUC_LOAD_STATUS_READY),
-			     GS_UKERNEL_MASK, 200, &status);
+			     GS_UKERNEL_MASK, 200000, &status);
 
 	if (ret) {
 		struct drm_device *drm = &xe->drm;
@@ -670,7 +671,7 @@ int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len)
 	ret = xe_mmio_wait32(gt, reply_reg,
 			     FIELD_PREP(GUC_HXG_MSG_0_ORIGIN,
 					GUC_HXG_ORIGIN_GUC),
-			     GUC_HXG_MSG_0_ORIGIN, 50, &reply);
+			     GUC_HXG_MSG_0_ORIGIN, 50000, &reply);
 	if (ret) {
 timeout:
 		drm_err(&xe->drm, "mmio request 0x%08x: no reply 0x%08x\n",
@@ -685,7 +686,7 @@ int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len)
 		ret = xe_mmio_wait32(gt, reply_reg,
 				     FIELD_PREP(GUC_HXG_MSG_0_TYPE,
 						GUC_HXG_TYPE_RESPONSE_SUCCESS),
-				     GUC_HXG_MSG_0_TYPE, 1000, &header);
+				     GUC_HXG_MSG_0_TYPE, 1000000, &header);
 
 		if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=
 			     GUC_HXG_ORIGIN_GUC))
diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
index c8c93bdf4760..9cb15bb40a38 100644
--- a/drivers/gpu/drm/xe/xe_huc.c
+++ b/drivers/gpu/drm/xe/xe_huc.c
@@ -85,7 +85,7 @@ int xe_huc_auth(struct xe_huc *huc)
 
 	ret = xe_mmio_wait32(gt, GEN11_HUC_KERNEL_LOAD_INFO.reg,
 			     HUC_LOAD_SUCCESSFUL,
-			     HUC_LOAD_SUCCESSFUL, 100, NULL);
+			     HUC_LOAD_SUCCESSFUL, 100000, NULL);
 	if (ret) {
 		drm_err(&xe->drm, "HuC: Firmware not verified %d\n", ret);
 		goto fail;
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index faba1694eeba..2edf3a166515 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -74,10 +74,10 @@ static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
 }
 
 static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val,
-				 u32 mask, u32 timeout_ms, u32 *out_val)
+				 u32 mask, u32 timeout_us, u32 *out_val)
 {
 	ktime_t cur = ktime_get_raw();
-	const ktime_t end = ktime_add_ms(cur, timeout_ms);
+	const ktime_t end = ktime_add_us(cur, timeout_us);
 	int ret = -ETIMEDOUT;
 	s64 wait = 10;
 	u32 read;
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index edd6a5d2db34..bbb931bc19ce 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -352,7 +352,7 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
 			_MASKED_BIT_ENABLE(dma_flags | START_DMA));
 
 	/* Wait for DMA to finish */
-	ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100, &dma_ctrl);
+	ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100000, &dma_ctrl);
 	if (ret)
 		drm_err(&xe->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
 			xe_uc_fw_type_repr(uc_fw->type), dma_ctrl);
-- 
2.38.1

[Intel-xe] [PATCH 11/37] drm/xe: Remove i915_utils dependency from xe_pcode.

[Rodrigo Vivi]

Expand xe_mmio_wait32 to accept atomic and then use
that directly when possible, and create own routine to
wait for the pcode status.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/display/intel_de.h |  6 +-
 drivers/gpu/drm/xe/xe_force_wake.c    |  4 +-
 drivers/gpu/drm/xe/xe_gt.c            |  2 +-
 drivers/gpu/drm/xe/xe_gt_mcr.c        |  3 +-
 drivers/gpu/drm/xe/xe_guc.c           |  9 +--
 drivers/gpu/drm/xe/xe_huc.c           |  2 +-
 drivers/gpu/drm/xe/xe_mmio.h          |  9 ++-
 drivers/gpu/drm/xe/xe_pcode.c         | 94 +++++++++++----------------
 drivers/gpu/drm/xe/xe_uc_fw.c         |  3 +-
 9 files changed, 61 insertions(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/intel_de.h b/drivers/gpu/drm/xe/display/intel_de.h
index 80cc8c9e48b8..678b4247464a 100644
--- a/drivers/gpu/drm/xe/display/intel_de.h
+++ b/drivers/gpu/drm/xe/display/intel_de.h
@@ -41,14 +41,16 @@ static inline int
 intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
 			   u32 mask, u32 value, unsigned int timeout)
 {
-	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout, NULL);
+	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout, NULL,
+			      false);
 }
 
 static inline int
 intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,
 			      u32 mask, u32 value, unsigned int timeout)
 {
-	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout, NULL);
+	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout, NULL,
+			      false);
 }
 
 static inline int
diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
index 9c613a68b8d5..f4dad04bd5d6 100644
--- a/drivers/gpu/drm/xe/xe_force_wake.c
+++ b/drivers/gpu/drm/xe/xe_force_wake.c
@@ -125,7 +125,7 @@ static int domain_wake_wait(struct xe_gt *gt,
 {
 	return xe_mmio_wait32(gt, domain->reg_ack, domain->val, domain->val,
 			      XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,
-			      NULL);
+			      NULL, false);
 }
 
 static void domain_sleep(struct xe_gt *gt, struct xe_force_wake_domain *domain)
@@ -138,7 +138,7 @@ static int domain_sleep_wait(struct xe_gt *gt,
 {
 	return xe_mmio_wait32(gt, domain->reg_ack, 0, domain->val,
 			      XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,
-			      NULL);
+			      NULL, false);
 }
 
 #define for_each_fw_domain_masked(domain__, mask__, fw__, tmp__) \
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index bf173f374e73..ccb87a7c6554 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -560,7 +560,7 @@ int do_gt_reset(struct xe_gt *gt)
 
 	xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_FULL);
 	err = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_FULL, 5000,
-			     NULL);
+			     NULL, false);
 	if (err)
 		drm_err(&xe->drm,
 			"GT reset failed to clear GEN11_GRDOM_FULL\n");
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 51badd3d6e90..d940a576b47c 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -376,7 +376,8 @@ static void mcr_lock(struct xe_gt *gt)
 	 * shares the same steering control register.
 	 */
 	if (GRAPHICS_VERx100(xe) >= 1270)
-		ret = xe_mmio_wait32(gt, STEER_SEMAPHORE, 0, 0x1, 10, NULL);
+		ret = xe_mmio_wait32(gt, STEER_SEMAPHORE, 0, 0x1, 10, NULL,
+				     false);
 
 	drm_WARN_ON_ONCE(&xe->drm, ret == -ETIMEDOUT);
 }
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index de24d289c635..34d7d20a2ce7 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -325,7 +325,7 @@ int xe_guc_reset(struct xe_guc *guc)
 	xe_mmio_write32(gt, GEN6_GDRST.reg, GEN11_GRDOM_GUC);
 
 	ret = xe_mmio_wait32(gt, GEN6_GDRST.reg, 0, GEN11_GRDOM_GUC, 5000,
-			     &gdrst);
+			     &gdrst, false);
 	if (ret) {
 		drm_err(&xe->drm, "GuC reset timed out, GEN6_GDRST=0x%8x\n",
 			gdrst);
@@ -423,7 +423,7 @@ static int guc_wait_ucode(struct xe_guc *guc)
 	ret = xe_mmio_wait32(guc_to_gt(guc), GUC_STATUS.reg,
 			     FIELD_PREP(GS_UKERNEL_MASK,
 					XE_GUC_LOAD_STATUS_READY),
-			     GS_UKERNEL_MASK, 200000, &status);
+			     GS_UKERNEL_MASK, 200000, &status, false);
 
 	if (ret) {
 		struct drm_device *drm = &xe->drm;
@@ -671,7 +671,7 @@ int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len)
 	ret = xe_mmio_wait32(gt, reply_reg,
 			     FIELD_PREP(GUC_HXG_MSG_0_ORIGIN,
 					GUC_HXG_ORIGIN_GUC),
-			     GUC_HXG_MSG_0_ORIGIN, 50000, &reply);
+			     GUC_HXG_MSG_0_ORIGIN, 50000, &reply, false);
 	if (ret) {
 timeout:
 		drm_err(&xe->drm, "mmio request 0x%08x: no reply 0x%08x\n",
@@ -686,7 +686,8 @@ int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len)
 		ret = xe_mmio_wait32(gt, reply_reg,
 				     FIELD_PREP(GUC_HXG_MSG_0_TYPE,
 						GUC_HXG_TYPE_RESPONSE_SUCCESS),
-				     GUC_HXG_MSG_0_TYPE, 1000000, &header);
+				     GUC_HXG_MSG_0_TYPE, 1000000, &header,
+				     false);
 
 		if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=
 			     GUC_HXG_ORIGIN_GUC))
diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
index 9cb15bb40a38..82e7fb3a6292 100644
--- a/drivers/gpu/drm/xe/xe_huc.c
+++ b/drivers/gpu/drm/xe/xe_huc.c
@@ -85,7 +85,7 @@ int xe_huc_auth(struct xe_huc *huc)
 
 	ret = xe_mmio_wait32(gt, GEN11_HUC_KERNEL_LOAD_INFO.reg,
 			     HUC_LOAD_SUCCESSFUL,
-			     HUC_LOAD_SUCCESSFUL, 100000, NULL);
+			     HUC_LOAD_SUCCESSFUL, 100000, NULL, false);
 	if (ret) {
 		drm_err(&xe->drm, "HuC: Firmware not verified %d\n", ret);
 		goto fail;
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 2edf3a166515..009bc14a24f4 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -73,8 +73,8 @@ static inline int xe_mmio_write32_and_verify(struct xe_gt *gt,
 	return (reg_val & mask) != eval ? -EINVAL : 0;
 }
 
-static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val,
-				 u32 mask, u32 timeout_us, u32 *out_val)
+static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val, u32 mask,
+				 u32 timeout_us, u32 *out_val, bool atomic)
 {
 	ktime_t cur = ktime_get_raw();
 	const ktime_t end = ktime_add_us(cur, timeout_us);
@@ -99,7 +99,10 @@ static inline int xe_mmio_wait32(struct xe_gt *gt, u32 reg, u32 val,
 		if (ktime_after(ktime_add_us(cur, wait), end))
 			wait = ktime_us_delta(end, cur);
 
-		usleep_range(wait, wait << 1);
+		if (atomic)
+			udelay(wait);
+		else
+			usleep_range(wait, wait << 1);
 		wait <<= 1;
 	}
 
diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
index 313ccd70d1a9..39712e843728 100644
--- a/drivers/gpu/drm/xe/xe_pcode.c
+++ b/drivers/gpu/drm/xe/xe_pcode.c
@@ -12,11 +12,6 @@
 #include <linux/errno.h>
 
 #include <linux/delay.h>
-/*
- * FIXME: This header has been deemed evil and we need to kill it. Temporarily
- * including so we can use 'wait_for'.
- */
-#include "i915_utils.h"
 
 /**
  * DOC: PCODE
@@ -59,28 +54,24 @@ static int pcode_mailbox_status(struct xe_gt *gt)
 	return 0;
 }
 
-static bool pcode_mailbox_done(struct xe_gt *gt)
-{
-	lockdep_assert_held(&gt->pcode.lock);
-	return (xe_mmio_read32(gt, PCODE_MAILBOX.reg) & PCODE_READY) == 0;
-}
-
 static int pcode_mailbox_rw(struct xe_gt *gt, u32 mbox, u32 *data0, u32 *data1,
-			    unsigned int timeout, bool return_data, bool atomic)
+			    unsigned int timeout_ms, bool return_data,
+			    bool atomic)
 {
+	int err;
 	lockdep_assert_held(&gt->pcode.lock);
 
-	if (!pcode_mailbox_done(gt))
+	if ((xe_mmio_read32(gt, PCODE_MAILBOX.reg) & PCODE_READY) != 0)
 		return -EAGAIN;
 
 	xe_mmio_write32(gt, PCODE_DATA0.reg, *data0);
 	xe_mmio_write32(gt, PCODE_DATA1.reg, data1 ? *data1 : 0);
 	xe_mmio_write32(gt, PCODE_MAILBOX.reg, PCODE_READY | mbox);
 
-	if (atomic)
-		_wait_for_atomic(pcode_mailbox_done(gt), timeout * 1000, 1);
-	else
-		wait_for(pcode_mailbox_done(gt), timeout);
+	err = xe_mmio_wait32(gt, PCODE_MAILBOX.reg, 0, PCODE_READY,
+			     timeout_ms * 1000, NULL, atomic);
+	if (err)
+		return err;
 
 	if (return_data) {
 		*data0 = xe_mmio_read32(gt, PCODE_DATA0.reg);
@@ -113,13 +104,26 @@ int xe_pcode_read(struct xe_gt *gt, u32 mbox, u32 *val, u32 *val1)
 	return err;
 }
 
-static bool xe_pcode_try_request(struct xe_gt *gt, u32 mbox,
-				  u32 request, u32 reply_mask, u32 reply,
-				  u32 *status, bool atomic)
+static int xe_pcode_try_request(struct xe_gt *gt, u32 mbox,
+				u32 request, u32 reply_mask, u32 reply,
+				u32 *status, bool atomic, int timeout_us)
 {
-	*status = pcode_mailbox_rw(gt, mbox, &request, NULL, 1, true, atomic);
+	int slept, wait = 10;
+
+	for (slept = 0; slept < timeout_us; slept += wait) {
+		*status = pcode_mailbox_rw(gt, mbox, &request, NULL, 1, true,
+					   atomic);
+		if ((*status == 0) && ((request & reply_mask) == reply))
+			return 0;
+
+		if (atomic)
+			udelay(wait);
+		else
+			usleep_range(wait, wait << 1);
+		wait <<= 1;
+	}
 
-	return (*status == 0) && ((request & reply_mask) == reply);
+	return -ETIMEDOUT;
 }
 
 /**
@@ -146,25 +150,12 @@ int xe_pcode_request(struct xe_gt *gt, u32 mbox, u32 request,
 {
 	u32 status;
 	int ret;
-	bool atomic = false;
 
 	mutex_lock(&gt->pcode.lock);
 
-#define COND \
-	xe_pcode_try_request(gt, mbox, request, reply_mask, reply, &status, atomic)
-
-	/*
-	 * Prime the PCODE by doing a request first. Normally it guarantees
-	 * that a subsequent request, at most @timeout_base_ms later, succeeds.
-	 * _wait_for() doesn't guarantee when its passed condition is evaluated
-	 * first, so send the first request explicitly.
-	 */
-	if (COND) {
-		ret = 0;
-		goto out;
-	}
-	ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
-	if (!ret)
+	ret = xe_pcode_try_request(gt, mbox, request, reply_mask, reply, &status,
+				   false, timeout_base_ms * 1000);
+	if (ret)
 		goto out;
 
 	/*
@@ -181,15 +172,13 @@ int xe_pcode_request(struct xe_gt *gt, u32 mbox, u32 request,
 		"PCODE timeout, retrying with preemption disabled\n");
 	drm_WARN_ON_ONCE(&gt_to_xe(gt)->drm, timeout_base_ms > 1);
 	preempt_disable();
-	atomic = true;
-	ret = wait_for_atomic(COND, 50);
-	atomic = false;
+	ret = xe_pcode_try_request(gt, mbox, request, reply_mask, reply, &status,
+				   true, timeout_base_ms * 1000);
 	preempt_enable();
 
 out:
 	mutex_unlock(&gt->pcode.lock);
 	return status ? status : ret;
-#undef COND
 }
 /**
  * xe_pcode_init_min_freq_table - Initialize PCODE's QOS frequency table
@@ -243,16 +232,6 @@ int xe_pcode_init_min_freq_table(struct xe_gt *gt, u32 min_gt_freq,
 	return ret;
 }
 
-static bool pcode_dgfx_status_complete(struct xe_gt *gt)
-{
-	u32 data = DGFX_GET_INIT_STATUS;
-	int status = pcode_mailbox_rw(gt, DGFX_PCODE_STATUS,
-				      &data, NULL, 1, true, false);
-
-	return status == 0 &&
-		(data & DGFX_INIT_STATUS_COMPLETE) == DGFX_INIT_STATUS_COMPLETE;
-}
-
 /**
  * xe_pcode_init - Ensure PCODE is initialized
  * @gt: gt instance
@@ -264,20 +243,23 @@ static bool pcode_dgfx_status_complete(struct xe_gt *gt)
  */
 int xe_pcode_init(struct xe_gt *gt)
 {
-	int timeout = 180000; /* 3 min */
+	u32 status, request = DGFX_GET_INIT_STATUS;
+	int timeout_us = 180000000; /* 3 min */
 	int ret;
 
 	if (!IS_DGFX(gt_to_xe(gt)))
 		return 0;
 
 	mutex_lock(&gt->pcode.lock);
-	ret = wait_for(pcode_dgfx_status_complete(gt), timeout);
+	ret = xe_pcode_try_request(gt, DGFX_PCODE_STATUS, request,
+				   DGFX_INIT_STATUS_COMPLETE,
+				   DGFX_INIT_STATUS_COMPLETE,
+				   &status, false, timeout_us);
 	mutex_unlock(&gt->pcode.lock);
 
 	if (ret)
 		drm_err(&gt_to_xe(gt)->drm,
-			"PCODE initialization timedout after: %d min\n",
-			timeout / 60000);
+			"PCODE initialization timedout after: 3 min\n");
 
 	return ret;
 }
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index bbb931bc19ce..cd264cf50d30 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -352,7 +352,8 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
 			_MASKED_BIT_ENABLE(dma_flags | START_DMA));
 
 	/* Wait for DMA to finish */
-	ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100000, &dma_ctrl);
+	ret = xe_mmio_wait32(gt, DMA_CTRL.reg, 0, START_DMA, 100000, &dma_ctrl,
+			     false);
 	if (ret)
 		drm_err(&xe->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
 			xe_uc_fw_type_repr(uc_fw->type), dma_ctrl);
-- 
2.38.1

[Intel-xe] [PATCH 12/37] drm/xe/migrate: Add kerneldoc for the migrate subsystem

[Rodrigo Vivi]

From: Thomas Hellström <thomas.hellstrom@linux.intel.com>

Add kerneldoc for structs and external functions.

Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_migrate.c | 108 +++++++++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_migrate.h |  16 ++++-
 2 files changed, 120 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 01177ee31d43..7b9f3de11b47 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -27,16 +27,37 @@
 
 #include "../i915/gt/intel_gpu_commands.h"
 
+/**
+ * struct xe_migrate - migrate context.
+ */
 struct xe_migrate {
+	/** @eng: Default engine used for migration */
 	struct xe_engine *eng;
+	/** @gt: Backpointer to the gt this struct xe_migrate belongs to. */
 	struct xe_gt *gt;
+	/** @job_mutex: Timeline mutex for @eng. */
 	struct mutex job_mutex;
+	/** @pt_bo: Page-table buffer object. */
 	struct xe_bo *pt_bo;
+	/**
+	 * @cleared_bo: Zeroed out bo used as a source for CCS metadata clears
+	 */
 	struct xe_bo *cleared_bo;
+	/** @batch_base_ofs: VM offset of the migration batch buffer */
 	u64 batch_base_ofs;
+	/** @usm_batch_base_ofs: VM offset of the usm batch buffer */
 	u64 usm_batch_base_ofs;
+	/** @cleared_vram_ofs: VM offset of @cleared_bo. */
 	u64 cleared_vram_ofs;
+	/**
+	 * @fence: dma-fence representing the last migration job batch.
+	 * Protected by @job_mutex.
+	 */
 	struct dma_fence *fence;
+	/**
+	 * @vm_update_sa: For integrated, used to suballocate page-tables
+	 * out of the pt_bo.
+	 */
 	struct drm_suballoc_manager vm_update_sa;
 };
 
@@ -45,6 +66,15 @@ struct xe_migrate {
 #define NUM_PT_SLOTS 32
 #define NUM_PT_PER_BLIT (MAX_PREEMPTDISABLE_TRANSFER / SZ_2M)
 
+/**
+ * xe_gt_migrate_engine() - Get this gt's migrate engine.
+ * @gt: The gt.
+ *
+ * Returns the default migrate engine of this gt.
+ * TODO: Perhaps this function is slightly misplaced, and even unneeded?
+ *
+ * Return: The default migrate engine
+ */
 struct xe_engine *xe_gt_migrate_engine(struct xe_gt *gt)
 {
 	return gt->migrate->eng;
@@ -271,6 +301,12 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
 	return 0;
 }
 
+/**
+ * xe_migrate_init() - Initialize a migrate context
+ * @gt: Back-pointer to the gt we're initializing for.
+ *
+ * Return: Pointer to a migrate context on success. Error pointer on error.
+ */
 struct xe_migrate *xe_migrate_init(struct xe_gt *gt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
@@ -540,6 +576,24 @@ static u32 xe_migrate_ccs_copy(struct xe_migrate *m,
 	return flush_flags;
 }
 
+/**
+ * xe_migrate_copy() - Copy content of TTM resources.
+ * @m: The migration context.
+ * @bo: The buffer object @src is currently bound to.
+ * @src: The source TTM resource.
+ * @dst: The dst TTM resource.
+ *
+ * Copies the contents of @src to @dst: On flat CCS devices,
+ * the CCS metadata is copied as well if needed, or if not present,
+ * the CCS metadata of @dst is cleared for security reasons.
+ * It's currently not possible to copy between two system resources,
+ * since that would require two TTM page-vectors.
+ * TODO: Eliminate the @bo argument and supply two TTM page-vectors.
+ *
+ * Return: Pointer to a dma_fence representing the last copy batch, or
+ * an error pointer on failure. If there is a failure, any copy operation
+ * started by the function call has been synced.
+ */
 struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
 				  struct xe_bo *bo,
 				  struct ttm_resource *src,
@@ -683,7 +737,7 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
 		xe_bb_free(bb, NULL);
 
 err_sync:
-		/* Sync partial copy if any. */
+		/* Sync partial copy if any. FIXME: under job_mutex? */
 		if (fence) {
 			dma_fence_wait(fence, false);
 			dma_fence_put(fence);
@@ -733,6 +787,21 @@ static int emit_clear(struct xe_gt *gt, struct xe_bb *bb, u64 src_ofs,
 	return 0;
 }
 
+/**
+ * xe_migrate_clear() - Copy content of TTM resources.
+ * @m: The migration context.
+ * @bo: The buffer object @dst is currently bound to.
+ * @dst: The dst TTM resource to be cleared.
+ * @value: Clear value.
+ *
+ * Clear the contents of @dst. On flat CCS devices,
+ * the CCS metadata is cleared to zero as well on VRAM destionations.
+ * TODO: Eliminate the @bo argument.
+ *
+ * Return: Pointer to a dma_fence representing the last clear batch, or
+ * an error pointer on failure. If there is a failure, any clear operation
+ * started by the function call has been synced.
+ */
 struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
 				   struct xe_bo *bo,
 				   struct ttm_resource *dst,
@@ -836,7 +905,7 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
 		mutex_unlock(&m->job_mutex);
 		xe_bb_free(bb, NULL);
 err_sync:
-		/* Sync partial copies if any. */
+		/* Sync partial copies if any. FIXME: job_mutex? */
 		if (fence) {
 			dma_fence_wait(m->fence, false);
 			dma_fence_put(fence);
@@ -974,6 +1043,33 @@ static bool engine_is_idle(struct xe_engine *e)
 		xe_lrc_seqno(&e->lrc[0]) == e->lrc[0].fence_ctx.next_seqno;
 }
 
+/**
+ * xe_migrate_update_pgtables() - Pipelined page-table update
+ * @m: The migrate context.
+ * @vm: The vm we'll be updating.
+ * @bo: The bo whose dma-resv we will await before updating, or NULL if userptr.
+ * @eng: The engine to be used for the update or NULL if the default
+ * migration engine is to be used.
+ * @updates: An array of update descriptors.
+ * @num_updates: Number of descriptors in @updates.
+ * @syncs: Array of xe_sync_entry to await before updating. Note that waits
+ * will block the engine timeline.
+ * @num_syncs: Number of entries in @syncs.
+ * @pt_update: Pointer to a struct xe_migrate_pt_update, which contains
+ * pointers to callback functions and, if subclassed, private arguments to
+ * those.
+ *
+ * Perform a pipelined page-table update. The update descriptors are typically
+ * built under the same lock critical section as a call to this function. If
+ * using the default engine for the updates, they will be performed in the
+ * order they grab the job_mutex. If different engines are used, external
+ * synchronization is needed for overlapping updates to maintain page-table
+ * consistency. Note that the meaing of "overlapping" is that the updates
+ * touch the same page-table, which might be a higher-level page-directory.
+ * If no pipelining is needed, then updates may be performed by the cpu.
+ *
+ * Return: A dma_fence that, when signaled, indicates the update completion.
+ */
 struct dma_fence *
 xe_migrate_update_pgtables(struct xe_migrate *m,
 			   struct xe_vm *vm,
@@ -1157,6 +1253,14 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
 	return ERR_PTR(err);
 }
 
+/**
+ * xe_migrate_wait() - Complete all operations using the xe_migrate context
+ * @m: Migrate context to wait for.
+ *
+ * Waits until the GPU no longer uses the migrate context's default engine
+ * or its page-table objects. FIXME: What about separate page-table update
+ * engines?
+ */
 void xe_migrate_wait(struct xe_migrate *m)
 {
 	if (m->fence)
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index 267057a3847f..b2d55283252f 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -23,9 +23,13 @@ struct xe_vm;
 struct xe_vm_pgtable_update;
 struct xe_vma;
 
+/**
+ * struct xe_migrate_pt_update_ops - Callbacks for the
+ * xe_migrate_update_pgtables() function.
+ */
 struct xe_migrate_pt_update_ops {
 	/**
-	 * populate() - Populate a command buffer or page-table with ptes.
+	 * @populate: Populate a command buffer or page-table with ptes.
 	 * @pt_update: Embeddable callback argument.
 	 * @gt: The gt for the current operation.
 	 * @map: struct iosys_map into the memory to be populated.
@@ -44,7 +48,7 @@ struct xe_migrate_pt_update_ops {
 			 const struct xe_vm_pgtable_update *update);
 
 	/**
-	 * pre_commit(): Callback to be called just before arming the
+	 * @pre_commit: Callback to be called just before arming the
 	 * sched_job.
 	 * @pt_update: Pointer to embeddable callback argument.
 	 *
@@ -53,8 +57,16 @@ struct xe_migrate_pt_update_ops {
 	int (*pre_commit)(struct xe_migrate_pt_update *pt_update);
 };
 
+/**
+ * struct xe_migrate_pt_update - Argument to the
+ * struct xe_migrate_pt_update_ops callbacks.
+ *
+ * Intended to be subclassed to support additional arguments if necessary.
+ */
 struct xe_migrate_pt_update {
+	/** @ops: Pointer to the struct xe_migrate_pt_update_ops callbacks */
 	const struct xe_migrate_pt_update_ops *ops;
+	/** @vma: The vma we're updating the pagetable for. */
 	struct xe_vma *vma;
 };
 
-- 
2.38.1

[Intel-xe] [PATCH 13/37] drm/xe: Take memory ref on kernel job creation

[Rodrigo Vivi]

From: Matthew Brost <matthew.brost@intel.com>

When a job is inflight we may access memory to read the hardware seqno.
All user jobs have VM open which has a ref but kernel jobs do not
require VM so it is possible to not have memory ref. To avoid this, take
a memory ref on kernel job creation.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_sched_job.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c
index 5c4cf3d0d7a4..2985caa6097b 100644
--- a/drivers/gpu/drm/xe/xe_sched_job.c
+++ b/drivers/gpu/drm/xe/xe_sched_job.c
@@ -8,7 +8,7 @@
 #include <linux/dma-fence-array.h>
 #include <linux/slab.h>
 
-#include "xe_device_types.h"
+#include "xe_device.h"
 #include "xe_engine.h"
 #include "xe_gt.h"
 #include "xe_hw_engine_types.h"
@@ -72,6 +72,11 @@ static void job_free(struct xe_sched_job *job)
 			xe_sched_job_parallel_slab : xe_sched_job_slab, job);
 }
 
+static struct xe_device *job_to_xe(struct xe_sched_job *job)
+{
+	return gt_to_xe(job->engine->gt);
+}
+
 struct xe_sched_job *xe_sched_job_create(struct xe_engine *e,
 					 u64 *batch_addr)
 {
@@ -149,6 +154,11 @@ struct xe_sched_job *xe_sched_job_create(struct xe_engine *e,
 	for (i = 0; i < width; ++i)
 		job->batch_addr[i] = batch_addr[i];
 
+	/* All other jobs require a VM to be open which has a ref */
+	if (unlikely(e->flags & ENGINE_FLAG_KERNEL))
+		xe_device_mem_access_get(job_to_xe(job));
+	xe_device_assert_mem_access(job_to_xe(job));
+
 	trace_xe_sched_job_create(job);
 	return job;
 
@@ -178,6 +188,8 @@ void xe_sched_job_destroy(struct kref *ref)
 	struct xe_sched_job *job =
 		container_of(ref, struct xe_sched_job, refcount);
 
+	if (unlikely(job->engine->flags & ENGINE_FLAG_KERNEL))
+		xe_device_mem_access_put(job_to_xe(job));
 	xe_engine_put(job->engine);
 	dma_fence_put(job->fence);
 	drm_sched_job_cleanup(&job->drm);
-- 
2.38.1

[Intel-xe] [PATCH 14/37] drm/xe: Add intel_pps support too

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

I misguidedly believed that this was i915 only due to support on old
platforms, but if I look at intel_num_pps() the code is valid
on all gen12+ platforms too.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pps.c    | 14 ++++++-
 drivers/gpu/drm/xe/Makefile                 |  2 +-
 drivers/gpu/drm/xe/display/intel_pps.c      |  1 +
 drivers/gpu/drm/xe/display/intel_pps_stub.c | 43 ---------------------
 4 files changed, 14 insertions(+), 46 deletions(-)
 create mode 120000 drivers/gpu/drm/xe/display/intel_pps.c
 delete mode 100644 drivers/gpu/drm/xe/display/intel_pps_stub.c

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 7b21438edd9b..9f3675456913 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -3,7 +3,6 @@
  * Copyright © 2020 Intel Corporation
  */
 
-#include "g4x_dp.h"
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_de.h"
@@ -16,6 +15,11 @@
 #include "intel_pps.h"
 #include "intel_quirks.h"
 
+#ifdef I915
+#include "g4x_dp.h"
+#include "intel_dpio_phy.h"
+#endif
+
 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 				      enum pipe pipe);
 
@@ -81,6 +85,7 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
 	return 0;
 }
 
+#ifdef I915
 static void
 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 {
@@ -265,6 +270,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 
 	return pps_idx;
 }
+#endif
 
 typedef bool (*pps_check)(struct drm_i915_private *dev_priv, int pps_idx);
 
@@ -478,16 +484,18 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
 				    struct pps_registers *regs)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	int pps_idx;
+	int pps_idx = 0;
 
 	memset(regs, 0, sizeof(*regs));
 
+#ifdef I915
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		pps_idx = vlv_power_sequencer_pipe(intel_dp);
 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 		pps_idx = bxt_power_sequencer_idx(intel_dp);
 	else
 		pps_idx = intel_dp->pps.pps_idx;
+#endif
 
 	regs->pp_ctrl = PP_CONTROL(pps_idx);
 	regs->pp_stat = PP_STATUS(pps_idx);
@@ -1684,6 +1692,7 @@ void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
 		return;
 
 	if (HAS_PCH_SPLIT(dev_priv)) {
+#ifdef I915
 		u32 port_sel;
 
 		pp_reg = PP_CONTROL(0);
@@ -1710,6 +1719,7 @@ void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
 		/* presumably write lock depends on pipe, not port select */
 		pp_reg = PP_CONTROL(pipe);
 		panel_pipe = pipe;
+#endif
 	} else {
 		u32 port_sel;
 
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 5db7a811efdf..36996fe7d7a4 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -167,7 +167,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	display/intel_opregion.o \
 	display/intel_panel.o \
 	display/intel_pipe_crc.o \
-	display/intel_pps_stub.o \
+	display/intel_pps.o \
 	display/intel_psr.o \
 	display/intel_qp_tables.o \
 	display/intel_quirks.o \
diff --git a/drivers/gpu/drm/xe/display/intel_pps.c b/drivers/gpu/drm/xe/display/intel_pps.c
new file mode 120000
index 000000000000..ce8eef664f23
--- /dev/null
+++ b/drivers/gpu/drm/xe/display/intel_pps.c
@@ -0,0 +1 @@
+../../i915/display/intel_pps.c
\ No newline at end of file
diff --git a/drivers/gpu/drm/xe/display/intel_pps_stub.c b/drivers/gpu/drm/xe/display/intel_pps_stub.c
deleted file mode 100644
index 65a8174165f9..000000000000
--- a/drivers/gpu/drm/xe/display/intel_pps_stub.c
+++ /dev/null
@@ -1,43 +0,0 @@
-#include "intel_pps.h"
-#include "intel_display.h"
-
-intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
-{
-        return 0;
-}
-
-intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
-{
-        return wakeref;
-}
-
-void intel_pps_backlight_on(struct intel_dp *intel_dp) {}
-void intel_pps_backlight_off(struct intel_dp *intel_dp) {}
-void intel_pps_backlight_power(struct intel_connector *connector, bool enable) {}
-
-bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp) { return false; }
-void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync) {}
-void intel_pps_on_unlocked(struct intel_dp *intel_dp) {}
-void intel_pps_off_unlocked(struct intel_dp *intel_dp) {}
-void intel_pps_check_power_unlocked(struct intel_dp *intel_dp) {}
-
-void intel_pps_vdd_on(struct intel_dp *intel_dp) {}
-void intel_pps_on(struct intel_dp *intel_dp) {}
-void intel_pps_off(struct intel_dp *intel_dp) {}
-void intel_pps_vdd_off_sync(struct intel_dp *intel_dp) {}
-bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp) { return false; }
-void intel_pps_wait_power_cycle(struct intel_dp *intel_dp) {}
-
-bool intel_pps_init(struct intel_dp *intel_dp) { return false; }
-void intel_pps_init_late(struct intel_dp *intel_dp) {}
-void intel_pps_encoder_reset(struct intel_dp *intel_dp) {}
-void intel_pps_reset_all(struct drm_i915_private *i915) {}
-
-void vlv_pps_init(struct intel_encoder *encoder,
-		  const struct intel_crtc_state *crtc_state) {}
-
-void intel_pps_unlock_regs_wa(struct drm_i915_private *i915) {}
-void intel_pps_setup(struct drm_i915_private *i915) {}
-
-void assert_pps_unlocked(struct drm_i915_private *i915, enum pipe pipe) {}
-
-- 
2.38.1

[Intel-xe] [PATCH 15/37] drm/xe: Rework initialisation ordering slightly so we can inherit fb

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

To inherit the framebuffer, we need to have TTM initialisation for
memory allocations, but not a single allocation needs to be done
because the FB is put at the start, and the first memory allocation
will likely wipe out the initial framebuffer.

There's still a small flicker, as we should probably set GGTT to exactly
the same adress, but the contents are preserved.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_device.c | 28 +++++++++----
 drivers/gpu/drm/xe/xe_ggtt.c   | 72 ++++++++++++++++++++++------------
 drivers/gpu/drm/xe/xe_ggtt.h   |  1 +
 drivers/gpu/drm/xe/xe_gt.c     | 41 +++++++++++++++++--
 drivers/gpu/drm/xe/xe_gt.h     |  1 +
 5 files changed, 105 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 0b154c0a1381..bd6c54aa5649 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -335,7 +335,7 @@ static int xe_device_init_display_noirq(struct xe_device *xe)
 }
 
 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
-static inline void xe_device_fini_display_early(struct drm_device *dev, void *dummy)
+static void xe_device_fini_display_noaccel(struct drm_device *dev, void *dummy)
 {
 	struct xe_device *xe = to_xe_device(dev);
 
@@ -343,20 +343,20 @@ static inline void xe_device_fini_display_early(struct drm_device *dev, void *du
 }
 #endif
 
-static int xe_device_init_display_early(struct xe_device *xe)
+static int xe_device_init_display_noaccel(struct xe_device *xe)
 {
 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
 	int err = intel_modeset_init_nogem(xe);
 	if (err)
 		return err;
 
-	return drmm_add_action_or_reset(&xe->drm, xe_device_fini_display_early, NULL);
+	return drmm_add_action_or_reset(&xe->drm, xe_device_fini_display_noaccel, NULL);
 #else
 	return 0;
 #endif
 }
 
-static int xe_device_init_display_late(struct xe_device *xe)
+static int xe_device_init_display(struct xe_device *xe)
 {
 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
 	return intel_modeset_init(xe);
@@ -412,17 +412,29 @@ int xe_device_probe(struct xe_device *xe)
 	if (err)
 		goto err;
 
-	err = xe_device_init_display_early(xe);
+	for_each_gt(gt, xe, id) {
+		err = xe_gt_init_early(gt);
+		if (err)
+			goto err_irq_shutdown;
+	}
+
+	err = xe_mmio_probe_vram(xe);
 	if (err)
 		goto err_irq_shutdown;
 
 	for_each_gt(gt, xe, id) {
-		err = xe_gt_init_early(gt);
+		err = xe_gt_init_noalloc(gt);
 		if (err)
 			goto err_irq_shutdown;
 	}
 
-	err = xe_mmio_probe_vram(xe);
+	/*
+	 * Now that GT is initialized (TTM in particular),
+	 * we can try to init display, and inherit the initial fb.
+	 * This is the reason the first allocation needs to be done
+	 * inside display.
+	 */
+	err = xe_device_init_display_noaccel(xe);
 	if (err)
 		goto err_irq_shutdown;
 
@@ -432,7 +444,7 @@ int xe_device_probe(struct xe_device *xe)
 			goto err_irq_shutdown;
 	}
 
-	err = xe_device_init_display_late(xe);
+	err = xe_device_init_display(xe);
 	if (err)
 		goto err_fini_display;
 
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 3ace37d90f8d..d67f66b33aed 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -68,7 +68,10 @@ static void xe_ggtt_clear(struct xe_ggtt *ggtt, u64 start, u64 size)
 
 	XE_BUG_ON(start >= end);
 
-	scratch_pte = xe_ggtt_pte_encode(ggtt->scratch, 0);
+	if (ggtt->scratch)
+		scratch_pte = xe_ggtt_pte_encode(ggtt->scratch, 0);
+	else
+		scratch_pte = 0;
 
 	while (start < end) {
 		xe_ggtt_set_pte(ggtt, start, scratch_pte);
@@ -76,7 +79,7 @@ static void xe_ggtt_clear(struct xe_ggtt *ggtt, u64 start, u64 size)
 	}
 }
 
-static void ggtt_fini(struct drm_device *drm, void *arg)
+static void ggtt_fini_noalloc(struct drm_device *drm, void *arg)
 {
 	struct xe_ggtt *ggtt = arg;
 
@@ -86,12 +89,11 @@ static void ggtt_fini(struct drm_device *drm, void *arg)
 	xe_bo_unpin_map_no_vm(ggtt->scratch);
 }
 
-int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
+int xe_ggtt_init_noalloc(struct xe_gt *gt, struct xe_ggtt *ggtt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
 	unsigned int gsm_size;
-	int err;
 
 	XE_BUG_ON(xe_gt_is_media_type(gt));
 
@@ -104,22 +106,7 @@ int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
 	}
 
 	ggtt->gsm = gt->mmio.regs + SZ_8M;
-	ggtt->scratch = xe_bo_create_locked(xe, gt, NULL, GEN8_PAGE_SIZE,
-					    ttm_bo_type_kernel,
-					    XE_BO_CREATE_VRAM_IF_DGFX(gt) |
-					    XE_BO_CREATE_PINNED_BIT);
-	if (IS_ERR(ggtt->scratch)) {
-		err = PTR_ERR(ggtt->scratch);
-		goto err_iomap;
-	}
-
-	err = xe_bo_pin(ggtt->scratch);
-	xe_bo_unlock_no_vm(ggtt->scratch);
-	if (err)
-		goto err_scratch;
-
 	ggtt->size = (gsm_size / 8) * (u64)GEN8_PAGE_SIZE;
-	xe_ggtt_clear(ggtt, 0, ggtt->size - 1);
 
 	/*
 	 * 8B per entry, each points to a 4KB page.
@@ -142,15 +129,48 @@ int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
 		    ggtt->size - xe_wopcm_size(xe));
 	mutex_init(&ggtt->lock);
 
-	err = drmm_add_action_or_reset(&xe->drm, ggtt_fini, ggtt);
-	if (err)
-		return err;
+	return drmm_add_action_or_reset(&xe->drm, ggtt_fini_noalloc, ggtt);
+}
 
-	return 0;
+static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)
+{
+	struct drm_mm_node *hole;
+	u64 start, end;
+
+	/* Display may have allocated inside ggtt, so be careful with clearing here */
+	mutex_lock(&ggtt->lock);
+	drm_mm_for_each_hole(hole, &ggtt->mm, start, end)
+		xe_ggtt_clear(ggtt, start, end - start);
 
-err_scratch:
-	xe_bo_put(ggtt->scratch);
-err_iomap:
+	xe_ggtt_invalidate(ggtt->gt);
+	mutex_unlock(&ggtt->lock);
+}
+
+int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt)
+{
+	struct xe_device *xe = gt_to_xe(gt);
+	int err;
+
+	ggtt->scratch = xe_bo_create_locked(xe, gt, NULL, GEN8_PAGE_SIZE,
+					    ttm_bo_type_kernel,
+					    XE_BO_CREATE_VRAM_IF_DGFX(gt) |
+					    XE_BO_CREATE_PINNED_BIT);
+	if (IS_ERR(ggtt->scratch)) {
+		err = PTR_ERR(ggtt->scratch);
+		goto err;
+	}
+
+	err = xe_bo_pin(ggtt->scratch);
+	xe_bo_unlock_no_vm(ggtt->scratch);
+	if (err) {
+		xe_bo_put(ggtt->scratch);
+		goto err;
+	}
+
+	xe_ggtt_initial_clear(ggtt);
+	return 0;
+err:
+	ggtt->scratch = NULL;
 	return err;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_ggtt.h b/drivers/gpu/drm/xe/xe_ggtt.h
index ebb5c312f331..289c6852ad1a 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.h
+++ b/drivers/gpu/drm/xe/xe_ggtt.h
@@ -11,6 +11,7 @@
 u64 xe_ggtt_pte_encode(struct xe_bo *bo, u64 bo_offset);
 void xe_ggtt_set_pte(struct xe_ggtt *ggtt, u64 addr, u64 pte);
 void xe_ggtt_invalidate(struct xe_gt *gt);
+int xe_ggtt_init_noalloc(struct xe_gt *gt, struct xe_ggtt *ggtt);
 int xe_ggtt_init(struct xe_gt *gt, struct xe_ggtt *ggtt);
 void xe_ggtt_printk(struct xe_ggtt *ggtt, const char *prefix);
 
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index ccb87a7c6554..6cea15725cae 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -389,6 +389,43 @@ int xe_gt_init_early(struct xe_gt *gt)
 	return 0;
 }
 
+/**
+ * xe_gt_init_noalloc - Init GT up to the point where allocations can happen.
+ * @gt: The GT to initialize.
+ *
+ * This function prepares the GT to allow memory allocations to VRAM, but is not
+ * allowed to allocate memory itself. This state is useful for display readout,
+ * because the inherited display framebuffer will otherwise be overwritten as it
+ * is usually put at the start of VRAM.
+ *
+ * Returns: 0 on success, negative error code on error.
+ */
+int xe_gt_init_noalloc(struct xe_gt *gt)
+{
+	int err, err2;
+
+	if (xe_gt_is_media_type(gt))
+		return 0;
+
+	xe_device_mem_access_get(gt_to_xe(gt));
+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+	if (err)
+		goto err;
+
+	err = gt_ttm_mgr_init(gt);
+	if (err)
+		goto err_force_wake;
+
+	err = xe_ggtt_init_noalloc(gt, gt->mem.ggtt);
+
+err_force_wake:
+	err2 = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
+	XE_WARN_ON(err2);
+	xe_device_mem_access_put(gt_to_xe(gt));
+err:
+	return err;
+}
+
 static int gt_fw_domain_init(struct xe_gt *gt)
 {
 	int err, i;
@@ -399,10 +436,6 @@ static int gt_fw_domain_init(struct xe_gt *gt)
 		goto err_hw_fence_irq;
 
 	if (!xe_gt_is_media_type(gt)) {
-		err = gt_ttm_mgr_init(gt);
-		if (err)
-			goto err_force_wake;
-
 		err = xe_ggtt_init(gt, gt->mem.ggtt);
 		if (err)
 			goto err_force_wake;
diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
index 1e070ab4e5aa..5dc08a993cfe 100644
--- a/drivers/gpu/drm/xe/xe_gt.h
+++ b/drivers/gpu/drm/xe/xe_gt.h
@@ -18,6 +18,7 @@
 
 int xe_gt_alloc(struct xe_device *xe, struct xe_gt *gt);
 int xe_gt_init_early(struct xe_gt *gt);
+int xe_gt_init_noalloc(struct xe_gt *gt);
 int xe_gt_init(struct xe_gt *gt);
 int xe_gt_record_default_lrcs(struct xe_gt *gt);
 void xe_gt_suspend_prepare(struct xe_gt *gt);
-- 
2.38.1

[Intel-xe] [PATCH 16/37] drm/xe: Implement stolen memory.

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

This adds support for stolen memory, with the same allocator as
vram_mgr. This allows us to skip a whole lot of copy-paste,
by re-using parts of xe_ttm_vram_mgr.

The stolen memory may be bound using VM_BIND, so it performs like any
other memory region.

We should be able to map a stolen BO directly using the physical memory
location instead of through GGTT even on old platforms, but I don't know
what the effects are on coherency.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/Makefile                |   1 +
 drivers/gpu/drm/xe/xe_bo.c                 | 172 ++++++++++++---
 drivers/gpu/drm/xe/xe_bo.h                 |  11 +-
 drivers/gpu/drm/xe/xe_debugfs.c            |   4 +
 drivers/gpu/drm/xe/xe_device.c             |   4 +
 drivers/gpu/drm/xe/xe_mmio.c               |  58 +++--
 drivers/gpu/drm/xe/xe_mmio.h               |   1 +
 drivers/gpu/drm/xe/xe_pt.c                 |   5 +-
 drivers/gpu/drm/xe/xe_res_cursor.h         |  47 ++--
 drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c     | 244 +++++++++++++++++++++
 drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h     |  21 ++
 drivers/gpu/drm/xe/xe_ttm_vram_mgr.c       |  91 ++++----
 drivers/gpu/drm/xe/xe_ttm_vram_mgr.h       |  18 +-
 drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h |   2 +
 14 files changed, 554 insertions(+), 125 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
 create mode 100644 drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 36996fe7d7a4..06bed3f12b54 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -90,6 +90,7 @@ xe-y += xe_bb.o \
 	xe_sync.o \
 	xe_trace.o \
 	xe_ttm_gtt_mgr.o \
+	xe_ttm_stolen_mgr.o \
 	xe_ttm_vram_mgr.o \
 	xe_tuning.o \
 	xe_uc.o \
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 7c46c3cafc32..314f9b5d34f1 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -24,6 +24,7 @@
 #include "xe_preempt_fence.h"
 #include "xe_res_cursor.h"
 #include "xe_trace.h"
+#include "xe_ttm_stolen_mgr.h"
 #include "xe_vm.h"
 
 static const struct ttm_place sys_placement_flags = {
@@ -42,7 +43,12 @@ static struct ttm_placement sys_placement = {
 
 bool mem_type_is_vram(u32 mem_type)
 {
-	return mem_type >= XE_PL_VRAM0;
+	return mem_type >= XE_PL_VRAM0 && mem_type != XE_PL_STOLEN;
+}
+
+static bool resource_is_stolen_vram(struct xe_device *xe, struct ttm_resource *res)
+{
+	return res->mem_type == XE_PL_STOLEN && IS_DGFX(xe);
 }
 
 static bool resource_is_vram(struct ttm_resource *res)
@@ -52,7 +58,13 @@ static bool resource_is_vram(struct ttm_resource *res)
 
 bool xe_bo_is_vram(struct xe_bo *bo)
 {
-	return resource_is_vram(bo->ttm.resource);
+	return resource_is_vram(bo->ttm.resource) ||
+		resource_is_stolen_vram(xe_bo_device(bo), bo->ttm.resource);
+}
+
+bool xe_bo_is_stolen(struct xe_bo *bo)
+{
+	return bo->ttm.resource->mem_type == XE_PL_STOLEN;
 }
 
 static bool xe_bo_is_user(struct xe_bo *bo)
@@ -63,9 +75,9 @@ static bool xe_bo_is_user(struct xe_bo *bo)
 static struct xe_gt *
 mem_type_to_gt(struct xe_device *xe, u32 mem_type)
 {
-	XE_BUG_ON(!mem_type_is_vram(mem_type));
+	XE_BUG_ON(mem_type != XE_PL_STOLEN && !mem_type_is_vram(mem_type));
 
-	return xe_device_get_gt(xe, mem_type - XE_PL_VRAM0);
+	return xe_device_get_gt(xe, mem_type == XE_PL_STOLEN ? 0 : (mem_type - XE_PL_VRAM0));
 }
 
 static void try_add_system(struct xe_bo *bo, struct ttm_place *places,
@@ -134,6 +146,20 @@ static void try_add_vram1(struct xe_device *xe, struct xe_bo *bo,
 	}
 }
 
+static void try_add_stolen(struct xe_device *xe, struct xe_bo *bo,
+			   struct ttm_place *places, u32 bo_flags, u32 *c)
+{
+	if (bo_flags & XE_BO_CREATE_STOLEN_BIT) {
+		places[*c] = (struct ttm_place) {
+			.mem_type = XE_PL_STOLEN,
+			.flags = bo_flags & (XE_BO_CREATE_PINNED_BIT |
+					     XE_BO_CREATE_GGTT_BIT) ?
+				TTM_PL_FLAG_CONTIGUOUS : 0,
+		};
+		*c += 1;
+	}
+}
+
 static int __xe_bo_placement_for_flags(struct xe_device *xe, struct xe_bo *bo,
 				       u32 bo_flags)
 {
@@ -162,6 +188,7 @@ static int __xe_bo_placement_for_flags(struct xe_device *xe, struct xe_bo *bo,
 		try_add_vram1(xe, bo, places, bo_flags, &c);
 		try_add_system(bo, places, bo_flags, &c);
 	}
+	try_add_stolen(xe, bo, places, bo_flags, &c);
 
 	if (!c)
 		return -EINVAL;
@@ -209,6 +236,7 @@ static void xe_evict_flags(struct ttm_buffer_object *tbo,
 	switch (tbo->resource->mem_type) {
 	case XE_PL_VRAM0:
 	case XE_PL_VRAM1:
+	case XE_PL_STOLEN:
 	case XE_PL_TT:
 	default:
 		/* for now kick out to system */
@@ -364,11 +392,12 @@ static int xe_ttm_io_mem_reserve(struct ttm_device *bdev,
 #if  !defined(CONFIG_X86)
 		mem->bus.caching = ttm_write_combined;
 #endif
-		break;
+		return 0;
+	case XE_PL_STOLEN:
+		return xe_ttm_stolen_io_mem_reserve(xe, mem);
 	default:
 		return -EINVAL;
 	}
-	return 0;
 }
 
 static int xe_bo_trigger_rebind(struct xe_device *xe, struct xe_bo *bo,
@@ -663,14 +692,18 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict,
 
 }
 
-static unsigned long xe_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
+static unsigned long xe_ttm_io_mem_pfn(struct ttm_buffer_object *ttm_bo,
 				       unsigned long page_offset)
 {
-	struct xe_device *xe = ttm_to_xe_device(bo->bdev);
-	struct xe_gt *gt = mem_type_to_gt(xe, bo->resource->mem_type);
+	struct xe_device *xe = ttm_to_xe_device(ttm_bo->bdev);
+	struct xe_bo *bo = ttm_to_xe_bo(ttm_bo);
+	struct xe_gt *gt = mem_type_to_gt(xe, ttm_bo->resource->mem_type);
 	struct xe_res_cursor cursor;
 
-	xe_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, &cursor);
+	if (ttm_bo->resource->mem_type == XE_PL_STOLEN)
+		return xe_ttm_stolen_io_offset(bo, page_offset << PAGE_SHIFT) >> PAGE_SHIFT;
+
+	xe_res_first(ttm_bo->resource, (u64)page_offset << PAGE_SHIFT, 0, &cursor);
 	return (gt->mem.vram.io_start + cursor.start) >> PAGE_SHIFT;
 }
 
@@ -936,7 +969,8 @@ struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
 			return bo;
 	}
 
-	if (flags & (XE_BO_CREATE_VRAM0_BIT | XE_BO_CREATE_VRAM1_BIT) &&
+	if (flags & (XE_BO_CREATE_VRAM0_BIT | XE_BO_CREATE_VRAM1_BIT |
+		     XE_BO_CREATE_STOLEN_BIT) &&
 	    !(flags & XE_BO_CREATE_IGNORE_MIN_PAGE_SIZE_BIT) &&
 	    xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K) {
 		size = ALIGN(size, SZ_64K);
@@ -964,9 +998,11 @@ struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
 		ctx.resv = resv;
 	}
 
-	err = __xe_bo_placement_for_flags(xe, bo, bo->flags);
-	if (WARN_ON(err))
-		return ERR_PTR(err);
+	if (!(flags & XE_BO_FIXED_PLACEMENT_BIT)) {
+		err = __xe_bo_placement_for_flags(xe, bo, bo->flags);
+		if (WARN_ON(err))
+			return ERR_PTR(err);
+	}
 
 	/* Defer populating type_sg bos */
 	placement = (type == ttm_bo_type_sg ||
@@ -984,16 +1020,73 @@ struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
 	return bo;
 }
 
-struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_gt *gt,
-				  struct xe_vm *vm, size_t size,
-				  enum ttm_bo_type type, u32 flags)
+static int __xe_bo_fixed_placement(struct xe_device *xe,
+				   struct xe_bo *bo,
+				   u32 flags,
+				   u64 offset, u64 size)
 {
-	struct xe_bo *bo;
+	struct ttm_place *place = bo->placements;
+
+	if (flags & (XE_BO_CREATE_USER_BIT|XE_BO_CREATE_SYSTEM_BIT))
+		return -EINVAL;
+
+	place->flags = TTM_PL_FLAG_CONTIGUOUS;
+	place->fpfn = offset >> PAGE_SHIFT;
+	place->lpfn = (offset + size) >> PAGE_SHIFT;
+
+	switch (flags & (XE_BO_CREATE_STOLEN_BIT |
+		XE_BO_CREATE_VRAM0_BIT |XE_BO_CREATE_VRAM1_BIT)) {
+	case XE_BO_CREATE_VRAM0_BIT:
+		place->mem_type = XE_PL_VRAM0;
+		break;
+	case XE_BO_CREATE_VRAM1_BIT:
+		place->mem_type = XE_PL_VRAM1;
+		break;
+	case XE_BO_CREATE_STOLEN_BIT:
+		place->mem_type = XE_PL_STOLEN;
+		break;
+
+	default:
+		/* 0 or multiple of the above set */
+		return -EINVAL;
+	}
+
+	bo->placement = (struct ttm_placement) {
+		.num_placement = 1,
+		.placement = place,
+		.num_busy_placement = 1,
+		.busy_placement = place,
+	};
+
+	return 0;
+}
+
+static struct xe_bo *
+xe_bo_create_locked_at(struct xe_device *xe,
+		       struct xe_gt *gt, struct xe_vm *vm,
+		       size_t size, u64 offset,
+		       enum ttm_bo_type type, u32 flags)
+{
+	struct xe_bo *bo = NULL;
 	int err;
 
 	if (vm)
 		xe_vm_assert_held(vm);
-	bo = __xe_bo_create_locked(xe, NULL, gt, vm ? &vm->resv : NULL, size,
+
+	if (offset != ~0ULL) {
+		bo = xe_bo_alloc();
+		if (IS_ERR(bo))
+			return bo;
+
+		flags |= XE_BO_FIXED_PLACEMENT_BIT;
+		err = __xe_bo_fixed_placement(xe, bo, flags, offset, size);
+		if (err) {
+			xe_bo_free(bo);
+			return ERR_PTR(err);
+		}
+	}
+
+	bo = __xe_bo_create_locked(xe, bo, gt, vm ? &vm->resv : NULL, size,
 				   type, flags);
 	if (IS_ERR(bo))
 		return bo;
@@ -1002,7 +1095,11 @@ struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_gt *gt,
 		xe_vm_get(vm);
 	bo->vm = vm;
 
-	if (flags & XE_BO_CREATE_GGTT_BIT) {
+	if (bo->flags & XE_BO_CREATE_GGTT_BIT) {
+
+		if (!gt && flags & XE_BO_CREATE_STOLEN_BIT)
+			gt = xe_device_get_gt(xe, 0);
+
 		XE_BUG_ON(!gt);
 
 		err = xe_ggtt_insert_bo(gt->mem.ggtt, bo);
@@ -1018,6 +1115,13 @@ struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_gt *gt,
 	return ERR_PTR(err);
 }
 
+struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_gt *gt,
+				  struct xe_vm *vm, size_t size,
+				  enum ttm_bo_type type, u32 flags)
+{
+	return xe_bo_create_locked_at(xe, gt, vm, size, ~0ULL, type, flags);
+}
+
 struct xe_bo *xe_bo_create(struct xe_device *xe, struct xe_gt *gt,
 			   struct xe_vm *vm, size_t size,
 			   enum ttm_bo_type type, u32 flags)
@@ -1030,13 +1134,19 @@ struct xe_bo *xe_bo_create(struct xe_device *xe, struct xe_gt *gt,
 	return bo;
 }
 
-struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_gt *gt,
-				   struct xe_vm *vm, size_t size,
-				   enum ttm_bo_type type, u32 flags)
+struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_gt *gt,
+				      struct xe_vm *vm,
+				      size_t size, u64 offset,
+				      enum ttm_bo_type type, u32 flags)
 {
-	struct xe_bo *bo = xe_bo_create_locked(xe, gt, vm, size, type, flags);
+	struct xe_bo *bo;
 	int err;
 
+	if (flags & XE_BO_CREATE_STOLEN_BIT &&
+	    xe_ttm_stolen_inaccessible(xe))
+		flags |= XE_BO_CREATE_GGTT_BIT;
+
+	bo = xe_bo_create_locked_at(xe, gt, vm, size, offset, type, flags);
 	if (IS_ERR(bo))
 		return bo;
 
@@ -1060,6 +1170,13 @@ struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_gt *gt,
 	return ERR_PTR(err);
 }
 
+struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_gt *gt,
+				   struct xe_vm *vm, size_t size,
+				   enum ttm_bo_type type, u32 flags)
+{
+	return xe_bo_create_pin_map_at(xe, gt, vm, size, ~0ULL, type, flags);
+}
+
 struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_gt *gt,
 				     const void *data, size_t size,
 				     enum ttm_bo_type type, u32 flags)
@@ -1084,6 +1201,9 @@ static uint64_t vram_region_io_offset(struct xe_bo *bo)
 	struct xe_device *xe = xe_bo_device(bo);
 	struct xe_gt *gt = mem_type_to_gt(xe, bo->ttm.resource->mem_type);
 
+	if (bo->ttm.resource->mem_type == XE_PL_STOLEN)
+		return xe_ttm_stolen_gpu_offset(xe);
+
 	return gt->mem.vram.io_start - xe->mem.vram.io_start;
 }
 
@@ -1165,7 +1285,7 @@ int xe_bo_pin(struct xe_bo *bo)
 		bool lmem;
 
 		XE_BUG_ON(!(place->flags & TTM_PL_FLAG_CONTIGUOUS));
-		XE_BUG_ON(!mem_type_is_vram(place->mem_type));
+		XE_BUG_ON(!mem_type_is_vram(place->mem_type) && place->mem_type != XE_PL_STOLEN);
 
 		place->fpfn = (xe_bo_addr(bo, 0, PAGE_SIZE, &lmem) -
 			       vram_region_io_offset(bo)) >> PAGE_SHIFT;
@@ -1296,7 +1416,7 @@ dma_addr_t xe_bo_addr(struct xe_bo *bo, u64 offset,
 
 	*is_lmem = xe_bo_is_vram(bo);
 
-	if (!*is_lmem) {
+	if (!*is_lmem && !xe_bo_is_stolen(bo)) {
 		XE_BUG_ON(!bo->ttm.ttm);
 
 		xe_res_first_sg(xe_bo_get_sg(bo), page << PAGE_SHIFT,
diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
index 1a49c0a3c4c6..ed71b594f407 100644
--- a/drivers/gpu/drm/xe/xe_bo.h
+++ b/drivers/gpu/drm/xe/xe_bo.h
@@ -12,8 +12,9 @@
 
 #define XE_DEFAULT_GTT_SIZE_MB          3072ULL /* 3GB by default */
 
-#define XE_BO_CREATE_USER_BIT		BIT(1)
-#define XE_BO_CREATE_SYSTEM_BIT		BIT(2)
+#define XE_BO_CREATE_USER_BIT		BIT(0)
+#define XE_BO_CREATE_SYSTEM_BIT		BIT(1)
+#define XE_BO_CREATE_STOLEN_BIT		BIT(2)
 #define XE_BO_CREATE_VRAM0_BIT		BIT(3)
 #define XE_BO_CREATE_VRAM1_BIT		BIT(4)
 #define XE_BO_CREATE_VRAM_IF_DGFX(gt) \
@@ -24,6 +25,7 @@
 #define XE_BO_CREATE_PINNED_BIT		BIT(7)
 #define XE_BO_DEFER_BACKING		BIT(8)
 #define XE_BO_SCANOUT_BIT		BIT(9)
+#define XE_BO_FIXED_PLACEMENT_BIT	BIT(10)
 /* this one is trigger internally only */
 #define XE_BO_INTERNAL_TEST		BIT(30)
 #define XE_BO_INTERNAL_64K		BIT(31)
@@ -64,6 +66,7 @@
 #define XE_PL_TT		TTM_PL_TT
 #define XE_PL_VRAM0		TTM_PL_VRAM
 #define XE_PL_VRAM1		(XE_PL_VRAM0 + 1)
+#define XE_PL_STOLEN		(TTM_NUM_MEM_TYPES - 1)
 
 #define XE_BO_PROPS_INVALID	(-1)
 
@@ -85,6 +88,9 @@ struct xe_bo *xe_bo_create(struct xe_device *xe, struct xe_gt *gt,
 struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_gt *gt,
 				   struct xe_vm *vm, size_t size,
 				   enum ttm_bo_type type, u32 flags);
+struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_gt *gt,
+				      struct xe_vm *vm, size_t size, u64 offset,
+				      enum ttm_bo_type type, u32 flags);
 struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_gt *gt,
 				     const void *data, size_t size,
 				     enum ttm_bo_type type, u32 flags);
@@ -206,6 +212,7 @@ void xe_bo_vunmap(struct xe_bo *bo);
 
 bool mem_type_is_vram(u32 mem_type);
 bool xe_bo_is_vram(struct xe_bo *bo);
+bool xe_bo_is_stolen(struct xe_bo *bo);
 
 bool xe_bo_can_migrate(struct xe_bo *bo, u32 mem_type);
 
diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
index 84db7b3f501e..b0f8b157ffa3 100644
--- a/drivers/gpu/drm/xe/xe_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_debugfs.c
@@ -124,6 +124,10 @@ void xe_debugfs_register(struct xe_device *xe)
 	man = ttm_manager_type(bdev, XE_PL_TT);
 	ttm_resource_manager_create_debugfs(man, root, "gtt_mm");
 
+	man = ttm_manager_type(bdev, XE_PL_STOLEN);
+	if (man)
+		ttm_resource_manager_create_debugfs(man, root, "stolen_mm");
+
 	for_each_gt(gt, xe, id)
 		xe_gt_debugfs_register(gt);
 }
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index bd6c54aa5649..86e386931206 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -24,6 +24,7 @@
 #include "xe_pcode.h"
 #include "xe_pm.h"
 #include "xe_query.h"
+#include "xe_ttm_stolen_mgr.h"
 #include "xe_vm.h"
 #include "xe_vm_madvise.h"
 #include "xe_wait_user_fence.h"
@@ -428,6 +429,9 @@ int xe_device_probe(struct xe_device *xe)
 			goto err_irq_shutdown;
 	}
 
+	/* Harmless if stolen initialization fails */
+	xe_ttm_stolen_mgr_init(xe);
+
 	/*
 	 * Now that GT is initialized (TTM in particular),
 	 * we can try to init display, and inherit the initial fb.
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 9ab74ce3ff6d..4d679027fc98 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -153,6 +153,38 @@ static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)
 	return true;
 }
 
+int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *flat_ccs_base)
+{
+	struct xe_gt *gt = xe_device_get_gt(xe, 0);
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+	int err;
+	u32 reg;
+
+	if (!xe->info.has_flat_ccs)  {
+		*vram_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
+		if (flat_ccs_base)
+			*flat_ccs_base = *vram_size;
+		return 0;
+	}
+
+	err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
+	if (err)
+		return err;
+
+	reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE0_ADDR_RANGE);
+	*vram_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
+	if (flat_ccs_base) {
+		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
+		*flat_ccs_base = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;
+	}
+
+	if (flat_ccs_base)
+		drm_info(&xe->drm, "lmem_size: 0x%llx flat_ccs_base: 0x%llx\n",
+			 *vram_size, *flat_ccs_base);
+
+	return xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
+}
+
 int xe_mmio_probe_vram(struct xe_device *xe)
 {
 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
@@ -162,7 +194,7 @@ int xe_mmio_probe_vram(struct xe_device *xe)
 	u64 original_size;
 	u64 current_size;
 	u64 flat_ccs_base;
-	int resize_result;
+	int resize_result, err;
 
 	if (!IS_DGFX(xe)) {
 		xe->mem.vram.mapping = 0;
@@ -187,27 +219,9 @@ int xe_mmio_probe_vram(struct xe_device *xe)
 
 	original_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
 
-	if (xe->info.has_flat_ccs)  {
-		int err;
-		u32 reg;
-
-		err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
-		if (err)
-			return err;
-		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE0_ADDR_RANGE);
-		lmem_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
-		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
-		flat_ccs_base = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;
-
-		drm_info(&xe->drm, "lmem_size: 0x%llx flat_ccs_base: 0x%llx\n",
-			 lmem_size, flat_ccs_base);
-
-		err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
-		if (err)
-			return err;
-	} else {
-		flat_ccs_base = lmem_size;
-	}
+	err = xe_mmio_total_vram_size(xe, &lmem_size, &flat_ccs_base);
+	if (err)
+		return err;
 
 	resize_result = xe_resize_lmem_bar(xe, lmem_size);
 	current_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 009bc14a24f4..7e7149c8d5ec 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -121,5 +121,6 @@ static inline bool xe_mmio_in_range(const struct xe_mmio_range *range, u32 reg)
 }
 
 int xe_mmio_probe_vram(struct xe_device *xe);
+int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *flat_ccs_base);
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 71e8d3091640..c8b3b1975098 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -13,6 +13,7 @@
 #include "xe_pt_types.h"
 #include "xe_vm.h"
 #include "xe_res_cursor.h"
+#include "xe_ttm_stolen_mgr.h"
 
 struct xe_pt_dir {
 	struct xe_pt pt;
@@ -757,12 +758,14 @@ xe_pt_stage_bind(struct xe_gt *gt, struct xe_vma *vma,
 		else
 			xe_walk.cache = XE_CACHE_WB;
 	}
+	if (xe_bo_is_stolen(bo))
+		xe_walk.dma_offset = xe_ttm_stolen_gpu_offset(xe_bo_device(bo));
 
 	xe_bo_assert_held(bo);
 	if (xe_vma_is_userptr(vma))
 		xe_res_first_sg(vma->userptr.sg, 0, vma->end - vma->start + 1,
 				&curs);
-	else if (xe_bo_is_vram(bo))
+	else if (xe_bo_is_vram(bo) || xe_bo_is_stolen(bo))
 		xe_res_first(bo->ttm.resource, vma->bo_offset,
 			     vma->end - vma->start + 1, &curs);
 	else
diff --git a/drivers/gpu/drm/xe/xe_res_cursor.h b/drivers/gpu/drm/xe/xe_res_cursor.h
index f54409850d74..365c8ad7aeb8 100644
--- a/drivers/gpu/drm/xe/xe_res_cursor.h
+++ b/drivers/gpu/drm/xe/xe_res_cursor.h
@@ -33,10 +33,11 @@
 #include <drm/ttm/ttm_tt.h>
 
 #include "xe_bo.h"
+#include "xe_device.h"
 #include "xe_macros.h"
 #include "xe_ttm_vram_mgr.h"
 
-/* state back for walking over vram_mgr and gtt_mgr allocations */
+/* state back for walking over vram_mgr, stolen_mgr, and gtt_mgr allocations */
 struct xe_res_cursor {
 	u64 start;
 	u64 size;
@@ -44,8 +45,23 @@ struct xe_res_cursor {
 	void *node;
 	u32 mem_type;
 	struct scatterlist *sgl;
+	struct drm_buddy *mm;
 };
 
+static struct drm_buddy *xe_res_get_buddy(struct ttm_resource *res)
+{
+	struct xe_device *xe = ttm_to_xe_device(res->bo->bdev);
+
+	if (res->mem_type != XE_PL_STOLEN) {
+		return &xe_device_get_gt(xe, res->mem_type - XE_PL_VRAM0)->mem.vram_mgr->mm;
+	} else {
+		struct ttm_resource_manager *mgr =
+			ttm_manager_type(&xe->ttm, XE_PL_STOLEN);
+
+		return &to_xe_ttm_vram_mgr(mgr)->mm;
+	}
+}
+
 /**
  * xe_res_first - initialize a xe_res_cursor
  *
@@ -60,9 +76,6 @@ static inline void xe_res_first(struct ttm_resource *res,
 				u64 start, u64 size,
 				struct xe_res_cursor *cur)
 {
-	struct drm_buddy_block *block;
-	struct list_head *head, *next;
-
 	cur->sgl = NULL;
 	if (!res)
 		goto fallback;
@@ -72,8 +85,13 @@ static inline void xe_res_first(struct ttm_resource *res,
 	cur->mem_type = res->mem_type;
 
 	switch (cur->mem_type) {
+	case XE_PL_STOLEN:
 	case XE_PL_VRAM0:
-	case XE_PL_VRAM1:
+	case XE_PL_VRAM1: {
+		struct drm_buddy_block *block;
+		struct list_head *head, *next;
+		struct drm_buddy *mm = xe_res_get_buddy(res);
+
 		head = &to_xe_ttm_vram_mgr_resource(res)->blocks;
 
 		block = list_first_entry_or_null(head,
@@ -82,8 +100,8 @@ static inline void xe_res_first(struct ttm_resource *res,
 		if (!block)
 			goto fallback;
 
-		while (start >= xe_ttm_vram_mgr_block_size(block)) {
-			start -= xe_ttm_vram_mgr_block_size(block);
+		while (start >= drm_buddy_block_size(mm, block)) {
+			start -= drm_buddy_block_size(mm, block);
 
 			next = block->link.next;
 			if (next != head)
@@ -91,12 +109,14 @@ static inline void xe_res_first(struct ttm_resource *res,
 						   link);
 		}
 
-		cur->start = xe_ttm_vram_mgr_block_start(block) + start;
-		cur->size = min(xe_ttm_vram_mgr_block_size(block) - start,
+		cur->mm = mm;
+		cur->start = drm_buddy_block_offset(block) + start;
+		cur->size = min(drm_buddy_block_size(mm, block) - start,
 				size);
 		cur->remaining = size;
 		cur->node = block;
 		break;
+	}
 	default:
 		goto fallback;
 	}
@@ -188,6 +208,7 @@ static inline void xe_res_next(struct xe_res_cursor *cur, u64 size)
 	}
 
 	switch (cur->mem_type) {
+	case XE_PL_STOLEN:
 	case XE_PL_VRAM0:
 	case XE_PL_VRAM1:
 		start = size - cur->size;
@@ -197,15 +218,15 @@ static inline void xe_res_next(struct xe_res_cursor *cur, u64 size)
 		block = list_entry(next, struct drm_buddy_block, link);
 
 
-		while (start >= xe_ttm_vram_mgr_block_size(block)) {
-			start -= xe_ttm_vram_mgr_block_size(block);
+		while (start >= drm_buddy_block_size(cur->mm, block)) {
+			start -= drm_buddy_block_size(cur->mm, block);
 
 			next = block->link.next;
 			block = list_entry(next, struct drm_buddy_block, link);
 		}
 
-		cur->start = xe_ttm_vram_mgr_block_start(block) + start;
-		cur->size = min(xe_ttm_vram_mgr_block_size(block) - start,
+		cur->start = drm_buddy_block_offset(block) + start;
+		cur->size = min(drm_buddy_block_size(cur->mm, block) - start,
 				cur->remaining);
 		cur->node = block;
 		break;
diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
new file mode 100644
index 000000000000..21ca7f79e63b
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021-2022 Intel Corporation
+ * Copyright (C) 2021-2002 Red Hat
+ */
+
+#include <drm/drm_managed.h>
+#include <drm/drm_mm.h>
+
+#include <drm/ttm/ttm_device.h>
+#include <drm/ttm/ttm_range_manager.h>
+#include <drm/ttm/ttm_placement.h>
+
+#include "../i915/i915_reg.h"
+
+#include "xe_bo.h"
+#include "xe_device.h"
+#include "xe_gt.h"
+#include "xe_mmio.h"
+#include "xe_res_cursor.h"
+#include "xe_ttm_stolen_mgr.h"
+#include "xe_ttm_vram_mgr.h"
+
+bool xe_ttm_stolen_inaccessible(struct xe_device *xe)
+{
+	return !IS_DGFX(xe) && GRAPHICS_VERx100(xe) < 1270;
+}
+
+struct xe_ttm_stolen_mgr {
+	struct xe_ttm_vram_mgr base;
+
+	/* PCI base offset */
+	resource_size_t io_base;
+	/* GPU base offset */
+	resource_size_t stolen_base;
+
+	void *__iomem mapping;
+};
+
+static inline struct xe_ttm_stolen_mgr *
+to_stolen_mgr(struct ttm_resource_manager *man)
+{
+	return container_of(man, struct xe_ttm_stolen_mgr, base.manager);
+}
+
+static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)
+{
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+	struct xe_gt *gt = to_gt(xe);
+	u64 vram_size, stolen_size;
+	int err;
+
+	err = xe_mmio_total_vram_size(xe, &vram_size, NULL);
+	if (err) {
+		drm_info(&xe->drm, "Querying total vram size failed\n");
+		return 0;
+	}
+
+	/* Use DSM base address instead for stolen memory */
+	mgr->stolen_base = xe_mmio_read64(gt, GEN12_DSMBASE.reg) & GEN12_BDSM_MASK;
+	if (drm_WARN_ON(&xe->drm, vram_size < mgr->stolen_base))
+		return 0;
+
+	stolen_size = vram_size - mgr->stolen_base;
+	if (mgr->stolen_base + stolen_size <= pci_resource_len(pdev, 2))
+		mgr->io_base = pci_resource_start(pdev, 2) + mgr->stolen_base;
+
+	return stolen_size;
+}
+
+static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)
+{
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+	u32 stolen_size;
+	u32 ggc, gms;
+
+	ggc = xe_mmio_read32(to_gt(xe), GGC.reg);
+
+	/* check GGMS, should be fixed 0x3 (8MB) */
+	if (drm_WARN_ON(&xe->drm, (ggc & GGMS_MASK) != GGMS_MASK))
+		return 0;
+
+	mgr->stolen_base = mgr->io_base = pci_resource_start(pdev, 2) + SZ_8M;
+
+	/* return valid GMS value, -EIO if invalid */
+	gms = REG_FIELD_GET(GMS_MASK, ggc);
+	switch (gms) {
+	case 0x0 ... 0x04:
+		stolen_size = gms * 32 * SZ_1M;
+		break;
+	case 0xf0 ... 0xfe:
+		stolen_size = (gms - 0xf0 + 1) * 4 * SZ_1M;
+		break;
+	default:
+		return 0;
+	}
+
+	if (drm_WARN_ON(&xe->drm, stolen_size + SZ_8M > pci_resource_len(pdev, 2)))
+		return 0;
+
+	return stolen_size;
+}
+
+extern struct resource intel_graphics_stolen_res;
+
+static u64 detect_stolen(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)
+{
+#ifdef CONFIG_X86
+	/* Map into GGTT */
+	mgr->io_base = pci_resource_start(to_pci_dev(xe->drm.dev), 2);
+
+	/* Stolen memory is x86 only */
+	mgr->stolen_base = intel_graphics_stolen_res.start;
+	return resource_size(&intel_graphics_stolen_res);
+#else
+	return 0;
+#endif
+}
+
+void xe_ttm_stolen_mgr_init(struct xe_device *xe)
+{
+	struct xe_ttm_stolen_mgr *mgr = drmm_kzalloc(&xe->drm, sizeof(*mgr), GFP_KERNEL);
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+	u64 stolen_size, pgsize;
+	int err;
+
+	if (IS_DGFX(xe))
+		stolen_size = detect_bar2_dgfx(xe, mgr);
+	else if (!xe_ttm_stolen_inaccessible(xe))
+		stolen_size = detect_bar2_integrated(xe, mgr);
+	else
+		stolen_size = detect_stolen(xe, mgr);
+
+	if (!stolen_size) {
+		drm_dbg_kms(&xe->drm, "No stolen memory support\n");
+		return;
+	}
+
+	pgsize = xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;
+	if (pgsize < PAGE_SIZE)
+		pgsize = PAGE_SIZE;
+
+
+	err = __xe_ttm_vram_mgr_init(xe, &mgr->base, XE_PL_STOLEN, stolen_size, pgsize);
+	if (err) {
+		drm_dbg_kms(&xe->drm, "Stolen mgr init failed: %i\n", err);
+		return;
+	}
+
+	drm_dbg_kms(&xe->drm, "Initialized stolen memory support with %llu bytes\n",
+		    stolen_size);
+
+	if (!xe_ttm_stolen_inaccessible(xe))
+		mgr->mapping = devm_ioremap_wc(&pdev->dev, mgr->io_base, stolen_size);
+}
+
+u64 xe_ttm_stolen_io_offset(struct xe_bo *bo, u32 offset)
+{
+	struct xe_device *xe = xe_bo_device(bo);
+	struct ttm_resource_manager *ttm_mgr = ttm_manager_type(&xe->ttm, XE_PL_STOLEN);
+	struct xe_ttm_stolen_mgr *mgr = to_stolen_mgr(ttm_mgr);
+	struct xe_res_cursor cur;
+
+	if (!mgr->io_base)
+		return 0;
+
+	if (!IS_DGFX(xe) && xe_ttm_stolen_inaccessible(xe))
+		return mgr->io_base + xe_bo_ggtt_addr(bo) + offset;
+
+	xe_res_first(bo->ttm.resource, offset, 4096, &cur);
+	return mgr->io_base + cur.start;
+}
+
+static int __xe_ttm_stolen_io_mem_reserve_bar2(struct xe_device *xe,
+					       struct xe_ttm_stolen_mgr *mgr,
+					       struct ttm_resource *mem)
+{
+	struct xe_res_cursor cur;
+
+	if (!mgr->io_base)
+		return -EIO;
+
+	xe_res_first(mem, 0, 4096, &cur);
+	mem->bus.offset = cur.start;
+
+	drm_WARN_ON(&xe->drm, !(mem->placement & TTM_PL_FLAG_CONTIGUOUS));
+	WARN_ON_ONCE(1);
+
+	if (mem->placement & TTM_PL_FLAG_CONTIGUOUS && mgr->mapping)
+		mem->bus.addr = (u8 *)mgr->mapping + mem->bus.offset;
+
+	mem->bus.offset += mgr->io_base;
+	mem->bus.is_iomem = true;
+	mem->bus.caching = ttm_write_combined;
+
+	return 0;
+}
+
+static int __xe_ttm_stolen_io_mem_reserve_stolen(struct xe_device *xe,
+						 struct xe_ttm_stolen_mgr *mgr,
+						 struct ttm_resource *mem)
+{
+#ifdef CONFIG_X86
+	struct xe_bo *bo = ttm_to_xe_bo(mem->bo);
+
+	/* XXX: Require BO to be mapped to GGTT? */
+	if (drm_WARN_ON(&xe->drm, !(bo->flags & XE_BO_CREATE_GGTT_BIT)))
+		return -EIO;
+
+	/* GGTT is always contiguously mapped */
+	mem->bus.offset = xe_bo_ggtt_addr(bo) + mgr->io_base;
+
+	mem->bus.is_iomem = true;
+	mem->bus.caching = ttm_write_combined;
+
+	return 0;
+#else
+	/* How is it even possible to get here without gen12 stolen? */
+	drm_WARN_ON(&xe->drm, 1);
+	return -EIO;
+#endif
+}
+
+int xe_ttm_stolen_io_mem_reserve(struct xe_device *xe, struct ttm_resource *mem)
+{
+	struct ttm_resource_manager *ttm_mgr = ttm_manager_type(&xe->ttm, XE_PL_STOLEN);
+	struct xe_ttm_stolen_mgr *mgr = ttm_mgr ? to_stolen_mgr(ttm_mgr) : NULL;
+
+	if (!mgr || !mgr->io_base)
+		return -EIO;
+
+	if (!xe_ttm_stolen_inaccessible(xe))
+		return __xe_ttm_stolen_io_mem_reserve_bar2(xe, mgr, mem);
+	else
+		return __xe_ttm_stolen_io_mem_reserve_stolen(xe, mgr, mem);
+}
+
+u64 xe_ttm_stolen_gpu_offset(struct xe_device *xe)
+{
+	struct xe_ttm_stolen_mgr *mgr =
+		to_stolen_mgr(ttm_manager_type(&xe->ttm, XE_PL_STOLEN));
+
+	return mgr->stolen_base;
+}
diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h
new file mode 100644
index 000000000000..ade37abb0623
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _XE_TTM_STOLEN_MGR_H_
+#define _XE_TTM_STOLEN_MGR_H_
+
+#include <linux/types.h>
+
+struct ttm_resource;
+struct xe_bo;
+struct xe_device;
+
+void xe_ttm_stolen_mgr_init(struct xe_device *xe);
+int xe_ttm_stolen_io_mem_reserve(struct xe_device *xe, struct ttm_resource *mem);
+bool xe_ttm_stolen_inaccessible(struct xe_device *xe);
+u64 xe_ttm_stolen_io_offset(struct xe_bo *bo, u32 offset);
+u64 xe_ttm_stolen_gpu_offset(struct xe_device *xe);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
index e391e81d3640..c7e21673b8fd 100644
--- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
+++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c
@@ -15,25 +15,14 @@
 #include "xe_res_cursor.h"
 #include "xe_ttm_vram_mgr.h"
 
-static inline struct xe_ttm_vram_mgr *
-to_vram_mgr(struct ttm_resource_manager *man)
-{
-	return container_of(man, struct xe_ttm_vram_mgr, manager);
-}
-
-static inline struct xe_gt *
-mgr_to_gt(struct xe_ttm_vram_mgr *mgr)
-{
-	return mgr->gt;
-}
-
 static inline struct drm_buddy_block *
 xe_ttm_vram_mgr_first_block(struct list_head *list)
 {
 	return list_first_entry_or_null(list, struct drm_buddy_block, link);
 }
 
-static inline bool xe_is_vram_mgr_blocks_contiguous(struct list_head *head)
+static inline bool xe_is_vram_mgr_blocks_contiguous(struct drm_buddy *mm,
+						    struct list_head *head)
 {
 	struct drm_buddy_block *block;
 	u64 start, size;
@@ -43,12 +32,12 @@ static inline bool xe_is_vram_mgr_blocks_contiguous(struct list_head *head)
 		return false;
 
 	while (head != block->link.next) {
-		start = xe_ttm_vram_mgr_block_start(block);
-		size = xe_ttm_vram_mgr_block_size(block);
+		start = drm_buddy_block_offset(block);
+		size = drm_buddy_block_size(mm, block);
 
 		block = list_entry(block->link.next, struct drm_buddy_block,
 				   link);
-		if (start + size != xe_ttm_vram_mgr_block_start(block))
+		if (start + size != drm_buddy_block_offset(block))
 			return false;
 	}
 
@@ -61,7 +50,7 @@ static int xe_ttm_vram_mgr_new(struct ttm_resource_manager *man,
 			       struct ttm_resource **res)
 {
 	u64 max_bytes, cur_size, min_block_size;
-	struct xe_ttm_vram_mgr *mgr = to_vram_mgr(man);
+	struct xe_ttm_vram_mgr *mgr = to_xe_ttm_vram_mgr(man);
 	struct xe_ttm_vram_mgr_resource *vres;
 	u64 size, remaining_size, lpfn, fpfn;
 	struct drm_buddy *mm = &mgr->mm;
@@ -70,12 +59,12 @@ static int xe_ttm_vram_mgr_new(struct ttm_resource_manager *man,
 	int r;
 
 	lpfn = (u64)place->lpfn << PAGE_SHIFT;
-	if (!lpfn)
+	if (!lpfn || lpfn > man->size)
 		lpfn = man->size;
 
 	fpfn = (u64)place->fpfn << PAGE_SHIFT;
 
-	max_bytes = mgr->gt->mem.vram.size;
+	max_bytes = mgr->manager.size;
 	if (place->flags & TTM_PL_FLAG_CONTIGUOUS) {
 		pages_per_block = ~0ul;
 	} else {
@@ -183,7 +172,7 @@ static int xe_ttm_vram_mgr_new(struct ttm_resource_manager *man,
 			 * Compute the original_size value by subtracting the
 			 * last block size with (aligned size - original size)
 			 */
-			original_size = xe_ttm_vram_mgr_block_size(block) -
+			original_size = drm_buddy_block_size(mm, block) -
 				(size - cur_size);
 		}
 
@@ -201,8 +190,8 @@ static int xe_ttm_vram_mgr_new(struct ttm_resource_manager *man,
 	list_for_each_entry(block, &vres->blocks, link) {
 		unsigned long start;
 
-		start = xe_ttm_vram_mgr_block_start(block) +
-			xe_ttm_vram_mgr_block_size(block);
+		start = drm_buddy_block_offset(block) +
+			drm_buddy_block_size(mm, block);
 		start >>= PAGE_SHIFT;
 
 		if (start > PFN_UP(vres->base.size))
@@ -212,7 +201,7 @@ static int xe_ttm_vram_mgr_new(struct ttm_resource_manager *man,
 		vres->base.start = max(vres->base.start, start);
 	}
 
-	if (xe_is_vram_mgr_blocks_contiguous(&vres->blocks))
+	if (xe_is_vram_mgr_blocks_contiguous(mm, &vres->blocks))
 		vres->base.placement |= TTM_PL_FLAG_CONTIGUOUS;
 
 	*res = &vres->base;
@@ -233,7 +222,7 @@ static void xe_ttm_vram_mgr_del(struct ttm_resource_manager *man,
 {
 	struct xe_ttm_vram_mgr_resource *vres =
 		to_xe_ttm_vram_mgr_resource(res);
-	struct xe_ttm_vram_mgr *mgr = to_vram_mgr(man);
+	struct xe_ttm_vram_mgr *mgr = to_xe_ttm_vram_mgr(man);
 	struct drm_buddy *mm = &mgr->mm;
 
 	mutex_lock(&mgr->lock);
@@ -248,7 +237,7 @@ static void xe_ttm_vram_mgr_del(struct ttm_resource_manager *man,
 static void xe_ttm_vram_mgr_debug(struct ttm_resource_manager *man,
 				  struct drm_printer *printer)
 {
-	struct xe_ttm_vram_mgr *mgr = to_vram_mgr(man);
+	struct xe_ttm_vram_mgr *mgr = to_xe_ttm_vram_mgr(man);
 	struct drm_buddy *mm = &mgr->mm;
 
 	mutex_lock(&mgr->lock);
@@ -263,54 +252,54 @@ static const struct ttm_resource_manager_func xe_ttm_vram_mgr_func = {
 	.debug	= xe_ttm_vram_mgr_debug
 };
 
-static void ttm_vram_mgr_fini(struct drm_device *drm, void *arg)
+static void ttm_vram_mgr_fini(struct drm_device *dev, void *arg)
 {
+	struct xe_device *xe = to_xe_device(dev);
 	struct xe_ttm_vram_mgr *mgr = arg;
-	struct xe_device *xe = gt_to_xe(mgr->gt);
 	struct ttm_resource_manager *man = &mgr->manager;
-	int err;
 
 	ttm_resource_manager_set_used(man, false);
 
-	err = ttm_resource_manager_evict_all(&xe->ttm, man);
-	if (err)
+	if (ttm_resource_manager_evict_all(&xe->ttm, man))
 		return;
 
 	drm_buddy_fini(&mgr->mm);
 
-	ttm_resource_manager_cleanup(man);
-	ttm_set_driver_manager(&xe->ttm, XE_PL_VRAM0 + mgr->gt->info.vram_id,
-			       NULL);
+	ttm_resource_manager_cleanup(&mgr->manager);
+
+	ttm_set_driver_manager(&xe->ttm, mgr->mem_type, NULL);
 }
 
-int xe_ttm_vram_mgr_init(struct xe_gt *gt, struct xe_ttm_vram_mgr *mgr)
+int __xe_ttm_vram_mgr_init(struct xe_device *xe, struct xe_ttm_vram_mgr *mgr,
+			   u32 mem_type, u64 size, u64 default_page_size)
 {
-	struct xe_device *xe = gt_to_xe(gt);
 	struct ttm_resource_manager *man = &mgr->manager;
 	int err;
 
-	XE_BUG_ON(xe_gt_is_media_type(gt));
-
-	mgr->gt = gt;
 	man->func = &xe_ttm_vram_mgr_func;
+	mgr->mem_type = mem_type;
+	mutex_init(&mgr->lock);
+	mgr->default_page_size = default_page_size;
 
-	ttm_resource_manager_init(man, &xe->ttm, gt->mem.vram.size);
-	err = drm_buddy_init(&mgr->mm, man->size, PAGE_SIZE);
-	if (err)
-		return err;
+	ttm_resource_manager_init(man, &xe->ttm, size);
+	err = drm_buddy_init(&mgr->mm, man->size, default_page_size);
 
-	mutex_init(&mgr->lock);
-	mgr->default_page_size = PAGE_SIZE;
+	ttm_set_driver_manager(&xe->ttm, mem_type, &mgr->manager);
+	ttm_resource_manager_set_used(&mgr->manager, true);
+
+	return drmm_add_action_or_reset(&xe->drm, ttm_vram_mgr_fini, mgr);
+}
+
+int xe_ttm_vram_mgr_init(struct xe_gt *gt, struct xe_ttm_vram_mgr *mgr)
+{
+	struct xe_device *xe = gt_to_xe(gt);
 
-	ttm_set_driver_manager(&xe->ttm, XE_PL_VRAM0 + gt->info.vram_id,
-			       &mgr->manager);
-	ttm_resource_manager_set_used(man, true);
+	XE_BUG_ON(xe_gt_is_media_type(gt));
 
-	err = drmm_add_action_or_reset(&xe->drm, ttm_vram_mgr_fini, mgr);
-	if (err)
-		return err;
+	mgr->gt = gt;
 
-	return 0;
+	return __xe_ttm_vram_mgr_init(xe, mgr, XE_PL_VRAM0 + gt->info.vram_id,
+				      gt->mem.vram.size, PAGE_SIZE);
 }
 
 int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe,
diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
index 537fccec4318..78f332d26224 100644
--- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
+++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
@@ -12,6 +12,8 @@ enum dma_data_direction;
 struct xe_device;
 struct xe_gt;
 
+int __xe_ttm_vram_mgr_init(struct xe_device *xe, struct xe_ttm_vram_mgr *mgr,
+			   u32 mem_type, u64 size, u64 default_page_size);
 int xe_ttm_vram_mgr_init(struct xe_gt *gt, struct xe_ttm_vram_mgr *mgr);
 int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe,
 			      struct ttm_resource *res,
@@ -22,20 +24,16 @@ int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe,
 void xe_ttm_vram_mgr_free_sgt(struct device *dev, enum dma_data_direction dir,
 			      struct sg_table *sgt);
 
-static inline u64 xe_ttm_vram_mgr_block_start(struct drm_buddy_block *block)
-{
-	return drm_buddy_block_offset(block);
-}
-
-static inline u64 xe_ttm_vram_mgr_block_size(struct drm_buddy_block *block)
-{
-	return PAGE_SIZE << drm_buddy_block_order(block);
-}
-
 static inline struct xe_ttm_vram_mgr_resource *
 to_xe_ttm_vram_mgr_resource(struct ttm_resource *res)
 {
 	return container_of(res, struct xe_ttm_vram_mgr_resource, base);
 }
 
+static inline struct xe_ttm_vram_mgr *
+to_xe_ttm_vram_mgr(struct ttm_resource_manager *man)
+{
+	return container_of(man, struct xe_ttm_vram_mgr, manager);
+}
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h b/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
index 39b93c71c21b..cf02c62ff427 100644
--- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
+++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
@@ -27,6 +27,8 @@ struct xe_ttm_vram_mgr {
 	u64 default_page_size;
 	/** @lock: protects allocations of VRAM */
 	struct mutex lock;
+
+	u32 mem_type;
 };
 
 /**
-- 
2.38.1

[Intel-xe] [PATCH 17/37] drm/xe: Allow fbdev to allocate stolen memory

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbdev.c | 55 ++++++++++++----------
 1 file changed, 31 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 176e0e44a268..52dc33c5f6d8 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -45,6 +45,7 @@
 #include "gem/i915_gem_lmem.h"
 #else
 #include "xe_gt.h"
+#include "xe_ttm_stolen_mgr.h"
 #endif
 
 #include "i915_drv.h"
@@ -171,8 +172,8 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
 
 	size = mode_cmd.pitches[0] * mode_cmd.height;
 	size = PAGE_ALIGN(size);
-#ifdef I915
 	obj = ERR_PTR(-ENODEV);
+#ifdef I915
 	if (HAS_LMEM(dev_priv)) {
 		obj = i915_gem_object_create_lmem(dev_priv, size,
 						  I915_BO_ALLOC_CONTIGUOUS);
@@ -188,11 +189,22 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
 			obj = i915_gem_object_create_shmem(dev_priv, size);
 	}
 #else
-	/* XXX: Care about stolen? */
-	obj = xe_bo_create_pin_map(dev_priv, to_gt(dev_priv), NULL, size,
-				   ttm_bo_type_kernel,
-				   XE_BO_CREATE_VRAM_IF_DGFX(to_gt(dev_priv)) |
-				   XE_BO_CREATE_PINNED_BIT | XE_BO_SCANOUT_BIT);
+	if (!IS_DGFX(dev_priv)) {
+		obj = xe_bo_create_pin_map(dev_priv, to_gt(dev_priv), NULL, size,
+					   ttm_bo_type_kernel, XE_BO_SCANOUT_BIT |
+					   XE_BO_CREATE_STOLEN_BIT |
+					   XE_BO_CREATE_PINNED_BIT);
+		if (!IS_ERR(obj))
+			drm_info(&dev_priv->drm, "Allocated fbdev into stolen\n");
+		else
+			drm_info(&dev_priv->drm, "Allocated fbdev into stolen failed: %li\n", PTR_ERR(obj));
+	}
+	if (IS_ERR(obj)) {
+		obj = xe_bo_create_pin_map(dev_priv, to_gt(dev_priv), NULL, size,
+					  ttm_bo_type_kernel, XE_BO_SCANOUT_BIT |
+					  XE_BO_CREATE_VRAM_IF_DGFX(to_gt(dev_priv)) |
+					  XE_BO_CREATE_PINNED_BIT);
+	}
 #endif
 
 	if (IS_ERR(obj)) {
@@ -317,33 +329,28 @@ static int intelfb_create(struct drm_fb_helper *helper,
 		info->fix.smem_len = vma->size;
 	}
 	vaddr = i915_vma_pin_iomap(vma);
-
 #else
-	/* XXX: Could be pure fiction.. */
-	if (obj->flags & XE_BO_CREATE_VRAM0_BIT) {
-		struct xe_gt *gt = to_gt(dev_priv);
+	info->apertures->ranges[0].base = pci_resource_start(pdev, 2);
+	info->apertures->ranges[0].size = pci_resource_len(pdev, 2);
+	if (!(obj->flags & XE_BO_CREATE_SYSTEM_BIT)) {
 		bool lmem;
 
-		info->apertures->ranges[0].base = gt->mem.vram.io_start;
-		info->apertures->ranges[0].size = gt->mem.vram.size;
+		if (obj->flags & XE_BO_CREATE_STOLEN_BIT)
+			info->fix.smem_start = xe_ttm_stolen_io_offset(obj, 0);
+		else
+			info->fix.smem_start =
+				pci_resource_start(pdev, 2) +
+				xe_bo_addr(obj, 0, GEN8_PAGE_SIZE, &lmem);
 
-		info->fix.smem_start =
-			(unsigned long)(gt->mem.vram.io_start + xe_bo_addr(obj, 0, 4096, &lmem));
 		info->fix.smem_len = obj->ttm.base.size;
-
 	} else {
-		struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
-
-		info->apertures->ranges[0].base = pci_resource_start(pdev, 2);
-		info->apertures->ranges[0].size =
-			pci_resource_end(pdev, 2) - pci_resource_start(pdev, 2);
-
-		info->fix.smem_start = info->apertures->ranges[0].base + xe_bo_ggtt_addr(obj);
+		/* XXX: Pure fiction, as the BO may not be physically accessible.. */
+		info->fix.smem_start = 0;
 		info->fix.smem_len = obj->ttm.base.size;
 	}
 
-	/* TODO: ttm_bo_kmap? */
-	vaddr = obj->vmap.vaddr;
+	XE_WARN_ON(iosys_map_is_null(&obj->vmap));
+	vaddr = obj->vmap.vaddr_iomem;
 #endif
 
 	if (IS_ERR(vaddr)) {
-- 
2.38.1

[Intel-xe] [PATCH 18/37] drm/xe: Implement initial hw readout for framebuffer

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fb.c       |   9 +
 drivers/gpu/drm/i915/display/intel_fbdev.c    |  11 +-
 drivers/gpu/drm/xe/display/xe_plane_initial.c | 224 ++++++------------
 3 files changed, 89 insertions(+), 155 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index e0a8d9e9df9a..cf047353fd84 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -1847,6 +1847,15 @@ static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
 #ifdef I915
 	if (intel_fb_uses_dpt(fb))
 		intel_dpt_destroy(intel_fb->dpt_vm);
+#else
+	if (intel_fb_obj(fb)->flags & XE_BO_CREATE_PINNED_BIT) {
+		struct xe_bo *bo = intel_fb_obj(fb);
+
+		/* Unpin our kernel fb first */
+		xe_bo_lock_no_vm(bo, NULL);
+		xe_bo_unpin(bo);
+		xe_bo_unlock_no_vm(bo);
+	}
 #endif
 
 	drm_gem_object_put(fb->obj[0]);
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 52dc33c5f6d8..d1e5b730433d 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -415,17 +415,8 @@ static void intel_fbdev_destroy(struct intel_fbdev *ifbdev)
 	if (ifbdev->vma)
 		intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
 
-	if (ifbdev->fb) {
-#ifndef I915
-		struct xe_bo *bo = intel_fb_obj(&ifbdev->fb->base);
-
-		/* Unpin our kernel fb first */
-		xe_bo_lock_no_vm(bo, NULL);
-		xe_bo_unpin(bo);
-		xe_bo_unlock_no_vm(bo);
-#endif
+	if (ifbdev->fb)
 		drm_framebuffer_remove(&ifbdev->fb->base);
-	}
 
 	kfree(ifbdev);
 }
diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c
index 0b3ad417d607..c442733d34b1 100644
--- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
+++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
@@ -3,29 +3,24 @@
  * Copyright © 2021 Intel Corporation
  */
 
-#ifdef I915
-#include "gem/i915_gem_region.h"
-#endif
+/* for ioread64 */
+#include <linux/io-64-nonatomic-lo-hi.h>
+
+#include "xe_ggtt.h"
+
 #include "i915_drv.h"
 #include "intel_atomic_plane.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
 #include "intel_fb.h"
+#include "intel_fb_pin.h"
 #include "intel_frontbuffer.h"
 #include "intel_plane_initial.h"
 
-#if 0
-#ifndef I915
-typedef u64 gen8_pte_t;
-#define I915_GTT_PAGE_SIZE SZ_4K
-#define I915_GTT_PAGE_MASK ~(SZ_4K - 1)
-#endif
-
 static bool
 intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
 			      const struct intel_initial_plane_config *plane_config,
-			      struct drm_framebuffer **fb,
-			      struct i915_vma **vma)
+			      struct drm_framebuffer **fb)
 {
 	struct intel_crtc *crtc;
 
@@ -45,7 +40,6 @@ intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
 
 		if (intel_plane_ggtt_offset(plane_state) == plane_config->base) {
 			*fb = plane_state->hw.fb;
-			*vma = plane_state->ggtt_vma;
 			return true;
 		}
 	}
@@ -53,118 +47,84 @@ intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
 	return false;
 }
 
-static struct i915_vma *
-initial_plane_vma(struct drm_i915_private *i915,
-		  struct intel_initial_plane_config *plane_config)
+static struct xe_bo *
+initial_plane_bo(struct xe_device *xe,
+		 struct intel_initial_plane_config *plane_config)
 {
-	struct intel_memory_region *mem;
-	struct drm_i915_gem_object *obj;
-	struct i915_vma *vma;
+	struct xe_gt *gt0 = xe_device_get_gt(xe, 0);
+	struct xe_bo *bo;
 	resource_size_t phys_base;
-	u32 base, size;
-	u64 pinctl;
+	u32 base, size, flags;
+	u64 page_size = xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;
 
 	if (plane_config->size == 0)
 		return NULL;
 
-	base = round_down(plane_config->base, I915_GTT_PAGE_SIZE);
-	if (IS_DGFX(i915)) {
-		gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
-		gen8_pte_t pte;
+	flags = XE_BO_CREATE_PINNED_BIT | XE_BO_SCANOUT_BIT;
 
-		gte += base / I915_GTT_PAGE_SIZE;
+	base = round_down(plane_config->base, page_size);
+	if (IS_DGFX(xe)) {
+		u64 __iomem *gte = gt0->mem.ggtt->gsm;
+		u64 pte;
+
+		gte += base / GEN8_PAGE_SIZE;
 
 		pte = ioread64(gte);
 		if (!(pte & GEN12_GGTT_PTE_LM)) {
-			drm_err(&i915->drm,
+			drm_err(&xe->drm,
 				"Initial plane programming missing PTE_LM bit\n");
 			return NULL;
 		}
 
-		phys_base = pte & I915_GTT_PAGE_MASK;
-		mem = i915->mm.regions[INTEL_REGION_LMEM_0];
+		phys_base = pte & ~(page_size - 1);
+		flags |= XE_BO_CREATE_VRAM0_BIT;
 
 		/*
 		 * We don't currently expect this to ever be placed in the
 		 * stolen portion.
 		 */
-		if (phys_base >= resource_size(&mem->region)) {
-			drm_err(&i915->drm,
+		if (phys_base >= gt0->mem.vram.size) {
+			drm_err(&xe->drm,
 				"Initial plane programming using invalid range, phys_base=%pa\n",
 				&phys_base);
 			return NULL;
 		}
 
-		drm_dbg(&i915->drm,
+		drm_dbg(&xe->drm,
 			"Using phys_base=%pa, based on initial plane programming\n",
 			&phys_base);
 	} else {
+		struct ttm_resource_manager *stolen = ttm_manager_type(&xe->ttm, XE_PL_STOLEN);
+
+		if (!stolen)
+			return NULL;
 		phys_base = base;
-		mem = i915->mm.stolen_region;
-	}
+		flags |= XE_BO_CREATE_STOLEN_BIT;
 
-	if (!mem)
-		return NULL;
+		/*
+		 * If the FB is too big, just don't use it since fbdev is not very
+		 * important and we should probably use that space with FBC or other
+		 * features.
+		 */
+		if (!stolen || (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
+				plane_config->size * 2 >> PAGE_SHIFT >= stolen->size))
+			return NULL;
+	}
 
 	size = round_up(plane_config->base + plane_config->size,
-			mem->min_page_size);
+			page_size);
 	size -= base;
 
-	/*
-	 * If the FB is too big, just don't use it since fbdev is not very
-	 * important and we should probably use that space with FBC or other
-	 * features.
-	 */
-	if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
-	    mem == i915->mm.stolen_region &&
-	    size * 2 > i915->stolen_usable_size)
+	bo = xe_bo_create_pin_map_at(xe, gt0, NULL, size, phys_base,
+				     ttm_bo_type_kernel, flags);
+	if (IS_ERR(bo)) {
+		drm_dbg(&xe->drm,
+			"Failed to create bo phys_base=%pa size %u with flags %x: %li\n",
+			&phys_base, size, flags, PTR_ERR(bo));
 		return NULL;
-
-	obj = i915_gem_object_create_region_at(mem, phys_base, size, 0);
-	if (IS_ERR(obj))
-		return NULL;
-
-	/*
-	 * Mark it WT ahead of time to avoid changing the
-	 * cache_level during fbdev initialization. The
-	 * unbind there would get stuck waiting for rcu.
-	 */
-	i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
-					    I915_CACHE_WT : I915_CACHE_NONE);
-
-	switch (plane_config->tiling) {
-	case I915_TILING_NONE:
-		break;
-	case I915_TILING_X:
-	case I915_TILING_Y:
-		obj->tiling_and_stride =
-			plane_config->fb->base.pitches[0] |
-			plane_config->tiling;
-		break;
-	default:
-		MISSING_CASE(plane_config->tiling);
-		goto err_obj;
 	}
 
-	vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL);
-	if (IS_ERR(vma))
-		goto err_obj;
-
-	pinctl = PIN_GLOBAL | PIN_OFFSET_FIXED | base;
-	if (HAS_GMCH(i915))
-		pinctl |= PIN_MAPPABLE;
-	if (i915_vma_pin(vma, 0, 0, pinctl))
-		goto err_obj;
-
-	if (i915_gem_object_is_tiled(obj) &&
-	    !i915_vma_is_map_and_fenceable(vma))
-		goto err_obj;
-
-	return vma;
-
-err_obj:
-	i915_gem_object_put(obj);
-	return NULL;
+	return bo;
 }
 
 static bool
@@ -175,7 +135,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
 	struct drm_framebuffer *fb = &plane_config->fb->base;
-	struct i915_vma *vma;
+	struct xe_bo *bo;
 
 	switch (fb->modifier) {
 	case DRM_FORMAT_MOD_LINEAR:
@@ -197,21 +157,20 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
 	mode_cmd.modifier[0] = fb->modifier;
 	mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
 
-	vma = initial_plane_vma(dev_priv, plane_config);
-	if (!vma)
+	bo = initial_plane_bo(dev_priv, plane_config);
+	if (!bo)
 		return false;
 
 	if (intel_framebuffer_init(to_intel_framebuffer(fb),
-				   vma->obj, &mode_cmd)) {
+				   bo, &mode_cmd)) {
 		drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
-		goto err_vma;
+		goto err_bo;
 	}
 
-	plane_config->vma = vma;
 	return true;
 
-err_vma:
-	i915_vma_put(vma);
+err_bo:
+	xe_bo_unpin_map_no_vm(bo);
 	return false;
 }
 
@@ -236,43 +195,21 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc,
 	if (!plane_config->fb)
 		return;
 
-	if (intel_alloc_initial_plane_obj(crtc, plane_config)) {
+	if (intel_alloc_initial_plane_obj(crtc, plane_config))
 		fb = &plane_config->fb->base;
-		vma = plane_config->vma;
-		goto valid_fb;
-	}
+	else if (!intel_reuse_initial_plane_obj(dev_priv, plane_config, &fb))
+		goto nofb;
 
-	/*
-	 * Failed to alloc the obj, check to see if we should share
-	 * an fb with another CRTC instead
-	 */
-	if (intel_reuse_initial_plane_obj(dev_priv, plane_config, &fb, &vma))
-		goto valid_fb;
-
-	/*
-	 * We've failed to reconstruct the BIOS FB.  Current display state
-	 * indicates that the primary plane is visible, but has a NULL FB,
-	 * which will lead to problems later if we don't fix it up.  The
-	 * simplest solution is to just disable the primary plane now and
-	 * pretend the BIOS never had it enabled.
-	 */
-	intel_plane_disable_noatomic(crtc, plane);
-
-	return;
-
-valid_fb:
 	plane_state->uapi.rotation = plane_config->rotation;
 	intel_fb_fill_view(to_intel_framebuffer(fb),
 			   plane_state->uapi.rotation, &plane_state->view);
 
-	__i915_vma_pin(vma);
-	plane_state->ggtt_vma = i915_vma_get(vma);
-#ifdef I915
-	if (intel_plane_uses_fence(plane_state) &&
-	    i915_vma_pin_fence(vma) == 0 && vma->fence)
-		plane_state->flags |= PLANE_HAS_FENCE;
-#endif
+	vma = intel_pin_and_fence_fb_obj(fb, false, &plane_state->view.gtt,
+					 false, &plane_state->flags);
+	if (IS_ERR(vma))
+		goto nofb;
 
+	plane_state->ggtt_vma = vma;
 	plane_state->uapi.src_x = 0;
 	plane_state->uapi.src_y = 0;
 	plane_state->uapi.src_w = fb->width << 16;
@@ -283,11 +220,6 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc,
 	plane_state->uapi.crtc_w = fb->width;
 	plane_state->uapi.crtc_h = fb->height;
 
-#ifdef I915
-	if (plane_config->tiling)
-		dev_priv->preserve_bios_swizzle = true;
-#endif
-
 	plane_state->uapi.fb = fb;
 	drm_framebuffer_get(fb);
 
@@ -295,6 +227,19 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc,
 	intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc);
 
 	atomic_or(plane->frontbuffer_bit, &to_intel_framebuffer(fb)->bits);
+	return;
+
+nofb:
+	/*
+	 * We've failed to reconstruct the BIOS FB.  Current display state
+	 * indicates that the primary plane is visible, but has a NULL FB,
+	 * which will lead to problems later if we don't fix it up.  The
+	 * simplest solution is to just disable the primary plane now and
+	 * pretend the BIOS never had it enabled.
+	 */
+	intel_plane_disable_noatomic(crtc, plane);
+
+	return;
 }
 
 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
@@ -308,16 +253,11 @@ static void plane_config_fini(struct intel_initial_plane_config *plane_config)
 		else
 			kfree(fb);
 	}
-
-	if (plane_config->vma)
-		i915_vma_put(plane_config->vma);
 }
-#endif
 
 void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
 {
-#if 0
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct xe_device *xe = to_xe_device(crtc->base.dev);
 	struct intel_initial_plane_config plane_config = {};
 
 	/*
@@ -327,7 +267,7 @@ void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
 	 * can even allow for smooth boot transitions if the BIOS
 	 * fb is large enough for the active pipe configuration.
 	 */
-	dev_priv->display.funcs.crtc->get_initial_plane_config(crtc, &plane_config);
+	xe->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
 
 	/*
 	 * If the fb is shared between multiple heads, we'll
@@ -336,10 +276,4 @@ void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
 	intel_find_initial_plane_obj(crtc, &plane_config);
 
 	plane_config_fini(&plane_config);
-#else
-	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
-
-	/* No support for stolen memory yet, just disable all, worry about smoothness later! */
-	intel_plane_disable_noatomic(crtc, plane);
-#endif
 }
-- 
2.38.1

[Intel-xe] [PATCH 19/37] drm/xe: Put DPT into stolen memory, if available

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Same as i915 does, why not?

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/display/xe_fb_pin.c | 40 +++++++++++++++-----------
 1 file changed, 23 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index b989d37b94f1..f23d00daf574 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -48,16 +48,31 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
 	struct xe_bo *bo = intel_fb_obj(&fb->base), *dpt;
 	u32 dpt_size, size = bo->ttm.base.size;
 
-	if (view->type == I915_GTT_VIEW_NORMAL) {
-		u32 x;
-
+	if (view->type == I915_GTT_VIEW_NORMAL)
 		dpt_size = ALIGN(size / GEN8_PAGE_SIZE * 8, GEN8_PAGE_SIZE);
+	else
+		/* display uses 4K tiles instead of bytes here, convert to entries.. */
+		dpt_size = ALIGN(intel_rotation_info_size(&view->rotated) * 8, GEN8_PAGE_SIZE);
+
+	dpt = xe_bo_create_pin_map(xe, to_gt(xe), NULL, dpt_size,
+				  ttm_bo_type_kernel,
+				  XE_BO_CREATE_VRAM0_BIT |
+				  XE_BO_CREATE_GGTT_BIT);
+	if (IS_ERR(dpt))
+		dpt = xe_bo_create_pin_map(xe, to_gt(xe), NULL, dpt_size,
+					   ttm_bo_type_kernel,
+					   XE_BO_CREATE_STOLEN_BIT |
+					   XE_BO_CREATE_GGTT_BIT);
+	if (IS_ERR(dpt))
 		dpt = xe_bo_create_pin_map(xe, to_gt(xe), NULL, dpt_size,
-					  ttm_bo_type_kernel,
-					  XE_BO_CREATE_VRAM_IF_DGFX(to_gt(xe)) |
-					  XE_BO_CREATE_GGTT_BIT);
-		if (IS_ERR(dpt))
-			return PTR_ERR(dpt);
+					   ttm_bo_type_kernel,
+					   XE_BO_CREATE_SYSTEM_BIT |
+					   XE_BO_CREATE_GGTT_BIT);
+	if (IS_ERR(dpt))
+		return PTR_ERR(dpt);
+
+	if (view->type == I915_GTT_VIEW_NORMAL) {
+		u32 x;
 
 		for (x = 0; x < size / GEN8_PAGE_SIZE; x++)
 			iosys_map_wr(&dpt->vmap, x * 8, u64,
@@ -66,15 +81,6 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
 		const struct intel_rotation_info *rot_info = &view->rotated;
 		u32 i, dpt_ofs = 0;
 
-		/* display uses 4K tiles instead of bytes here, convert to entries.. */
-		dpt_size = ALIGN(intel_rotation_info_size(rot_info) * 8, GEN8_PAGE_SIZE);
-		dpt = xe_bo_create_pin_map(xe, to_gt(xe), NULL, dpt_size,
-					  ttm_bo_type_kernel,
-					  XE_BO_CREATE_VRAM_IF_DGFX(to_gt(xe)) |
-					  XE_BO_CREATE_GGTT_BIT);
-		if (IS_ERR(dpt))
-			return PTR_ERR(dpt);
-
 		for (i = 0; i < ARRAY_SIZE(rot_info->plane); i++)
 			write_dpt_rotated(bo, &dpt->vmap, &dpt_ofs,
 					  rot_info->plane[i].offset,
-- 
2.38.1

[Intel-xe] [PATCH 20/37] drm/xe: Implement FBC support

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Initialise the stolen memory allocator earlier to make it available
when FBC is initialised, so we can check if it's succesfull there.

With this, we can easily implement FBC by hooking a few calls
inside intel_fbc.c

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 85 +++++++++++++++++-------
 drivers/gpu/drm/xe/xe_bo.c               | 29 ++++----
 drivers/gpu/drm/xe/xe_bo.h               |  5 ++
 drivers/gpu/drm/xe/xe_device.c           |  6 +-
 4 files changed, 85 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 77c848b5b7ae..2804db71d630 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -45,9 +45,6 @@
 
 #include "i915_drv.h"
 #include "i915_utils.h"
-#ifdef I915
-#include "i915_vgpu.h"
-#endif
 #include "intel_cdclk.h"
 #include "intel_de.h"
 #include "intel_display_trace.h"
@@ -57,28 +54,66 @@
 
 #ifdef I915
 
+#include "i915_vgpu.h"
+
 #define i915_gem_stolen_initialized(i915) (drm_mm_initialized(&(i915)->mm.stolen))
+#define i915_gem_stolen_allocated(node) drm_mm_node_allocated(&(node))
+#define i915_gem_stolen_compressed_offset(node) ((node).start)
+#define i915_gem_stolen_compressed_size(node) ((node).size)
 
 #else
 
-/* No stolen memory support in xe yet */
-static int i915_gem_stolen_insert_node_in_range(struct xe_device *xe, void *ptr, u32 size, u32 align, u32 start, u32 end)
+#include "xe_ttm_stolen_mgr.h"
+#include "xe_res_cursor.h"
+
+static int i915_gem_stolen_insert_node_in_range(struct xe_device *xe, struct xe_bo **bo, u32 size, u32 align, u32 start, u32 end)
 {
-	return -ENODEV;
+	int err;
+	u32 flags = XE_BO_CREATE_PINNED_BIT | XE_BO_CREATE_STOLEN_BIT;
+
+	*bo = xe_bo_create_locked_range(xe, to_gt(xe), NULL, size, start, end,
+					ttm_bo_type_kernel, flags);
+	if (IS_ERR(*bo)) {
+		err = PTR_ERR(*bo);
+		bo = NULL;
+		return err;
+	}
+	err = xe_bo_pin(*bo);
+	xe_bo_unlock_vm_held(*bo);
+
+	if (err) {
+		xe_bo_put(*bo);
+		*bo = NULL;
+	}
+
+	return err;
 }
 
-static int i915_gem_stolen_insert_node(struct xe_device *xe, void *ptr, u32 size, u32 align)
+static int i915_gem_stolen_insert_node(struct xe_device *xe, struct xe_bo **bo, u32 size, u32 align)
 {
-	XE_WARN_ON(1);
+	/* Not used on xe */
+	BUG_ON(1);
 	return -ENODEV;
 }
 
-static void i915_gem_stolen_remove_node(struct xe_device *xe, void *ptr)
+static void i915_gem_stolen_remove_node(struct xe_device *xe, struct xe_bo **bo)
 {
+	xe_bo_unpin_map_no_vm(*bo);
+	*bo = NULL;
 }
 
-#define i915_gem_stolen_initialized(xe) ((xe) && 0)
+#define i915_gem_stolen_initialized(xe) (!!ttm_manager_type(&(xe)->ttm, XE_PL_STOLEN))
+#define i915_gem_stolen_allocated(bo) (!!(bo))
+
+static u32 i915_gem_stolen_compressed_offset(struct xe_bo *bo)
+{
+	struct xe_res_cursor res;
+
+	xe_res_first(bo->ttm.resource, 0, 4096, &res);
+	return res.start;
+}
 
+#define i915_gem_stolen_compressed_size(fb) ((u64)((fb)->ttm.base.size))
 #endif
 
 #define for_each_fbc_id(__dev_priv, __fbc_id) \
@@ -121,8 +156,11 @@ struct intel_fbc {
 	struct mutex lock;
 	unsigned int busy_bits;
 
-	struct drm_mm_node compressed_fb;
-	struct drm_mm_node compressed_llb;
+#ifdef I915
+	struct drm_mm_node compressed_fb, compressed_llb;
+#else
+	struct xe_bo *compressed_fb, *compressed_llb;
+#endif
 
 	enum intel_fbc_id id;
 
@@ -476,7 +514,8 @@ static void g4x_fbc_program_cfb(struct intel_fbc *fbc)
 {
 	struct drm_i915_private *i915 = fbc->i915;
 
-	intel_de_write(i915, DPFC_CB_BASE, fbc->compressed_fb.start);
+	intel_de_write(i915, DPFC_CB_BASE,
+		       i915_gem_stolen_compressed_offset(fbc->compressed_fb));
 }
 
 static const struct intel_fbc_funcs g4x_fbc_funcs = {
@@ -527,7 +566,8 @@ static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
 {
 	struct drm_i915_private *i915 = fbc->i915;
 
-	intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fbc->compressed_fb.start);
+	intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id),
+		       i915_gem_stolen_compressed_offset(fbc->compressed_fb));
 }
 
 static const struct intel_fbc_funcs ilk_fbc_funcs = {
@@ -747,8 +787,6 @@ static u64 intel_fbc_stolen_end(struct drm_i915_private *i915)
 	    (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915)))
 		end = resource_size(&i915->dsm) - 8 * 1024 * 1024;
 	else
-#else
-	/* TODO */
 #endif
 		end = U64_MAX;
 
@@ -805,9 +843,9 @@ static int intel_fbc_alloc_cfb(struct intel_fbc *fbc,
 	int ret;
 
 	drm_WARN_ON(&i915->drm,
-		    drm_mm_node_allocated(&fbc->compressed_fb));
+		    i915_gem_stolen_allocated(fbc->compressed_fb));
 	drm_WARN_ON(&i915->drm,
-		    drm_mm_node_allocated(&fbc->compressed_llb));
+		    i915_gem_stolen_allocated(fbc->compressed_llb));
 
 	if (DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) {
 		ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb,
@@ -827,12 +865,12 @@ static int intel_fbc_alloc_cfb(struct intel_fbc *fbc,
 
 	drm_dbg_kms(&i915->drm,
 		    "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n",
-		    fbc->compressed_fb.size, fbc->limit);
+		    i915_gem_stolen_compressed_size(fbc->compressed_fb), fbc->limit);
 
 	return 0;
 
 err_llb:
-	if (drm_mm_node_allocated(&fbc->compressed_llb))
+	if (i915_gem_stolen_allocated(fbc->compressed_llb))
 		i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
 err:
 	if (i915_gem_stolen_initialized(i915))
@@ -860,9 +898,9 @@ static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
 	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
 		return;
 
-	if (drm_mm_node_allocated(&fbc->compressed_llb))
+	if (i915_gem_stolen_allocated(fbc->compressed_llb))
 		i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
-	if (drm_mm_node_allocated(&fbc->compressed_fb))
+	if (i915_gem_stolen_allocated(fbc->compressed_fb))
 		i915_gem_stolen_remove_node(i915, &fbc->compressed_fb);
 }
 
@@ -1070,7 +1108,8 @@ static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state)
 	struct intel_fbc *fbc = plane->fbc;
 
 	return intel_fbc_min_limit(plane_state) <= fbc->limit &&
-		intel_fbc_cfb_size(plane_state) <= fbc->compressed_fb.size * fbc->limit;
+		intel_fbc_cfb_size(plane_state) <= fbc->limit *
+			i915_gem_stolen_compressed_size(fbc->compressed_fb);
 }
 
 static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state)
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 314f9b5d34f1..0889c3c89511 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -1023,7 +1023,7 @@ struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
 static int __xe_bo_fixed_placement(struct xe_device *xe,
 				   struct xe_bo *bo,
 				   u32 flags,
-				   u64 offset, u64 size)
+				   u64 start, u64 end, u64 size)
 {
 	struct ttm_place *place = bo->placements;
 
@@ -1031,8 +1031,8 @@ static int __xe_bo_fixed_placement(struct xe_device *xe,
 		return -EINVAL;
 
 	place->flags = TTM_PL_FLAG_CONTIGUOUS;
-	place->fpfn = offset >> PAGE_SHIFT;
-	place->lpfn = (offset + size) >> PAGE_SHIFT;
+	place->fpfn = start >> PAGE_SHIFT;
+	place->lpfn = end >> PAGE_SHIFT;
 
 	switch (flags & (XE_BO_CREATE_STOLEN_BIT |
 		XE_BO_CREATE_VRAM0_BIT |XE_BO_CREATE_VRAM1_BIT)) {
@@ -1061,11 +1061,11 @@ static int __xe_bo_fixed_placement(struct xe_device *xe,
 	return 0;
 }
 
-static struct xe_bo *
-xe_bo_create_locked_at(struct xe_device *xe,
-		       struct xe_gt *gt, struct xe_vm *vm,
-		       size_t size, u64 offset,
-		       enum ttm_bo_type type, u32 flags)
+struct xe_bo *
+xe_bo_create_locked_range(struct xe_device *xe,
+			  struct xe_gt *gt, struct xe_vm *vm,
+			  size_t size, u64 start, u64 end,
+			  enum ttm_bo_type type, u32 flags)
 {
 	struct xe_bo *bo = NULL;
 	int err;
@@ -1073,13 +1073,13 @@ xe_bo_create_locked_at(struct xe_device *xe,
 	if (vm)
 		xe_vm_assert_held(vm);
 
-	if (offset != ~0ULL) {
+	if (start || end != ~0ULL) {
 		bo = xe_bo_alloc();
 		if (IS_ERR(bo))
 			return bo;
 
 		flags |= XE_BO_FIXED_PLACEMENT_BIT;
-		err = __xe_bo_fixed_placement(xe, bo, flags, offset, size);
+		err = __xe_bo_fixed_placement(xe, bo, flags, start, end, size);
 		if (err) {
 			xe_bo_free(bo);
 			return ERR_PTR(err);
@@ -1096,7 +1096,6 @@ xe_bo_create_locked_at(struct xe_device *xe,
 	bo->vm = vm;
 
 	if (bo->flags & XE_BO_CREATE_GGTT_BIT) {
-
 		if (!gt && flags & XE_BO_CREATE_STOLEN_BIT)
 			gt = xe_device_get_gt(xe, 0);
 
@@ -1119,7 +1118,7 @@ struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_gt *gt,
 				  struct xe_vm *vm, size_t size,
 				  enum ttm_bo_type type, u32 flags)
 {
-	return xe_bo_create_locked_at(xe, gt, vm, size, ~0ULL, type, flags);
+	return xe_bo_create_locked_range(xe, gt, vm, size, 0, ~0ULL, type, flags);
 }
 
 struct xe_bo *xe_bo_create(struct xe_device *xe, struct xe_gt *gt,
@@ -1141,12 +1140,14 @@ struct xe_bo *xe_bo_create_pin_map_at(struct xe_device *xe, struct xe_gt *gt,
 {
 	struct xe_bo *bo;
 	int err;
+	u64 start = offset == ~0ull ? 0 : offset;
+	u64 end = offset == ~0ull ? offset : start + size;
 
 	if (flags & XE_BO_CREATE_STOLEN_BIT &&
 	    xe_ttm_stolen_inaccessible(xe))
 		flags |= XE_BO_CREATE_GGTT_BIT;
 
-	bo = xe_bo_create_locked_at(xe, gt, vm, size, offset, type, flags);
+	bo = xe_bo_create_locked_range(xe, gt, vm, size, start, end, type, flags);
 	if (IS_ERR(bo))
 		return bo;
 
@@ -1174,7 +1175,7 @@ struct xe_bo *xe_bo_create_pin_map(struct xe_device *xe, struct xe_gt *gt,
 				   struct xe_vm *vm, size_t size,
 				   enum ttm_bo_type type, u32 flags)
 {
-	return xe_bo_create_pin_map_at(xe, gt, vm, size, ~0ULL, type, flags);
+	return xe_bo_create_pin_map_at(xe, gt, vm, size, ~0ull, type, flags);
 }
 
 struct xe_bo *xe_bo_create_from_data(struct xe_device *xe, struct xe_gt *gt,
diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
index ed71b594f407..8d8a3332dbc8 100644
--- a/drivers/gpu/drm/xe/xe_bo.h
+++ b/drivers/gpu/drm/xe/xe_bo.h
@@ -79,6 +79,11 @@ struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
 				    struct xe_gt *gt, struct dma_resv *resv,
 				    size_t size, enum ttm_bo_type type,
 				    u32 flags);
+struct xe_bo *
+xe_bo_create_locked_range(struct xe_device *xe,
+			  struct xe_gt *gt, struct xe_vm *vm,
+			  size_t size, u64 start, u64 end,
+			  enum ttm_bo_type type, u32 flags);
 struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_gt *gt,
 				  struct xe_vm *vm, size_t size,
 				  enum ttm_bo_type type, u32 flags);
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 86e386931206..c8b4c580bd98 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -405,6 +405,9 @@ int xe_device_probe(struct xe_device *xe)
 			return err;
 	}
 
+	/* Harmless if stolen initialization fails */
+	xe_ttm_stolen_mgr_init(xe);
+
 	err = xe_device_init_display_noirq(xe);
 	if (err)
 		return err;
@@ -429,9 +432,6 @@ int xe_device_probe(struct xe_device *xe)
 			goto err_irq_shutdown;
 	}
 
-	/* Harmless if stolen initialization fails */
-	xe_ttm_stolen_mgr_init(xe);
-
 	/*
 	 * Now that GT is initialized (TTM in particular),
 	 * we can try to init display, and inherit the initial fb.
-- 
2.38.1

[Intel-xe] [PATCH 21/37] drm/i915: Remove i915_drm_suspend_mode

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

enum i915_drm_suspend_mode suspend_mode is only used in
intel_display_power, while we only care about whether we perform a
s2idle. Remove it and use a simple bool.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 .../gpu/drm/i915/display/intel_display_power.c   |  8 +++-----
 .../gpu/drm/i915/display/intel_display_power.h   |  3 +--
 drivers/gpu/drm/i915/i915_driver.c               | 16 ++--------------
 drivers/gpu/drm/i915/intel_runtime_pm.h          |  6 ------
 4 files changed, 6 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c3a57ec0d2f3..00e32a423708 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2039,7 +2039,7 @@ void intel_power_domains_disable(struct drm_i915_private *i915)
 /**
  * intel_power_domains_suspend - suspend power domain state
  * @i915: i915 device instance
- * @suspend_mode: specifies the target suspend state (idle, mem, hibernation)
+ * @s2idle: specifies whether we go to idle, or deeper sleep
  *
  * This function prepares the hardware power domain state before entering
  * system suspend.
@@ -2047,8 +2047,7 @@ void intel_power_domains_disable(struct drm_i915_private *i915)
  * It must be called with power domains already disabled (after a call to
  * intel_power_domains_disable()) and paired with intel_power_domains_resume().
  */
-void intel_power_domains_suspend(struct drm_i915_private *i915,
-				 enum i915_drm_suspend_mode suspend_mode)
+void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle)
 {
 	struct i915_power_domains *power_domains = &i915->display.power.domains;
 	intel_wakeref_t wakeref __maybe_unused =
@@ -2064,8 +2063,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
 	 * that would be blocked if the firmware was inactive.
 	 */
 	if (!(i915->display.dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
-	    suspend_mode == I915_DRM_SUSPEND_IDLE &&
-	    intel_dmc_has_payload(i915)) {
+	    s2idle && intel_dmc_has_payload(i915)) {
 		intel_display_power_flush_work(i915);
 		intel_power_domains_verify_state(i915);
 		return;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 3aae045749f7..d8d9309c1f19 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -172,8 +172,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
-void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
-				 enum i915_drm_suspend_mode);
+void intel_power_domains_suspend(struct drm_i915_private *dev_priv, bool s2idle);
 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
 void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index f4201f9c5f84..c72f37f8c593 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1235,18 +1235,6 @@ static int i915_drm_suspend(struct drm_device *dev)
 	return 0;
 }
 
-static enum i915_drm_suspend_mode
-get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
-{
-	if (hibernate)
-		return I915_DRM_SUSPEND_HIBERNATE;
-
-	if (suspend_to_idle(dev_priv))
-		return I915_DRM_SUSPEND_IDLE;
-
-	return I915_DRM_SUSPEND_MEM;
-}
-
 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1254,6 +1242,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 	struct intel_gt *gt;
 	int ret, i;
+	bool s2idle = !hibernation && suspend_to_idle(dev_priv);
 
 	disable_rpm_wakeref_asserts(rpm);
 
@@ -1264,8 +1253,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
 	for_each_gt(gt, dev_priv, i)
 		intel_uncore_suspend(gt->uncore);
 
-	intel_power_domains_suspend(dev_priv,
-				    get_suspend_mode(dev_priv, hibernation));
+	intel_power_domains_suspend(dev_priv, s2idle);
 
 	intel_display_power_suspend_late(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h
index e592e8d6499a..764b183ae452 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.h
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
@@ -16,12 +16,6 @@ struct device;
 struct drm_i915_private;
 struct drm_printer;
 
-enum i915_drm_suspend_mode {
-	I915_DRM_SUSPEND_IDLE,
-	I915_DRM_SUSPEND_MEM,
-	I915_DRM_SUSPEND_HIBERNATE,
-};
-
 /*
  * This struct helps tracking the state needed for runtime PM, which puts the
  * device in PCI D3 state. Notice that when this happens, nothing on the
-- 
2.38.1

[Intel-xe] [PATCH 22/37] drm/xe: Fix compilation when Xe driver is builtin

[Rodrigo Vivi]

From: Mauro Carvalho Chehab <mchehab@kernel.org>

Trying to build the driver as builtin with ACPI_WMI=m causes
a Kconfig error:

	WARNING: unmet direct dependencies detected for ACPI_VIDEO
	  Depends on [m]: ACPI [=y] && BACKLIGHT_CLASS_DEVICE [=y] && INPUT [=y] && (ACPI_WMI [=m] || !X86 [=y])
	  Selected by [y]:
	  - DRM_XE [=y] && HAS_IOMEM [=y] && DRM [=y] && PCI [=y] && MMU [=y] && X86 [=y] && ACPI [=y]

As a workaround, let's also select ACPI_WMI. It should be noticed
that the real solution would be to avoid doing so many selects, using
a depends on instead, but that would require a major rework on Xe
(and probably i915) Kconfig files.

Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
index f7780c120731..3815e25d0eec 100644
--- a/drivers/gpu/drm/xe/Kconfig
+++ b/drivers/gpu/drm/xe/Kconfig
@@ -24,6 +24,7 @@ config DRM_XE
 	select INPUT if ACPI
 	select ACPI_VIDEO if X86 && ACPI
 	select ACPI_BUTTON if ACPI
+	select ACPI_WMI if ACPI
 	select SYNC_FILE
 	select IOSF_MBI
 	select CRC32
-- 
2.38.1

[Intel-xe] [PATCH 23/37] drm/xe: Fix dumb bo create

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_bo.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 0889c3c89511..da2c8a1c19ec 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -1784,10 +1784,12 @@ int xe_bo_dumb_create(struct drm_file *file_priv,
 	uint32_t handle;
 	int cpp = DIV_ROUND_UP(args->bpp, 8);
 	int err;
+	u32 page_size = max_t(u32, PAGE_SIZE,
+		xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K);
 
-	/* Align to ggtt page size, which we start requiring for xe display */
-	args->pitch = ALIGN(args->width * cpp, GEN8_PAGE_SIZE);
-	args->size = mul_u32_u32(args->pitch, args->height);
+	args->pitch = ALIGN(args->width * cpp, 64);
+	args->size = ALIGN(mul_u32_u32(args->pitch, args->height),
+			   page_size);
 
 	bo = xe_bo_create(xe, NULL, NULL, args->size, ttm_bo_type_device,
 			  XE_BO_CREATE_VRAM_IF_DGFX(to_gt(xe)) |
-- 
2.38.1

[Intel-xe] [PATCH 24/37] drm/i915: Expand force_probe to block probe of devices as well.

[Rodrigo Vivi]

There are new cases where we want to block i915 probe, such
as when experimenting or developing the new Xe driver.

But also, with the new hybrid cards, users or developers might
want to use i915 only on integrated and fully block the probe
of the i915 for the discrete. Or vice versa.

There are even older development and validation reasons,
like when you use some distro where the modprobe.blacklist is
not present.

But in any case, let's introduce a more granular control, but without
introducing yet another parameter, but using the existent force_probe
one.

Just by adding a ! in the begin of the id in the force_probe, like
in this case where we would block the probe for Alder Lake:

$ insmod i915.ko force_probe='!46a6'

v2: Take care of '*' and  '!*' cases as pointed out by
    Gustavo and Jani.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230103194701.1492984-1-rodrigo.vivi@intel.com
---
 drivers/gpu/drm/i915/Kconfig       | 15 +++++++++++---
 drivers/gpu/drm/i915/i915_params.c |  2 +-
 drivers/gpu/drm/i915/i915_pci.c    | 33 +++++++++++++++++++++++++-----
 3 files changed, 41 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 3efce05d7b57..8eb3e60aeec9 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -54,24 +54,33 @@ config DRM_I915
 	  If "M" is selected, the module will be called i915.
 
 config DRM_I915_FORCE_PROBE
-	string "Force probe driver for selected new Intel hardware"
+	string "Force probe i915 for selected Intel hardware IDs"
 	depends on DRM_I915
 	help
 	  This is the default value for the i915.force_probe module
 	  parameter. Using the module parameter overrides this option.
 
-	  Force probe the driver for new Intel graphics devices that are
+	  Force probe the i915 for Intel graphics devices that are
 	  recognized but not properly supported by this kernel version. It is
 	  recommended to upgrade to a kernel version with proper support as soon
 	  as it is available.
 
+	  It can also be used to block the probe of recognized and fully
+	  supported devices.
+
 	  Use "" to disable force probe. If in doubt, use this.
 
-	  Use "<pci-id>[,<pci-id>,...]" to force probe the driver for listed
+	  Use "<pci-id>[,<pci-id>,...]" to force probe the i915 for listed
 	  devices. For example, "4500" or "4500,4571".
 
 	  Use "*" to force probe the driver for all known devices.
 
+	  Use "!" right before the ID to block the probe of the device. For
+	  example, "4500,!4571" forces the probe of 4500 and blocks the probe of
+	  4571.
+
+	  Use "!*" to block the probe of the driver for all known devices.
+
 config DRM_I915_CAPTURE_ERROR
 	bool "Enable capturing GPU state following a hang"
 	depends on DRM_I915
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 61578f2860cd..d634bd3f641a 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -122,7 +122,7 @@ i915_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400,
 	"Default: 0");
 
 i915_param_named_unsafe(force_probe, charp, 0400,
-	"Force probe the driver for specified devices. "
+	"Force probe options for specified supported devices. "
 	"See CONFIG_DRM_I915_FORCE_PROBE for details.");
 
 i915_param_named_unsafe(disable_power_well, int, 0400,
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 668e9da52584..bc6fc268739d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1253,7 +1253,7 @@ static void i915_pci_remove(struct pci_dev *pdev)
 }
 
 /* is device_id present in comma separated list of ids */
-static bool force_probe(u16 device_id, const char *devices)
+static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
 {
 	char *s, *p, *tok;
 	bool ret;
@@ -1262,7 +1262,9 @@ static bool force_probe(u16 device_id, const char *devices)
 		return false;
 
 	/* match everything */
-	if (strcmp(devices, "*") == 0)
+	if (negative && strcmp(devices, "!*") == 0)
+		return true;
+	if (!negative && strcmp(devices, "*") == 0)
 		return true;
 
 	s = kstrdup(devices, GFP_KERNEL);
@@ -1272,6 +1274,12 @@ static bool force_probe(u16 device_id, const char *devices)
 	for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
 		u16 val;
 
+		if (negative && tok[0] == '!')
+			tok++;
+		else if ((negative && tok[0] != '!') ||
+			 (!negative && tok[0] == '!'))
+			continue;
+
 		if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
 			ret = true;
 			break;
@@ -1283,6 +1291,16 @@ static bool force_probe(u16 device_id, const char *devices)
 	return ret;
 }
 
+static bool id_forced(u16 device_id)
+{
+	return device_id_in_list(device_id, i915_modparams.force_probe, false);
+}
+
+static bool id_blocked(u16 device_id)
+{
+	return device_id_in_list(device_id, i915_modparams.force_probe, true);
+}
+
 bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
 {
 	if (!pci_resource_flags(pdev, bar))
@@ -1308,10 +1326,9 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 		(struct intel_device_info *) ent->driver_data;
 	int err;
 
-	if (intel_info->require_force_probe &&
-	    !force_probe(pdev->device, i915_modparams.force_probe)) {
+	if (intel_info->require_force_probe && !id_forced(pdev->device)) {
 		dev_info(&pdev->dev,
-			 "Your graphics device %04x is not properly supported by the driver in this\n"
+			 "Your graphics device %04x is not properly supported by i915 in this\n"
 			 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
 			 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
 			 "or (recommended) check for kernel updates.\n",
@@ -1319,6 +1336,12 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 		return -ENODEV;
 	}
 
+	if (id_blocked(pdev->device)) {
+		dev_info(&pdev->dev, "I915 probe blocked for Device ID %04x.\n",
+			 pdev->device);
+		return -ENODEV;
+	}
+
 	/* Only bind to function 0 of the device. Early generations
 	 * used function 1 as a placeholder for multi-head. This causes
 	 * us confusion instead, especially on the systems where both
-- 
2.38.1

[Intel-xe] [PATCH 25/37] drm/xe: Introduce force_probe parameter.

[Rodrigo Vivi]

Following the i915 ones and its rules.

So, with this in place, developers can select which driver should
take control of which device.

This is specially useful on hybrid device where developer might
want to use i915 driving everything including display on your ADL-P
while working with xe
on the DG2:

i915.force_probe=!5690,46a6 xe.force_probe=5690,!46a6

or vice versa:

i915.force_probe=5690,!46a6 xe.force_probe=!5690,46a6

This commit also ensures that all current platforms are marked as
require_force_probe at a top level, since this will likely remain
forever in upstream and only be removed after the official switch
on a later platform.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/Kconfig  | 28 +++++++++++++
 drivers/gpu/drm/xe/xe_pci.c | 79 +++++++++++++++++++++++++++++++++++--
 2 files changed, 104 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
index 3815e25d0eec..22e47918bfcf 100644
--- a/drivers/gpu/drm/xe/Kconfig
+++ b/drivers/gpu/drm/xe/Kconfig
@@ -40,6 +40,34 @@ config DRM_XE
 
 	  If "M" is selected, the module will be called xe.
 
+config DRM_XE_FORCE_PROBE
+	string "Force probe xe for selected Intel hardware IDs"
+	depends on DRM_XE
+	help
+	  This is the default value for the xe.force_probe module
+	  parameter. Using the module parameter overrides this option.
+
+	  Force probe the xe for Intel graphics devices that are
+	  recognized but not properly supported by this kernel version. It is
+	  recommended to upgrade to a kernel version with proper support as soon
+	  as it is available.
+
+	  It can also be used to block the probe of recognized and fully
+	  supported devices.
+
+	  Use "" to disable force probe. If in doubt, use this.
+
+	  Use "<pci-id>[,<pci-id>,...]" to force probe the xe for listed
+	  devices. For example, "4500" or "4500,4571".
+
+	  Use "*" to force probe the driver for all known devices.
+
+	  Use "!" right before the ID to block the probe of the device. For
+	  example, "4500,!4571" forces the probe of 4500 and blocks the probe of
+	  4571.
+
+	  Use "!*" to block the probe of the driver for all known devices.
+
 menu "drm/Xe Debugging"
 depends on DRM_XE
 depends on EXPERT
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 91a6fba95ac7..bcf6fd610881 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -22,6 +22,12 @@
 
 #include "../i915/i915_reg.h"
 
+static char *xe_param_force_probe = CONFIG_DRM_XE_FORCE_PROBE;
+module_param_named_unsafe(force_probe, xe_param_force_probe, charp, 0400);
+MODULE_PARM_DESC(force_probe,
+		 "Force probe options for specified devices. "
+		 "See CONFIG_DRM_XE_FORCE_PROBE for details.");
+
 #define DEV_INFO_FOR_EACH_FLAG(func) \
 	func(require_force_probe); \
 	func(is_dgfx); \
@@ -148,6 +154,7 @@ struct xe_device_desc {
 
 /* Keep in gen based order, and chronological order within a gen */
 #define GEN12_FEATURES \
+	.require_force_probe = true, \
 	.graphics_ver = 12, \
 	.media_ver = 12, \
 	.dma_mask_size = 39, \
@@ -196,7 +203,6 @@ static const struct xe_device_desc dg1_desc = {
 	DGFX_FEATURES,
 	.graphics_rel = 10,
 	PLATFORM(XE_DG1),
-	.require_force_probe = true,
 	.platform_engine_mask =
 		BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
 		BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VCS0) |
@@ -204,6 +210,7 @@ static const struct xe_device_desc dg1_desc = {
 };
 
 #define XE_HP_FEATURES \
+	.require_force_probe = true, \
 	.graphics_ver = 12, \
 	.graphics_rel = 50, \
 	.has_flat_ccs = true, \
@@ -288,7 +295,6 @@ static const struct xe_device_desc pvc_desc = {
 	.has_flat_ccs = 0,
 	.media_rel = 60,
 	.platform_engine_mask = PVC_ENGINES,
-	.require_force_probe = true,
 	.vram_flags = XE_VRAM_FLAGS_NEED64K,
 	.dma_mask_size = 52,
 	.max_tiles = 2,
@@ -319,6 +325,7 @@ static const struct xe_device_desc mtl_desc = {
 	 * Real graphics IP version will be obtained from hardware GMD_ID
 	 * register.  Value provided here is just for sanity checking.
 	 */
+	.require_force_probe = true,
 	.graphics_ver = 12,
 	.graphics_rel = 70,
 	.dma_mask_size = 46,
@@ -328,7 +335,6 @@ static const struct xe_device_desc mtl_desc = {
 	PLATFORM(XE_METEORLAKE),
 	.extra_gts = xelpmp_gts,
 	.platform_engine_mask = MTL_MAIN_ENGINES,
-	.require_force_probe = 1,
 	GEN13_DISPLAY,
 	.display.ver = 14,
 	.display.has_cdclk_crawl = 1,
@@ -363,6 +369,55 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
 
 #undef INTEL_VGA_DEVICE
 
+/* is device_id present in comma separated list of ids */
+static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
+{
+	char *s, *p, *tok;
+	bool ret;
+
+	if (!devices || !*devices)
+		return false;
+
+	/* match everything */
+	if (negative && strcmp(devices, "!*") == 0)
+		return true;
+	if (!negative && strcmp(devices, "*") == 0)
+		return true;
+
+	s = kstrdup(devices, GFP_KERNEL);
+	if (!s)
+		return false;
+
+	for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
+		u16 val;
+
+		if (negative && tok[0] == '!')
+			tok++;
+		else if ((negative && tok[0] != '!') ||
+			 (!negative && tok[0] == '!'))
+			continue;
+
+		if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
+			ret = true;
+			break;
+		}
+	}
+
+	kfree(s);
+
+	return ret;
+}
+
+static bool id_forced(u16 device_id)
+{
+	return device_id_in_list(device_id, xe_param_force_probe, false);
+}
+
+static bool id_blocked(u16 device_id)
+{
+	return device_id_in_list(device_id, xe_param_force_probe, true);
+}
+
 static const struct xe_subplatform_desc *
 subplatform_get(const struct xe_device *xe, const struct xe_device_desc *desc)
 {
@@ -398,6 +453,24 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 	u8 id;
 	int err;
 
+	if (desc->require_force_probe && !id_forced(pdev->device)) {
+		dev_info(&pdev->dev,
+			 "Your graphics device %04x is not officially supported\n"
+			 "by xe driver in this kernel version. To force Xe probe,\n"
+			 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n"
+			 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n"
+			 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n",
+			 pdev->device, pdev->device, pdev->device,
+			 pdev->device, pdev->device);
+		return -ENODEV;
+	}
+
+	if (id_blocked(pdev->device)) {
+		dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n",
+			 pdev->vendor, pdev->device);
+		return -ENODEV;
+	}
+
 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
 	/* Detect if we need to wait for other drivers early on */
 	if (intel_modeset_probe_defer(pdev))
-- 
2.38.1

[Intel-xe] [PATCH 26/37] Revert "drm/xe: Validate BO on CPU fault"

[Rodrigo Vivi]

From: Matthew Brost <matthew.brost@intel.com>

This reverts commit 48d84660be7607ccaacd76a2d653f51709cc5693.

Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_bo.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index da2c8a1c19ec..e224405bc4f6 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -875,14 +875,13 @@ static vm_fault_t xe_gem_fault(struct vm_fault *vmf)
 
 		trace_xe_bo_cpu_fault(bo);
 
-		if (should_migrate_to_system(bo))
+		if (should_migrate_to_system(bo)) {
 			r = xe_bo_migrate(bo, XE_PL_TT);
-		else
-			r = xe_bo_validate(bo, NULL, false);
-		if (r == -EBUSY || r == -ERESTARTSYS)
-			ret = VM_FAULT_NOPAGE;
-		else if (r)
-			ret = VM_FAULT_SIGBUS;
+			if (r == -EBUSY || r == -ERESTARTSYS || r == -EINTR)
+				ret = VM_FAULT_NOPAGE;
+			else if (r)
+				ret = VM_FAULT_SIGBUS;
+		}
 		if (!ret)
 			ret = ttm_bo_vm_fault_reserved(vmf,
 						       vmf->vma->vm_page_prot,
-- 
2.38.1

[Intel-xe] [PATCH 27/37] drm/xe: Ensure VMA not userptr before calling xe_bo_is_stolen

[Rodrigo Vivi]

From: Matthew Brost <matthew.brost@intel.com>

Fix the below splat:

[  142.510525] [IGT] xe_exec_basic: starting subtest once-userptr
[  142.511339] BUG: kernel NULL pointer dereference, address: 0000000000000228
[  142.518311] #PF: supervisor read access in kernel mode
[  142.523458] #PF: error_code(0x0000) - not-present page
[  142.528604] PGD 0 P4D 0
[  142.531153] Oops: 0000 [#1] PREEMPT SMP NOPTI
[  142.535518] CPU: 4 PID: 1199 Comm: kworker/u16:8 Not tainted 6.1.0-rc1-xe+ #1
[  142.542656] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.3243.A01.2006102133 06/10/2020
[  142.556033] Workqueue: events_unbound async_op_work_func [xe]
[  142.561810] RIP: 0010:xe_bo_is_stolen+0x0/0x20 [xe]
[  142.566709] Code: 20 c8 75 05 83 fa 07 74 05 c3 cc cc cc cc 48 8b 87 08 02 00 00 0f b6 80 2c ff ff ff c3 cc cc cc cc 66 0f 1f 84 00 00 00 00 00 <48> 8b 87 28 02 00 00 83 78 10 07 0f 94 c0 c3 cc cc cc cc 66 66 2e
[  142.585447] RSP: 0018:ffffc900019eb888 EFLAGS: 00010246
[  142.590678] RAX: 0000000000000002 RBX: 0000000000000000 RCX: ffff88813f6a2108
[  142.597821] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000
[  142.604962] RBP: ffffc900019ebbc0 R08: 0000000000000001 R09: 0000000000000000
[  142.612101] R10: 0000000000000001 R11: 0000000000000001 R12: ffff88814107d600
[  142.619242] R13: ffffc900019eba20 R14: ffff888140442000 R15: 0000000000000000
[  142.626378] FS:  0000000000000000(0000) GS:ffff88849fa00000(0000) knlGS:0000000000000000
[  142.634468] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[  142.640219] CR2: 0000000000000228 CR3: 000000010a4c0006 CR4: 0000000000770ee0
[  142.647361] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[  142.654505] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[  142.661639] PKRU: 55555554
[  142.664367] Call Trace:
[  142.666830]  <TASK>
[  142.668947]  __xe_pt_bind_vma+0x1a1/0xa50 [xe]
[  142.673417]  ? unwind_next_frame+0x187/0x770
[  142.677699]  ? __thaw_task+0xc0/0xc0
[  142.681293]  ? __lock_acquire+0x5e4/0x26e0
[  142.685409]  ? lockdep_hardirqs_on+0xbf/0x140
[  142.689779]  ? lock_acquire+0xd2/0x310
[  142.693548]  ? mark_held_locks+0x49/0x80
[  142.697485]  ? xe_vm_bind_vma+0xf1/0x3d0 [xe]
[  142.701866]  xe_vm_bind_vma+0xf1/0x3d0 [xe]
[  142.706082]  xe_vm_bind+0x76/0x140 [xe]
[  142.709944]  vm_bind_ioctl+0x26f/0xb40 [xe]
[  142.714161]  ? async_op_work_func+0x20c/0x450 [xe]
[  142.718974]  async_op_work_func+0x20c/0x450 [xe]
[  142.723620]  process_one_work+0x263/0x580
[  142.727645]  ? process_one_work+0x580/0x580
[  142.731839]  worker_thread+0x4d/0x3b0
[  142.735518]  ? process_one_work+0x580/0x580
[  142.739714]  kthread+0xeb/0x120
[  142.742872]  ? kthread_complete_and_exit+0x20/0x20
[  142.747671]  ret_from_fork+0x1f/0x30
[  142.751264]  </TASK>

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_pt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index c8b3b1975098..9e07ad41a007 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -758,7 +758,7 @@ xe_pt_stage_bind(struct xe_gt *gt, struct xe_vma *vma,
 		else
 			xe_walk.cache = XE_CACHE_WB;
 	}
-	if (xe_bo_is_stolen(bo))
+	if (!xe_vma_is_userptr(vma) && xe_bo_is_stolen(bo))
 		xe_walk.dma_offset = xe_ttm_stolen_gpu_offset(xe_bo_device(bo));
 
 	xe_bo_assert_held(bo);
-- 
2.38.1

[Intel-xe] [PATCH 28/37] drm/xe: Don't use engine_mask until after hwconfig parse

[Rodrigo Vivi]

From: Matthew Brost <matthew.brost@intel.com>

The IRQ and MCR init used engine_mask before hwconfig parse (currently
faked), move these steps after the hwconfig parse.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt.c  |  7 +++++++
 drivers/gpu/drm/xe/xe_irq.c | 34 +++++++++++++++++++---------------
 drivers/gpu/drm/xe/xe_irq.h |  2 ++
 3 files changed, 28 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 6cea15725cae..75150077d62c 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -21,6 +21,7 @@
 #include "xe_gt_sysfs.h"
 #include "xe_gt_topology.h"
 #include "xe_hw_fence.h"
+#include "xe_irq.h"
 #include "xe_lrc.h"
 #include "xe_map.h"
 #include "xe_migrate.h"
@@ -449,6 +450,12 @@ static int gt_fw_domain_init(struct xe_gt *gt)
 	if (err)
 		goto err_force_wake;
 
+	/* Enables per hw engine IRQs */
+	xe_gt_irq_postinstall(gt);
+
+	/* Rerun MCR init as we now have hw engine list */
+	xe_gt_mcr_init(gt);
+
 	err = xe_hw_engines_init_early(gt);
 	if (err)
 		goto err_force_wake;
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index edebe1817400..92fe6b38d735 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -492,26 +492,32 @@ void xe_irq_reset(struct xe_device *xe)
 #endif
 }
 
-void xe_irq_postinstall(struct xe_device *xe)
+void xe_gt_irq_postinstall(struct xe_gt *gt)
 {
-	struct xe_gt *gt;
-	u8 id;
+	struct xe_device *xe = gt_to_xe(gt);
 
-	for_each_gt(gt, xe, id) {
-		if (GRAPHICS_VERx100(xe) >= 1210) {
-			dg1_irq_postinstall(xe, gt);
-		} else if (GRAPHICS_VER(xe) >= 11) {
-			gen11_irq_postinstall(xe, gt);
-		} else {
-			drm_err(&xe->drm, "No interrupt postinstall hook");
-		}
-	}
+	if (GRAPHICS_VERx100(xe) >= 1210)
+		dg1_irq_postinstall(xe, gt);
+	else if (GRAPHICS_VER(xe) >= 11)
+		gen11_irq_postinstall(xe, gt);
+	else
+		drm_err(&xe->drm, "No interrupt postinstall hook");
 
 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
-	gen11_display_irq_postinstall(xe);
+	if (gt->info.id == XE_GT0)
+		gen11_display_irq_postinstall(gt_to_xe(gt));
 #endif
 }
 
+static void xe_irq_postinstall(struct xe_device *xe)
+{
+	struct xe_gt *gt;
+	u8 id;
+
+	for_each_gt(gt, xe, id)
+		xe_gt_irq_postinstall(gt);
+}
+
 static irq_handler_t xe_irq_handler(struct xe_device *xe)
 {
 	if (GRAPHICS_VERx100(xe) >= 1210) {
@@ -566,8 +572,6 @@ int xe_irq_install(struct xe_device *xe)
 	if (err)
 		return err;
 
-	xe_irq_postinstall(xe);
-
 	return err;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h
index 7aee8d259353..34ecf22b32d3 100644
--- a/drivers/gpu/drm/xe/xe_irq.h
+++ b/drivers/gpu/drm/xe/xe_irq.h
@@ -7,8 +7,10 @@
 #define _XE_IRQ_H_
 
 struct xe_device;
+struct xe_gt;
 
 int xe_irq_install(struct xe_device *xe);
+void xe_gt_irq_postinstall(struct xe_gt *gt);
 void xe_irq_shutdown(struct xe_device *xe);
 void xe_irq_suspend(struct xe_device *xe);
 void xe_irq_resume(struct xe_device *xe);
-- 
2.38.1

[Intel-xe] [PATCH 29/37] drm/xe: Fake pulling gt->info.engine_mask from hwconfig blob

[Rodrigo Vivi]

From: Matthew Brost <matthew.brost@intel.com>

The blob doesn't fully support this yet, so fake for now to ensure our
driver load order is correct.

Once the blob supports pulling gt->info.engine_mask from the blob, this
patch can be removed.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt.c       | 3 +++
 drivers/gpu/drm/xe/xe_gt_types.h | 6 ++++++
 drivers/gpu/drm/xe/xe_pci.c      | 4 ++--
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 75150077d62c..cb837745d893 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -450,6 +450,9 @@ static int gt_fw_domain_init(struct xe_gt *gt)
 	if (err)
 		goto err_force_wake;
 
+	/* XXX: Fake that we pull the engine mask from hwconfig blob */
+	gt->info.engine_mask = gt->info.__engine_mask;
+
 	/* Enables per hw engine IRQs */
 	xe_gt_irq_postinstall(gt);
 
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index c80a9215098d..2dbc8cedd630 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -93,6 +93,12 @@ struct xe_gt {
 		u32 clock_freq;
 		/** @engine_mask: mask of engines present on GT */
 		u64 engine_mask;
+		/**
+		 * @__engine_mask: mask of engines present on GT read from
+		 * xe_pci.c, used to fake reading the engine_mask from the
+		 * hwconfig blob.
+		 */
+		u64 __engine_mask;
 	} info;
 
 	/**
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index bcf6fd610881..d654f2351557 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -509,13 +509,13 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 		if (id == 0) {
 			gt->info.type = XE_GT_TYPE_MAIN;
 			gt->info.vram_id = id;
-			gt->info.engine_mask = desc->platform_engine_mask;
+			gt->info.__engine_mask = desc->platform_engine_mask;
 			gt->mmio.adj_limit = 0;
 			gt->mmio.adj_offset = 0;
 		} else {
 			gt->info.type = desc->extra_gts[id - 1].type;
 			gt->info.vram_id = desc->extra_gts[id - 1].vram_id;
-			gt->info.engine_mask =
+			gt->info.__engine_mask =
 				desc->extra_gts[id - 1].engine_mask;
 			gt->mmio.adj_limit =
 				desc->extra_gts[id - 1].mmio_adj_limit;
-- 
2.38.1

[Intel-xe] [PATCH 30/37] drm/xe/guc: Report submission version of GuC firmware

[Rodrigo Vivi]

From: Matthew Brost <matthew.brost@intel.com>

Starting in 70.6.* GuC firmware the CSS header includes the submission
version, pull this from the CSS header. Prior 70.* versions accidentally
omitted this informatio so hard code to the correct values. This
information will be used by VFs when communicating with the PF.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Cc: Philippe Lecluse <philippe.lecluse@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_types.h |  9 ++++++
 drivers/gpu/drm/xe/xe_uc_fw.c     | 46 ++++++++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_uc_fw_abi.h |  6 +++-
 3 files changed, 59 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
index ca177853cc12..c2a484282ef2 100644
--- a/drivers/gpu/drm/xe/xe_guc_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_types.h
@@ -51,6 +51,15 @@ struct xe_guc {
 			/** @seqno: suspend fences seqno */
 			u32 seqno;
 		} suspend;
+		/** @version: submission version */
+		struct {
+			/** @major: major version of GuC submission */
+			u32 major;
+			/** @minor: minor version of GuC submission */
+			u32 minor;
+			/** @patch: patch version of GuC submission */
+			u32 patch;
+		} version;
 	} submission_state;
 	/** @hwconfig: Hardware config state */
 	struct {
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index cd264cf50d30..ff94eec9cafe 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -184,6 +184,40 @@ static void uc_fw_fini(struct drm_device *drm, void *arg)
 	xe_uc_fw_change_status(uc_fw, XE_UC_FIRMWARE_SELECTED);
 }
 
+static void guc_read_css_info(struct xe_uc_fw *uc_fw, struct uc_css_header *css)
+{
+	struct xe_gt *gt = uc_fw_to_gt(uc_fw);
+	struct xe_guc *guc = &gt->uc.guc;
+
+	XE_BUG_ON(uc_fw->type != XE_UC_FW_TYPE_GUC);
+	XE_WARN_ON(uc_fw->major_ver_found < 70);
+
+	if (uc_fw->minor_ver_found >= 6) {
+		/* v70.6.0 adds CSS header support */
+		guc->submission_state.version.major =
+			FIELD_GET(CSS_SW_VERSION_UC_MAJOR,
+				  css->submission_version);
+		guc->submission_state.version.minor =
+			FIELD_GET(CSS_SW_VERSION_UC_MINOR,
+				  css->submission_version);
+		guc->submission_state.version.patch =
+			FIELD_GET(CSS_SW_VERSION_UC_PATCH,
+				  css->submission_version);
+	} else if (uc_fw->minor_ver_found >= 3) {
+		/* v70.3.0 introduced v1.1.0 */
+		guc->submission_state.version.major = 1;
+		guc->submission_state.version.minor = 1;
+		guc->submission_state.version.patch = 0;
+	} else {
+		/* v70.0.0 introduced v1.0.0 */
+		guc->submission_state.version.major = 1;
+		guc->submission_state.version.minor = 0;
+		guc->submission_state.version.patch = 0;
+	}
+
+	uc_fw->private_data_size = css->private_data_size;
+}
+
 int xe_uc_fw_init(struct xe_uc_fw *uc_fw)
 {
 	struct xe_device *xe = uc_fw_to_xe(uc_fw);
@@ -278,7 +312,7 @@ int xe_uc_fw_init(struct xe_uc_fw *uc_fw)
 	}
 
 	if (uc_fw->type == XE_UC_FW_TYPE_GUC)
-		uc_fw->private_data_size = css->private_data_size;
+		guc_read_css_info(uc_fw, css);
 
 	obj = xe_bo_create_from_data(xe, gt, fw->data, fw->size,
 				     ttm_bo_type_kernel,
@@ -403,4 +437,14 @@ void xe_uc_fw_print(struct xe_uc_fw *uc_fw, struct drm_printer *p)
 		   uc_fw->major_ver_found, uc_fw->minor_ver_found);
 	drm_printf(p, "\tuCode: %u bytes\n", uc_fw->ucode_size);
 	drm_printf(p, "\tRSA: %u bytes\n", uc_fw->rsa_size);
+
+	if (uc_fw->type == XE_UC_FW_TYPE_GUC) {
+		struct xe_gt *gt = uc_fw_to_gt(uc_fw);
+		struct xe_guc *guc = &gt->uc.guc;
+
+		drm_printf(p, "\tSubmit version: %u.%u.%u\n",
+			   guc->submission_state.version.major,
+			   guc->submission_state.version.minor,
+			   guc->submission_state.version.patch);
+	}
 }
diff --git a/drivers/gpu/drm/xe/xe_uc_fw_abi.h b/drivers/gpu/drm/xe/xe_uc_fw_abi.h
index dafd26cb0c41..fc7b1855ee90 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw_abi.h
+++ b/drivers/gpu/drm/xe/xe_uc_fw_abi.h
@@ -69,7 +69,11 @@ struct uc_css_header {
 #define CSS_SW_VERSION_UC_MAJOR		(0xFF << 16)
 #define CSS_SW_VERSION_UC_MINOR		(0xFF << 8)
 #define CSS_SW_VERSION_UC_PATCH		(0xFF << 0)
-	u32 reserved0[13];
+	union {
+		u32 submission_version; /* only applies to GuC */
+		u32 reserved2;
+	};
+	u32 reserved0[12];
 	union {
 		u32 private_data_size; /* only applies to GuC */
 		u32 reserved1;
-- 
2.38.1

[Intel-xe] [PATCH 31/37] drm/xe/guc: s/xe_guc_send_mmio/xe_guc_mmio_send

[Rodrigo Vivi]

From: Matthew Brost <matthew.brost@intel.com>

Now aligns with the xe_guc_ct_send naming.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Cc: Philippe Lecluse <philippe.lecluse@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_guc.c          | 6 +++---
 drivers/gpu/drm/xe/xe_guc.h          | 2 +-
 drivers/gpu/drm/xe/xe_guc_ct.c       | 2 +-
 drivers/gpu/drm/xe/xe_guc_hwconfig.c | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 34d7d20a2ce7..731b26cc49a9 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -599,7 +599,7 @@ int xe_guc_suspend(struct xe_guc *guc)
 		XE_GUC_ACTION_CLIENT_SOFT_RESET,
 	};
 
-	ret = xe_guc_send_mmio(guc, action, ARRAY_SIZE(action));
+	ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));
 	if (ret) {
 		drm_err(&guc_to_xe(guc)->drm,
 			"GuC suspend: CLIENT_SOFT_RESET fail: %d!\n", ret);
@@ -630,7 +630,7 @@ int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr)
 #define MEDIA_SOFT_SCRATCH(n)           _MMIO(0x190310 + (n) * 4)
 #define MEDIA_SOFT_SCRATCH_COUNT        4
 
-int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len)
+int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len)
 {
 	struct xe_device *xe = guc_to_xe(guc);
 	struct xe_gt *gt = guc_to_gt(guc);
@@ -747,7 +747,7 @@ static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val)
 	XE_BUG_ON(len == 1 && upper_32_bits(val));
 
 	/* Self config must go over MMIO */
-	ret = xe_guc_send_mmio(guc, request, ARRAY_SIZE(request));
+	ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request));
 
 	if (unlikely(ret < 0))
 		return ret;
diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
index 72b71d75566c..923efee90991 100644
--- a/drivers/gpu/drm/xe/xe_guc.h
+++ b/drivers/gpu/drm/xe/xe_guc.h
@@ -22,7 +22,7 @@ int xe_guc_enable_communication(struct xe_guc *guc);
 int xe_guc_suspend(struct xe_guc *guc);
 void xe_guc_notify(struct xe_guc *guc);
 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr);
-int xe_guc_send_mmio(struct xe_guc *guc, const u32 *request, u32 len);
+int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len);
 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val);
 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val);
 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir);
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 61a424c41779..f48eb01847ef 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -268,7 +268,7 @@ static int guc_ct_control_toggle(struct xe_guc_ct *ct, bool enable)
 			   enable ? GUC_CTB_CONTROL_ENABLE :
 			   GUC_CTB_CONTROL_DISABLE),
 	};
-	int ret = xe_guc_send_mmio(ct_to_guc(ct), request, ARRAY_SIZE(request));
+	int ret = xe_guc_mmio_send(ct_to_guc(ct), request, ARRAY_SIZE(request));
 
 	return ret > 0 ? -EPROTO : ret;
 }
diff --git a/drivers/gpu/drm/xe/xe_guc_hwconfig.c b/drivers/gpu/drm/xe/xe_guc_hwconfig.c
index 8dfd48f71a7c..57640d608787 100644
--- a/drivers/gpu/drm/xe/xe_guc_hwconfig.c
+++ b/drivers/gpu/drm/xe/xe_guc_hwconfig.c
@@ -33,7 +33,7 @@ static int send_get_hwconfig(struct xe_guc *guc, u32 ggtt_addr, u32 size)
 		size,
 	};
 
-	return xe_guc_send_mmio(guc, action, ARRAY_SIZE(action));
+	return xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));
 }
 
 static int guc_hwconfig_size(struct xe_guc *guc, u32 *size)
-- 
2.38.1

[Intel-xe] [PATCH 32/37] drm/xe/guc: Add support GuC MMIO send / recv

[Rodrigo Vivi]

From: Matthew Brost <matthew.brost@intel.com>

SRIOV has a use case of GuC MMIO send / recv, add a function for it.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Cc: Philippe Lecluse <philippe.lecluse@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_guc.c | 18 +++++++++++++++++-
 drivers/gpu/drm/xe/xe_guc.h |  2 ++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 731b26cc49a9..7f84d761283b 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -630,7 +630,8 @@ int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr)
 #define MEDIA_SOFT_SCRATCH(n)           _MMIO(0x190310 + (n) * 4)
 #define MEDIA_SOFT_SCRATCH_COUNT        4
 
-int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len)
+int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
+			  u32 len, u32 *response_buf)
 {
 	struct xe_device *xe = guc_to_xe(guc);
 	struct xe_gt *gt = guc_to_gt(guc);
@@ -640,6 +641,7 @@ int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len)
 	int ret;
 	int i;
 
+	BUILD_BUG_ON(GEN11_SOFT_SCRATCH_COUNT != MEDIA_SOFT_SCRATCH_COUNT);
 	XE_BUG_ON(guc->ct.enabled);
 	XE_BUG_ON(!len);
 	XE_BUG_ON(len > GEN11_SOFT_SCRATCH_COUNT);
@@ -723,10 +725,24 @@ int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len)
 		return -EPROTO;
 	}
 
+	/* Just copy entire possible message response */
+	if (response_buf) {
+		response_buf[0] = header;
+
+		for (i = 1; i < GEN11_SOFT_SCRATCH_COUNT; i++)
+			response_buf[i] =
+				xe_mmio_read32(gt, reply_reg + i * sizeof(u32));
+	}
+
 	/* Use data from the GuC response as our return value */
 	return FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header);
 }
 
+int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len)
+{
+	return xe_guc_mmio_send_recv(guc, request, len, NULL);
+}
+
 static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val)
 {
 	u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = {
diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
index 923efee90991..7be33458eef6 100644
--- a/drivers/gpu/drm/xe/xe_guc.h
+++ b/drivers/gpu/drm/xe/xe_guc.h
@@ -23,6 +23,8 @@ int xe_guc_suspend(struct xe_guc *guc);
 void xe_guc_notify(struct xe_guc *guc);
 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr);
 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len);
+int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, u32 len,
+			  u32 *response_buf);
 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val);
 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val);
 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir);
-- 
2.38.1

[Intel-xe] [PATCH 33/37] drm/xe: Make FBC check stolen at use time.

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

In case of xe, stolen is not initialised until much later, so just
assume it works, and check at runtime if required.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Philippe Lecluse <philippe.lecluse@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 2804db71d630..82bc21b09332 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1133,6 +1133,13 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 	if (!fbc)
 		return 0;
 
+#ifndef I915
+	if (!i915_gem_stolen_initialized(i915)) {
+		plane_state->no_fbc_reason = "stolen memory not initialised";
+		return 0;
+	}
+#endif
+
 	if (intel_vgpu_active(i915)) {
 		plane_state->no_fbc_reason = "VGPU active";
 		return 0;
@@ -1786,8 +1793,10 @@ void intel_fbc_init(struct drm_i915_private *i915)
 {
 	enum intel_fbc_id fbc_id;
 
+#ifdef I915
 	if (!i915_gem_stolen_initialized(i915))
 		RUNTIME_INFO(i915)->fbc_mask = 0;
+#endif
 
 	if (need_fbc_vtd_wa(i915))
 		RUNTIME_INFO(i915)->fbc_mask = 0;
-- 
2.38.1

[Intel-xe] [PATCH 34/37] drm/xe: Move xe_ttm_stolen_mgr_init back

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Philippe Lecluse <philippe.lecluse@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_device.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index c8b4c580bd98..14af3f58c75d 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -405,9 +405,6 @@ int xe_device_probe(struct xe_device *xe)
 			return err;
 	}
 
-	/* Harmless if stolen initialization fails */
-	xe_ttm_stolen_mgr_init(xe);
-
 	err = xe_device_init_display_noirq(xe);
 	if (err)
 		return err;
@@ -432,6 +429,9 @@ int xe_device_probe(struct xe_device *xe)
 			goto err_irq_shutdown;
 	}
 
+	/* Allocate and map stolen after potential VRAM resize */
+	xe_ttm_stolen_mgr_init(xe);
+
 	/*
 	 * Now that GT is initialized (TTM in particular),
 	 * we can try to init display, and inherit the initial fb.
-- 
2.38.1

[Intel-xe] [PATCH 35/37] drm/xe: Fix hidden gotcha regression with bo create

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

The bo_create ioctl relied on the internal ordering of memory regions to
be the same, make sure we don't allocate stolen instead of VRAM0.

Also remove a debug warning left in.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Philippe Lecluse <philippe.lecluse@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_bo.h             | 8 +++++---
 drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 1 -
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
index 8d8a3332dbc8..8c2cdbe51ab5 100644
--- a/drivers/gpu/drm/xe/xe_bo.h
+++ b/drivers/gpu/drm/xe/xe_bo.h
@@ -13,10 +13,12 @@
 #define XE_DEFAULT_GTT_SIZE_MB          3072ULL /* 3GB by default */
 
 #define XE_BO_CREATE_USER_BIT		BIT(0)
+/* The bits below need to be contiguous, or things break */
 #define XE_BO_CREATE_SYSTEM_BIT		BIT(1)
-#define XE_BO_CREATE_STOLEN_BIT		BIT(2)
-#define XE_BO_CREATE_VRAM0_BIT		BIT(3)
-#define XE_BO_CREATE_VRAM1_BIT		BIT(4)
+#define XE_BO_CREATE_VRAM0_BIT		BIT(2)
+#define XE_BO_CREATE_VRAM1_BIT		BIT(3)
+/* -- */
+#define XE_BO_CREATE_STOLEN_BIT		BIT(4)
 #define XE_BO_CREATE_VRAM_IF_DGFX(gt) \
 	(IS_DGFX(gt_to_xe(gt)) ? XE_BO_CREATE_VRAM0_BIT << gt->info.vram_id : \
 	 XE_BO_CREATE_SYSTEM_BIT)
diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
index 21ca7f79e63b..b4e9c88644e4 100644
--- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
+++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
@@ -184,7 +184,6 @@ static int __xe_ttm_stolen_io_mem_reserve_bar2(struct xe_device *xe,
 	mem->bus.offset = cur.start;
 
 	drm_WARN_ON(&xe->drm, !(mem->placement & TTM_PL_FLAG_CONTIGUOUS));
-	WARN_ON_ONCE(1);
 
 	if (mem->placement & TTM_PL_FLAG_CONTIGUOUS && mgr->mapping)
 		mem->bus.addr = (u8 *)mgr->mapping + mem->bus.offset;
-- 
2.38.1

[Intel-xe] [PATCH 36/37] drm/xe: Fix xe_mmio_wait32 timeouts.

[Rodrigo Vivi]

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

The call uses us, not ms now. Fix this to make display working again.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/display/intel_de.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/intel_de.h b/drivers/gpu/drm/xe/display/intel_de.h
index 678b4247464a..f0c1d16fa6f8 100644
--- a/drivers/gpu/drm/xe/display/intel_de.h
+++ b/drivers/gpu/drm/xe/display/intel_de.h
@@ -41,7 +41,7 @@ static inline int
 intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
 			   u32 mask, u32 value, unsigned int timeout)
 {
-	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout, NULL,
+	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
 			      false);
 }
 
@@ -49,7 +49,7 @@ static inline int
 intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,
 			      u32 mask, u32 value, unsigned int timeout)
 {
-	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout, NULL,
+	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
 			      false);
 }
 
-- 
2.38.1

[Intel-xe] [PATCH 37/37] drm/xe: enforce GSMBASE for DG1 instead of BAR2

[Rodrigo Vivi]

From: Philippe Lecluse <philippe.lecluse@intel.com>

v2: move to logic in probed vram_size
    rename flat_ccs_base to more generic usable_size

Signed-off-by: Philippe Lecluse <philippe.lecluse@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_mmio.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 4d679027fc98..b3c1a39ef79d 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -153,7 +153,7 @@ static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)
 	return true;
 }
 
-int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *flat_ccs_base)
+int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_size)
 {
 	struct xe_gt *gt = xe_device_get_gt(xe, 0);
 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
@@ -162,8 +162,12 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *flat_ccs_
 
 	if (!xe->info.has_flat_ccs)  {
 		*vram_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
-		if (flat_ccs_base)
-			*flat_ccs_base = *vram_size;
+		if (usable_size) {
+			if (xe->info.platform == XE_DG1)
+				*usable_size = xe_mmio_read64(gt, GEN12_GSMBASE.reg);
+			else
+				*usable_size = *vram_size;
+		}
 		return 0;
 	}
 
@@ -173,15 +177,13 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *flat_ccs_
 
 	reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE0_ADDR_RANGE);
 	*vram_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
-	if (flat_ccs_base) {
+	if (usable_size) {
 		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
-		*flat_ccs_base = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;
+		*usable_size = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;
+		drm_info(&xe->drm, "lmem_size: 0x%llx usable_size: 0x%llx\n",
+			 *vram_size, *usable_size);
 	}
 
-	if (flat_ccs_base)
-		drm_info(&xe->drm, "lmem_size: 0x%llx flat_ccs_base: 0x%llx\n",
-			 *vram_size, *flat_ccs_base);
-
 	return xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
 }
 
@@ -193,7 +195,7 @@ int xe_mmio_probe_vram(struct xe_device *xe)
 	u64 lmem_size;
 	u64 original_size;
 	u64 current_size;
-	u64 flat_ccs_base;
+	u64 usable_size;
 	int resize_result, err;
 
 	if (!IS_DGFX(xe)) {
@@ -215,11 +217,9 @@ int xe_mmio_probe_vram(struct xe_device *xe)
 	}
 
 	gt = xe_device_get_gt(xe, 0);
-	lmem_size = xe_mmio_read64(gt, GEN12_GSMBASE.reg);
-
 	original_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
 
-	err = xe_mmio_total_vram_size(xe, &lmem_size, &flat_ccs_base);
+	err = xe_mmio_total_vram_size(xe, &lmem_size, &usable_size);
 	if (err)
 		return err;
 
@@ -247,7 +247,7 @@ int xe_mmio_probe_vram(struct xe_device *xe)
 	xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.size);
 #endif
 
-	xe->mem.vram.size = min_t(u64, xe->mem.vram.size, flat_ccs_base);
+	xe->mem.vram.size = min_t(u64, xe->mem.vram.size, usable_size);
 
 	drm_info(&xe->drm, "TOTAL VRAM: %pa, %pa\n", &xe->mem.vram.io_start, &xe->mem.vram.size);
 
-- 
2.38.1

Re: [Intel-xe] [PATCH 12/37] drm/xe/migrate: Add kerneldoc for the migrate subsystem

[Mauro Carvalho Chehab]

Em Thu, 12 Jan 2023 17:25:13 -0500
Rodrigo Vivi <rodrigo.vivi@intel.com> escreveu:

> From: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> 
> Add kerneldoc for structs and external functions.
> 
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>

LGTM.
Reviewed-by: Mauro Carvalho Chehab <mchehab@kernel.org>

> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_migrate.c | 108 +++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/xe/xe_migrate.h |  16 ++++-
>  2 files changed, 120 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 01177ee31d43..7b9f3de11b47 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -27,16 +27,37 @@
>  
>  #include "../i915/gt/intel_gpu_commands.h"
>  
> +/**
> + * struct xe_migrate - migrate context.
> + */
>  struct xe_migrate {
> +	/** @eng: Default engine used for migration */
>  	struct xe_engine *eng;
> +	/** @gt: Backpointer to the gt this struct xe_migrate belongs to. */
>  	struct xe_gt *gt;
> +	/** @job_mutex: Timeline mutex for @eng. */
>  	struct mutex job_mutex;
> +	/** @pt_bo: Page-table buffer object. */
>  	struct xe_bo *pt_bo;
> +	/**
> +	 * @cleared_bo: Zeroed out bo used as a source for CCS metadata clears
> +	 */
>  	struct xe_bo *cleared_bo;
> +	/** @batch_base_ofs: VM offset of the migration batch buffer */
>  	u64 batch_base_ofs;
> +	/** @usm_batch_base_ofs: VM offset of the usm batch buffer */
>  	u64 usm_batch_base_ofs;
> +	/** @cleared_vram_ofs: VM offset of @cleared_bo. */
>  	u64 cleared_vram_ofs;
> +	/**
> +	 * @fence: dma-fence representing the last migration job batch.
> +	 * Protected by @job_mutex.
> +	 */
>  	struct dma_fence *fence;
> +	/**
> +	 * @vm_update_sa: For integrated, used to suballocate page-tables
> +	 * out of the pt_bo.
> +	 */
>  	struct drm_suballoc_manager vm_update_sa;
>  };
>  
> @@ -45,6 +66,15 @@ struct xe_migrate {
>  #define NUM_PT_SLOTS 32
>  #define NUM_PT_PER_BLIT (MAX_PREEMPTDISABLE_TRANSFER / SZ_2M)
>  
> +/**
> + * xe_gt_migrate_engine() - Get this gt's migrate engine.
> + * @gt: The gt.
> + *
> + * Returns the default migrate engine of this gt.
> + * TODO: Perhaps this function is slightly misplaced, and even unneeded?
> + *
> + * Return: The default migrate engine
> + */
>  struct xe_engine *xe_gt_migrate_engine(struct xe_gt *gt)
>  {
>  	return gt->migrate->eng;
> @@ -271,6 +301,12 @@ static int xe_migrate_prepare_vm(struct xe_gt *gt, struct xe_migrate *m,
>  	return 0;
>  }
>  
> +/**
> + * xe_migrate_init() - Initialize a migrate context
> + * @gt: Back-pointer to the gt we're initializing for.
> + *
> + * Return: Pointer to a migrate context on success. Error pointer on error.
> + */
>  struct xe_migrate *xe_migrate_init(struct xe_gt *gt)
>  {
>  	struct xe_device *xe = gt_to_xe(gt);
> @@ -540,6 +576,24 @@ static u32 xe_migrate_ccs_copy(struct xe_migrate *m,
>  	return flush_flags;
>  }
>  
> +/**
> + * xe_migrate_copy() - Copy content of TTM resources.
> + * @m: The migration context.
> + * @bo: The buffer object @src is currently bound to.
> + * @src: The source TTM resource.
> + * @dst: The dst TTM resource.
> + *
> + * Copies the contents of @src to @dst: On flat CCS devices,
> + * the CCS metadata is copied as well if needed, or if not present,
> + * the CCS metadata of @dst is cleared for security reasons.
> + * It's currently not possible to copy between two system resources,
> + * since that would require two TTM page-vectors.
> + * TODO: Eliminate the @bo argument and supply two TTM page-vectors.
> + *
> + * Return: Pointer to a dma_fence representing the last copy batch, or
> + * an error pointer on failure. If there is a failure, any copy operation
> + * started by the function call has been synced.
> + */
>  struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
>  				  struct xe_bo *bo,
>  				  struct ttm_resource *src,
> @@ -683,7 +737,7 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m,
>  		xe_bb_free(bb, NULL);
>  
>  err_sync:
> -		/* Sync partial copy if any. */
> +		/* Sync partial copy if any. FIXME: under job_mutex? */
>  		if (fence) {
>  			dma_fence_wait(fence, false);
>  			dma_fence_put(fence);
> @@ -733,6 +787,21 @@ static int emit_clear(struct xe_gt *gt, struct xe_bb *bb, u64 src_ofs,
>  	return 0;
>  }
>  
> +/**
> + * xe_migrate_clear() - Copy content of TTM resources.
> + * @m: The migration context.
> + * @bo: The buffer object @dst is currently bound to.
> + * @dst: The dst TTM resource to be cleared.
> + * @value: Clear value.
> + *
> + * Clear the contents of @dst. On flat CCS devices,
> + * the CCS metadata is cleared to zero as well on VRAM destionations.
> + * TODO: Eliminate the @bo argument.
> + *
> + * Return: Pointer to a dma_fence representing the last clear batch, or
> + * an error pointer on failure. If there is a failure, any clear operation
> + * started by the function call has been synced.
> + */
>  struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
>  				   struct xe_bo *bo,
>  				   struct ttm_resource *dst,
> @@ -836,7 +905,7 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
>  		mutex_unlock(&m->job_mutex);
>  		xe_bb_free(bb, NULL);
>  err_sync:
> -		/* Sync partial copies if any. */
> +		/* Sync partial copies if any. FIXME: job_mutex? */
>  		if (fence) {
>  			dma_fence_wait(m->fence, false);
>  			dma_fence_put(fence);
> @@ -974,6 +1043,33 @@ static bool engine_is_idle(struct xe_engine *e)
>  		xe_lrc_seqno(&e->lrc[0]) == e->lrc[0].fence_ctx.next_seqno;
>  }
>  
> +/**
> + * xe_migrate_update_pgtables() - Pipelined page-table update
> + * @m: The migrate context.
> + * @vm: The vm we'll be updating.
> + * @bo: The bo whose dma-resv we will await before updating, or NULL if userptr.
> + * @eng: The engine to be used for the update or NULL if the default
> + * migration engine is to be used.
> + * @updates: An array of update descriptors.
> + * @num_updates: Number of descriptors in @updates.
> + * @syncs: Array of xe_sync_entry to await before updating. Note that waits
> + * will block the engine timeline.
> + * @num_syncs: Number of entries in @syncs.
> + * @pt_update: Pointer to a struct xe_migrate_pt_update, which contains
> + * pointers to callback functions and, if subclassed, private arguments to
> + * those.
> + *
> + * Perform a pipelined page-table update. The update descriptors are typically
> + * built under the same lock critical section as a call to this function. If
> + * using the default engine for the updates, they will be performed in the
> + * order they grab the job_mutex. If different engines are used, external
> + * synchronization is needed for overlapping updates to maintain page-table
> + * consistency. Note that the meaing of "overlapping" is that the updates
> + * touch the same page-table, which might be a higher-level page-directory.
> + * If no pipelining is needed, then updates may be performed by the cpu.
> + *
> + * Return: A dma_fence that, when signaled, indicates the update completion.
> + */
>  struct dma_fence *
>  xe_migrate_update_pgtables(struct xe_migrate *m,
>  			   struct xe_vm *vm,
> @@ -1157,6 +1253,14 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
>  	return ERR_PTR(err);
>  }
>  
> +/**
> + * xe_migrate_wait() - Complete all operations using the xe_migrate context
> + * @m: Migrate context to wait for.
> + *
> + * Waits until the GPU no longer uses the migrate context's default engine
> + * or its page-table objects. FIXME: What about separate page-table update
> + * engines?
> + */
>  void xe_migrate_wait(struct xe_migrate *m)
>  {
>  	if (m->fence)
> diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
> index 267057a3847f..b2d55283252f 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.h
> +++ b/drivers/gpu/drm/xe/xe_migrate.h
> @@ -23,9 +23,13 @@ struct xe_vm;
>  struct xe_vm_pgtable_update;
>  struct xe_vma;
>  
> +/**
> + * struct xe_migrate_pt_update_ops - Callbacks for the
> + * xe_migrate_update_pgtables() function.
> + */
>  struct xe_migrate_pt_update_ops {
>  	/**
> -	 * populate() - Populate a command buffer or page-table with ptes.
> +	 * @populate: Populate a command buffer or page-table with ptes.
>  	 * @pt_update: Embeddable callback argument.
>  	 * @gt: The gt for the current operation.
>  	 * @map: struct iosys_map into the memory to be populated.
> @@ -44,7 +48,7 @@ struct xe_migrate_pt_update_ops {
>  			 const struct xe_vm_pgtable_update *update);
>  
>  	/**
> -	 * pre_commit(): Callback to be called just before arming the
> +	 * @pre_commit: Callback to be called just before arming the
>  	 * sched_job.
>  	 * @pt_update: Pointer to embeddable callback argument.
>  	 *
> @@ -53,8 +57,16 @@ struct xe_migrate_pt_update_ops {
>  	int (*pre_commit)(struct xe_migrate_pt_update *pt_update);
>  };
>  
> +/**
> + * struct xe_migrate_pt_update - Argument to the
> + * struct xe_migrate_pt_update_ops callbacks.
> + *
> + * Intended to be subclassed to support additional arguments if necessary.
> + */
>  struct xe_migrate_pt_update {
> +	/** @ops: Pointer to the struct xe_migrate_pt_update_ops callbacks */
>  	const struct xe_migrate_pt_update_ops *ops;
> +	/** @vma: The vma we're updating the pagetable for. */
>  	struct xe_vma *vma;
>  };
>  



Thanks,
Mauro

Re: [Intel-xe] [PATCH 25/37] drm/xe: Introduce force_probe parameter.

[Mauro Carvalho Chehab]

Em Thu, 12 Jan 2023 17:25:26 -0500
Rodrigo Vivi <rodrigo.vivi@intel.com> escreveu:

> Following the i915 ones and its rules.
> 
> So, with this in place, developers can select which driver should
> take control of which device.
> 
> This is specially useful on hybrid device where developer might
> want to use i915 driving everything including display on your ADL-P
> while working with xe
> on the DG2:
> 
> i915.force_probe=!5690,46a6 xe.force_probe=5690,!46a6
> 
> or vice versa:
> 
> i915.force_probe=5690,!46a6 xe.force_probe=!5690,46a6
> 
> This commit also ensures that all current platforms are marked as
> require_force_probe at a top level, since this will likely remain
> forever in upstream and only be removed after the official switch
> on a later platform.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>

LGTM.
Reviewed-by: Mauro Carvalho Chehab <mchehab@kernel.org>

> ---
>  drivers/gpu/drm/xe/Kconfig  | 28 +++++++++++++
>  drivers/gpu/drm/xe/xe_pci.c | 79 +++++++++++++++++++++++++++++++++++--
>  2 files changed, 104 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig
> index 3815e25d0eec..22e47918bfcf 100644
> --- a/drivers/gpu/drm/xe/Kconfig
> +++ b/drivers/gpu/drm/xe/Kconfig
> @@ -40,6 +40,34 @@ config DRM_XE
>  
>  	  If "M" is selected, the module will be called xe.
>  
> +config DRM_XE_FORCE_PROBE
> +	string "Force probe xe for selected Intel hardware IDs"
> +	depends on DRM_XE
> +	help
> +	  This is the default value for the xe.force_probe module
> +	  parameter. Using the module parameter overrides this option.
> +
> +	  Force probe the xe for Intel graphics devices that are
> +	  recognized but not properly supported by this kernel version. It is
> +	  recommended to upgrade to a kernel version with proper support as soon
> +	  as it is available.
> +
> +	  It can also be used to block the probe of recognized and fully
> +	  supported devices.
> +
> +	  Use "" to disable force probe. If in doubt, use this.
> +
> +	  Use "<pci-id>[,<pci-id>,...]" to force probe the xe for listed
> +	  devices. For example, "4500" or "4500,4571".
> +
> +	  Use "*" to force probe the driver for all known devices.
> +
> +	  Use "!" right before the ID to block the probe of the device. For
> +	  example, "4500,!4571" forces the probe of 4500 and blocks the probe of
> +	  4571.
> +
> +	  Use "!*" to block the probe of the driver for all known devices.
> +
>  menu "drm/Xe Debugging"
>  depends on DRM_XE
>  depends on EXPERT
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 91a6fba95ac7..bcf6fd610881 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -22,6 +22,12 @@
>  
>  #include "../i915/i915_reg.h"
>  
> +static char *xe_param_force_probe = CONFIG_DRM_XE_FORCE_PROBE;
> +module_param_named_unsafe(force_probe, xe_param_force_probe, charp, 0400);
> +MODULE_PARM_DESC(force_probe,
> +		 "Force probe options for specified devices. "
> +		 "See CONFIG_DRM_XE_FORCE_PROBE for details.");
> +
>  #define DEV_INFO_FOR_EACH_FLAG(func) \
>  	func(require_force_probe); \
>  	func(is_dgfx); \
> @@ -148,6 +154,7 @@ struct xe_device_desc {
>  
>  /* Keep in gen based order, and chronological order within a gen */
>  #define GEN12_FEATURES \
> +	.require_force_probe = true, \
>  	.graphics_ver = 12, \
>  	.media_ver = 12, \
>  	.dma_mask_size = 39, \
> @@ -196,7 +203,6 @@ static const struct xe_device_desc dg1_desc = {
>  	DGFX_FEATURES,
>  	.graphics_rel = 10,
>  	PLATFORM(XE_DG1),
> -	.require_force_probe = true,
>  	.platform_engine_mask =
>  		BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
>  		BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_VCS0) |
> @@ -204,6 +210,7 @@ static const struct xe_device_desc dg1_desc = {
>  };
>  
>  #define XE_HP_FEATURES \
> +	.require_force_probe = true, \
>  	.graphics_ver = 12, \
>  	.graphics_rel = 50, \
>  	.has_flat_ccs = true, \
> @@ -288,7 +295,6 @@ static const struct xe_device_desc pvc_desc = {
>  	.has_flat_ccs = 0,
>  	.media_rel = 60,
>  	.platform_engine_mask = PVC_ENGINES,
> -	.require_force_probe = true,
>  	.vram_flags = XE_VRAM_FLAGS_NEED64K,
>  	.dma_mask_size = 52,
>  	.max_tiles = 2,
> @@ -319,6 +325,7 @@ static const struct xe_device_desc mtl_desc = {
>  	 * Real graphics IP version will be obtained from hardware GMD_ID
>  	 * register.  Value provided here is just for sanity checking.
>  	 */
> +	.require_force_probe = true,
>  	.graphics_ver = 12,
>  	.graphics_rel = 70,
>  	.dma_mask_size = 46,
> @@ -328,7 +335,6 @@ static const struct xe_device_desc mtl_desc = {
>  	PLATFORM(XE_METEORLAKE),
>  	.extra_gts = xelpmp_gts,
>  	.platform_engine_mask = MTL_MAIN_ENGINES,
> -	.require_force_probe = 1,
>  	GEN13_DISPLAY,
>  	.display.ver = 14,
>  	.display.has_cdclk_crawl = 1,
> @@ -363,6 +369,55 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
>  
>  #undef INTEL_VGA_DEVICE
>  
> +/* is device_id present in comma separated list of ids */
> +static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
> +{
> +	char *s, *p, *tok;
> +	bool ret;
> +
> +	if (!devices || !*devices)
> +		return false;
> +
> +	/* match everything */
> +	if (negative && strcmp(devices, "!*") == 0)
> +		return true;
> +	if (!negative && strcmp(devices, "*") == 0)
> +		return true;
> +
> +	s = kstrdup(devices, GFP_KERNEL);
> +	if (!s)
> +		return false;
> +
> +	for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
> +		u16 val;
> +
> +		if (negative && tok[0] == '!')
> +			tok++;
> +		else if ((negative && tok[0] != '!') ||
> +			 (!negative && tok[0] == '!'))
> +			continue;
> +
> +		if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
> +			ret = true;
> +			break;
> +		}
> +	}
> +
> +	kfree(s);
> +
> +	return ret;
> +}
> +
> +static bool id_forced(u16 device_id)
> +{
> +	return device_id_in_list(device_id, xe_param_force_probe, false);
> +}
> +
> +static bool id_blocked(u16 device_id)
> +{
> +	return device_id_in_list(device_id, xe_param_force_probe, true);
> +}
> +
>  static const struct xe_subplatform_desc *
>  subplatform_get(const struct xe_device *xe, const struct xe_device_desc *desc)
>  {
> @@ -398,6 +453,24 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>  	u8 id;
>  	int err;
>  
> +	if (desc->require_force_probe && !id_forced(pdev->device)) {
> +		dev_info(&pdev->dev,
> +			 "Your graphics device %04x is not officially supported\n"
> +			 "by xe driver in this kernel version. To force Xe probe,\n"
> +			 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n"
> +			 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n"
> +			 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n",
> +			 pdev->device, pdev->device, pdev->device,
> +			 pdev->device, pdev->device);
> +		return -ENODEV;
> +	}
> +
> +	if (id_blocked(pdev->device)) {
> +		dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n",
> +			 pdev->vendor, pdev->device);
> +		return -ENODEV;
> +	}
> +
>  #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>  	/* Detect if we need to wait for other drivers early on */
>  	if (intel_modeset_probe_defer(pdev))



Thanks,
Mauro

Re: [Intel-xe] [PATCH 24/37] drm/i915: Expand force_probe to block probe of devices as well.

[Mauro Carvalho Chehab]

Em Thu, 12 Jan 2023 17:25:25 -0500
Rodrigo Vivi <rodrigo.vivi@intel.com> escreveu:

> There are new cases where we want to block i915 probe, such
> as when experimenting or developing the new Xe driver.
> 
> But also, with the new hybrid cards, users or developers might
> want to use i915 only on integrated and fully block the probe
> of the i915 for the discrete. Or vice versa.
> 
> There are even older development and validation reasons,
> like when you use some distro where the modprobe.blacklist is
> not present.
> 
> But in any case, let's introduce a more granular control, but without
> introducing yet another parameter, but using the existent force_probe
> one.
> 
> Just by adding a ! in the begin of the id in the force_probe, like
> in this case where we would block the probe for Alder Lake:
> 
> $ insmod i915.ko force_probe='!46a6'
> 
> v2: Take care of '*' and  '!*' cases as pointed out by
>     Gustavo and Jani.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Acked-by: Gustavo Sousa <gustavo.sousa@intel.com>

LGTM.

Reviewed-by: Mauro Carvalho Chehab <mchehab@kernel.org>

> Link: https://patchwork.freedesktop.org/patch/msgid/20230103194701.1492984-1-rodrigo.vivi@intel.com
> ---
>  drivers/gpu/drm/i915/Kconfig       | 15 +++++++++++---
>  drivers/gpu/drm/i915/i915_params.c |  2 +-
>  drivers/gpu/drm/i915/i915_pci.c    | 33 +++++++++++++++++++++++++-----
>  3 files changed, 41 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> index 3efce05d7b57..8eb3e60aeec9 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -54,24 +54,33 @@ config DRM_I915
>  	  If "M" is selected, the module will be called i915.
>  
>  config DRM_I915_FORCE_PROBE
> -	string "Force probe driver for selected new Intel hardware"
> +	string "Force probe i915 for selected Intel hardware IDs"
>  	depends on DRM_I915
>  	help
>  	  This is the default value for the i915.force_probe module
>  	  parameter. Using the module parameter overrides this option.
>  
> -	  Force probe the driver for new Intel graphics devices that are
> +	  Force probe the i915 for Intel graphics devices that are
>  	  recognized but not properly supported by this kernel version. It is
>  	  recommended to upgrade to a kernel version with proper support as soon
>  	  as it is available.
>  
> +	  It can also be used to block the probe of recognized and fully
> +	  supported devices.
> +
>  	  Use "" to disable force probe. If in doubt, use this.
>  
> -	  Use "<pci-id>[,<pci-id>,...]" to force probe the driver for listed
> +	  Use "<pci-id>[,<pci-id>,...]" to force probe the i915 for listed
>  	  devices. For example, "4500" or "4500,4571".
>  
>  	  Use "*" to force probe the driver for all known devices.
>  
> +	  Use "!" right before the ID to block the probe of the device. For
> +	  example, "4500,!4571" forces the probe of 4500 and blocks the probe of
> +	  4571.
> +
> +	  Use "!*" to block the probe of the driver for all known devices.
> +
>  config DRM_I915_CAPTURE_ERROR
>  	bool "Enable capturing GPU state following a hang"
>  	depends on DRM_I915
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 61578f2860cd..d634bd3f641a 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -122,7 +122,7 @@ i915_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400,
>  	"Default: 0");
>  
>  i915_param_named_unsafe(force_probe, charp, 0400,
> -	"Force probe the driver for specified devices. "
> +	"Force probe options for specified supported devices. "
>  	"See CONFIG_DRM_I915_FORCE_PROBE for details.");
>  
>  i915_param_named_unsafe(disable_power_well, int, 0400,
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 668e9da52584..bc6fc268739d 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1253,7 +1253,7 @@ static void i915_pci_remove(struct pci_dev *pdev)
>  }
>  
>  /* is device_id present in comma separated list of ids */
> -static bool force_probe(u16 device_id, const char *devices)
> +static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
>  {
>  	char *s, *p, *tok;
>  	bool ret;
> @@ -1262,7 +1262,9 @@ static bool force_probe(u16 device_id, const char *devices)
>  		return false;
>  
>  	/* match everything */
> -	if (strcmp(devices, "*") == 0)
> +	if (negative && strcmp(devices, "!*") == 0)
> +		return true;
> +	if (!negative && strcmp(devices, "*") == 0)
>  		return true;
>  
>  	s = kstrdup(devices, GFP_KERNEL);
> @@ -1272,6 +1274,12 @@ static bool force_probe(u16 device_id, const char *devices)
>  	for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
>  		u16 val;
>  
> +		if (negative && tok[0] == '!')
> +			tok++;
> +		else if ((negative && tok[0] != '!') ||
> +			 (!negative && tok[0] == '!'))
> +			continue;
> +
>  		if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
>  			ret = true;
>  			break;
> @@ -1283,6 +1291,16 @@ static bool force_probe(u16 device_id, const char *devices)
>  	return ret;
>  }
>  
> +static bool id_forced(u16 device_id)
> +{
> +	return device_id_in_list(device_id, i915_modparams.force_probe, false);
> +}
> +
> +static bool id_blocked(u16 device_id)
> +{
> +	return device_id_in_list(device_id, i915_modparams.force_probe, true);
> +}
> +
>  bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
>  {
>  	if (!pci_resource_flags(pdev, bar))
> @@ -1308,10 +1326,9 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>  		(struct intel_device_info *) ent->driver_data;
>  	int err;
>  
> -	if (intel_info->require_force_probe &&
> -	    !force_probe(pdev->device, i915_modparams.force_probe)) {
> +	if (intel_info->require_force_probe && !id_forced(pdev->device)) {
>  		dev_info(&pdev->dev,
> -			 "Your graphics device %04x is not properly supported by the driver in this\n"
> +			 "Your graphics device %04x is not properly supported by i915 in this\n"
>  			 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
>  			 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
>  			 "or (recommended) check for kernel updates.\n",
> @@ -1319,6 +1336,12 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>  		return -ENODEV;
>  	}
>  
> +	if (id_blocked(pdev->device)) {
> +		dev_info(&pdev->dev, "I915 probe blocked for Device ID %04x.\n",
> +			 pdev->device);
> +		return -ENODEV;
> +	}
> +
>  	/* Only bind to function 0 of the device. Early generations
>  	 * used function 1 as a placeholder for multi-head. This causes
>  	 * us confusion instead, especially on the systems where both



Thanks,
Mauro

Re: [Intel-xe] [PATCH 17/37] drm/xe: Allow fbdev to allocate stolen memory

[Rodrigo Vivi]

On Thu, Jan 12, 2023 at 05:25:18PM -0500, Rodrigo Vivi wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Hi Maarten, could you please reply here with a commit msg for this patch?
I will add that on the next round or while merging it.

> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbdev.c | 55 ++++++++++++----------
>  1 file changed, 31 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
> index 176e0e44a268..52dc33c5f6d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
> @@ -45,6 +45,7 @@
>  #include "gem/i915_gem_lmem.h"
>  #else
>  #include "xe_gt.h"
> +#include "xe_ttm_stolen_mgr.h"
>  #endif
>  
>  #include "i915_drv.h"
> @@ -171,8 +172,8 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
>  
>  	size = mode_cmd.pitches[0] * mode_cmd.height;
>  	size = PAGE_ALIGN(size);
> -#ifdef I915
>  	obj = ERR_PTR(-ENODEV);
> +#ifdef I915
>  	if (HAS_LMEM(dev_priv)) {
>  		obj = i915_gem_object_create_lmem(dev_priv, size,
>  						  I915_BO_ALLOC_CONTIGUOUS);
> @@ -188,11 +189,22 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
>  			obj = i915_gem_object_create_shmem(dev_priv, size);
>  	}
>  #else
> -	/* XXX: Care about stolen? */
> -	obj = xe_bo_create_pin_map(dev_priv, to_gt(dev_priv), NULL, size,
> -				   ttm_bo_type_kernel,
> -				   XE_BO_CREATE_VRAM_IF_DGFX(to_gt(dev_priv)) |
> -				   XE_BO_CREATE_PINNED_BIT | XE_BO_SCANOUT_BIT);
> +	if (!IS_DGFX(dev_priv)) {
> +		obj = xe_bo_create_pin_map(dev_priv, to_gt(dev_priv), NULL, size,
> +					   ttm_bo_type_kernel, XE_BO_SCANOUT_BIT |
> +					   XE_BO_CREATE_STOLEN_BIT |
> +					   XE_BO_CREATE_PINNED_BIT);
> +		if (!IS_ERR(obj))
> +			drm_info(&dev_priv->drm, "Allocated fbdev into stolen\n");
> +		else
> +			drm_info(&dev_priv->drm, "Allocated fbdev into stolen failed: %li\n", PTR_ERR(obj));
> +	}
> +	if (IS_ERR(obj)) {
> +		obj = xe_bo_create_pin_map(dev_priv, to_gt(dev_priv), NULL, size,
> +					  ttm_bo_type_kernel, XE_BO_SCANOUT_BIT |
> +					  XE_BO_CREATE_VRAM_IF_DGFX(to_gt(dev_priv)) |
> +					  XE_BO_CREATE_PINNED_BIT);
> +	}
>  #endif
>  
>  	if (IS_ERR(obj)) {
> @@ -317,33 +329,28 @@ static int intelfb_create(struct drm_fb_helper *helper,
>  		info->fix.smem_len = vma->size;
>  	}
>  	vaddr = i915_vma_pin_iomap(vma);
> -
>  #else
> -	/* XXX: Could be pure fiction.. */
> -	if (obj->flags & XE_BO_CREATE_VRAM0_BIT) {
> -		struct xe_gt *gt = to_gt(dev_priv);
> +	info->apertures->ranges[0].base = pci_resource_start(pdev, 2);
> +	info->apertures->ranges[0].size = pci_resource_len(pdev, 2);
> +	if (!(obj->flags & XE_BO_CREATE_SYSTEM_BIT)) {
>  		bool lmem;
>  
> -		info->apertures->ranges[0].base = gt->mem.vram.io_start;
> -		info->apertures->ranges[0].size = gt->mem.vram.size;
> +		if (obj->flags & XE_BO_CREATE_STOLEN_BIT)
> +			info->fix.smem_start = xe_ttm_stolen_io_offset(obj, 0);
> +		else
> +			info->fix.smem_start =
> +				pci_resource_start(pdev, 2) +
> +				xe_bo_addr(obj, 0, GEN8_PAGE_SIZE, &lmem);
>  
> -		info->fix.smem_start =
> -			(unsigned long)(gt->mem.vram.io_start + xe_bo_addr(obj, 0, 4096, &lmem));
>  		info->fix.smem_len = obj->ttm.base.size;
> -
>  	} else {
> -		struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> -
> -		info->apertures->ranges[0].base = pci_resource_start(pdev, 2);
> -		info->apertures->ranges[0].size =
> -			pci_resource_end(pdev, 2) - pci_resource_start(pdev, 2);
> -
> -		info->fix.smem_start = info->apertures->ranges[0].base + xe_bo_ggtt_addr(obj);
> +		/* XXX: Pure fiction, as the BO may not be physically accessible.. */
> +		info->fix.smem_start = 0;
>  		info->fix.smem_len = obj->ttm.base.size;
>  	}
>  
> -	/* TODO: ttm_bo_kmap? */
> -	vaddr = obj->vmap.vaddr;
> +	XE_WARN_ON(iosys_map_is_null(&obj->vmap));
> +	vaddr = obj->vmap.vaddr_iomem;
>  #endif
>  
>  	if (IS_ERR(vaddr)) {
> -- 
> 2.38.1
> 

Re: [Intel-xe] [PATCH 18/37] drm/xe: Implement initial hw readout for framebuffer

[Rodrigo Vivi]

On Thu, Jan 12, 2023 at 05:25:19PM -0500, Rodrigo Vivi wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

commit msg needed on this one as well.

> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fb.c       |   9 +
>  drivers/gpu/drm/i915/display/intel_fbdev.c    |  11 +-
>  drivers/gpu/drm/xe/display/xe_plane_initial.c | 224 ++++++------------
>  3 files changed, 89 insertions(+), 155 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index e0a8d9e9df9a..cf047353fd84 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -1847,6 +1847,15 @@ static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
>  #ifdef I915
>  	if (intel_fb_uses_dpt(fb))
>  		intel_dpt_destroy(intel_fb->dpt_vm);
> +#else
> +	if (intel_fb_obj(fb)->flags & XE_BO_CREATE_PINNED_BIT) {
> +		struct xe_bo *bo = intel_fb_obj(fb);
> +
> +		/* Unpin our kernel fb first */
> +		xe_bo_lock_no_vm(bo, NULL);
> +		xe_bo_unpin(bo);
> +		xe_bo_unlock_no_vm(bo);
> +	}
>  #endif
>  
>  	drm_gem_object_put(fb->obj[0]);
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
> index 52dc33c5f6d8..d1e5b730433d 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
> @@ -415,17 +415,8 @@ static void intel_fbdev_destroy(struct intel_fbdev *ifbdev)
>  	if (ifbdev->vma)
>  		intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
>  
> -	if (ifbdev->fb) {
> -#ifndef I915
> -		struct xe_bo *bo = intel_fb_obj(&ifbdev->fb->base);
> -
> -		/* Unpin our kernel fb first */
> -		xe_bo_lock_no_vm(bo, NULL);
> -		xe_bo_unpin(bo);
> -		xe_bo_unlock_no_vm(bo);
> -#endif
> +	if (ifbdev->fb)
>  		drm_framebuffer_remove(&ifbdev->fb->base);
> -	}
>  
>  	kfree(ifbdev);
>  }
> diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c
> index 0b3ad417d607..c442733d34b1 100644
> --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c
> +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c
> @@ -3,29 +3,24 @@
>   * Copyright � 2021 Intel Corporation
>   */
>  
> -#ifdef I915
> -#include "gem/i915_gem_region.h"
> -#endif
> +/* for ioread64 */
> +#include <linux/io-64-nonatomic-lo-hi.h>
> +
> +#include "xe_ggtt.h"
> +
>  #include "i915_drv.h"
>  #include "intel_atomic_plane.h"
>  #include "intel_display.h"
>  #include "intel_display_types.h"
>  #include "intel_fb.h"
> +#include "intel_fb_pin.h"
>  #include "intel_frontbuffer.h"
>  #include "intel_plane_initial.h"
>  
> -#if 0
> -#ifndef I915
> -typedef u64 gen8_pte_t;
> -#define I915_GTT_PAGE_SIZE SZ_4K
> -#define I915_GTT_PAGE_MASK ~(SZ_4K - 1)
> -#endif
> -
>  static bool
>  intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
>  			      const struct intel_initial_plane_config *plane_config,
> -			      struct drm_framebuffer **fb,
> -			      struct i915_vma **vma)
> +			      struct drm_framebuffer **fb)
>  {
>  	struct intel_crtc *crtc;
>  
> @@ -45,7 +40,6 @@ intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
>  
>  		if (intel_plane_ggtt_offset(plane_state) == plane_config->base) {
>  			*fb = plane_state->hw.fb;
> -			*vma = plane_state->ggtt_vma;
>  			return true;
>  		}
>  	}
> @@ -53,118 +47,84 @@ intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
>  	return false;
>  }
>  
> -static struct i915_vma *
> -initial_plane_vma(struct drm_i915_private *i915,
> -		  struct intel_initial_plane_config *plane_config)
> +static struct xe_bo *
> +initial_plane_bo(struct xe_device *xe,
> +		 struct intel_initial_plane_config *plane_config)
>  {
> -	struct intel_memory_region *mem;
> -	struct drm_i915_gem_object *obj;
> -	struct i915_vma *vma;
> +	struct xe_gt *gt0 = xe_device_get_gt(xe, 0);
> +	struct xe_bo *bo;
>  	resource_size_t phys_base;
> -	u32 base, size;
> -	u64 pinctl;
> +	u32 base, size, flags;
> +	u64 page_size = xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;
>  
>  	if (plane_config->size == 0)
>  		return NULL;
>  
> -	base = round_down(plane_config->base, I915_GTT_PAGE_SIZE);
> -	if (IS_DGFX(i915)) {
> -		gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
> -		gen8_pte_t pte;
> +	flags = XE_BO_CREATE_PINNED_BIT | XE_BO_SCANOUT_BIT;
>  
> -		gte += base / I915_GTT_PAGE_SIZE;
> +	base = round_down(plane_config->base, page_size);
> +	if (IS_DGFX(xe)) {
> +		u64 __iomem *gte = gt0->mem.ggtt->gsm;
> +		u64 pte;
> +
> +		gte += base / GEN8_PAGE_SIZE;
>  
>  		pte = ioread64(gte);
>  		if (!(pte & GEN12_GGTT_PTE_LM)) {
> -			drm_err(&i915->drm,
> +			drm_err(&xe->drm,
>  				"Initial plane programming missing PTE_LM bit\n");
>  			return NULL;
>  		}
>  
> -		phys_base = pte & I915_GTT_PAGE_MASK;
> -		mem = i915->mm.regions[INTEL_REGION_LMEM_0];
> +		phys_base = pte & ~(page_size - 1);
> +		flags |= XE_BO_CREATE_VRAM0_BIT;
>  
>  		/*
>  		 * We don't currently expect this to ever be placed in the
>  		 * stolen portion.
>  		 */
> -		if (phys_base >= resource_size(&mem->region)) {
> -			drm_err(&i915->drm,
> +		if (phys_base >= gt0->mem.vram.size) {
> +			drm_err(&xe->drm,
>  				"Initial plane programming using invalid range, phys_base=%pa\n",
>  				&phys_base);
>  			return NULL;
>  		}
>  
> -		drm_dbg(&i915->drm,
> +		drm_dbg(&xe->drm,
>  			"Using phys_base=%pa, based on initial plane programming\n",
>  			&phys_base);
>  	} else {
> +		struct ttm_resource_manager *stolen = ttm_manager_type(&xe->ttm, XE_PL_STOLEN);
> +
> +		if (!stolen)
> +			return NULL;
>  		phys_base = base;
> -		mem = i915->mm.stolen_region;
> -	}
> +		flags |= XE_BO_CREATE_STOLEN_BIT;
>  
> -	if (!mem)
> -		return NULL;
> +		/*
> +		 * If the FB is too big, just don't use it since fbdev is not very
> +		 * important and we should probably use that space with FBC or other
> +		 * features.
> +		 */
> +		if (!stolen || (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
> +				plane_config->size * 2 >> PAGE_SHIFT >= stolen->size))
> +			return NULL;
> +	}
>  
>  	size = round_up(plane_config->base + plane_config->size,
> -			mem->min_page_size);
> +			page_size);
>  	size -= base;
>  
> -	/*
> -	 * If the FB is too big, just don't use it since fbdev is not very
> -	 * important and we should probably use that space with FBC or other
> -	 * features.
> -	 */
> -	if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
> -	    mem == i915->mm.stolen_region &&
> -	    size * 2 > i915->stolen_usable_size)
> +	bo = xe_bo_create_pin_map_at(xe, gt0, NULL, size, phys_base,
> +				     ttm_bo_type_kernel, flags);
> +	if (IS_ERR(bo)) {
> +		drm_dbg(&xe->drm,
> +			"Failed to create bo phys_base=%pa size %u with flags %x: %li\n",
> +			&phys_base, size, flags, PTR_ERR(bo));
>  		return NULL;
> -
> -	obj = i915_gem_object_create_region_at(mem, phys_base, size, 0);
> -	if (IS_ERR(obj))
> -		return NULL;
> -
> -	/*
> -	 * Mark it WT ahead of time to avoid changing the
> -	 * cache_level during fbdev initialization. The
> -	 * unbind there would get stuck waiting for rcu.
> -	 */
> -	i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
> -					    I915_CACHE_WT : I915_CACHE_NONE);
> -
> -	switch (plane_config->tiling) {
> -	case I915_TILING_NONE:
> -		break;
> -	case I915_TILING_X:
> -	case I915_TILING_Y:
> -		obj->tiling_and_stride =
> -			plane_config->fb->base.pitches[0] |
> -			plane_config->tiling;
> -		break;
> -	default:
> -		MISSING_CASE(plane_config->tiling);
> -		goto err_obj;
>  	}
>  
> -	vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL);
> -	if (IS_ERR(vma))
> -		goto err_obj;
> -
> -	pinctl = PIN_GLOBAL | PIN_OFFSET_FIXED | base;
> -	if (HAS_GMCH(i915))
> -		pinctl |= PIN_MAPPABLE;
> -	if (i915_vma_pin(vma, 0, 0, pinctl))
> -		goto err_obj;
> -
> -	if (i915_gem_object_is_tiled(obj) &&
> -	    !i915_vma_is_map_and_fenceable(vma))
> -		goto err_obj;
> -
> -	return vma;
> -
> -err_obj:
> -	i915_gem_object_put(obj);
> -	return NULL;
> +	return bo;
>  }
>  
>  static bool
> @@ -175,7 +135,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
>  	struct drm_framebuffer *fb = &plane_config->fb->base;
> -	struct i915_vma *vma;
> +	struct xe_bo *bo;
>  
>  	switch (fb->modifier) {
>  	case DRM_FORMAT_MOD_LINEAR:
> @@ -197,21 +157,20 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
>  	mode_cmd.modifier[0] = fb->modifier;
>  	mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
>  
> -	vma = initial_plane_vma(dev_priv, plane_config);
> -	if (!vma)
> +	bo = initial_plane_bo(dev_priv, plane_config);
> +	if (!bo)
>  		return false;
>  
>  	if (intel_framebuffer_init(to_intel_framebuffer(fb),
> -				   vma->obj, &mode_cmd)) {
> +				   bo, &mode_cmd)) {
>  		drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
> -		goto err_vma;
> +		goto err_bo;
>  	}
>  
> -	plane_config->vma = vma;
>  	return true;
>  
> -err_vma:
> -	i915_vma_put(vma);
> +err_bo:
> +	xe_bo_unpin_map_no_vm(bo);
>  	return false;
>  }
>  
> @@ -236,43 +195,21 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc,
>  	if (!plane_config->fb)
>  		return;
>  
> -	if (intel_alloc_initial_plane_obj(crtc, plane_config)) {
> +	if (intel_alloc_initial_plane_obj(crtc, plane_config))
>  		fb = &plane_config->fb->base;
> -		vma = plane_config->vma;
> -		goto valid_fb;
> -	}
> +	else if (!intel_reuse_initial_plane_obj(dev_priv, plane_config, &fb))
> +		goto nofb;
>  
> -	/*
> -	 * Failed to alloc the obj, check to see if we should share
> -	 * an fb with another CRTC instead
> -	 */
> -	if (intel_reuse_initial_plane_obj(dev_priv, plane_config, &fb, &vma))
> -		goto valid_fb;
> -
> -	/*
> -	 * We've failed to reconstruct the BIOS FB.  Current display state
> -	 * indicates that the primary plane is visible, but has a NULL FB,
> -	 * which will lead to problems later if we don't fix it up.  The
> -	 * simplest solution is to just disable the primary plane now and
> -	 * pretend the BIOS never had it enabled.
> -	 */
> -	intel_plane_disable_noatomic(crtc, plane);
> -
> -	return;
> -
> -valid_fb:
>  	plane_state->uapi.rotation = plane_config->rotation;
>  	intel_fb_fill_view(to_intel_framebuffer(fb),
>  			   plane_state->uapi.rotation, &plane_state->view);
>  
> -	__i915_vma_pin(vma);
> -	plane_state->ggtt_vma = i915_vma_get(vma);
> -#ifdef I915
> -	if (intel_plane_uses_fence(plane_state) &&
> -	    i915_vma_pin_fence(vma) == 0 && vma->fence)
> -		plane_state->flags |= PLANE_HAS_FENCE;
> -#endif
> +	vma = intel_pin_and_fence_fb_obj(fb, false, &plane_state->view.gtt,
> +					 false, &plane_state->flags);
> +	if (IS_ERR(vma))
> +		goto nofb;
>  
> +	plane_state->ggtt_vma = vma;
>  	plane_state->uapi.src_x = 0;
>  	plane_state->uapi.src_y = 0;
>  	plane_state->uapi.src_w = fb->width << 16;
> @@ -283,11 +220,6 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc,
>  	plane_state->uapi.crtc_w = fb->width;
>  	plane_state->uapi.crtc_h = fb->height;
>  
> -#ifdef I915
> -	if (plane_config->tiling)
> -		dev_priv->preserve_bios_swizzle = true;
> -#endif
> -
>  	plane_state->uapi.fb = fb;
>  	drm_framebuffer_get(fb);
>  
> @@ -295,6 +227,19 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc,
>  	intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc);
>  
>  	atomic_or(plane->frontbuffer_bit, &to_intel_framebuffer(fb)->bits);
> +	return;
> +
> +nofb:
> +	/*
> +	 * We've failed to reconstruct the BIOS FB.  Current display state
> +	 * indicates that the primary plane is visible, but has a NULL FB,
> +	 * which will lead to problems later if we don't fix it up.  The
> +	 * simplest solution is to just disable the primary plane now and
> +	 * pretend the BIOS never had it enabled.
> +	 */
> +	intel_plane_disable_noatomic(crtc, plane);
> +
> +	return;
>  }
>  
>  static void plane_config_fini(struct intel_initial_plane_config *plane_config)
> @@ -308,16 +253,11 @@ static void plane_config_fini(struct intel_initial_plane_config *plane_config)
>  		else
>  			kfree(fb);
>  	}
> -
> -	if (plane_config->vma)
> -		i915_vma_put(plane_config->vma);
>  }
> -#endif
>  
>  void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
>  {
> -#if 0
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct xe_device *xe = to_xe_device(crtc->base.dev);
>  	struct intel_initial_plane_config plane_config = {};
>  
>  	/*
> @@ -327,7 +267,7 @@ void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
>  	 * can even allow for smooth boot transitions if the BIOS
>  	 * fb is large enough for the active pipe configuration.
>  	 */
> -	dev_priv->display.funcs.crtc->get_initial_plane_config(crtc, &plane_config);
> +	xe->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
>  
>  	/*
>  	 * If the fb is shared between multiple heads, we'll
> @@ -336,10 +276,4 @@ void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
>  	intel_find_initial_plane_obj(crtc, &plane_config);
>  
>  	plane_config_fini(&plane_config);
> -#else
> -	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> -
> -	/* No support for stolen memory yet, just disable all, worry about smoothness later! */
> -	intel_plane_disable_noatomic(crtc, plane);
> -#endif
>  }
> -- 
> 2.38.1
> 

Re: [Intel-xe] [PATCH 26/37] Revert "drm/xe: Validate BO on CPU fault"

[Rodrigo Vivi]

On Thu, Jan 12, 2023 at 05:25:27PM -0500, Rodrigo Vivi wrote:
> From: Matthew Brost <matthew.brost@intel.com>
> 
> This reverts commit 48d84660be7607ccaacd76a2d653f51709cc5693.

Hi Matt, this commit doesn't exist after the big squased initial patch.
Could you please reply here with a commit subject and message?
I will add on a next interaction or when merging it.

Thanks,
Rodrigo.

> 
> Cc: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_bo.c | 13 ++++++-------
>  1 file changed, 6 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> index da2c8a1c19ec..e224405bc4f6 100644
> --- a/drivers/gpu/drm/xe/xe_bo.c
> +++ b/drivers/gpu/drm/xe/xe_bo.c
> @@ -875,14 +875,13 @@ static vm_fault_t xe_gem_fault(struct vm_fault *vmf)
>  
>  		trace_xe_bo_cpu_fault(bo);
>  
> -		if (should_migrate_to_system(bo))
> +		if (should_migrate_to_system(bo)) {
>  			r = xe_bo_migrate(bo, XE_PL_TT);
> -		else
> -			r = xe_bo_validate(bo, NULL, false);
> -		if (r == -EBUSY || r == -ERESTARTSYS)
> -			ret = VM_FAULT_NOPAGE;
> -		else if (r)
> -			ret = VM_FAULT_SIGBUS;
> +			if (r == -EBUSY || r == -ERESTARTSYS || r == -EINTR)
> +				ret = VM_FAULT_NOPAGE;
> +			else if (r)
> +				ret = VM_FAULT_SIGBUS;
> +		}
>  		if (!ret)
>  			ret = ttm_bo_vm_fault_reserved(vmf,
>  						       vmf->vma->vm_page_prot,
> -- 
> 2.38.1
> 

Re: [Intel-xe] [PATCH 37/37] drm/xe: enforce GSMBASE for DG1 instead of BAR2

[Rodrigo Vivi]

On Thu, Jan 12, 2023 at 05:25:38PM -0500, Rodrigo Vivi wrote:
> From: Philippe Lecluse <philippe.lecluse@intel.com>

Hi Phil, could you please reply with a commit message to this patch?
I will add on the next interaction or while merging it.

Thanks,
Rodrigo.

> 
> v2: move to logic in probed vram_size
>     rename flat_ccs_base to more generic usable_size
> 
> Signed-off-by: Philippe Lecluse <philippe.lecluse@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_mmio.c | 28 ++++++++++++++--------------
>  1 file changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 4d679027fc98..b3c1a39ef79d 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -153,7 +153,7 @@ static bool xe_pci_resource_valid(struct pci_dev *pdev, int bar)
>  	return true;
>  }
>  
> -int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *flat_ccs_base)
> +int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *usable_size)
>  {
>  	struct xe_gt *gt = xe_device_get_gt(xe, 0);
>  	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> @@ -162,8 +162,12 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *flat_ccs_
>  
>  	if (!xe->info.has_flat_ccs)  {
>  		*vram_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
> -		if (flat_ccs_base)
> -			*flat_ccs_base = *vram_size;
> +		if (usable_size) {
> +			if (xe->info.platform == XE_DG1)
> +				*usable_size = xe_mmio_read64(gt, GEN12_GSMBASE.reg);
> +			else
> +				*usable_size = *vram_size;
> +		}
>  		return 0;
>  	}
>  
> @@ -173,15 +177,13 @@ int xe_mmio_total_vram_size(struct xe_device *xe, u64 *vram_size, u64 *flat_ccs_
>  
>  	reg = xe_gt_mcr_unicast_read_any(gt, XEHP_TILE0_ADDR_RANGE);
>  	*vram_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
> -	if (flat_ccs_base) {
> +	if (usable_size) {
>  		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
> -		*flat_ccs_base = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;
> +		*usable_size = (u64)REG_FIELD_GET(GENMASK(31, 8), reg) * SZ_64K;
> +		drm_info(&xe->drm, "lmem_size: 0x%llx usable_size: 0x%llx\n",
> +			 *vram_size, *usable_size);
>  	}
>  
> -	if (flat_ccs_base)
> -		drm_info(&xe->drm, "lmem_size: 0x%llx flat_ccs_base: 0x%llx\n",
> -			 *vram_size, *flat_ccs_base);
> -
>  	return xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
>  }
>  
> @@ -193,7 +195,7 @@ int xe_mmio_probe_vram(struct xe_device *xe)
>  	u64 lmem_size;
>  	u64 original_size;
>  	u64 current_size;
> -	u64 flat_ccs_base;
> +	u64 usable_size;
>  	int resize_result, err;
>  
>  	if (!IS_DGFX(xe)) {
> @@ -215,11 +217,9 @@ int xe_mmio_probe_vram(struct xe_device *xe)
>  	}
>  
>  	gt = xe_device_get_gt(xe, 0);
> -	lmem_size = xe_mmio_read64(gt, GEN12_GSMBASE.reg);
> -
>  	original_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
>  
> -	err = xe_mmio_total_vram_size(xe, &lmem_size, &flat_ccs_base);
> +	err = xe_mmio_total_vram_size(xe, &lmem_size, &usable_size);
>  	if (err)
>  		return err;
>  
> @@ -247,7 +247,7 @@ int xe_mmio_probe_vram(struct xe_device *xe)
>  	xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.size);
>  #endif
>  
> -	xe->mem.vram.size = min_t(u64, xe->mem.vram.size, flat_ccs_base);
> +	xe->mem.vram.size = min_t(u64, xe->mem.vram.size, usable_size);
>  
>  	drm_info(&xe->drm, "TOTAL VRAM: %pa, %pa\n", &xe->mem.vram.io_start, &xe->mem.vram.size);
>  
> -- 
> 2.38.1
> 

Re: [Intel-xe] [PATCH 37/37] drm/xe: enforce GSMBASE for DG1 instead of BAR2

[Lecluse, Philippe]

On DG1, BAR2 is not reliable for reporting Vram size, need to use GSMBASE.
Simplify xe_mmio_total_vram_size to report vram size and usable size.

-----Original Message-----
From: Vivi, Rodrigo <rodrigo.vivi@intel.com> 
Sent: Tuesday, January 24, 2023 4:46 PM
To: intel-xe@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>; maarten.lankhorst@linux.intel.com; Lecluse, Philippe <philippe.lecluse@intel.com>; mchehab@kernel.org
Cc: Auld, Matthew <matthew.auld@intel.com>
Subject: Re: [Intel-xe] [PATCH 37/37] drm/xe: enforce GSMBASE for DG1 instead of BAR2

On Thu, Jan 12, 2023 at 05:25:38PM -0500, Rodrigo Vivi wrote:
> From: Philippe Lecluse <philippe.lecluse@intel.com>

Hi Phil, could you please reply with a commit message to this patch?
I will add on the next interaction or while merging it.

Thanks,
Rodrigo.
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Re: [Intel-xe] [PATCH 01/37] drm/msm: Fix compile error

[Rodrigo Vivi]

On Thu, Jan 12, 2023 at 05:25:02PM -0500, Rodrigo Vivi wrote:
> From: Matthew Brost <matthew.brost@intel.com>
> 
> When changing the DRM scheduler from a kthread to a work queue the MSM
> driver was not updated to reflect this change. Fix this.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>

Thomas, may I convert your gitlab approvals in reviewed-bys,
or do you want to go patch by patch that you have approved
in gitlab and drop individual reviewed-bys here in the ml?

> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index 628806423f7d..37cf74a2cbc3 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -660,7 +660,7 @@ static void suspend_scheduler(struct msm_gpu *gpu)
>  	 */
>  	for (i = 0; i < gpu->nr_rings; i++) {
>  		struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;
> -		kthread_park(sched->thread);
> +		drm_sched_run_wq_stop(sched);
>  	}
>  }
>  
> @@ -670,7 +670,7 @@ static void resume_scheduler(struct msm_gpu *gpu)
>  
>  	for (i = 0; i < gpu->nr_rings; i++) {
>  		struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched;
> -		kthread_unpark(sched->thread);
> +		drm_sched_run_wq_start(sched);
>  	}
>  }
>  
> -- 
> 2.38.1
> 

Re: [Intel-xe] [PATCH 02/37] drm/xe: Implement a local xe_mmio_wait32

[Rodrigo Vivi]

On Thu, Jan 12, 2023 at 05:25:03PM -0500, Rodrigo Vivi wrote:
> Then, move the i915_utils.h include to its user.
> 
> The overall goal is to kill all the usages of the i915_utils
> stuff.
> 
> Yes, wait_for also depends on <linux/delay.h>, so they go
> together to where it is needed. It will be likely needed
> anyway directly for udelay or usleep_range.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>

Matt, may I convert your gitlab approvals in reviewed-bys?
or do you want to go one by one here in the ml?

> ---
>  drivers/gpu/drm/xe/xe_force_wake.c |  6 ++++++
>  drivers/gpu/drm/xe/xe_gt_mcr.c     |  7 +++++++
>  drivers/gpu/drm/xe/xe_guc.c        |  7 +++++++
>  drivers/gpu/drm/xe/xe_guc_pc.c     |  7 +++++++
>  drivers/gpu/drm/xe/xe_mmio.h       | 29 ++++++++++++++++++++---------
>  drivers/gpu/drm/xe/xe_pcode.c      |  7 +++++++
>  6 files changed, 54 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
> index 5a5b6e3e715d..04b22eeb8ab5 100644
> --- a/drivers/gpu/drm/xe/xe_force_wake.c
> +++ b/drivers/gpu/drm/xe/xe_force_wake.c
> @@ -10,6 +10,12 @@
>  #include "xe_mmio.h"
>  #include "../i915/gt/intel_gt_regs.h"
>  
> +/*
> + * FIXME: This header has been deemed evil and we need to kill it. Temporarily
> + * including so we can use '__mask_next_bit'.
> + */
> +#include "i915_utils.h"
> +
>  #define XE_FORCE_WAKE_ACK_TIMEOUT_MS	50
>  
>  static struct xe_gt *
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index 63829d8c8b54..ce776b260750 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -11,6 +11,13 @@
>  
>  #include "../i915/gt/intel_gt_regs.h"
>  
> +#include <linux/delay.h>
> +/*
> + * FIXME: This header has been deemed evil and we need to kill it. Temporar
> + * including so we can use 'wait_for'.
> + */
> +#include "i915_utils.h"
> +
>  /**
>   * DOC: GT Multicast/Replicated (MCR) Register Support
>   *
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index b5557375804f..373c94230fc3 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -22,6 +22,13 @@
>  #include "i915_reg_defs.h"
>  #include "../i915/gt/intel_gt_regs.h"
>  
> +#include <linux/delay.h>
> +/*
> + * FIXME: This header has been deemed evil and we need to kill it. Temporarily
> + * including so we can use 'wait_for' and range_overflow_t.
> + */
> +#include "i915_utils.h"
> +
>  /* TODO: move to common file */
>  #define GUC_PVC_MOCS_INDEX_MASK		REG_GENMASK(25, 24)
>  #define PVC_MOCS_UC_INDEX		1
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 38b1275ea655..515b7aab03c3 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -16,6 +16,13 @@
>  #include "i915_reg_defs.h"
>  #include "../i915/i915_reg.h"
>  
> +#include <linux/delay.h>
> +/*
> + * FIXME: This header has been deemed evil and we need to kill it. Temporarily
> + * including so we can use 'wait_for'.
> + */
> +#include "i915_utils.h"
> +
>  #include "../i915/intel_mchbar_regs.h"
>  /* For GEN6_RP_STATE_CAP.reg to be merged when the definition moves to Xe */
>  #define   RP0_MASK	REG_GENMASK(7, 0)
> diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
> index e7cca6d2f81f..d3bc0989ce2e 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.h
> +++ b/drivers/gpu/drm/xe/xe_mmio.h
> @@ -10,13 +10,6 @@
>  
>  #include "xe_gt_types.h"
>  
> -/*
> - * FIXME: This header has been deemed evil and we need to kill it. Temporarily
> - * including so we can use 'wait_for' and unblock initial development. A follow
> - * should replace 'wait_for' with a sane version and drop including this header.
> - */
> -#include "i915_utils.h"
> -
>  struct drm_device;
>  struct drm_file;
>  struct xe_device;
> @@ -84,8 +77,26 @@ static inline int xe_mmio_wait32(struct xe_gt *gt,
>  				 u32 reg, u32 val,
>  				 u32 mask, u32 timeout_ms)
>  {
> -	return wait_for((xe_mmio_read32(gt, reg) & mask) == val,
> -			timeout_ms);
> +	ktime_t cur = ktime_get_raw();
> +	const ktime_t end = ktime_add_ms(cur, timeout_ms);
> +	s64 wait = 10;
> +
> +	for (;;) {
> +		if ((xe_mmio_read32(gt, reg) & mask) == val)
> +			return 0;
> +
> +		cur = ktime_get_raw();
> +		if (!ktime_before(cur, end))
> +			return -ETIMEDOUT;
> +
> +		if (ktime_after(ktime_add_us(cur, wait), end))
> +			wait = ktime_us_delta(end, cur);
> +
> +		usleep_range(wait, wait << 1);
> +		wait <<= 1;
> +	}
> +
> +	return -ETIMEDOUT;
>  }
>  
>  int xe_mmio_ioctl(struct drm_device *dev, void *data,
> diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
> index 236159c8a6c0..313ccd70d1a9 100644
> --- a/drivers/gpu/drm/xe/xe_pcode.c
> +++ b/drivers/gpu/drm/xe/xe_pcode.c
> @@ -11,6 +11,13 @@
>  
>  #include <linux/errno.h>
>  
> +#include <linux/delay.h>
> +/*
> + * FIXME: This header has been deemed evil and we need to kill it. Temporarily
> + * including so we can use 'wait_for'.
> + */
> +#include "i915_utils.h"
> +
>  /**
>   * DOC: PCODE
>   *
> -- 
> 2.38.1
> 

Re: [Intel-xe] [PATCH 28/37] drm/xe: Don't use engine_mask until after hwconfig parse

[Rodrigo Vivi]

On Thu, Jan 12, 2023 at 05:25:29PM -0500, Rodrigo Vivi wrote:
> From: Matthew Brost <matthew.brost@intel.com>
> 
> The IRQ and MCR init used engine_mask before hwconfig parse (currently
> faked), move these steps after the hwconfig parse.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_gt.c  |  7 +++++++
>  drivers/gpu/drm/xe/xe_irq.c | 34 +++++++++++++++++++---------------
>  drivers/gpu/drm/xe/xe_irq.h |  2 ++
>  3 files changed, 28 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 6cea15725cae..75150077d62c 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -21,6 +21,7 @@
>  #include "xe_gt_sysfs.h"
>  #include "xe_gt_topology.h"
>  #include "xe_hw_fence.h"
> +#include "xe_irq.h"
>  #include "xe_lrc.h"
>  #include "xe_map.h"
>  #include "xe_migrate.h"
> @@ -449,6 +450,12 @@ static int gt_fw_domain_init(struct xe_gt *gt)
>  	if (err)
>  		goto err_force_wake;
>  
> +	/* Enables per hw engine IRQs */
> +	xe_gt_irq_postinstall(gt);
> +
> +	/* Rerun MCR init as we now have hw engine list */
> +	xe_gt_mcr_init(gt);
> +
>  	err = xe_hw_engines_init_early(gt);
>  	if (err)
>  		goto err_force_wake;
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index edebe1817400..92fe6b38d735 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -492,26 +492,32 @@ void xe_irq_reset(struct xe_device *xe)
>  #endif
>  }
>  
> -void xe_irq_postinstall(struct xe_device *xe)
> +void xe_gt_irq_postinstall(struct xe_gt *gt)
>  {
> -	struct xe_gt *gt;
> -	u8 id;
> +	struct xe_device *xe = gt_to_xe(gt);
>  
> -	for_each_gt(gt, xe, id) {
> -		if (GRAPHICS_VERx100(xe) >= 1210) {
> -			dg1_irq_postinstall(xe, gt);
> -		} else if (GRAPHICS_VER(xe) >= 11) {
> -			gen11_irq_postinstall(xe, gt);
> -		} else {
> -			drm_err(&xe->drm, "No interrupt postinstall hook");
> -		}
> -	}
> +	if (GRAPHICS_VERx100(xe) >= 1210)
> +		dg1_irq_postinstall(xe, gt);
> +	else if (GRAPHICS_VER(xe) >= 11)
> +		gen11_irq_postinstall(xe, gt);
> +	else
> +		drm_err(&xe->drm, "No interrupt postinstall hook");
>  
>  #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> -	gen11_display_irq_postinstall(xe);
> +	if (gt->info.id == XE_GT0)
> +		gen11_display_irq_postinstall(gt_to_xe(gt));
>  #endif
>  }
>  
> +static void xe_irq_postinstall(struct xe_device *xe)
> +{
> +	struct xe_gt *gt;
> +	u8 id;
> +
> +	for_each_gt(gt, xe, id)
> +		xe_gt_irq_postinstall(gt);
> +}
> +
>  static irq_handler_t xe_irq_handler(struct xe_device *xe)
>  {
>  	if (GRAPHICS_VERx100(xe) >= 1210) {
> @@ -566,8 +572,6 @@ int xe_irq_install(struct xe_device *xe)
>  	if (err)
>  		return err;
>  
> -	xe_irq_postinstall(xe);
> -
>  	return err;
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h
> index 7aee8d259353..34ecf22b32d3 100644
> --- a/drivers/gpu/drm/xe/xe_irq.h
> +++ b/drivers/gpu/drm/xe/xe_irq.h
> @@ -7,8 +7,10 @@
>  #define _XE_IRQ_H_
>  
>  struct xe_device;
> +struct xe_gt;
>  
>  int xe_irq_install(struct xe_device *xe);
> +void xe_gt_irq_postinstall(struct xe_gt *gt);
>  void xe_irq_shutdown(struct xe_device *xe);
>  void xe_irq_suspend(struct xe_device *xe);
>  void xe_irq_resume(struct xe_device *xe);
> -- 
> 2.38.1
> 

Re: [Intel-xe] [PATCH 29/37] drm/xe: Fake pulling gt->info.engine_mask from hwconfig blob

[Rodrigo Vivi]

On Thu, Jan 12, 2023 at 05:25:30PM -0500, Rodrigo Vivi wrote:
> From: Matthew Brost <matthew.brost@intel.com>
> 
> The blob doesn't fully support this yet, so fake for now to ensure our
> driver load order is correct.
> 
> Once the blob supports pulling gt->info.engine_mask from the blob, this
> patch can be removed.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_gt.c       | 3 +++
>  drivers/gpu/drm/xe/xe_gt_types.h | 6 ++++++
>  drivers/gpu/drm/xe/xe_pci.c      | 4 ++--
>  3 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 75150077d62c..cb837745d893 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -450,6 +450,9 @@ static int gt_fw_domain_init(struct xe_gt *gt)
>  	if (err)
>  		goto err_force_wake;
>  
> +	/* XXX: Fake that we pull the engine mask from hwconfig blob */
> +	gt->info.engine_mask = gt->info.__engine_mask;
> +
>  	/* Enables per hw engine IRQs */
>  	xe_gt_irq_postinstall(gt);
>  
> diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
> index c80a9215098d..2dbc8cedd630 100644
> --- a/drivers/gpu/drm/xe/xe_gt_types.h
> +++ b/drivers/gpu/drm/xe/xe_gt_types.h
> @@ -93,6 +93,12 @@ struct xe_gt {
>  		u32 clock_freq;
>  		/** @engine_mask: mask of engines present on GT */
>  		u64 engine_mask;
> +		/**
> +		 * @__engine_mask: mask of engines present on GT read from
> +		 * xe_pci.c, used to fake reading the engine_mask from the
> +		 * hwconfig blob.
> +		 */
> +		u64 __engine_mask;
>  	} info;
>  
>  	/**
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index bcf6fd610881..d654f2351557 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -509,13 +509,13 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>  		if (id == 0) {
>  			gt->info.type = XE_GT_TYPE_MAIN;
>  			gt->info.vram_id = id;
> -			gt->info.engine_mask = desc->platform_engine_mask;
> +			gt->info.__engine_mask = desc->platform_engine_mask;
>  			gt->mmio.adj_limit = 0;
>  			gt->mmio.adj_offset = 0;
>  		} else {
>  			gt->info.type = desc->extra_gts[id - 1].type;
>  			gt->info.vram_id = desc->extra_gts[id - 1].vram_id;
> -			gt->info.engine_mask =
> +			gt->info.__engine_mask =
>  				desc->extra_gts[id - 1].engine_mask;
>  			gt->mmio.adj_limit =
>  				desc->extra_gts[id - 1].mmio_adj_limit;
> -- 
> 2.38.1
> 

Re: [Intel-xe] [PATCH 37/37] drm/xe: enforce GSMBASE for DG1 instead of BAR2

[Rodrigo Vivi]

On Tue, Jan 24, 2023 at 04:25:16PM +0000, Lecluse, Philippe wrote:
> On DG1, BAR2 is not reliable for reporting Vram size, need to use GSMBASE.
> Simplify xe_mmio_total_vram_size to report vram size and usable size.

Matt, with this can I convert your gitlab approval in a rv-b?

> 
> -----Original Message-----
> From: Vivi, Rodrigo <rodrigo.vivi@intel.com> 
> Sent: Tuesday, January 24, 2023 4:46 PM
> To: intel-xe@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>; maarten.lankhorst@linux.intel.com; Lecluse, Philippe <philippe.lecluse@intel.com>; mchehab@kernel.org
> Cc: Auld, Matthew <matthew.auld@intel.com>
> Subject: Re: [Intel-xe] [PATCH 37/37] drm/xe: enforce GSMBASE for DG1 instead of BAR2
> 
> On Thu, Jan 12, 2023 at 05:25:38PM -0500, Rodrigo Vivi wrote:
> > From: Philippe Lecluse <philippe.lecluse@intel.com>
> 
> Hi Phil, could you please reply with a commit message to this patch?
> I will add on the next interaction or while merging it.
> 
> Thanks,
> Rodrigo.
> ---------------------------------------------------------------------
> Intel Benelux B.V.
> Registered in The Netherlands under number 24134020
> Statutory seat: Rotterdam
> Registered address: Capronilaan 37, 1119NG Schiphol-Rijk
> 
> This e-mail and any attachments may contain confidential material for
> the sole use of the intended recipient(s). Any review or distribution
> by others is strictly prohibited. If you are not the intended
> recipient, please contact the sender and delete all copies.
> 

Re: [Intel-xe] [PATCH 37/37] drm/xe: enforce GSMBASE for DG1 instead of BAR2

[Rodrigo Vivi]

On Tue, Jan 24, 2023 at 04:25:16PM +0000, Lecluse, Philippe wrote:
> On DG1, BAR2 is not reliable for reporting Vram size, need to use GSMBASE.
> Simplify xe_mmio_total_vram_size to report vram size and usable size.

Matt, with this as commit msg of this patch, can I convert your gitlab approval in rv-b?

What about other gitlab approvals? can I convert them to rv-b or
do you intend to go patch by patch here in the ml?

Thanks,
Rodrigo.

> 
> -----Original Message-----
> From: Vivi, Rodrigo <rodrigo.vivi@intel.com> 
> Sent: Tuesday, January 24, 2023 4:46 PM
> To: intel-xe@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>; maarten.lankhorst@linux.intel.com; Lecluse, Philippe <philippe.lecluse@intel.com>; mchehab@kernel.org
> Cc: Auld, Matthew <matthew.auld@intel.com>
> Subject: Re: [Intel-xe] [PATCH 37/37] drm/xe: enforce GSMBASE for DG1 instead of BAR2
> 
> On Thu, Jan 12, 2023 at 05:25:38PM -0500, Rodrigo Vivi wrote:
> > From: Philippe Lecluse <philippe.lecluse@intel.com>
> 
> Hi Phil, could you please reply with a commit message to this patch?
> I will add on the next interaction or while merging it.
> 
> Thanks,
> Rodrigo.
> ---------------------------------------------------------------------
> Intel Benelux B.V.
> Registered in The Netherlands under number 24134020
> Statutory seat: Rotterdam
> Registered address: Capronilaan 37, 1119NG Schiphol-Rijk
> 
> This e-mail and any attachments may contain confidential material for
> the sole use of the intended recipient(s). Any review or distribution
> by others is strictly prohibited. If you are not the intended
> recipient, please contact the sender and delete all copies.
> 

Re: [Intel-xe] [PATCH 02/37] drm/xe: Implement a local xe_mmio_wait32

[Matthew Brost]

On Tue, Jan 31, 2023 at 01:49:02PM -0500, Rodrigo Vivi wrote:
> On Thu, Jan 12, 2023 at 05:25:03PM -0500, Rodrigo Vivi wrote:
> > Then, move the i915_utils.h include to its user.
> > 
> > The overall goal is to kill all the usages of the i915_utils
> > stuff.
> > 
> > Yes, wait_for also depends on <linux/delay.h>, so they go
> > together to where it is needed. It will be likely needed
> > anyway directly for udelay or usleep_range.
> > 
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Matthew Brost <matthew.brost@intel.com>
> 
> Matt, may I convert your gitlab approvals in reviewed-bys?
> or do you want to go one by one here in the ml?
> 

Please consider any of my gitlab approvals as:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> > ---
> >  drivers/gpu/drm/xe/xe_force_wake.c |  6 ++++++
> >  drivers/gpu/drm/xe/xe_gt_mcr.c     |  7 +++++++
> >  drivers/gpu/drm/xe/xe_guc.c        |  7 +++++++
> >  drivers/gpu/drm/xe/xe_guc_pc.c     |  7 +++++++
> >  drivers/gpu/drm/xe/xe_mmio.h       | 29 ++++++++++++++++++++---------
> >  drivers/gpu/drm/xe/xe_pcode.c      |  7 +++++++
> >  6 files changed, 54 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
> > index 5a5b6e3e715d..04b22eeb8ab5 100644
> > --- a/drivers/gpu/drm/xe/xe_force_wake.c
> > +++ b/drivers/gpu/drm/xe/xe_force_wake.c
> > @@ -10,6 +10,12 @@
> >  #include "xe_mmio.h"
> >  #include "../i915/gt/intel_gt_regs.h"
> >  
> > +/*
> > + * FIXME: This header has been deemed evil and we need to kill it. Temporarily
> > + * including so we can use '__mask_next_bit'.
> > + */
> > +#include "i915_utils.h"
> > +
> >  #define XE_FORCE_WAKE_ACK_TIMEOUT_MS	50
> >  
> >  static struct xe_gt *
> > diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> > index 63829d8c8b54..ce776b260750 100644
> > --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> > +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> > @@ -11,6 +11,13 @@
> >  
> >  #include "../i915/gt/intel_gt_regs.h"
> >  
> > +#include <linux/delay.h>
> > +/*
> > + * FIXME: This header has been deemed evil and we need to kill it. Temporar
> > + * including so we can use 'wait_for'.
> > + */
> > +#include "i915_utils.h"
> > +
> >  /**
> >   * DOC: GT Multicast/Replicated (MCR) Register Support
> >   *
> > diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> > index b5557375804f..373c94230fc3 100644
> > --- a/drivers/gpu/drm/xe/xe_guc.c
> > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > @@ -22,6 +22,13 @@
> >  #include "i915_reg_defs.h"
> >  #include "../i915/gt/intel_gt_regs.h"
> >  
> > +#include <linux/delay.h>
> > +/*
> > + * FIXME: This header has been deemed evil and we need to kill it. Temporarily
> > + * including so we can use 'wait_for' and range_overflow_t.
> > + */
> > +#include "i915_utils.h"
> > +
> >  /* TODO: move to common file */
> >  #define GUC_PVC_MOCS_INDEX_MASK		REG_GENMASK(25, 24)
> >  #define PVC_MOCS_UC_INDEX		1
> > diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> > index 38b1275ea655..515b7aab03c3 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> > @@ -16,6 +16,13 @@
> >  #include "i915_reg_defs.h"
> >  #include "../i915/i915_reg.h"
> >  
> > +#include <linux/delay.h>
> > +/*
> > + * FIXME: This header has been deemed evil and we need to kill it. Temporarily
> > + * including so we can use 'wait_for'.
> > + */
> > +#include "i915_utils.h"
> > +
> >  #include "../i915/intel_mchbar_regs.h"
> >  /* For GEN6_RP_STATE_CAP.reg to be merged when the definition moves to Xe */
> >  #define   RP0_MASK	REG_GENMASK(7, 0)
> > diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
> > index e7cca6d2f81f..d3bc0989ce2e 100644
> > --- a/drivers/gpu/drm/xe/xe_mmio.h
> > +++ b/drivers/gpu/drm/xe/xe_mmio.h
> > @@ -10,13 +10,6 @@
> >  
> >  #include "xe_gt_types.h"
> >  
> > -/*
> > - * FIXME: This header has been deemed evil and we need to kill it. Temporarily
> > - * including so we can use 'wait_for' and unblock initial development. A follow
> > - * should replace 'wait_for' with a sane version and drop including this header.
> > - */
> > -#include "i915_utils.h"
> > -
> >  struct drm_device;
> >  struct drm_file;
> >  struct xe_device;
> > @@ -84,8 +77,26 @@ static inline int xe_mmio_wait32(struct xe_gt *gt,
> >  				 u32 reg, u32 val,
> >  				 u32 mask, u32 timeout_ms)
> >  {
> > -	return wait_for((xe_mmio_read32(gt, reg) & mask) == val,
> > -			timeout_ms);
> > +	ktime_t cur = ktime_get_raw();
> > +	const ktime_t end = ktime_add_ms(cur, timeout_ms);
> > +	s64 wait = 10;
> > +
> > +	for (;;) {
> > +		if ((xe_mmio_read32(gt, reg) & mask) == val)
> > +			return 0;
> > +
> > +		cur = ktime_get_raw();
> > +		if (!ktime_before(cur, end))
> > +			return -ETIMEDOUT;
> > +
> > +		if (ktime_after(ktime_add_us(cur, wait), end))
> > +			wait = ktime_us_delta(end, cur);
> > +
> > +		usleep_range(wait, wait << 1);
> > +		wait <<= 1;
> > +	}
> > +
> > +	return -ETIMEDOUT;
> >  }
> >  
> >  int xe_mmio_ioctl(struct drm_device *dev, void *data,
> > diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
> > index 236159c8a6c0..313ccd70d1a9 100644
> > --- a/drivers/gpu/drm/xe/xe_pcode.c
> > +++ b/drivers/gpu/drm/xe/xe_pcode.c
> > @@ -11,6 +11,13 @@
> >  
> >  #include <linux/errno.h>
> >  
> > +#include <linux/delay.h>
> > +/*
> > + * FIXME: This header has been deemed evil and we need to kill it. Temporarily
> > + * including so we can use 'wait_for'.
> > + */
> > +#include "i915_utils.h"
> > +
> >  /**
> >   * DOC: PCODE
> >   *
> > -- 
> > 2.38.1
> > 

Re: [Intel-xe] [PATCH 37/37] drm/xe: enforce GSMBASE for DG1 instead of BAR2

[Matthew Auld]

On 31/01/2023 19:13, Rodrigo Vivi wrote:
> On Tue, Jan 24, 2023 at 04:25:16PM +0000, Lecluse, Philippe wrote:
>> On DG1, BAR2 is not reliable for reporting Vram size, need to use GSMBASE.
>> Simplify xe_mmio_total_vram_size to report vram size and usable size.

s/reliable/valid/
s/Vram size/usable VRAM size/

> 
> Matt, with this as commit msg of this patch, can I convert your gitlab approval in rv-b?

Reviewed-by: Matthew Auld <matthew.auld@intel.com>

> 
> What about other gitlab approvals? can I convert them to rv-b or
> do you intend to go patch by patch here in the ml?

Sure.

> 
> Thanks,
> Rodrigo.
> 
>>
>> -----Original Message-----
>> From: Vivi, Rodrigo <rodrigo.vivi@intel.com>
>> Sent: Tuesday, January 24, 2023 4:46 PM
>> To: intel-xe@lists.freedesktop.org; Brost, Matthew <matthew.brost@intel.com>; maarten.lankhorst@linux.intel.com; Lecluse, Philippe <philippe.lecluse@intel.com>; mchehab@kernel.org
>> Cc: Auld, Matthew <matthew.auld@intel.com>
>> Subject: Re: [Intel-xe] [PATCH 37/37] drm/xe: enforce GSMBASE for DG1 instead of BAR2
>>
>> On Thu, Jan 12, 2023 at 05:25:38PM -0500, Rodrigo Vivi wrote:
>>> From: Philippe Lecluse <philippe.lecluse@intel.com>
>>
>> Hi Phil, could you please reply with a commit message to this patch?
>> I will add on the next interaction or while merging it.
>>
>> Thanks,
>> Rodrigo.
>> ---------------------------------------------------------------------
>> Intel Benelux B.V.
>> Registered in The Netherlands under number 24134020
>> Statutory seat: Rotterdam
>> Registered address: Capronilaan 37, 1119NG Schiphol-Rijk
>>
>> This e-mail and any attachments may contain confidential material for
>> the sole use of the intended recipient(s). Any review or distribution
>> by others is strictly prohibited. If you are not the intended
>> recipient, please contact the sender and delete all copies.
>>

Re: [Intel-xe] [PATCH 37/37] drm/xe: enforce GSMBASE for DG1 instead of BAR2

[Matthew Auld]

On 01/02/2023 09:12, Matthew Auld wrote:
> On 31/01/2023 19:13, Rodrigo Vivi wrote:
>> On Tue, Jan 24, 2023 at 04:25:16PM +0000, Lecluse, Philippe wrote:
>>> On DG1, BAR2 is not reliable for reporting Vram size, need to use 
>>> GSMBASE.
>>> Simplify xe_mmio_total_vram_size to report vram size and usable size.
> 
> s/reliable/valid/
> s/Vram size/usable VRAM size/
> 
>>
>> Matt, with this as commit msg of this patch, can I convert your gitlab 
>> approval in rv-b?
> 
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> 
>>
>> What about other gitlab approvals? can I convert them to rv-b or
>> do you intend to go patch by patch here in the ml?
> 
> Sure.

I mean sure, feel free to convert to r-b.

> 
>>
>> Thanks,
>> Rodrigo.
>>
>>>
>>> -----Original Message-----
>>> From: Vivi, Rodrigo <rodrigo.vivi@intel.com>
>>> Sent: Tuesday, January 24, 2023 4:46 PM
>>> To: intel-xe@lists.freedesktop.org; Brost, Matthew 
>>> <matthew.brost@intel.com>; maarten.lankhorst@linux.intel.com; 
>>> Lecluse, Philippe <philippe.lecluse@intel.com>; mchehab@kernel.org
>>> Cc: Auld, Matthew <matthew.auld@intel.com>
>>> Subject: Re: [Intel-xe] [PATCH 37/37] drm/xe: enforce GSMBASE for DG1 
>>> instead of BAR2
>>>
>>> On Thu, Jan 12, 2023 at 05:25:38PM -0500, Rodrigo Vivi wrote:
>>>> From: Philippe Lecluse <philippe.lecluse@intel.com>
>>>
>>> Hi Phil, could you please reply with a commit message to this patch?
>>> I will add on the next interaction or while merging it.
>>>
>>> Thanks,
>>> Rodrigo.
>>> ---------------------------------------------------------------------
>>> Intel Benelux B.V.
>>> Registered in The Netherlands under number 24134020
>>> Statutory seat: Rotterdam
>>> Registered address: Capronilaan 37, 1119NG Schiphol-Rijk
>>>
>>> This e-mail and any attachments may contain confidential material for
>>> the sole use of the intended recipient(s). Any review or distribution
>>> by others is strictly prohibited. If you are not the intended
>>> recipient, please contact the sender and delete all copies.
>>>

Re: [Intel-xe] [PATCH 27/37] drm/xe: Ensure VMA not userptr before calling xe_bo_is_stolen

[Rodrigo Vivi]

On Thu, Jan 12, 2023 at 05:25:28PM -0500, Rodrigo Vivi wrote:
> From: Matthew Brost <matthew.brost@intel.com>
> 
> Fix the below splat:
> 
> [  142.510525] [IGT] xe_exec_basic: starting subtest once-userptr
> [  142.511339] BUG: kernel NULL pointer dereference, address: 0000000000000228
> [  142.518311] #PF: supervisor read access in kernel mode
> [  142.523458] #PF: error_code(0x0000) - not-present page
> [  142.528604] PGD 0 P4D 0
> [  142.531153] Oops: 0000 [#1] PREEMPT SMP NOPTI
> [  142.535518] CPU: 4 PID: 1199 Comm: kworker/u16:8 Not tainted 6.1.0-rc1-xe+ #1
> [  142.542656] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.3243.A01.2006102133 06/10/2020
> [  142.556033] Workqueue: events_unbound async_op_work_func [xe]
> [  142.561810] RIP: 0010:xe_bo_is_stolen+0x0/0x20 [xe]
> [  142.566709] Code: 20 c8 75 05 83 fa 07 74 05 c3 cc cc cc cc 48 8b 87 08 02 00 00 0f b6 80 2c ff ff ff c3 cc cc cc cc 66 0f 1f 84 00 00 00 00 00 <48> 8b 87 28 02 00 00 83 78 10 07 0f 94 c0 c3 cc cc cc cc 66 66 2e
> [  142.585447] RSP: 0018:ffffc900019eb888 EFLAGS: 00010246
> [  142.590678] RAX: 0000000000000002 RBX: 0000000000000000 RCX: ffff88813f6a2108
> [  142.597821] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000
> [  142.604962] RBP: ffffc900019ebbc0 R08: 0000000000000001 R09: 0000000000000000
> [  142.612101] R10: 0000000000000001 R11: 0000000000000001 R12: ffff88814107d600
> [  142.619242] R13: ffffc900019eba20 R14: ffff888140442000 R15: 0000000000000000
> [  142.626378] FS:  0000000000000000(0000) GS:ffff88849fa00000(0000) knlGS:0000000000000000
> [  142.634468] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [  142.640219] CR2: 0000000000000228 CR3: 000000010a4c0006 CR4: 0000000000770ee0
> [  142.647361] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> [  142.654505] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
> [  142.661639] PKRU: 55555554
> [  142.664367] Call Trace:
> [  142.666830]  <TASK>
> [  142.668947]  __xe_pt_bind_vma+0x1a1/0xa50 [xe]
> [  142.673417]  ? unwind_next_frame+0x187/0x770
> [  142.677699]  ? __thaw_task+0xc0/0xc0
> [  142.681293]  ? __lock_acquire+0x5e4/0x26e0
> [  142.685409]  ? lockdep_hardirqs_on+0xbf/0x140
> [  142.689779]  ? lock_acquire+0xd2/0x310
> [  142.693548]  ? mark_held_locks+0x49/0x80
> [  142.697485]  ? xe_vm_bind_vma+0xf1/0x3d0 [xe]
> [  142.701866]  xe_vm_bind_vma+0xf1/0x3d0 [xe]
> [  142.706082]  xe_vm_bind+0x76/0x140 [xe]
> [  142.709944]  vm_bind_ioctl+0x26f/0xb40 [xe]
> [  142.714161]  ? async_op_work_func+0x20c/0x450 [xe]
> [  142.718974]  async_op_work_func+0x20c/0x450 [xe]
> [  142.723620]  process_one_work+0x263/0x580
> [  142.727645]  ? process_one_work+0x580/0x580
> [  142.731839]  worker_thread+0x4d/0x3b0
> [  142.735518]  ? process_one_work+0x580/0x580
> [  142.739714]  kthread+0xeb/0x120
> [  142.742872]  ? kthread_complete_and_exit+0x20/0x20
> [  142.747671]  ret_from_fork+0x1f/0x30
> [  142.751264]  </TASK>
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_pt.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
> index c8b3b1975098..9e07ad41a007 100644
> --- a/drivers/gpu/drm/xe/xe_pt.c
> +++ b/drivers/gpu/drm/xe/xe_pt.c
> @@ -758,7 +758,7 @@ xe_pt_stage_bind(struct xe_gt *gt, struct xe_vma *vma,
>  		else
>  			xe_walk.cache = XE_CACHE_WB;
>  	}
> -	if (xe_bo_is_stolen(bo))
> +	if (!xe_vma_is_userptr(vma) && xe_bo_is_stolen(bo))
>  		xe_walk.dma_offset = xe_ttm_stolen_gpu_offset(xe_bo_device(bo));
>  
>  	xe_bo_assert_held(bo);
> -- 
> 2.38.1
>