* [PATCH v4 net 1/3] net: mediatek: sgmii: ensure the SGMII PHY is powered down on configuration
2023-01-25 18:15 [PATCH v4 net 0/3] fixes for mtk_eth_soc Bjørn Mork
@ 2023-01-25 18:16 ` Bjørn Mork
2023-01-26 7:29 ` Simon Horman
2023-01-25 18:16 ` [PATCH v4 net 2/3] net: mediatek: sgmii: fix duplex configuration Bjørn Mork
2023-01-25 18:16 ` [PATCH v4 net 3/3] mtk_sgmii: enable PCS polling to allow SFP work Bjørn Mork
2 siblings, 1 reply; 5+ messages in thread
From: Bjørn Mork @ 2023-01-25 18:16 UTC (permalink / raw)
To: netdev
Cc: Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Lorenzo Bianconi, Russell King, Daniel Golle, Alexander Couzens,
Simon Horman, Paolo Abeni, Russell King, Bjørn Mork
From: Alexander Couzens <lynxis@fe80.eu>
The code expect the PHY to be in power down which is only true after reset.
Allow changes of the SGMII parameters more than once.
Only power down when reconfiguring to avoid bouncing the link when there's
no reason to - based on code from Russell King.
There are cases when the SGMII_PHYA_PWD register contains 0x9 which
prevents SGMII from working. The SGMII still shows link but no traffic
can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
taken from a good working state of the SGMII interface.
Fixes: 42c03844e93d ("net-next: mediatek: add support for MediaTek MT7622 SoC")
Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
[ bmork: rebased and squashed into one patch ]
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 ++
drivers/net/ethernet/mediatek/mtk_sgmii.c | 39 +++++++++++++++------
2 files changed, 30 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 18a50529ce7b..b299a7df3c30 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -1037,10 +1037,12 @@ struct mtk_soc_data {
* SGMII modes
* @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
* @pcs: Phylink PCS structure
+ * @interface: Currently configured interface mode
*/
struct mtk_pcs {
struct regmap *regmap;
u32 ana_rgc3;
+ phy_interface_t interface;
struct phylink_pcs pcs;
};
diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethernet/mediatek/mtk_sgmii.c
index 5c286f2c9418..0a06995099cf 100644
--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
@@ -43,11 +43,6 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
int advertise, link_timer;
bool changed, use_an;
- if (interface == PHY_INTERFACE_MODE_2500BASEX)
- rgc3 = RG_PHY_SPEED_3_125G;
- else
- rgc3 = 0;
-
advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
advertising);
if (advertise < 0)
@@ -88,9 +83,22 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
bmcr = 0;
}
- /* Configure the underlying interface speed */
- regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
- RG_PHY_SPEED_3_125G, rgc3);
+ if (mpcs->interface != interface) {
+ /* PHYA power down */
+ regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
+ SGMII_PHYA_PWD, SGMII_PHYA_PWD);
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ rgc3 = RG_PHY_SPEED_3_125G;
+ else
+ rgc3 = 0;
+
+ /* Configure the underlying interface speed */
+ regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
+ RG_PHY_SPEED_3_125G, rgc3);
+
+ mpcs->interface = interface;
+ }
/* Update the advertisement, noting whether it has changed */
regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
@@ -108,9 +116,17 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
SGMII_AN_RESTART | SGMII_AN_ENABLE, bmcr);
- /* Release PHYA power down state */
- regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
- SGMII_PHYA_PWD, 0);
+ /* Release PHYA power down state
+ * Only removing bit SGMII_PHYA_PWD isn't enough.
+ * There are cases when the SGMII_PHYA_PWD register contains 0x9 which
+ * prevents SGMII from working. The SGMII still shows link but no traffic
+ * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
+ * taken from a good working state of the SGMII interface.
+ * Unknown how much the QPHY needs but it is racy without a sleep.
+ * Tested on mt7622 & mt7986.
+ */
+ usleep_range(50, 100);
+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
return changed;
}
@@ -171,6 +187,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
return PTR_ERR(ss->pcs[i].regmap);
ss->pcs[i].pcs.ops = &mtk_pcs_ops;
+ ss->pcs[i].interface = PHY_INTERFACE_MODE_NA;
}
return 0;
--
2.30.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v4 net 2/3] net: mediatek: sgmii: fix duplex configuration
2023-01-25 18:15 [PATCH v4 net 0/3] fixes for mtk_eth_soc Bjørn Mork
2023-01-25 18:16 ` [PATCH v4 net 1/3] net: mediatek: sgmii: ensure the SGMII PHY is powered down on configuration Bjørn Mork
@ 2023-01-25 18:16 ` Bjørn Mork
2023-01-25 18:16 ` [PATCH v4 net 3/3] mtk_sgmii: enable PCS polling to allow SFP work Bjørn Mork
2 siblings, 0 replies; 5+ messages in thread
From: Bjørn Mork @ 2023-01-25 18:16 UTC (permalink / raw)
To: netdev
Cc: Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Lorenzo Bianconi, Russell King, Daniel Golle, Alexander Couzens,
Simon Horman, Paolo Abeni, Bjørn Mork, Russell King
The logic of the duplex bit is inverted. Setting it means half
duplex, not full duplex.
Fix and rename macro to avoid confusion.
Fixes: 7e538372694b ("net: ethernet: mediatek: Re-add support SGMII")
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +-
drivers/net/ethernet/mediatek/mtk_sgmii.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index b299a7df3c30..966d8ed384ee 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -519,7 +519,7 @@
#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0)
#define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1)
#define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2)
-#define SGMII_DUPLEX_FULL BIT(4)
+#define SGMII_DUPLEX_HALF BIT(4)
#define SGMII_IF_MODE_BIT5 BIT(5)
#define SGMII_REMOTE_FAULT_DIS BIT(8)
#define SGMII_CODE_SYNC_SET_VAL BIT(9)
diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethernet/mediatek/mtk_sgmii.c
index 0a06995099cf..c4261069b521 100644
--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
@@ -154,11 +154,11 @@ static void mtk_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
else
sgm_mode = SGMII_SPEED_1000;
- if (duplex == DUPLEX_FULL)
- sgm_mode |= SGMII_DUPLEX_FULL;
+ if (duplex != DUPLEX_FULL)
+ sgm_mode |= SGMII_DUPLEX_HALF;
regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
- SGMII_DUPLEX_FULL | SGMII_SPEED_MASK,
+ SGMII_DUPLEX_HALF | SGMII_SPEED_MASK,
sgm_mode);
}
}
--
2.30.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v4 net 3/3] mtk_sgmii: enable PCS polling to allow SFP work
2023-01-25 18:15 [PATCH v4 net 0/3] fixes for mtk_eth_soc Bjørn Mork
2023-01-25 18:16 ` [PATCH v4 net 1/3] net: mediatek: sgmii: ensure the SGMII PHY is powered down on configuration Bjørn Mork
2023-01-25 18:16 ` [PATCH v4 net 2/3] net: mediatek: sgmii: fix duplex configuration Bjørn Mork
@ 2023-01-25 18:16 ` Bjørn Mork
2 siblings, 0 replies; 5+ messages in thread
From: Bjørn Mork @ 2023-01-25 18:16 UTC (permalink / raw)
To: netdev
Cc: Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Lorenzo Bianconi, Russell King, Daniel Golle, Alexander Couzens,
Simon Horman, Paolo Abeni, Russell King, Bjørn Mork
From: Alexander Couzens <lynxis@fe80.eu>
Currently there is no IRQ handling (even the SGMII supports it).
Enable polling to support SFP ports.
Fixes: 14a44ab0330d ("net: mtk_eth_soc: partially convert to phylink_pcs")
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
[ bmork: changed "1" => "true" ]
Signed-off-by: Bjørn Mork <bjorn@mork.no>
---
drivers/net/ethernet/mediatek/mtk_sgmii.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethernet/mediatek/mtk_sgmii.c
index c4261069b521..bb00de1003ac 100644
--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
@@ -187,6 +187,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
return PTR_ERR(ss->pcs[i].regmap);
ss->pcs[i].pcs.ops = &mtk_pcs_ops;
+ ss->pcs[i].pcs.poll = true;
ss->pcs[i].interface = PHY_INTERFACE_MODE_NA;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 5+ messages in thread