* [PATCH] tests/qtest/nvme-test: add persistent memory region test
[not found] <CGME20210618103850epcas5p49b85b7dc6e5f14b03b2bf35c10b3bdda@epcas5p4.samsung.com>
@ 2021-06-18 10:34 ` Gollu Appalanaidu
2021-06-28 17:07 ` Klaus Jensen
2021-07-09 6:58 ` Klaus Jensen
0 siblings, 2 replies; 3+ messages in thread
From: Gollu Appalanaidu @ 2021-06-18 10:34 UTC (permalink / raw)
To: qemu-devel
Cc: fam, kwolf, qemu-block, Gollu Appalanaidu, mreitz, its, stefanha, kbusch
This will test the PMR functionality.
Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com>
---
tests/qtest/nvme-test.c | 78 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 77 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c
index d32c953a38..6d557be6ca 100644
--- a/tests/qtest/nvme-test.c
+++ b/tests/qtest/nvme-test.c
@@ -13,6 +13,7 @@
#include "libqos/libqtest.h"
#include "libqos/qgraph.h"
#include "libqos/pci.h"
+#include "include/block/nvme.h"
typedef struct QNvme QNvme;
@@ -21,6 +22,9 @@ struct QNvme {
QPCIDevice dev;
};
+static char *t_path;
+#define TEST_IMAGE_SIZE (2 * 1024 * 1024)
+
static void *nvme_get_driver(void *obj, const char *interface)
{
QNvme *nvme = obj;
@@ -66,12 +70,77 @@ static void nvmetest_oob_cmb_test(void *obj, void *data, QGuestAllocator *alloc)
g_assert_cmpint(qpci_io_readl(pdev, bar, cmb_bar_size - 1), !=, 0x44332211);
}
+static void nvmetest_pmr_reg_test(void *obj, void *data, QGuestAllocator *alloc)
+{
+ QNvme *nvme = obj;
+ QPCIDevice *pdev = &nvme->dev;
+ QPCIBar pmr_bar, nvme_bar;
+ uint32_t pmrcap, pmrsts;
+
+ qpci_device_enable(pdev);
+ pmr_bar = qpci_iomap(pdev, 4, NULL);
+
+ /* Without Enabling PMRCTL check bar enablemet */
+ qpci_io_writel(pdev, pmr_bar, 0, 0xccbbaa99);
+ g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x99);
+ g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0xaa99);
+
+ /* Map NVMe Bar Register to Enable the Mem Region */
+ nvme_bar = qpci_iomap(pdev, 0, NULL);
+
+ pmrcap = qpci_io_readl(pdev, nvme_bar, 0xe00);
+ g_assert_cmpint(NVME_PMRCAP_RDS(pmrcap), ==, 0x1);
+ g_assert_cmpint(NVME_PMRCAP_WDS(pmrcap), ==, 0x1);
+ g_assert_cmpint(NVME_PMRCAP_BIR(pmrcap), ==, 0x4);
+ g_assert_cmpint(NVME_PMRCAP_PMRWBM(pmrcap), ==, 0x2);
+ g_assert_cmpint(NVME_PMRCAP_CMSS(pmrcap), ==, 0x1);
+
+ /* Enable PMRCTRL */
+ qpci_io_writel(pdev, nvme_bar, 0xe04, 0x1);
+
+ qpci_io_writel(pdev, pmr_bar, 0, 0x44332211);
+ g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), ==, 0x11);
+ g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), ==, 0x2211);
+ g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), ==, 0x44332211);
+
+ pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
+ g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x0);
+
+ /* Disable PMRCTRL */
+ qpci_io_writel(pdev, nvme_bar, 0xe04, 0x0);
+
+ qpci_io_writel(pdev, pmr_bar, 0, 0x88776655);
+ g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x55);
+ g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0x6655);
+ g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), !=, 0x88776655);
+
+ pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
+ g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x1);
+
+ qpci_iounmap(pdev, nvme_bar);
+ qpci_iounmap(pdev, pmr_bar);
+}
+
static void nvme_register_nodes(void)
{
+ int fd, ret;
+ t_path = g_strdup("/tmp/qtest.XXXXXX");
+
+ /* Create a temporary raw image*/
+ fd = mkstemp(t_path);
+ g_assert(fd >= 0);
+ ret = ftruncate(fd, TEST_IMAGE_SIZE);
+ g_assert(ret == 0);
+ close(fd);
+
+ char *pmr_cmd_line = g_strdup_printf("-object memory-backend-file,id=pmr0,"
+ "share=on,mem-path=%s,size=8", t_path);
+
QOSGraphEdgeOptions opts = {
.extra_device_opts = "addr=04.0,drive=drv0,serial=foo",
.before_cmd_line = "-drive id=drv0,if=none,file=null-co://,"
- "file.read-zeroes=on,format=raw",
+ "file.read-zeroes=on,format=raw ",
+ pmr_cmd_line,
};
add_qpci_address(&opts, &(QPCIAddress) { .devfn = QPCI_DEVFN(4, 0) });
@@ -83,6 +152,13 @@ static void nvme_register_nodes(void)
qos_add_test("oob-cmb-access", "nvme", nvmetest_oob_cmb_test, &(QOSGraphTestOptions) {
.edge.extra_device_opts = "cmb_size_mb=2"
});
+
+ qos_add_test("pmr-test-access", "nvme", nvmetest_pmr_reg_test,
+ &(QOSGraphTestOptions) {
+ .edge.extra_device_opts = "pmrdev=pmr0"
+ });
+
+ unlink(t_path);
}
libqos_init(nvme_register_nodes);
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] tests/qtest/nvme-test: add persistent memory region test
2021-06-18 10:34 ` [PATCH] tests/qtest/nvme-test: add persistent memory region test Gollu Appalanaidu
@ 2021-06-28 17:07 ` Klaus Jensen
2021-07-09 6:58 ` Klaus Jensen
1 sibling, 0 replies; 3+ messages in thread
From: Klaus Jensen @ 2021-06-28 17:07 UTC (permalink / raw)
To: Gollu Appalanaidu
Cc: fam, kwolf, qemu-block, qemu-devel, mreitz, stefanha, kbusch
[-- Attachment #1: Type: text/plain, Size: 4598 bytes --]
On Jun 18 16:04, Gollu Appalanaidu wrote:
>This will test the PMR functionality.
>
>Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com>
>---
> tests/qtest/nvme-test.c | 78 ++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 77 insertions(+), 1 deletion(-)
>
>diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c
>index d32c953a38..6d557be6ca 100644
>--- a/tests/qtest/nvme-test.c
>+++ b/tests/qtest/nvme-test.c
>@@ -13,6 +13,7 @@
> #include "libqos/libqtest.h"
> #include "libqos/qgraph.h"
> #include "libqos/pci.h"
>+#include "include/block/nvme.h"
>
> typedef struct QNvme QNvme;
>
>@@ -21,6 +22,9 @@ struct QNvme {
> QPCIDevice dev;
> };
>
>+static char *t_path;
>+#define TEST_IMAGE_SIZE (2 * 1024 * 1024)
>+
> static void *nvme_get_driver(void *obj, const char *interface)
> {
> QNvme *nvme = obj;
>@@ -66,12 +70,77 @@ static void nvmetest_oob_cmb_test(void *obj, void *data, QGuestAllocator *alloc)
> g_assert_cmpint(qpci_io_readl(pdev, bar, cmb_bar_size - 1), !=, 0x44332211);
> }
>
>+static void nvmetest_pmr_reg_test(void *obj, void *data, QGuestAllocator *alloc)
>+{
>+ QNvme *nvme = obj;
>+ QPCIDevice *pdev = &nvme->dev;
>+ QPCIBar pmr_bar, nvme_bar;
>+ uint32_t pmrcap, pmrsts;
>+
>+ qpci_device_enable(pdev);
>+ pmr_bar = qpci_iomap(pdev, 4, NULL);
>+
>+ /* Without Enabling PMRCTL check bar enablemet */
>+ qpci_io_writel(pdev, pmr_bar, 0, 0xccbbaa99);
>+ g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x99);
>+ g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0xaa99);
>+
>+ /* Map NVMe Bar Register to Enable the Mem Region */
>+ nvme_bar = qpci_iomap(pdev, 0, NULL);
>+
>+ pmrcap = qpci_io_readl(pdev, nvme_bar, 0xe00);
>+ g_assert_cmpint(NVME_PMRCAP_RDS(pmrcap), ==, 0x1);
>+ g_assert_cmpint(NVME_PMRCAP_WDS(pmrcap), ==, 0x1);
>+ g_assert_cmpint(NVME_PMRCAP_BIR(pmrcap), ==, 0x4);
>+ g_assert_cmpint(NVME_PMRCAP_PMRWBM(pmrcap), ==, 0x2);
>+ g_assert_cmpint(NVME_PMRCAP_CMSS(pmrcap), ==, 0x1);
>+
>+ /* Enable PMRCTRL */
>+ qpci_io_writel(pdev, nvme_bar, 0xe04, 0x1);
>+
>+ qpci_io_writel(pdev, pmr_bar, 0, 0x44332211);
>+ g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), ==, 0x11);
>+ g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), ==, 0x2211);
>+ g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), ==, 0x44332211);
>+
>+ pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
>+ g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x0);
>+
>+ /* Disable PMRCTRL */
>+ qpci_io_writel(pdev, nvme_bar, 0xe04, 0x0);
>+
>+ qpci_io_writel(pdev, pmr_bar, 0, 0x88776655);
>+ g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x55);
>+ g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0x6655);
>+ g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), !=, 0x88776655);
>+
>+ pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
>+ g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x1);
>+
>+ qpci_iounmap(pdev, nvme_bar);
>+ qpci_iounmap(pdev, pmr_bar);
>+}
>+
> static void nvme_register_nodes(void)
> {
>+ int fd, ret;
>+ t_path = g_strdup("/tmp/qtest.XXXXXX");
>+
>+ /* Create a temporary raw image*/
>+ fd = mkstemp(t_path);
>+ g_assert(fd >= 0);
>+ ret = ftruncate(fd, TEST_IMAGE_SIZE);
>+ g_assert(ret == 0);
>+ close(fd);
>+
>+ char *pmr_cmd_line = g_strdup_printf("-object memory-backend-file,id=pmr0,"
>+ "share=on,mem-path=%s,size=8", t_path);
>+
> QOSGraphEdgeOptions opts = {
> .extra_device_opts = "addr=04.0,drive=drv0,serial=foo",
> .before_cmd_line = "-drive id=drv0,if=none,file=null-co://,"
>- "file.read-zeroes=on,format=raw",
>+ "file.read-zeroes=on,format=raw ",
>+ pmr_cmd_line,
> };
>
> add_qpci_address(&opts, &(QPCIAddress) { .devfn = QPCI_DEVFN(4, 0) });
>@@ -83,6 +152,13 @@ static void nvme_register_nodes(void)
> qos_add_test("oob-cmb-access", "nvme", nvmetest_oob_cmb_test, &(QOSGraphTestOptions) {
> .edge.extra_device_opts = "cmb_size_mb=2"
> });
>+
>+ qos_add_test("pmr-test-access", "nvme", nvmetest_pmr_reg_test,
>+ &(QOSGraphTestOptions) {
>+ .edge.extra_device_opts = "pmrdev=pmr0"
>+ });
>+
>+ unlink(t_path);
> }
>
> libqos_init(nvme_register_nodes);
>--
>2.17.1
>
An extra test is always nice and looks fine,
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] tests/qtest/nvme-test: add persistent memory region test
2021-06-18 10:34 ` [PATCH] tests/qtest/nvme-test: add persistent memory region test Gollu Appalanaidu
2021-06-28 17:07 ` Klaus Jensen
@ 2021-07-09 6:58 ` Klaus Jensen
1 sibling, 0 replies; 3+ messages in thread
From: Klaus Jensen @ 2021-07-09 6:58 UTC (permalink / raw)
To: Gollu Appalanaidu
Cc: fam, kwolf, qemu-block, qemu-devel, mreitz, stefanha, kbusch
[-- Attachment #1: Type: text/plain, Size: 4627 bytes --]
On Jun 18 16:04, Gollu Appalanaidu wrote:
>This will test the PMR functionality.
>
>Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com>
>---
> tests/qtest/nvme-test.c | 78 ++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 77 insertions(+), 1 deletion(-)
>
>diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c
>index d32c953a38..6d557be6ca 100644
>--- a/tests/qtest/nvme-test.c
>+++ b/tests/qtest/nvme-test.c
>@@ -13,6 +13,7 @@
> #include "libqos/libqtest.h"
> #include "libqos/qgraph.h"
> #include "libqos/pci.h"
>+#include "include/block/nvme.h"
>
> typedef struct QNvme QNvme;
>
>@@ -21,6 +22,9 @@ struct QNvme {
> QPCIDevice dev;
> };
>
>+static char *t_path;
>+#define TEST_IMAGE_SIZE (2 * 1024 * 1024)
>+
> static void *nvme_get_driver(void *obj, const char *interface)
> {
> QNvme *nvme = obj;
>@@ -66,12 +70,77 @@ static void nvmetest_oob_cmb_test(void *obj, void *data, QGuestAllocator *alloc)
> g_assert_cmpint(qpci_io_readl(pdev, bar, cmb_bar_size - 1), !=, 0x44332211);
> }
>
>+static void nvmetest_pmr_reg_test(void *obj, void *data, QGuestAllocator *alloc)
>+{
>+ QNvme *nvme = obj;
>+ QPCIDevice *pdev = &nvme->dev;
>+ QPCIBar pmr_bar, nvme_bar;
>+ uint32_t pmrcap, pmrsts;
>+
>+ qpci_device_enable(pdev);
>+ pmr_bar = qpci_iomap(pdev, 4, NULL);
>+
>+ /* Without Enabling PMRCTL check bar enablemet */
>+ qpci_io_writel(pdev, pmr_bar, 0, 0xccbbaa99);
>+ g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x99);
>+ g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0xaa99);
>+
>+ /* Map NVMe Bar Register to Enable the Mem Region */
>+ nvme_bar = qpci_iomap(pdev, 0, NULL);
>+
>+ pmrcap = qpci_io_readl(pdev, nvme_bar, 0xe00);
>+ g_assert_cmpint(NVME_PMRCAP_RDS(pmrcap), ==, 0x1);
>+ g_assert_cmpint(NVME_PMRCAP_WDS(pmrcap), ==, 0x1);
>+ g_assert_cmpint(NVME_PMRCAP_BIR(pmrcap), ==, 0x4);
>+ g_assert_cmpint(NVME_PMRCAP_PMRWBM(pmrcap), ==, 0x2);
>+ g_assert_cmpint(NVME_PMRCAP_CMSS(pmrcap), ==, 0x1);
>+
>+ /* Enable PMRCTRL */
>+ qpci_io_writel(pdev, nvme_bar, 0xe04, 0x1);
>+
>+ qpci_io_writel(pdev, pmr_bar, 0, 0x44332211);
>+ g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), ==, 0x11);
>+ g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), ==, 0x2211);
>+ g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), ==, 0x44332211);
>+
>+ pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
>+ g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x0);
>+
>+ /* Disable PMRCTRL */
>+ qpci_io_writel(pdev, nvme_bar, 0xe04, 0x0);
>+
>+ qpci_io_writel(pdev, pmr_bar, 0, 0x88776655);
>+ g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x55);
>+ g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0x6655);
>+ g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), !=, 0x88776655);
>+
>+ pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
>+ g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x1);
>+
>+ qpci_iounmap(pdev, nvme_bar);
>+ qpci_iounmap(pdev, pmr_bar);
>+}
>+
> static void nvme_register_nodes(void)
> {
>+ int fd, ret;
>+ t_path = g_strdup("/tmp/qtest.XXXXXX");
>+
>+ /* Create a temporary raw image*/
>+ fd = mkstemp(t_path);
>+ g_assert(fd >= 0);
>+ ret = ftruncate(fd, TEST_IMAGE_SIZE);
>+ g_assert(ret == 0);
>+ close(fd);
>+
>+ char *pmr_cmd_line = g_strdup_printf("-object memory-backend-file,id=pmr0,"
>+ "share=on,mem-path=%s,size=8", t_path);
>+
> QOSGraphEdgeOptions opts = {
> .extra_device_opts = "addr=04.0,drive=drv0,serial=foo",
> .before_cmd_line = "-drive id=drv0,if=none,file=null-co://,"
>- "file.read-zeroes=on,format=raw",
>+ "file.read-zeroes=on,format=raw ",
>+ pmr_cmd_line,
> };
>
> add_qpci_address(&opts, &(QPCIAddress) { .devfn = QPCI_DEVFN(4, 0) });
>@@ -83,6 +152,13 @@ static void nvme_register_nodes(void)
> qos_add_test("oob-cmb-access", "nvme", nvmetest_oob_cmb_test, &(QOSGraphTestOptions) {
> .edge.extra_device_opts = "cmb_size_mb=2"
> });
>+
>+ qos_add_test("pmr-test-access", "nvme", nvmetest_pmr_reg_test,
>+ &(QOSGraphTestOptions) {
>+ .edge.extra_device_opts = "pmrdev=pmr0"
>+ });
>+
>+ unlink(t_path);
> }
>
> libqos_init(nvme_register_nodes);
>--
>2.17.1
>
Applied to nvme-next. I swapped the memory-backend-file with a
memory-backend-ram so we don't need to setup an actual file.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
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[not found] <CGME20210618103850epcas5p49b85b7dc6e5f14b03b2bf35c10b3bdda@epcas5p4.samsung.com>
2021-06-18 10:34 ` [PATCH] tests/qtest/nvme-test: add persistent memory region test Gollu Appalanaidu
2021-06-28 17:07 ` Klaus Jensen
2021-07-09 6:58 ` Klaus Jensen
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