* [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
@ 2021-07-09 11:41 ` Maarten Lankhorst
0 siblings, 0 replies; 18+ messages in thread
From: Maarten Lankhorst @ 2021-07-09 11:41 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
This is only used for ttm, and tells userspace that the mapping type is
ignored. This disables the other type of mmap offsets when discrete
memory is used, so fix the selftests as well.
Document the struct as well, so it shows up in docbook correctly.
Changes since v1:
- Add docbook entries.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
.../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
4 files changed, 82 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index a90f796e85c0..b34be9e5d094 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
return -ENODEV;
if (obj->ops->mmap_offset) {
+ if (mmap_type != I915_MMAP_TYPE_TTM)
+ return -ENODEV;
+
*offset = obj->ops->mmap_offset(obj);
return 0;
}
+ if (mmap_type == I915_MMAP_TYPE_TTM)
+ return -ENODEV;
+
if (mmap_type != I915_MMAP_TYPE_GTT &&
!i915_gem_object_has_struct_page(obj) &&
!i915_gem_object_has_iomem(obj))
@@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
{
enum i915_mmap_type mmap_type;
- if (boot_cpu_has(X86_FEATURE_PAT))
+ if (HAS_LMEM(to_i915(dev)))
+ mmap_type = I915_MMAP_TYPE_TTM;
+ else if (boot_cpu_has(X86_FEATURE_PAT))
mmap_type = I915_MMAP_TYPE_WC;
else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
return -ENODEV;
@@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
type = I915_MMAP_TYPE_UC;
break;
+ case I915_MMAP_OFFSET_TTM:
+ type = I915_MMAP_TYPE_TTM;
+ break;
+
default:
return -EINVAL;
}
@@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
vma->vm_ops = &vm_ops_cpu;
break;
+ case I915_MMAP_TYPE_TTM:
+ GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
+ /* fall-through */
case I915_MMAP_TYPE_WB:
vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
vma->vm_ops = &vm_ops_cpu;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index ef3de2ae9723..d4c42bcdfeb6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -105,6 +105,7 @@ enum i915_mmap_type {
I915_MMAP_TYPE_WC,
I915_MMAP_TYPE_WB,
I915_MMAP_TYPE_UC,
+ I915_MMAP_TYPE_TTM,
};
struct i915_mmap_offset {
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 1da8bd675e54..27a35d88e5f5 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
return 0;
}
+static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
+{
+ if (HAS_LMEM(i915))
+ return I915_MMAP_TYPE_TTM;
+
+ return I915_MMAP_TYPE_GTT;
+}
+
static bool assert_mmap_offset(struct drm_i915_private *i915,
unsigned long size,
int expected)
@@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
if (IS_ERR(obj))
return expected && expected == PTR_ERR(obj);
- ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
+ ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
i915_gem_object_put(obj);
return ret == expected;
@@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
goto out;
}
- err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
+ err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
if (err) {
pr_err("Unable to insert object into reclaimed hole\n");
goto err_obj;
@@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
bool no_map;
+ if (HAS_LMEM(i915))
+ return type == I915_MMAP_TYPE_TTM;
+ else if (type == I915_MMAP_TYPE_TTM)
+ return false;
+
if (type == I915_MMAP_TYPE_GTT &&
!i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
return false;
@@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
if (err == 0)
err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
+ if (err == 0)
+ err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
i915_gem_object_put(obj);
if (err)
@@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
case I915_MMAP_TYPE_WB: return "wb";
case I915_MMAP_TYPE_WC: return "wc";
case I915_MMAP_TYPE_UC: return "uc";
+ case I915_MMAP_TYPE_TTM: return "ttm";
default: return "unknown";
}
}
@@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
if (err == 0)
err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
+ if (err == 0)
+ err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
i915_gem_object_put(obj);
if (err)
@@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
if (err == 0)
err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
+ if (err == 0)
+ err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
i915_gem_object_put(obj);
if (err)
@@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
if (err == 0)
err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
+ if (err == 0)
+ err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
i915_gem_object_put(obj);
if (err)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index e334a8b14ef2..1610ed40b4b5 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
__u64 offset;
};
+/**
+ * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
+ *
+ * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
+ * and is used to retrieve the fake offset to mmap an object specified by &handle.
+ *
+ * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
+ * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
+ * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
+ */
struct drm_i915_gem_mmap_offset {
- /** Handle for the object being mapped. */
+ /** @handle: Handle for the object being mapped. */
__u32 handle;
+ /** @pad: Must be zero */
__u32 pad;
/**
- * Fake offset to use for subsequent mmap call
+ * @offset: The fake offset to use for subsequent mmap call
*
* This is a fixed-size type for 32/64 compatibility.
*/
__u64 offset;
/**
- * Flags for extended behaviour.
+ * @flags: Flags for extended behaviour.
+ *
+ * It is mandatory that one of the `MMAP_OFFSET` types
+ * should be included:
+ * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
+ * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
+ * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
+ * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
+ *
+ * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
+ * devices without local memory, this caching mode is invalid.
*
- * It is mandatory that one of the MMAP_OFFSET types
- * (GTT, WC, WB, UC, etc) should be included.
+ * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
+ * be used, depending on the object placement. WC will be used
+ * when the object resides in local memory, WB otherwise.
*/
__u64 flags;
-#define I915_MMAP_OFFSET_GTT 0
-#define I915_MMAP_OFFSET_WC 1
-#define I915_MMAP_OFFSET_WB 2
-#define I915_MMAP_OFFSET_UC 3
- /*
- * Zero-terminated chain of extensions.
+/** Use an mmap for the object by binding to GTT. */
+#define I915_MMAP_OFFSET_GTT 0
+/** Use Write-Combined caching. */
+#define I915_MMAP_OFFSET_WC 1
+/** Use Write-Back caching. */
+#define I915_MMAP_OFFSET_WB 2
+/** Do not use caching when binding this mmap. */
+#define I915_MMAP_OFFSET_UC 3
+/** Use the TTM binding, which determines the appropriate caching mode. */
+#define I915_MMAP_OFFSET_TTM 4
+
+ /**
+ * @extensions: Zero-terminated chain of extensions.
*
* No current extensions defined; mbz.
*/
--
2.31.0
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^ permalink raw reply related [flat|nested] 18+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add TTM offset argument to mmap. (rev2)
2021-07-09 11:41 ` [Intel-gfx] " Maarten Lankhorst
(?)
@ 2021-07-09 12:44 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2021-07-09 12:44 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Add TTM offset argument to mmap. (rev2)
URL : https://patchwork.freedesktop.org/series/92103/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
53107c2bf2c8 drm/i915: Add TTM offset argument to mmap.
-:66: WARNING:PREFER_FALLTHROUGH: Prefer 'fallthrough;' over fallthrough comment
#66: FILE: drivers/gpu/drm/i915/gem/i915_gem_mman.c:985:
+ /* fall-through */
total: 0 errors, 1 warnings, 0 checks, 206 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add TTM offset argument to mmap. (rev2)
2021-07-09 11:41 ` [Intel-gfx] " Maarten Lankhorst
(?)
(?)
@ 2021-07-09 13:11 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2021-07-09 13:11 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 1730 bytes --]
== Series Details ==
Series: drm/i915: Add TTM offset argument to mmap. (rev2)
URL : https://patchwork.freedesktop.org/series/92103/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10324 -> Patchwork_20562
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/index.html
Known issues
------------
Here are the changes found in Patchwork_20562 that come from known issues:
### IGT changes ###
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3717]: https://gitlab.freedesktop.org/drm/intel/issues/3717
[i915#3744]: https://gitlab.freedesktop.org/drm/intel/issues/3744
Participating hosts (40 -> 39)
------------------------------
Missing (1): fi-bsw-cyan
Build changes
-------------
* Linux: CI_DRM_10324 -> Patchwork_20562
CI-20190529: 20190529
CI_DRM_10324: 1db44678139ded724c2cd42b6b1c95574fe36047 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6133: b5c6b973e7f7d33e7521825e39ddd380e80af01a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20562: 53107c2bf2c8fd4aa4469649d2cc183bba2f8933 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
53107c2bf2c8 drm/i915: Add TTM offset argument to mmap.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/index.html
[-- Attachment #1.2: Type: text/html, Size: 1966 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
2021-07-09 11:41 ` [Intel-gfx] " Maarten Lankhorst
@ 2021-07-09 14:55 ` Daniel Vetter
-1 siblings, 0 replies; 18+ messages in thread
From: Daniel Vetter @ 2021-07-09 14:55 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx, dri-devel
On Fri, Jul 9, 2021 at 1:41 PM Maarten Lankhorst
<maarten.lankhorst@linux.intel.com> wrote:
>
> This is only used for ttm, and tells userspace that the mapping type is
> ignored. This disables the other type of mmap offsets when discrete
> memory is used, so fix the selftests as well.
>
> Document the struct as well, so it shows up in docbook correctly.
>
> Changes since v1:
> - Add docbook entries.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> .../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
> include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
> 4 files changed, 82 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index a90f796e85c0..b34be9e5d094 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
> return -ENODEV;
>
> if (obj->ops->mmap_offset) {
> + if (mmap_type != I915_MMAP_TYPE_TTM)
> + return -ENODEV;
> +
> *offset = obj->ops->mmap_offset(obj);
> return 0;
> }
>
> + if (mmap_type == I915_MMAP_TYPE_TTM)
> + return -ENODEV;
> +
> if (mmap_type != I915_MMAP_TYPE_GTT &&
> !i915_gem_object_has_struct_page(obj) &&
> !i915_gem_object_has_iomem(obj))
> @@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
> {
> enum i915_mmap_type mmap_type;
>
> - if (boot_cpu_has(X86_FEATURE_PAT))
> + if (HAS_LMEM(to_i915(dev)))
> + mmap_type = I915_MMAP_TYPE_TTM;
> + else if (boot_cpu_has(X86_FEATURE_PAT))
> mmap_type = I915_MMAP_TYPE_WC;
> else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
> return -ENODEV;
> @@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> type = I915_MMAP_TYPE_UC;
> break;
>
> + case I915_MMAP_OFFSET_TTM:
> + type = I915_MMAP_TYPE_TTM;
> + break;
> +
> default:
> return -EINVAL;
> }
> @@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> vma->vm_ops = &vm_ops_cpu;
> break;
>
> + case I915_MMAP_TYPE_TTM:
> + GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
This makse no sense at all, or at least it's very confused - the
conditiona is always 1, so just put that in there.. Also the ttm case
is taken care of a bit earlier, it would be good to maybe have another
check that the mmap_type is TTM.
Also long-term I think would be neat if we could just outright move to
the standard handler again, and leave this mess to old platforms.
> + /* fall-through */
> case I915_MMAP_TYPE_WB:
> vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> vma->vm_ops = &vm_ops_cpu;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index ef3de2ae9723..d4c42bcdfeb6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -105,6 +105,7 @@ enum i915_mmap_type {
> I915_MMAP_TYPE_WC,
> I915_MMAP_TYPE_WB,
> I915_MMAP_TYPE_UC,
> + I915_MMAP_TYPE_TTM,
> };
>
> struct i915_mmap_offset {
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> index 1da8bd675e54..27a35d88e5f5 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> @@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
> return 0;
> }
>
> +static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
> +{
> + if (HAS_LMEM(i915))
> + return I915_MMAP_TYPE_TTM;
> +
> + return I915_MMAP_TYPE_GTT;
> +}
> +
> static bool assert_mmap_offset(struct drm_i915_private *i915,
> unsigned long size,
> int expected)
> @@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
> if (IS_ERR(obj))
> return expected && expected == PTR_ERR(obj);
>
> - ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> + ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> i915_gem_object_put(obj);
>
> return ret == expected;
> @@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
> goto out;
> }
>
> - err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> + err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> if (err) {
> pr_err("Unable to insert object into reclaimed hole\n");
> goto err_obj;
> @@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
>
> static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
> {
> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> bool no_map;
>
> + if (HAS_LMEM(i915))
> + return type == I915_MMAP_TYPE_TTM;
> + else if (type == I915_MMAP_TYPE_TTM)
> + return false;
> +
> if (type == I915_MMAP_TYPE_GTT &&
> !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
> return false;
> @@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
> err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
> if (err == 0)
> err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
> + if (err == 0)
> + err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
Would be nice to have a wrapper for this. We probably need the same
fallback for igt in userspace. Something like igt_mmap_wc_fallbacks
(since on some really old platforms WC mmaps are not actually very
reliable and you really want the GTT wc).
>
> i915_gem_object_put(obj);
> if (err)
> @@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
> case I915_MMAP_TYPE_WB: return "wb";
> case I915_MMAP_TYPE_WC: return "wc";
> case I915_MMAP_TYPE_UC: return "uc";
> + case I915_MMAP_TYPE_TTM: return "ttm";
> default: return "unknown";
> }
> }
> @@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
> err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
> if (err == 0)
> err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
> + if (err == 0)
> + err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> @@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
> err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
> if (err == 0)
> err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
> + if (err == 0)
> + err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> @@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
> err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
> if (err == 0)
> err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
> + if (err == 0)
> + err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index e334a8b14ef2..1610ed40b4b5 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
> __u64 offset;
> };
>
> +/**
> + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> + *
> + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> + *
> + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> + */
> struct drm_i915_gem_mmap_offset {
> - /** Handle for the object being mapped. */
> + /** @handle: Handle for the object being mapped. */
> __u32 handle;
> + /** @pad: Must be zero */
> __u32 pad;
> /**
> - * Fake offset to use for subsequent mmap call
> + * @offset: The fake offset to use for subsequent mmap call
> *
> * This is a fixed-size type for 32/64 compatibility.
> */
> __u64 offset;
>
> /**
> - * Flags for extended behaviour.
> + * @flags: Flags for extended behaviour.
> + *
> + * It is mandatory that one of the `MMAP_OFFSET` types
> + * should be included:
> + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
GTT mmaps are also always WC.
> + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> + * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
> + *
> + * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
"On devices with local memory only `I915_MMAP_OFFSET_TTM` is valid."
> + * devices without local memory, this caching mode is invalid.
> *
> - * It is mandatory that one of the MMAP_OFFSET types
> - * (GTT, WC, WB, UC, etc) should be included.
> + * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
> + * be used, depending on the object placement. WC will be used
> + * when the object resides in local memory, WB otherwise.
I think Matt typed up a nice overview of the TTM mmap/coherency rules.
Please sync with map and just put a link to his stuff here.
> */
> __u64 flags;
> -#define I915_MMAP_OFFSET_GTT 0
> -#define I915_MMAP_OFFSET_WC 1
> -#define I915_MMAP_OFFSET_WB 2
> -#define I915_MMAP_OFFSET_UC 3
>
> - /*
> - * Zero-terminated chain of extensions.
> +/** Use an mmap for the object by binding to GTT. */
This /** I expect will confuse kerneldoc? Imo just remove these
comments, you have the list above.
> +#define I915_MMAP_OFFSET_GTT 0
> +/** Use Write-Combined caching. */
> +#define I915_MMAP_OFFSET_WC 1
> +/** Use Write-Back caching. */
> +#define I915_MMAP_OFFSET_WB 2
> +/** Do not use caching when binding this mmap. */
> +#define I915_MMAP_OFFSET_UC 3
> +/** Use the TTM binding, which determines the appropriate caching mode. */
> +#define I915_MMAP_OFFSET_TTM 4
> +
> + /**
> + * @extensions: Zero-terminated chain of extensions.
> *
> * No current extensions defined; mbz.
> */
> --
> 2.31.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
With the nits&issues addressed:
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Also pls make sure Jason or Ken ack this too.
Finally ... igt impact?
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
@ 2021-07-09 14:55 ` Daniel Vetter
0 siblings, 0 replies; 18+ messages in thread
From: Daniel Vetter @ 2021-07-09 14:55 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx, dri-devel
On Fri, Jul 9, 2021 at 1:41 PM Maarten Lankhorst
<maarten.lankhorst@linux.intel.com> wrote:
>
> This is only used for ttm, and tells userspace that the mapping type is
> ignored. This disables the other type of mmap offsets when discrete
> memory is used, so fix the selftests as well.
>
> Document the struct as well, so it shows up in docbook correctly.
>
> Changes since v1:
> - Add docbook entries.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> .../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
> include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
> 4 files changed, 82 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index a90f796e85c0..b34be9e5d094 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
> return -ENODEV;
>
> if (obj->ops->mmap_offset) {
> + if (mmap_type != I915_MMAP_TYPE_TTM)
> + return -ENODEV;
> +
> *offset = obj->ops->mmap_offset(obj);
> return 0;
> }
>
> + if (mmap_type == I915_MMAP_TYPE_TTM)
> + return -ENODEV;
> +
> if (mmap_type != I915_MMAP_TYPE_GTT &&
> !i915_gem_object_has_struct_page(obj) &&
> !i915_gem_object_has_iomem(obj))
> @@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
> {
> enum i915_mmap_type mmap_type;
>
> - if (boot_cpu_has(X86_FEATURE_PAT))
> + if (HAS_LMEM(to_i915(dev)))
> + mmap_type = I915_MMAP_TYPE_TTM;
> + else if (boot_cpu_has(X86_FEATURE_PAT))
> mmap_type = I915_MMAP_TYPE_WC;
> else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
> return -ENODEV;
> @@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> type = I915_MMAP_TYPE_UC;
> break;
>
> + case I915_MMAP_OFFSET_TTM:
> + type = I915_MMAP_TYPE_TTM;
> + break;
> +
> default:
> return -EINVAL;
> }
> @@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> vma->vm_ops = &vm_ops_cpu;
> break;
>
> + case I915_MMAP_TYPE_TTM:
> + GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
This makse no sense at all, or at least it's very confused - the
conditiona is always 1, so just put that in there.. Also the ttm case
is taken care of a bit earlier, it would be good to maybe have another
check that the mmap_type is TTM.
Also long-term I think would be neat if we could just outright move to
the standard handler again, and leave this mess to old platforms.
> + /* fall-through */
> case I915_MMAP_TYPE_WB:
> vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> vma->vm_ops = &vm_ops_cpu;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index ef3de2ae9723..d4c42bcdfeb6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -105,6 +105,7 @@ enum i915_mmap_type {
> I915_MMAP_TYPE_WC,
> I915_MMAP_TYPE_WB,
> I915_MMAP_TYPE_UC,
> + I915_MMAP_TYPE_TTM,
> };
>
> struct i915_mmap_offset {
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> index 1da8bd675e54..27a35d88e5f5 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> @@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
> return 0;
> }
>
> +static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
> +{
> + if (HAS_LMEM(i915))
> + return I915_MMAP_TYPE_TTM;
> +
> + return I915_MMAP_TYPE_GTT;
> +}
> +
> static bool assert_mmap_offset(struct drm_i915_private *i915,
> unsigned long size,
> int expected)
> @@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
> if (IS_ERR(obj))
> return expected && expected == PTR_ERR(obj);
>
> - ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> + ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> i915_gem_object_put(obj);
>
> return ret == expected;
> @@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
> goto out;
> }
>
> - err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> + err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> if (err) {
> pr_err("Unable to insert object into reclaimed hole\n");
> goto err_obj;
> @@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
>
> static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
> {
> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> bool no_map;
>
> + if (HAS_LMEM(i915))
> + return type == I915_MMAP_TYPE_TTM;
> + else if (type == I915_MMAP_TYPE_TTM)
> + return false;
> +
> if (type == I915_MMAP_TYPE_GTT &&
> !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
> return false;
> @@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
> err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
> if (err == 0)
> err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
> + if (err == 0)
> + err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
Would be nice to have a wrapper for this. We probably need the same
fallback for igt in userspace. Something like igt_mmap_wc_fallbacks
(since on some really old platforms WC mmaps are not actually very
reliable and you really want the GTT wc).
>
> i915_gem_object_put(obj);
> if (err)
> @@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
> case I915_MMAP_TYPE_WB: return "wb";
> case I915_MMAP_TYPE_WC: return "wc";
> case I915_MMAP_TYPE_UC: return "uc";
> + case I915_MMAP_TYPE_TTM: return "ttm";
> default: return "unknown";
> }
> }
> @@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
> err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
> if (err == 0)
> err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
> + if (err == 0)
> + err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> @@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
> err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
> if (err == 0)
> err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
> + if (err == 0)
> + err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> @@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
> err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
> if (err == 0)
> err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
> + if (err == 0)
> + err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index e334a8b14ef2..1610ed40b4b5 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
> __u64 offset;
> };
>
> +/**
> + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> + *
> + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> + *
> + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> + */
> struct drm_i915_gem_mmap_offset {
> - /** Handle for the object being mapped. */
> + /** @handle: Handle for the object being mapped. */
> __u32 handle;
> + /** @pad: Must be zero */
> __u32 pad;
> /**
> - * Fake offset to use for subsequent mmap call
> + * @offset: The fake offset to use for subsequent mmap call
> *
> * This is a fixed-size type for 32/64 compatibility.
> */
> __u64 offset;
>
> /**
> - * Flags for extended behaviour.
> + * @flags: Flags for extended behaviour.
> + *
> + * It is mandatory that one of the `MMAP_OFFSET` types
> + * should be included:
> + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
GTT mmaps are also always WC.
> + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> + * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
> + *
> + * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
"On devices with local memory only `I915_MMAP_OFFSET_TTM` is valid."
> + * devices without local memory, this caching mode is invalid.
> *
> - * It is mandatory that one of the MMAP_OFFSET types
> - * (GTT, WC, WB, UC, etc) should be included.
> + * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
> + * be used, depending on the object placement. WC will be used
> + * when the object resides in local memory, WB otherwise.
I think Matt typed up a nice overview of the TTM mmap/coherency rules.
Please sync with map and just put a link to his stuff here.
> */
> __u64 flags;
> -#define I915_MMAP_OFFSET_GTT 0
> -#define I915_MMAP_OFFSET_WC 1
> -#define I915_MMAP_OFFSET_WB 2
> -#define I915_MMAP_OFFSET_UC 3
>
> - /*
> - * Zero-terminated chain of extensions.
> +/** Use an mmap for the object by binding to GTT. */
This /** I expect will confuse kerneldoc? Imo just remove these
comments, you have the list above.
> +#define I915_MMAP_OFFSET_GTT 0
> +/** Use Write-Combined caching. */
> +#define I915_MMAP_OFFSET_WC 1
> +/** Use Write-Back caching. */
> +#define I915_MMAP_OFFSET_WB 2
> +/** Do not use caching when binding this mmap. */
> +#define I915_MMAP_OFFSET_UC 3
> +/** Use the TTM binding, which determines the appropriate caching mode. */
> +#define I915_MMAP_OFFSET_TTM 4
> +
> + /**
> + * @extensions: Zero-terminated chain of extensions.
> *
> * No current extensions defined; mbz.
> */
> --
> 2.31.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
With the nits&issues addressed:
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Also pls make sure Jason or Ken ack this too.
Finally ... igt impact?
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add TTM offset argument to mmap. (rev2)
2021-07-09 11:41 ` [Intel-gfx] " Maarten Lankhorst
` (3 preceding siblings ...)
(?)
@ 2021-07-10 5:31 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2021-07-10 5:31 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30272 bytes --]
== Series Details ==
Series: drm/i915: Add TTM offset argument to mmap. (rev2)
URL : https://patchwork.freedesktop.org/series/92103/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10324_full -> Patchwork_20562_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20562_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20562_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20562_full:
### CI changes ###
#### Possible regressions ####
* boot:
- shard-tglb: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [FAIL][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb7/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb7/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb7/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb7/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb6/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb6/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb6/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb6/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb6/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb5/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb5/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb5/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb3/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb3/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb3/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb3/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb3/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb2/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb2/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb2/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb2/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb1/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb1/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb1/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb1/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb6/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb5/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb5/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb5/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb5/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb3/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb3/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb3/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb3/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb2/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb2/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb2/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb2/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb1/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb1/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb1/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb1/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb7/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb7/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb7/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb7/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb6/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb6/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb6/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb6/boot.html
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_schedule@independent@vcs1:
- shard-kbl: [PASS][51] -> [FAIL][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-kbl1/igt@gem_exec_schedule@independent@vcs1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl2/igt@gem_exec_schedule@independent@vcs1.html
* igt@i915_selftest@live@hugepages:
- shard-skl: [PASS][53] -> [INCOMPLETE][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-skl8/igt@i915_selftest@live@hugepages.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-skl8/igt@i915_selftest@live@hugepages.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-tglb: [PASS][55] -> [INCOMPLETE][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs:
- {shard-rkl}: [FAIL][57] ([i915#3678]) -> [SKIP][58] +4 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-rkl-2/igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-rkl-6/igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs.html
Known issues
------------
Here are the changes found in Patchwork_20562_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#1099]) +10 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-snb5/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [PASS][60] -> [TIMEOUT][61] ([i915#3063])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb7/igt@gem_eio@in-flight-contexts-immediate.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb2/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][62] -> [FAIL][63] ([i915#2842])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-kbl1/igt@gem_exec_fair@basic-none@vecs0.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl2/igt@gem_exec_fair@basic-none@vecs0.html
- shard-apl: [PASS][64] -> [FAIL][65] ([i915#2842] / [i915#3468])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: NOTRUN -> [DMESG-WARN][66] ([i915#180])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl3/igt@gem_exec_suspend@basic-s3.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][67] ([i915#2658])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl3/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][68] -> [DMESG-WARN][69] ([i915#180]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-apl6/igt@gem_softpin@noreloc-s3.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl2/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@input-checking:
- shard-kbl: NOTRUN -> [DMESG-WARN][70] ([i915#3002])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl3/igt@gem_userptr_blits@input-checking.html
* igt@gem_workarounds@suspend-resume-context:
- shard-kbl: [PASS][71] -> [DMESG-WARN][72] ([i915#180])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-kbl3/igt@gem_workarounds@suspend-resume-context.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl4/igt@gem_workarounds@suspend-resume-context.html
* igt@gen7_exec_parse@basic-offset:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271]) +190 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl8/igt@gen7_exec_parse@basic-offset.html
* igt@gen7_exec_parse@load-register-reg:
- shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109289])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb2/igt@gen7_exec_parse@load-register-reg.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-tglb: NOTRUN -> [SKIP][75] ([fdo#112306])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb3/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-secure:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#112306])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb2/igt@gen9_exec_parse@bb-secure.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][77] -> [FAIL][78] ([i915#454])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-tglb: [PASS][79] -> [DMESG-WARN][80] ([i915#2411] / [i915#2868])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb2/igt@i915_pm_rpm@modeset-lpsp-stress.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb5/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-apl: NOTRUN -> [FAIL][81] ([i915#3745])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl3/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][82] -> [FAIL][83] ([i915#2521])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][84] ([fdo#111615])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb3/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109278]) +3 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb2/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][86] ([i915#3689])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb3/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-audio-edid:
- shard-skl: NOTRUN -> [SKIP][87] ([fdo#109271] / [fdo#111827]) +5 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-skl10/igt@kms_chamelium@dp-audio-edid.html
* igt@kms_chamelium@dp-frame-dump:
- shard-iclb: NOTRUN -> [SKIP][88] ([fdo#109284] / [fdo#111827]) +2 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb2/igt@kms_chamelium@dp-frame-dump.html
* igt@kms_color@pipe-d-ctm-0-5:
- shard-iclb: NOTRUN -> [SKIP][89] ([fdo#109278] / [i915#1149])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb2/igt@kms_color@pipe-d-ctm-0-5.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][90] ([fdo#109271] / [fdo#111827]) +23 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-snb2/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-b-ctm-0-25:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [fdo#111827]) +9 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl2/igt@kms_color_chamelium@pipe-b-ctm-0-25.html
* igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes:
- shard-apl: NOTRUN -> [SKIP][92] ([fdo#109271] / [fdo#111827]) +12 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl8/igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes.html
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> [TIMEOUT][93] ([i915#1319])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl8/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][94] ([i915#1319])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl3/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic:
- shard-tglb: NOTRUN -> [SKIP][95] ([fdo#111828])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb1/igt@kms_content_protection@lic.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][96] ([i915#2105])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl3/igt@kms_content_protection@uevent.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-snb: NOTRUN -> [SKIP][97] ([fdo#109271]) +503 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-snb2/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][98] -> [INCOMPLETE][99] ([i915#180])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-iclb: NOTRUN -> [SKIP][100] ([fdo#109274])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb2/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-skl: NOTRUN -> [SKIP][101] ([fdo#109271]) +78 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-skl10/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][102] -> [FAIL][103] ([i915#79])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-glk: [PASS][104] -> [FAIL][105] ([i915#79])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [PASS][106] -> [FAIL][107] ([i915#2122]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-kbl: NOTRUN -> [SKIP][108] ([fdo#109271]) +134 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt:
- shard-iclb: NOTRUN -> [SKIP][109] ([fdo#109280]) +2 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][110] -> [DMESG-WARN][111] ([i915#180] / [i915#1982])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][112] -> [FAIL][113] ([fdo#108145] / [i915#265])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][114] ([fdo#108145] / [i915#265])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl7/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][115] ([i915#265])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][116] ([fdo#108145] / [i915#265])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-kbl: NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#658]) +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
- shard-apl: NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#658]) +2 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_su@frontbuffer:
- shard-skl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#658]) +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-skl10/igt@kms_psr2_su@frontbuffer.html
- shard-iclb: [PASS][120] -> [SKIP][121] ([fdo#109642] / [fdo#111068] / [i915#658])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb5/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][122] -> [SKIP][123] ([fdo#109441]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-iclb2/igt@kms_psr@psr2_basic.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb4/igt@kms_psr@psr2_basic.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#2437]) +1 similar issue
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl6/igt@kms_writeback@writeback-fb-id.html
* igt@prime_nv_test@nv_write_i915_gtt_mmap_read:
- shard-iclb: NOTRUN -> [SKIP][125] ([fdo#109291])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb2/igt@prime_nv_test@nv_write_i915_gtt_mmap_read.html
* igt@sysfs_clients@busy:
- shard-iclb: NOTRUN -> [SKIP][126] ([i915#2994])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb2/igt@sysfs_clients@busy.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][127] ([fdo#109271] / [i915#2994]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-apl3/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@sema-50:
- shard-kbl: NOTRUN -> [SKIP][128] ([fdo#109271] / [i915#2994]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl3/igt@sysfs_clients@sema-50.html
* igt@vgem_basic@unload:
- shard-iclb: NOTRUN -> [INCOMPLETE][129] ([i915#3744])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb2/igt@vgem_basic@unload.html
#### Possible fixes ####
* igt@drm_mm@all@insert_range:
- shard-skl: [INCOMPLETE][130] ([i915#2485]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-skl6/igt@drm_mm@all@insert_range.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-skl1/igt@drm_mm@all@insert_range.html
* igt@fbdev@write:
- {shard-rkl}: [SKIP][132] ([i915#2582]) -> [PASS][133] +1 similar issue
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-rkl-2/igt@fbdev@write.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-rkl-6/igt@fbdev@write.html
* igt@gem_create@create-clear:
- shard-glk: [FAIL][134] ([i915#1888] / [i915#3160]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-glk8/igt@gem_create@create-clear.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-glk2/igt@gem_create@create-clear.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][136] ([i915#2842]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][138] ([i915#2842]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][140] ([i915#2849]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-scanout@vecs0:
- {shard-rkl}: [SKIP][142] ([i915#3639]) -> [PASS][143] +3 similar issues
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-rkl-2/igt@gem_exec_reloc@basic-scanout@vecs0.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-rkl-6/igt@gem_exec_reloc@basic-scanout@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][144] ([i915#2190]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-tglb7/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_offset@clear:
- shard-iclb: [FAIL][146] ([i915#3160]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-iclb7/igt@gem_mmap_offset@clear.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-iclb2/igt@gem_mmap_offset@clear.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][148] ([i915#1436] / [i915#716]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-skl1/igt@gen9_exec_parse@allowed-single.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-skl3/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rpm@gem-execbuf:
- {shard-rkl}: [SKIP][150] ([fdo#109308]) -> [PASS][151] +1 similar issue
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-rkl-1/igt@i915_pm_rpm@gem-execbuf.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-rkl-6/igt@i915_pm_rpm@gem-execbuf.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-rkl}: [SKIP][152] ([i915#1397]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-rkl-2/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_atomic@test-only:
- {shard-rkl}: [SKIP][154] ([i915#1845]) -> [PASS][155] +40 similar issues
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-rkl-2/igt@kms_atomic@test-only.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-rkl-6/igt@kms_atomic@test-only.html
* igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180:
- {shard-rkl}: [SKIP][156] ([i915#3721]) -> [PASS][157] +7 similar issues
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-rkl-5/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- shard-glk: [DMESG-WARN][158] ([i915#118] / [i915#95]) -> [PASS][159] +1 similar issue
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-glk4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- {shard-rkl}: [SKIP][160] ([i915#3638]) -> [PASS][161] +3 similar issues
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-rkl-5/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-rkl-6/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs:
- {shard-rkl}: [FAIL][162] ([i915#3678]) -> [PASS][163] +10 similar issues
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-rkl-1/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-rkl-6/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs.html
* igt@kms_color@pipe-a-ctm-red-to-blue:
- shard-skl: [DMESG-WARN][164] ([i915#1982]) -> [PASS][165] +1 similar issue
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-skl3/igt@kms_color@pipe-a-ctm-red-to-blue.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-skl2/igt@kms_color@pipe-a-ctm-red-to-blue.html
* igt@kms_color@pipe-c-ctm-red-to-blue:
- {shard-rkl}: [SKIP][166] ([i915#1149] / [i915#1849]) -> [PASS][167] +7 similar issues
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-rkl-5/igt@kms_color@pipe-c-ctm-red-to-blue.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-rkl-6/igt@kms_color@pipe-c-ctm-red-to-blue.html
* igt@kms_cursor_crc@pipe-c-cursor-64x64-random:
- {shard-rkl}: [SKIP][168] ([fdo#112022]) -> [PASS][169] +17 similar issues
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10324/shard-rkl-1/igt@kms_cursor_crc@pipe-c-cursor-64x64-random.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/shard-rkl-6/igt@kms_cursor_crc@pipe-c-cursor-64x64-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [INCOMPLETE][170] ([i915#300]) -> [PASS][171]
[170]: h
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20562/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
2021-07-09 11:41 ` [Intel-gfx] " Maarten Lankhorst
@ 2021-07-12 13:47 ` Jason Ekstrand
-1 siblings, 0 replies; 18+ messages in thread
From: Jason Ekstrand @ 2021-07-12 13:47 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: Intel GFX, Maling list - DRI developers
On Fri, Jul 9, 2021 at 6:41 AM Maarten Lankhorst
<maarten.lankhorst@linux.intel.com> wrote:
>
> This is only used for ttm, and tells userspace that the mapping type is
> ignored. This disables the other type of mmap offsets when discrete
> memory is used, so fix the selftests as well.
>
> Document the struct as well, so it shows up in docbook correctly.
>
> Changes since v1:
> - Add docbook entries.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> .../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
> include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
> 4 files changed, 82 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index a90f796e85c0..b34be9e5d094 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
> return -ENODEV;
>
> if (obj->ops->mmap_offset) {
> + if (mmap_type != I915_MMAP_TYPE_TTM)
> + return -ENODEV;
> +
> *offset = obj->ops->mmap_offset(obj);
> return 0;
> }
>
> + if (mmap_type == I915_MMAP_TYPE_TTM)
> + return -ENODEV;
> +
> if (mmap_type != I915_MMAP_TYPE_GTT &&
> !i915_gem_object_has_struct_page(obj) &&
> !i915_gem_object_has_iomem(obj))
> @@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
> {
> enum i915_mmap_type mmap_type;
>
> - if (boot_cpu_has(X86_FEATURE_PAT))
> + if (HAS_LMEM(to_i915(dev)))
> + mmap_type = I915_MMAP_TYPE_TTM;
> + else if (boot_cpu_has(X86_FEATURE_PAT))
> mmap_type = I915_MMAP_TYPE_WC;
> else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
> return -ENODEV;
> @@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> type = I915_MMAP_TYPE_UC;
> break;
>
> + case I915_MMAP_OFFSET_TTM:
> + type = I915_MMAP_TYPE_TTM;
> + break;
> +
> default:
> return -EINVAL;
> }
> @@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> vma->vm_ops = &vm_ops_cpu;
> break;
>
> + case I915_MMAP_TYPE_TTM:
> + GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
> + /* fall-through */
> case I915_MMAP_TYPE_WB:
> vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> vma->vm_ops = &vm_ops_cpu;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index ef3de2ae9723..d4c42bcdfeb6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -105,6 +105,7 @@ enum i915_mmap_type {
> I915_MMAP_TYPE_WC,
> I915_MMAP_TYPE_WB,
> I915_MMAP_TYPE_UC,
> + I915_MMAP_TYPE_TTM,
> };
>
> struct i915_mmap_offset {
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> index 1da8bd675e54..27a35d88e5f5 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> @@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
> return 0;
> }
>
> +static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
> +{
> + if (HAS_LMEM(i915))
> + return I915_MMAP_TYPE_TTM;
> +
> + return I915_MMAP_TYPE_GTT;
> +}
> +
> static bool assert_mmap_offset(struct drm_i915_private *i915,
> unsigned long size,
> int expected)
> @@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
> if (IS_ERR(obj))
> return expected && expected == PTR_ERR(obj);
>
> - ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> + ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> i915_gem_object_put(obj);
>
> return ret == expected;
> @@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
> goto out;
> }
>
> - err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> + err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> if (err) {
> pr_err("Unable to insert object into reclaimed hole\n");
> goto err_obj;
> @@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
>
> static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
> {
> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> bool no_map;
>
> + if (HAS_LMEM(i915))
> + return type == I915_MMAP_TYPE_TTM;
> + else if (type == I915_MMAP_TYPE_TTM)
> + return false;
> +
> if (type == I915_MMAP_TYPE_GTT &&
> !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
> return false;
> @@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
> err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
> if (err == 0)
> err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
> + if (err == 0)
> + err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> @@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
> case I915_MMAP_TYPE_WB: return "wb";
> case I915_MMAP_TYPE_WC: return "wc";
> case I915_MMAP_TYPE_UC: return "uc";
> + case I915_MMAP_TYPE_TTM: return "ttm";
> default: return "unknown";
> }
> }
> @@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
> err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
> if (err == 0)
> err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
> + if (err == 0)
> + err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> @@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
> err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
> if (err == 0)
> err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
> + if (err == 0)
> + err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> @@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
> err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
> if (err == 0)
> err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
> + if (err == 0)
> + err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index e334a8b14ef2..1610ed40b4b5 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
> __u64 offset;
> };
>
> +/**
> + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> + *
> + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> + *
> + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> + */
> struct drm_i915_gem_mmap_offset {
> - /** Handle for the object being mapped. */
> + /** @handle: Handle for the object being mapped. */
> __u32 handle;
> + /** @pad: Must be zero */
> __u32 pad;
> /**
> - * Fake offset to use for subsequent mmap call
> + * @offset: The fake offset to use for subsequent mmap call
> *
> * This is a fixed-size type for 32/64 compatibility.
> */
> __u64 offset;
>
> /**
> - * Flags for extended behaviour.
> + * @flags: Flags for extended behaviour.
> + *
> + * It is mandatory that one of the `MMAP_OFFSET` types
> + * should be included:
> + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
> + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> + * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
> + *
> + * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
> + * devices without local memory, this caching mode is invalid.
> *
> - * It is mandatory that one of the MMAP_OFFSET types
> - * (GTT, WC, WB, UC, etc) should be included.
> + * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
> + * be used, depending on the object placement. WC will be used
> + * when the object resides in local memory, WB otherwise.
> */
> __u64 flags;
> -#define I915_MMAP_OFFSET_GTT 0
> -#define I915_MMAP_OFFSET_WC 1
> -#define I915_MMAP_OFFSET_WB 2
> -#define I915_MMAP_OFFSET_UC 3
>
> - /*
> - * Zero-terminated chain of extensions.
> +/** Use an mmap for the object by binding to GTT. */
> +#define I915_MMAP_OFFSET_GTT 0
> +/** Use Write-Combined caching. */
> +#define I915_MMAP_OFFSET_WC 1
> +/** Use Write-Back caching. */
> +#define I915_MMAP_OFFSET_WB 2
> +/** Do not use caching when binding this mmap. */
> +#define I915_MMAP_OFFSET_UC 3
> +/** Use the TTM binding, which determines the appropriate caching mode. */
> +#define I915_MMAP_OFFSET_TTM 4
I'm not sure I like the name here. TTM is an implementation detail,
not a kind of map. I think we want something more like
I915_MMAP_OFFSET_IMPLICIT or something like that. The semantics here,
as far as I can tell, are "the mmap type is based on the object; you
can't change it." On DG1, the mmap type is fixed for all objects. On
integrated, we could have a BO create option for the mmap type but we
don't yet.
--Jason
> +
> + /**
> + * @extensions: Zero-terminated chain of extensions.
> *
> * No current extensions defined; mbz.
> */
> --
> 2.31.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
@ 2021-07-12 13:47 ` Jason Ekstrand
0 siblings, 0 replies; 18+ messages in thread
From: Jason Ekstrand @ 2021-07-12 13:47 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: Intel GFX, Maling list - DRI developers
On Fri, Jul 9, 2021 at 6:41 AM Maarten Lankhorst
<maarten.lankhorst@linux.intel.com> wrote:
>
> This is only used for ttm, and tells userspace that the mapping type is
> ignored. This disables the other type of mmap offsets when discrete
> memory is used, so fix the selftests as well.
>
> Document the struct as well, so it shows up in docbook correctly.
>
> Changes since v1:
> - Add docbook entries.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> .../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
> include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
> 4 files changed, 82 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index a90f796e85c0..b34be9e5d094 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
> return -ENODEV;
>
> if (obj->ops->mmap_offset) {
> + if (mmap_type != I915_MMAP_TYPE_TTM)
> + return -ENODEV;
> +
> *offset = obj->ops->mmap_offset(obj);
> return 0;
> }
>
> + if (mmap_type == I915_MMAP_TYPE_TTM)
> + return -ENODEV;
> +
> if (mmap_type != I915_MMAP_TYPE_GTT &&
> !i915_gem_object_has_struct_page(obj) &&
> !i915_gem_object_has_iomem(obj))
> @@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
> {
> enum i915_mmap_type mmap_type;
>
> - if (boot_cpu_has(X86_FEATURE_PAT))
> + if (HAS_LMEM(to_i915(dev)))
> + mmap_type = I915_MMAP_TYPE_TTM;
> + else if (boot_cpu_has(X86_FEATURE_PAT))
> mmap_type = I915_MMAP_TYPE_WC;
> else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
> return -ENODEV;
> @@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> type = I915_MMAP_TYPE_UC;
> break;
>
> + case I915_MMAP_OFFSET_TTM:
> + type = I915_MMAP_TYPE_TTM;
> + break;
> +
> default:
> return -EINVAL;
> }
> @@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> vma->vm_ops = &vm_ops_cpu;
> break;
>
> + case I915_MMAP_TYPE_TTM:
> + GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
> + /* fall-through */
> case I915_MMAP_TYPE_WB:
> vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> vma->vm_ops = &vm_ops_cpu;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index ef3de2ae9723..d4c42bcdfeb6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -105,6 +105,7 @@ enum i915_mmap_type {
> I915_MMAP_TYPE_WC,
> I915_MMAP_TYPE_WB,
> I915_MMAP_TYPE_UC,
> + I915_MMAP_TYPE_TTM,
> };
>
> struct i915_mmap_offset {
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> index 1da8bd675e54..27a35d88e5f5 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> @@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
> return 0;
> }
>
> +static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
> +{
> + if (HAS_LMEM(i915))
> + return I915_MMAP_TYPE_TTM;
> +
> + return I915_MMAP_TYPE_GTT;
> +}
> +
> static bool assert_mmap_offset(struct drm_i915_private *i915,
> unsigned long size,
> int expected)
> @@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
> if (IS_ERR(obj))
> return expected && expected == PTR_ERR(obj);
>
> - ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> + ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> i915_gem_object_put(obj);
>
> return ret == expected;
> @@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
> goto out;
> }
>
> - err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> + err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> if (err) {
> pr_err("Unable to insert object into reclaimed hole\n");
> goto err_obj;
> @@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
>
> static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
> {
> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> bool no_map;
>
> + if (HAS_LMEM(i915))
> + return type == I915_MMAP_TYPE_TTM;
> + else if (type == I915_MMAP_TYPE_TTM)
> + return false;
> +
> if (type == I915_MMAP_TYPE_GTT &&
> !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
> return false;
> @@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
> err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
> if (err == 0)
> err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
> + if (err == 0)
> + err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> @@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
> case I915_MMAP_TYPE_WB: return "wb";
> case I915_MMAP_TYPE_WC: return "wc";
> case I915_MMAP_TYPE_UC: return "uc";
> + case I915_MMAP_TYPE_TTM: return "ttm";
> default: return "unknown";
> }
> }
> @@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
> err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
> if (err == 0)
> err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
> + if (err == 0)
> + err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> @@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
> err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
> if (err == 0)
> err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
> + if (err == 0)
> + err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> @@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
> err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
> if (err == 0)
> err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
> + if (err == 0)
> + err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
>
> i915_gem_object_put(obj);
> if (err)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index e334a8b14ef2..1610ed40b4b5 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
> __u64 offset;
> };
>
> +/**
> + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> + *
> + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> + *
> + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> + */
> struct drm_i915_gem_mmap_offset {
> - /** Handle for the object being mapped. */
> + /** @handle: Handle for the object being mapped. */
> __u32 handle;
> + /** @pad: Must be zero */
> __u32 pad;
> /**
> - * Fake offset to use for subsequent mmap call
> + * @offset: The fake offset to use for subsequent mmap call
> *
> * This is a fixed-size type for 32/64 compatibility.
> */
> __u64 offset;
>
> /**
> - * Flags for extended behaviour.
> + * @flags: Flags for extended behaviour.
> + *
> + * It is mandatory that one of the `MMAP_OFFSET` types
> + * should be included:
> + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
> + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> + * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
> + *
> + * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
> + * devices without local memory, this caching mode is invalid.
> *
> - * It is mandatory that one of the MMAP_OFFSET types
> - * (GTT, WC, WB, UC, etc) should be included.
> + * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
> + * be used, depending on the object placement. WC will be used
> + * when the object resides in local memory, WB otherwise.
> */
> __u64 flags;
> -#define I915_MMAP_OFFSET_GTT 0
> -#define I915_MMAP_OFFSET_WC 1
> -#define I915_MMAP_OFFSET_WB 2
> -#define I915_MMAP_OFFSET_UC 3
>
> - /*
> - * Zero-terminated chain of extensions.
> +/** Use an mmap for the object by binding to GTT. */
> +#define I915_MMAP_OFFSET_GTT 0
> +/** Use Write-Combined caching. */
> +#define I915_MMAP_OFFSET_WC 1
> +/** Use Write-Back caching. */
> +#define I915_MMAP_OFFSET_WB 2
> +/** Do not use caching when binding this mmap. */
> +#define I915_MMAP_OFFSET_UC 3
> +/** Use the TTM binding, which determines the appropriate caching mode. */
> +#define I915_MMAP_OFFSET_TTM 4
I'm not sure I like the name here. TTM is an implementation detail,
not a kind of map. I think we want something more like
I915_MMAP_OFFSET_IMPLICIT or something like that. The semantics here,
as far as I can tell, are "the mmap type is based on the object; you
can't change it." On DG1, the mmap type is fixed for all objects. On
integrated, we could have a BO create option for the mmap type but we
don't yet.
--Jason
> +
> + /**
> + * @extensions: Zero-terminated chain of extensions.
> *
> * No current extensions defined; mbz.
> */
> --
> 2.31.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
2021-07-12 13:47 ` Jason Ekstrand
@ 2021-07-12 14:12 ` Daniel Vetter
-1 siblings, 0 replies; 18+ messages in thread
From: Daniel Vetter @ 2021-07-12 14:12 UTC (permalink / raw)
To: Jason Ekstrand; +Cc: Intel GFX, Maling list - DRI developers
On Mon, Jul 12, 2021 at 08:47:24AM -0500, Jason Ekstrand wrote:
> On Fri, Jul 9, 2021 at 6:41 AM Maarten Lankhorst
> <maarten.lankhorst@linux.intel.com> wrote:
> >
> > This is only used for ttm, and tells userspace that the mapping type is
> > ignored. This disables the other type of mmap offsets when discrete
> > memory is used, so fix the selftests as well.
> >
> > Document the struct as well, so it shows up in docbook correctly.
> >
> > Changes since v1:
> > - Add docbook entries.
> >
> > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
> > .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> > .../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
> > include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
> > 4 files changed, 82 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > index a90f796e85c0..b34be9e5d094 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > @@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
> > return -ENODEV;
> >
> > if (obj->ops->mmap_offset) {
> > + if (mmap_type != I915_MMAP_TYPE_TTM)
> > + return -ENODEV;
> > +
> > *offset = obj->ops->mmap_offset(obj);
> > return 0;
> > }
> >
> > + if (mmap_type == I915_MMAP_TYPE_TTM)
> > + return -ENODEV;
> > +
> > if (mmap_type != I915_MMAP_TYPE_GTT &&
> > !i915_gem_object_has_struct_page(obj) &&
> > !i915_gem_object_has_iomem(obj))
> > @@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
> > {
> > enum i915_mmap_type mmap_type;
> >
> > - if (boot_cpu_has(X86_FEATURE_PAT))
> > + if (HAS_LMEM(to_i915(dev)))
> > + mmap_type = I915_MMAP_TYPE_TTM;
> > + else if (boot_cpu_has(X86_FEATURE_PAT))
> > mmap_type = I915_MMAP_TYPE_WC;
> > else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
> > return -ENODEV;
> > @@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> > type = I915_MMAP_TYPE_UC;
> > break;
> >
> > + case I915_MMAP_OFFSET_TTM:
> > + type = I915_MMAP_TYPE_TTM;
> > + break;
> > +
> > default:
> > return -EINVAL;
> > }
> > @@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> > vma->vm_ops = &vm_ops_cpu;
> > break;
> >
> > + case I915_MMAP_TYPE_TTM:
> > + GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
> > + /* fall-through */
> > case I915_MMAP_TYPE_WB:
> > vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> > vma->vm_ops = &vm_ops_cpu;
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > index ef3de2ae9723..d4c42bcdfeb6 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > @@ -105,6 +105,7 @@ enum i915_mmap_type {
> > I915_MMAP_TYPE_WC,
> > I915_MMAP_TYPE_WB,
> > I915_MMAP_TYPE_UC,
> > + I915_MMAP_TYPE_TTM,
> > };
> >
> > struct i915_mmap_offset {
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > index 1da8bd675e54..27a35d88e5f5 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > @@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
> > return 0;
> > }
> >
> > +static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
> > +{
> > + if (HAS_LMEM(i915))
> > + return I915_MMAP_TYPE_TTM;
> > +
> > + return I915_MMAP_TYPE_GTT;
> > +}
> > +
> > static bool assert_mmap_offset(struct drm_i915_private *i915,
> > unsigned long size,
> > int expected)
> > @@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
> > if (IS_ERR(obj))
> > return expected && expected == PTR_ERR(obj);
> >
> > - ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > + ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > i915_gem_object_put(obj);
> >
> > return ret == expected;
> > @@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
> > goto out;
> > }
> >
> > - err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > + err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > if (err) {
> > pr_err("Unable to insert object into reclaimed hole\n");
> > goto err_obj;
> > @@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
> >
> > static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
> > {
> > + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> > bool no_map;
> >
> > + if (HAS_LMEM(i915))
> > + return type == I915_MMAP_TYPE_TTM;
> > + else if (type == I915_MMAP_TYPE_TTM)
> > + return false;
> > +
> > if (type == I915_MMAP_TYPE_GTT &&
> > !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
> > return false;
> > @@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
> > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
> > if (err == 0)
> > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
> > + if (err == 0)
> > + err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
> >
> > i915_gem_object_put(obj);
> > if (err)
> > @@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
> > case I915_MMAP_TYPE_WB: return "wb";
> > case I915_MMAP_TYPE_WC: return "wc";
> > case I915_MMAP_TYPE_UC: return "uc";
> > + case I915_MMAP_TYPE_TTM: return "ttm";
> > default: return "unknown";
> > }
> > }
> > @@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
> > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
> > if (err == 0)
> > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
> > + if (err == 0)
> > + err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
> >
> > i915_gem_object_put(obj);
> > if (err)
> > @@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
> > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
> > if (err == 0)
> > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
> > + if (err == 0)
> > + err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
> >
> > i915_gem_object_put(obj);
> > if (err)
> > @@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
> > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
> > if (err == 0)
> > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
> > + if (err == 0)
> > + err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
> >
> > i915_gem_object_put(obj);
> > if (err)
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index e334a8b14ef2..1610ed40b4b5 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
> > __u64 offset;
> > };
> >
> > +/**
> > + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> > + *
> > + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> > + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> > + *
> > + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> > + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> > + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> > + */
> > struct drm_i915_gem_mmap_offset {
> > - /** Handle for the object being mapped. */
> > + /** @handle: Handle for the object being mapped. */
> > __u32 handle;
> > + /** @pad: Must be zero */
> > __u32 pad;
> > /**
> > - * Fake offset to use for subsequent mmap call
> > + * @offset: The fake offset to use for subsequent mmap call
> > *
> > * This is a fixed-size type for 32/64 compatibility.
> > */
> > __u64 offset;
> >
> > /**
> > - * Flags for extended behaviour.
> > + * @flags: Flags for extended behaviour.
> > + *
> > + * It is mandatory that one of the `MMAP_OFFSET` types
> > + * should be included:
> > + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
> > + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> > + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> > + * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
> > + *
> > + * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
> > + * devices without local memory, this caching mode is invalid.
> > *
> > - * It is mandatory that one of the MMAP_OFFSET types
> > - * (GTT, WC, WB, UC, etc) should be included.
> > + * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
> > + * be used, depending on the object placement. WC will be used
> > + * when the object resides in local memory, WB otherwise.
> > */
> > __u64 flags;
> > -#define I915_MMAP_OFFSET_GTT 0
> > -#define I915_MMAP_OFFSET_WC 1
> > -#define I915_MMAP_OFFSET_WB 2
> > -#define I915_MMAP_OFFSET_UC 3
> >
> > - /*
> > - * Zero-terminated chain of extensions.
> > +/** Use an mmap for the object by binding to GTT. */
> > +#define I915_MMAP_OFFSET_GTT 0
> > +/** Use Write-Combined caching. */
> > +#define I915_MMAP_OFFSET_WC 1
> > +/** Use Write-Back caching. */
> > +#define I915_MMAP_OFFSET_WB 2
> > +/** Do not use caching when binding this mmap. */
> > +#define I915_MMAP_OFFSET_UC 3
> > +/** Use the TTM binding, which determines the appropriate caching mode. */
> > +#define I915_MMAP_OFFSET_TTM 4
>
> I'm not sure I like the name here. TTM is an implementation detail,
> not a kind of map. I think we want something more like
> I915_MMAP_OFFSET_IMPLICIT or something like that. The semantics here,
> as far as I can tell, are "the mmap type is based on the object; you
> can't change it." On DG1, the mmap type is fixed for all objects. On
> integrated, we could have a BO create option for the mmap type but we
> don't yet.
Yeah it's not a great name, but also we didn't come up with anything
substantially better on irc. More ideas:
- PREDEFINED
- PRESELECTED
Note that we want to pick a value here which also makes sense for when we
extend GEM_CREATE_EXT to allow you to select the single mmap mode you get
at creation time (for igfx cleanup of the uapi). So IMPLICIT isn't the
greatest name either, when we'll allow userspace to explicit chose it -
just not here anymore.
Anyway, pick a name and we'll paint this bikeshed, I don't care much
really. As long as there's kerneldoc :-)
-Daniel
>
> --Jason
>
> > +
> > + /**
> > + * @extensions: Zero-terminated chain of extensions.
> > *
> > * No current extensions defined; mbz.
> > */
> > --
> > 2.31.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
@ 2021-07-12 14:12 ` Daniel Vetter
0 siblings, 0 replies; 18+ messages in thread
From: Daniel Vetter @ 2021-07-12 14:12 UTC (permalink / raw)
To: Jason Ekstrand; +Cc: Intel GFX, Maling list - DRI developers
On Mon, Jul 12, 2021 at 08:47:24AM -0500, Jason Ekstrand wrote:
> On Fri, Jul 9, 2021 at 6:41 AM Maarten Lankhorst
> <maarten.lankhorst@linux.intel.com> wrote:
> >
> > This is only used for ttm, and tells userspace that the mapping type is
> > ignored. This disables the other type of mmap offsets when discrete
> > memory is used, so fix the selftests as well.
> >
> > Document the struct as well, so it shows up in docbook correctly.
> >
> > Changes since v1:
> > - Add docbook entries.
> >
> > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
> > .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> > .../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
> > include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
> > 4 files changed, 82 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > index a90f796e85c0..b34be9e5d094 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > @@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
> > return -ENODEV;
> >
> > if (obj->ops->mmap_offset) {
> > + if (mmap_type != I915_MMAP_TYPE_TTM)
> > + return -ENODEV;
> > +
> > *offset = obj->ops->mmap_offset(obj);
> > return 0;
> > }
> >
> > + if (mmap_type == I915_MMAP_TYPE_TTM)
> > + return -ENODEV;
> > +
> > if (mmap_type != I915_MMAP_TYPE_GTT &&
> > !i915_gem_object_has_struct_page(obj) &&
> > !i915_gem_object_has_iomem(obj))
> > @@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
> > {
> > enum i915_mmap_type mmap_type;
> >
> > - if (boot_cpu_has(X86_FEATURE_PAT))
> > + if (HAS_LMEM(to_i915(dev)))
> > + mmap_type = I915_MMAP_TYPE_TTM;
> > + else if (boot_cpu_has(X86_FEATURE_PAT))
> > mmap_type = I915_MMAP_TYPE_WC;
> > else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
> > return -ENODEV;
> > @@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> > type = I915_MMAP_TYPE_UC;
> > break;
> >
> > + case I915_MMAP_OFFSET_TTM:
> > + type = I915_MMAP_TYPE_TTM;
> > + break;
> > +
> > default:
> > return -EINVAL;
> > }
> > @@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> > vma->vm_ops = &vm_ops_cpu;
> > break;
> >
> > + case I915_MMAP_TYPE_TTM:
> > + GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
> > + /* fall-through */
> > case I915_MMAP_TYPE_WB:
> > vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> > vma->vm_ops = &vm_ops_cpu;
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > index ef3de2ae9723..d4c42bcdfeb6 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > @@ -105,6 +105,7 @@ enum i915_mmap_type {
> > I915_MMAP_TYPE_WC,
> > I915_MMAP_TYPE_WB,
> > I915_MMAP_TYPE_UC,
> > + I915_MMAP_TYPE_TTM,
> > };
> >
> > struct i915_mmap_offset {
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > index 1da8bd675e54..27a35d88e5f5 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > @@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
> > return 0;
> > }
> >
> > +static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
> > +{
> > + if (HAS_LMEM(i915))
> > + return I915_MMAP_TYPE_TTM;
> > +
> > + return I915_MMAP_TYPE_GTT;
> > +}
> > +
> > static bool assert_mmap_offset(struct drm_i915_private *i915,
> > unsigned long size,
> > int expected)
> > @@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
> > if (IS_ERR(obj))
> > return expected && expected == PTR_ERR(obj);
> >
> > - ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > + ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > i915_gem_object_put(obj);
> >
> > return ret == expected;
> > @@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
> > goto out;
> > }
> >
> > - err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > + err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > if (err) {
> > pr_err("Unable to insert object into reclaimed hole\n");
> > goto err_obj;
> > @@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
> >
> > static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
> > {
> > + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> > bool no_map;
> >
> > + if (HAS_LMEM(i915))
> > + return type == I915_MMAP_TYPE_TTM;
> > + else if (type == I915_MMAP_TYPE_TTM)
> > + return false;
> > +
> > if (type == I915_MMAP_TYPE_GTT &&
> > !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
> > return false;
> > @@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
> > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
> > if (err == 0)
> > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
> > + if (err == 0)
> > + err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
> >
> > i915_gem_object_put(obj);
> > if (err)
> > @@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
> > case I915_MMAP_TYPE_WB: return "wb";
> > case I915_MMAP_TYPE_WC: return "wc";
> > case I915_MMAP_TYPE_UC: return "uc";
> > + case I915_MMAP_TYPE_TTM: return "ttm";
> > default: return "unknown";
> > }
> > }
> > @@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
> > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
> > if (err == 0)
> > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
> > + if (err == 0)
> > + err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
> >
> > i915_gem_object_put(obj);
> > if (err)
> > @@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
> > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
> > if (err == 0)
> > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
> > + if (err == 0)
> > + err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
> >
> > i915_gem_object_put(obj);
> > if (err)
> > @@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
> > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
> > if (err == 0)
> > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
> > + if (err == 0)
> > + err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
> >
> > i915_gem_object_put(obj);
> > if (err)
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index e334a8b14ef2..1610ed40b4b5 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
> > __u64 offset;
> > };
> >
> > +/**
> > + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> > + *
> > + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> > + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> > + *
> > + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> > + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> > + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> > + */
> > struct drm_i915_gem_mmap_offset {
> > - /** Handle for the object being mapped. */
> > + /** @handle: Handle for the object being mapped. */
> > __u32 handle;
> > + /** @pad: Must be zero */
> > __u32 pad;
> > /**
> > - * Fake offset to use for subsequent mmap call
> > + * @offset: The fake offset to use for subsequent mmap call
> > *
> > * This is a fixed-size type for 32/64 compatibility.
> > */
> > __u64 offset;
> >
> > /**
> > - * Flags for extended behaviour.
> > + * @flags: Flags for extended behaviour.
> > + *
> > + * It is mandatory that one of the `MMAP_OFFSET` types
> > + * should be included:
> > + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
> > + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> > + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> > + * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
> > + *
> > + * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
> > + * devices without local memory, this caching mode is invalid.
> > *
> > - * It is mandatory that one of the MMAP_OFFSET types
> > - * (GTT, WC, WB, UC, etc) should be included.
> > + * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
> > + * be used, depending on the object placement. WC will be used
> > + * when the object resides in local memory, WB otherwise.
> > */
> > __u64 flags;
> > -#define I915_MMAP_OFFSET_GTT 0
> > -#define I915_MMAP_OFFSET_WC 1
> > -#define I915_MMAP_OFFSET_WB 2
> > -#define I915_MMAP_OFFSET_UC 3
> >
> > - /*
> > - * Zero-terminated chain of extensions.
> > +/** Use an mmap for the object by binding to GTT. */
> > +#define I915_MMAP_OFFSET_GTT 0
> > +/** Use Write-Combined caching. */
> > +#define I915_MMAP_OFFSET_WC 1
> > +/** Use Write-Back caching. */
> > +#define I915_MMAP_OFFSET_WB 2
> > +/** Do not use caching when binding this mmap. */
> > +#define I915_MMAP_OFFSET_UC 3
> > +/** Use the TTM binding, which determines the appropriate caching mode. */
> > +#define I915_MMAP_OFFSET_TTM 4
>
> I'm not sure I like the name here. TTM is an implementation detail,
> not a kind of map. I think we want something more like
> I915_MMAP_OFFSET_IMPLICIT or something like that. The semantics here,
> as far as I can tell, are "the mmap type is based on the object; you
> can't change it." On DG1, the mmap type is fixed for all objects. On
> integrated, we could have a BO create option for the mmap type but we
> don't yet.
Yeah it's not a great name, but also we didn't come up with anything
substantially better on irc. More ideas:
- PREDEFINED
- PRESELECTED
Note that we want to pick a value here which also makes sense for when we
extend GEM_CREATE_EXT to allow you to select the single mmap mode you get
at creation time (for igfx cleanup of the uapi). So IMPLICIT isn't the
greatest name either, when we'll allow userspace to explicit chose it -
just not here anymore.
Anyway, pick a name and we'll paint this bikeshed, I don't care much
really. As long as there's kerneldoc :-)
-Daniel
>
> --Jason
>
> > +
> > + /**
> > + * @extensions: Zero-terminated chain of extensions.
> > *
> > * No current extensions defined; mbz.
> > */
> > --
> > 2.31.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
2021-07-12 14:12 ` Daniel Vetter
@ 2021-07-12 14:31 ` Jason Ekstrand
-1 siblings, 0 replies; 18+ messages in thread
From: Jason Ekstrand @ 2021-07-12 14:31 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel GFX, Maling list - DRI developers
On Mon, Jul 12, 2021 at 9:12 AM Daniel Vetter <daniel@ffwll.ch> wrote:
>
> On Mon, Jul 12, 2021 at 08:47:24AM -0500, Jason Ekstrand wrote:
> > On Fri, Jul 9, 2021 at 6:41 AM Maarten Lankhorst
> > <maarten.lankhorst@linux.intel.com> wrote:
> > >
> > > This is only used for ttm, and tells userspace that the mapping type is
> > > ignored. This disables the other type of mmap offsets when discrete
> > > memory is used, so fix the selftests as well.
> > >
> > > Document the struct as well, so it shows up in docbook correctly.
> > >
> > > Changes since v1:
> > > - Add docbook entries.
> > >
> > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
> > > .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> > > .../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
> > > include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
> > > 4 files changed, 82 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > index a90f796e85c0..b34be9e5d094 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > @@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
> > > return -ENODEV;
> > >
> > > if (obj->ops->mmap_offset) {
> > > + if (mmap_type != I915_MMAP_TYPE_TTM)
> > > + return -ENODEV;
> > > +
> > > *offset = obj->ops->mmap_offset(obj);
> > > return 0;
> > > }
> > >
> > > + if (mmap_type == I915_MMAP_TYPE_TTM)
> > > + return -ENODEV;
> > > +
> > > if (mmap_type != I915_MMAP_TYPE_GTT &&
> > > !i915_gem_object_has_struct_page(obj) &&
> > > !i915_gem_object_has_iomem(obj))
> > > @@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
> > > {
> > > enum i915_mmap_type mmap_type;
> > >
> > > - if (boot_cpu_has(X86_FEATURE_PAT))
> > > + if (HAS_LMEM(to_i915(dev)))
> > > + mmap_type = I915_MMAP_TYPE_TTM;
> > > + else if (boot_cpu_has(X86_FEATURE_PAT))
> > > mmap_type = I915_MMAP_TYPE_WC;
> > > else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
> > > return -ENODEV;
> > > @@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> > > type = I915_MMAP_TYPE_UC;
> > > break;
> > >
> > > + case I915_MMAP_OFFSET_TTM:
> > > + type = I915_MMAP_TYPE_TTM;
> > > + break;
> > > +
> > > default:
> > > return -EINVAL;
> > > }
> > > @@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> > > vma->vm_ops = &vm_ops_cpu;
> > > break;
> > >
> > > + case I915_MMAP_TYPE_TTM:
> > > + GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
> > > + /* fall-through */
> > > case I915_MMAP_TYPE_WB:
> > > vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> > > vma->vm_ops = &vm_ops_cpu;
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > index ef3de2ae9723..d4c42bcdfeb6 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > @@ -105,6 +105,7 @@ enum i915_mmap_type {
> > > I915_MMAP_TYPE_WC,
> > > I915_MMAP_TYPE_WB,
> > > I915_MMAP_TYPE_UC,
> > > + I915_MMAP_TYPE_TTM,
> > > };
> > >
> > > struct i915_mmap_offset {
> > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > index 1da8bd675e54..27a35d88e5f5 100644
> > > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > @@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
> > > return 0;
> > > }
> > >
> > > +static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
> > > +{
> > > + if (HAS_LMEM(i915))
> > > + return I915_MMAP_TYPE_TTM;
> > > +
> > > + return I915_MMAP_TYPE_GTT;
> > > +}
> > > +
> > > static bool assert_mmap_offset(struct drm_i915_private *i915,
> > > unsigned long size,
> > > int expected)
> > > @@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
> > > if (IS_ERR(obj))
> > > return expected && expected == PTR_ERR(obj);
> > >
> > > - ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > > + ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > > i915_gem_object_put(obj);
> > >
> > > return ret == expected;
> > > @@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
> > > goto out;
> > > }
> > >
> > > - err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > > + err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > > if (err) {
> > > pr_err("Unable to insert object into reclaimed hole\n");
> > > goto err_obj;
> > > @@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
> > >
> > > static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
> > > {
> > > + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> > > bool no_map;
> > >
> > > + if (HAS_LMEM(i915))
> > > + return type == I915_MMAP_TYPE_TTM;
> > > + else if (type == I915_MMAP_TYPE_TTM)
> > > + return false;
> > > +
> > > if (type == I915_MMAP_TYPE_GTT &&
> > > !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
> > > return false;
> > > @@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
> > > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
> > > if (err == 0)
> > > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
> > > + if (err == 0)
> > > + err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
> > >
> > > i915_gem_object_put(obj);
> > > if (err)
> > > @@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
> > > case I915_MMAP_TYPE_WB: return "wb";
> > > case I915_MMAP_TYPE_WC: return "wc";
> > > case I915_MMAP_TYPE_UC: return "uc";
> > > + case I915_MMAP_TYPE_TTM: return "ttm";
> > > default: return "unknown";
> > > }
> > > }
> > > @@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
> > > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
> > > if (err == 0)
> > > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
> > > + if (err == 0)
> > > + err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
> > >
> > > i915_gem_object_put(obj);
> > > if (err)
> > > @@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
> > > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
> > > if (err == 0)
> > > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
> > > + if (err == 0)
> > > + err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
> > >
> > > i915_gem_object_put(obj);
> > > if (err)
> > > @@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
> > > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
> > > if (err == 0)
> > > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
> > > + if (err == 0)
> > > + err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
> > >
> > > i915_gem_object_put(obj);
> > > if (err)
> > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > index e334a8b14ef2..1610ed40b4b5 100644
> > > --- a/include/uapi/drm/i915_drm.h
> > > +++ b/include/uapi/drm/i915_drm.h
> > > @@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
> > > __u64 offset;
> > > };
> > >
> > > +/**
> > > + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> > > + *
> > > + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> > > + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> > > + *
> > > + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> > > + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> > > + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> > > + */
> > > struct drm_i915_gem_mmap_offset {
> > > - /** Handle for the object being mapped. */
> > > + /** @handle: Handle for the object being mapped. */
> > > __u32 handle;
> > > + /** @pad: Must be zero */
> > > __u32 pad;
> > > /**
> > > - * Fake offset to use for subsequent mmap call
> > > + * @offset: The fake offset to use for subsequent mmap call
> > > *
> > > * This is a fixed-size type for 32/64 compatibility.
> > > */
> > > __u64 offset;
> > >
> > > /**
> > > - * Flags for extended behaviour.
> > > + * @flags: Flags for extended behaviour.
> > > + *
> > > + * It is mandatory that one of the `MMAP_OFFSET` types
> > > + * should be included:
> > > + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
> > > + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> > > + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> > > + * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
> > > + *
> > > + * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
> > > + * devices without local memory, this caching mode is invalid.
> > > *
> > > - * It is mandatory that one of the MMAP_OFFSET types
> > > - * (GTT, WC, WB, UC, etc) should be included.
> > > + * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
> > > + * be used, depending on the object placement. WC will be used
> > > + * when the object resides in local memory, WB otherwise.
> > > */
> > > __u64 flags;
> > > -#define I915_MMAP_OFFSET_GTT 0
> > > -#define I915_MMAP_OFFSET_WC 1
> > > -#define I915_MMAP_OFFSET_WB 2
> > > -#define I915_MMAP_OFFSET_UC 3
> > >
> > > - /*
> > > - * Zero-terminated chain of extensions.
> > > +/** Use an mmap for the object by binding to GTT. */
> > > +#define I915_MMAP_OFFSET_GTT 0
> > > +/** Use Write-Combined caching. */
> > > +#define I915_MMAP_OFFSET_WC 1
> > > +/** Use Write-Back caching. */
> > > +#define I915_MMAP_OFFSET_WB 2
> > > +/** Do not use caching when binding this mmap. */
> > > +#define I915_MMAP_OFFSET_UC 3
> > > +/** Use the TTM binding, which determines the appropriate caching mode. */
> > > +#define I915_MMAP_OFFSET_TTM 4
> >
> > I'm not sure I like the name here. TTM is an implementation detail,
> > not a kind of map. I think we want something more like
> > I915_MMAP_OFFSET_IMPLICIT or something like that. The semantics here,
> > as far as I can tell, are "the mmap type is based on the object; you
> > can't change it." On DG1, the mmap type is fixed for all objects. On
> > integrated, we could have a BO create option for the mmap type but we
> > don't yet.
>
> Yeah it's not a great name, but also we didn't come up with anything
> substantially better on irc. More ideas:
> - PREDEFINED
> - PRESELECTED
>
> Note that we want to pick a value here which also makes sense for when we
> extend GEM_CREATE_EXT to allow you to select the single mmap mode you get
> at creation time (for igfx cleanup of the uapi). So IMPLICIT isn't the
> greatest name either, when we'll allow userspace to explicit chose it -
> just not here anymore.
Yeah, none of them are great. Maybe FIXED? Or PER_BO? Or BO_CREATE?
Or just BO? I think the semantics we want are "whatever was on the
BO at create time".
--Jason
>
> Anyway, pick a name and we'll paint this bikeshed, I don't care much
> really. As long as there's kerneldoc :-)
> -Daniel
>
> >
> > --Jason
> >
> > > +
> > > + /**
> > > + * @extensions: Zero-terminated chain of extensions.
> > > *
> > > * No current extensions defined; mbz.
> > > */
> > > --
> > > 2.31.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
@ 2021-07-12 14:31 ` Jason Ekstrand
0 siblings, 0 replies; 18+ messages in thread
From: Jason Ekstrand @ 2021-07-12 14:31 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel GFX, Maling list - DRI developers
On Mon, Jul 12, 2021 at 9:12 AM Daniel Vetter <daniel@ffwll.ch> wrote:
>
> On Mon, Jul 12, 2021 at 08:47:24AM -0500, Jason Ekstrand wrote:
> > On Fri, Jul 9, 2021 at 6:41 AM Maarten Lankhorst
> > <maarten.lankhorst@linux.intel.com> wrote:
> > >
> > > This is only used for ttm, and tells userspace that the mapping type is
> > > ignored. This disables the other type of mmap offsets when discrete
> > > memory is used, so fix the selftests as well.
> > >
> > > Document the struct as well, so it shows up in docbook correctly.
> > >
> > > Changes since v1:
> > > - Add docbook entries.
> > >
> > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
> > > .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> > > .../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
> > > include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
> > > 4 files changed, 82 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > index a90f796e85c0..b34be9e5d094 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > @@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
> > > return -ENODEV;
> > >
> > > if (obj->ops->mmap_offset) {
> > > + if (mmap_type != I915_MMAP_TYPE_TTM)
> > > + return -ENODEV;
> > > +
> > > *offset = obj->ops->mmap_offset(obj);
> > > return 0;
> > > }
> > >
> > > + if (mmap_type == I915_MMAP_TYPE_TTM)
> > > + return -ENODEV;
> > > +
> > > if (mmap_type != I915_MMAP_TYPE_GTT &&
> > > !i915_gem_object_has_struct_page(obj) &&
> > > !i915_gem_object_has_iomem(obj))
> > > @@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
> > > {
> > > enum i915_mmap_type mmap_type;
> > >
> > > - if (boot_cpu_has(X86_FEATURE_PAT))
> > > + if (HAS_LMEM(to_i915(dev)))
> > > + mmap_type = I915_MMAP_TYPE_TTM;
> > > + else if (boot_cpu_has(X86_FEATURE_PAT))
> > > mmap_type = I915_MMAP_TYPE_WC;
> > > else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
> > > return -ENODEV;
> > > @@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> > > type = I915_MMAP_TYPE_UC;
> > > break;
> > >
> > > + case I915_MMAP_OFFSET_TTM:
> > > + type = I915_MMAP_TYPE_TTM;
> > > + break;
> > > +
> > > default:
> > > return -EINVAL;
> > > }
> > > @@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> > > vma->vm_ops = &vm_ops_cpu;
> > > break;
> > >
> > > + case I915_MMAP_TYPE_TTM:
> > > + GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
> > > + /* fall-through */
> > > case I915_MMAP_TYPE_WB:
> > > vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> > > vma->vm_ops = &vm_ops_cpu;
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > index ef3de2ae9723..d4c42bcdfeb6 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > @@ -105,6 +105,7 @@ enum i915_mmap_type {
> > > I915_MMAP_TYPE_WC,
> > > I915_MMAP_TYPE_WB,
> > > I915_MMAP_TYPE_UC,
> > > + I915_MMAP_TYPE_TTM,
> > > };
> > >
> > > struct i915_mmap_offset {
> > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > index 1da8bd675e54..27a35d88e5f5 100644
> > > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > @@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
> > > return 0;
> > > }
> > >
> > > +static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
> > > +{
> > > + if (HAS_LMEM(i915))
> > > + return I915_MMAP_TYPE_TTM;
> > > +
> > > + return I915_MMAP_TYPE_GTT;
> > > +}
> > > +
> > > static bool assert_mmap_offset(struct drm_i915_private *i915,
> > > unsigned long size,
> > > int expected)
> > > @@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
> > > if (IS_ERR(obj))
> > > return expected && expected == PTR_ERR(obj);
> > >
> > > - ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > > + ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > > i915_gem_object_put(obj);
> > >
> > > return ret == expected;
> > > @@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
> > > goto out;
> > > }
> > >
> > > - err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > > + err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > > if (err) {
> > > pr_err("Unable to insert object into reclaimed hole\n");
> > > goto err_obj;
> > > @@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
> > >
> > > static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
> > > {
> > > + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> > > bool no_map;
> > >
> > > + if (HAS_LMEM(i915))
> > > + return type == I915_MMAP_TYPE_TTM;
> > > + else if (type == I915_MMAP_TYPE_TTM)
> > > + return false;
> > > +
> > > if (type == I915_MMAP_TYPE_GTT &&
> > > !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
> > > return false;
> > > @@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
> > > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
> > > if (err == 0)
> > > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
> > > + if (err == 0)
> > > + err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
> > >
> > > i915_gem_object_put(obj);
> > > if (err)
> > > @@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
> > > case I915_MMAP_TYPE_WB: return "wb";
> > > case I915_MMAP_TYPE_WC: return "wc";
> > > case I915_MMAP_TYPE_UC: return "uc";
> > > + case I915_MMAP_TYPE_TTM: return "ttm";
> > > default: return "unknown";
> > > }
> > > }
> > > @@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
> > > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
> > > if (err == 0)
> > > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
> > > + if (err == 0)
> > > + err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
> > >
> > > i915_gem_object_put(obj);
> > > if (err)
> > > @@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
> > > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
> > > if (err == 0)
> > > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
> > > + if (err == 0)
> > > + err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
> > >
> > > i915_gem_object_put(obj);
> > > if (err)
> > > @@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
> > > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
> > > if (err == 0)
> > > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
> > > + if (err == 0)
> > > + err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
> > >
> > > i915_gem_object_put(obj);
> > > if (err)
> > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > index e334a8b14ef2..1610ed40b4b5 100644
> > > --- a/include/uapi/drm/i915_drm.h
> > > +++ b/include/uapi/drm/i915_drm.h
> > > @@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
> > > __u64 offset;
> > > };
> > >
> > > +/**
> > > + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> > > + *
> > > + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> > > + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> > > + *
> > > + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> > > + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> > > + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> > > + */
> > > struct drm_i915_gem_mmap_offset {
> > > - /** Handle for the object being mapped. */
> > > + /** @handle: Handle for the object being mapped. */
> > > __u32 handle;
> > > + /** @pad: Must be zero */
> > > __u32 pad;
> > > /**
> > > - * Fake offset to use for subsequent mmap call
> > > + * @offset: The fake offset to use for subsequent mmap call
> > > *
> > > * This is a fixed-size type for 32/64 compatibility.
> > > */
> > > __u64 offset;
> > >
> > > /**
> > > - * Flags for extended behaviour.
> > > + * @flags: Flags for extended behaviour.
> > > + *
> > > + * It is mandatory that one of the `MMAP_OFFSET` types
> > > + * should be included:
> > > + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
> > > + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> > > + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> > > + * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
> > > + *
> > > + * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
> > > + * devices without local memory, this caching mode is invalid.
> > > *
> > > - * It is mandatory that one of the MMAP_OFFSET types
> > > - * (GTT, WC, WB, UC, etc) should be included.
> > > + * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
> > > + * be used, depending on the object placement. WC will be used
> > > + * when the object resides in local memory, WB otherwise.
> > > */
> > > __u64 flags;
> > > -#define I915_MMAP_OFFSET_GTT 0
> > > -#define I915_MMAP_OFFSET_WC 1
> > > -#define I915_MMAP_OFFSET_WB 2
> > > -#define I915_MMAP_OFFSET_UC 3
> > >
> > > - /*
> > > - * Zero-terminated chain of extensions.
> > > +/** Use an mmap for the object by binding to GTT. */
> > > +#define I915_MMAP_OFFSET_GTT 0
> > > +/** Use Write-Combined caching. */
> > > +#define I915_MMAP_OFFSET_WC 1
> > > +/** Use Write-Back caching. */
> > > +#define I915_MMAP_OFFSET_WB 2
> > > +/** Do not use caching when binding this mmap. */
> > > +#define I915_MMAP_OFFSET_UC 3
> > > +/** Use the TTM binding, which determines the appropriate caching mode. */
> > > +#define I915_MMAP_OFFSET_TTM 4
> >
> > I'm not sure I like the name here. TTM is an implementation detail,
> > not a kind of map. I think we want something more like
> > I915_MMAP_OFFSET_IMPLICIT or something like that. The semantics here,
> > as far as I can tell, are "the mmap type is based on the object; you
> > can't change it." On DG1, the mmap type is fixed for all objects. On
> > integrated, we could have a BO create option for the mmap type but we
> > don't yet.
>
> Yeah it's not a great name, but also we didn't come up with anything
> substantially better on irc. More ideas:
> - PREDEFINED
> - PRESELECTED
>
> Note that we want to pick a value here which also makes sense for when we
> extend GEM_CREATE_EXT to allow you to select the single mmap mode you get
> at creation time (for igfx cleanup of the uapi). So IMPLICIT isn't the
> greatest name either, when we'll allow userspace to explicit chose it -
> just not here anymore.
Yeah, none of them are great. Maybe FIXED? Or PER_BO? Or BO_CREATE?
Or just BO? I think the semantics we want are "whatever was on the
BO at create time".
--Jason
>
> Anyway, pick a name and we'll paint this bikeshed, I don't care much
> really. As long as there's kerneldoc :-)
> -Daniel
>
> >
> > --Jason
> >
> > > +
> > > + /**
> > > + * @extensions: Zero-terminated chain of extensions.
> > > *
> > > * No current extensions defined; mbz.
> > > */
> > > --
> > > 2.31.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
2021-07-12 14:31 ` Jason Ekstrand
@ 2021-07-12 14:38 ` Daniel Vetter
-1 siblings, 0 replies; 18+ messages in thread
From: Daniel Vetter @ 2021-07-12 14:38 UTC (permalink / raw)
To: Jason Ekstrand; +Cc: Intel GFX, Maling list - DRI developers
On Mon, Jul 12, 2021 at 09:31:13AM -0500, Jason Ekstrand wrote:
> On Mon, Jul 12, 2021 at 9:12 AM Daniel Vetter <daniel@ffwll.ch> wrote:
> >
> > On Mon, Jul 12, 2021 at 08:47:24AM -0500, Jason Ekstrand wrote:
> > > On Fri, Jul 9, 2021 at 6:41 AM Maarten Lankhorst
> > > <maarten.lankhorst@linux.intel.com> wrote:
> > > >
> > > > This is only used for ttm, and tells userspace that the mapping type is
> > > > ignored. This disables the other type of mmap offsets when discrete
> > > > memory is used, so fix the selftests as well.
> > > >
> > > > Document the struct as well, so it shows up in docbook correctly.
> > > >
> > > > Changes since v1:
> > > > - Add docbook entries.
> > > >
> > > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
> > > > .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> > > > .../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
> > > > include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
> > > > 4 files changed, 82 insertions(+), 14 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > index a90f796e85c0..b34be9e5d094 100644
> > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > @@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
> > > > return -ENODEV;
> > > >
> > > > if (obj->ops->mmap_offset) {
> > > > + if (mmap_type != I915_MMAP_TYPE_TTM)
> > > > + return -ENODEV;
> > > > +
> > > > *offset = obj->ops->mmap_offset(obj);
> > > > return 0;
> > > > }
> > > >
> > > > + if (mmap_type == I915_MMAP_TYPE_TTM)
> > > > + return -ENODEV;
> > > > +
> > > > if (mmap_type != I915_MMAP_TYPE_GTT &&
> > > > !i915_gem_object_has_struct_page(obj) &&
> > > > !i915_gem_object_has_iomem(obj))
> > > > @@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
> > > > {
> > > > enum i915_mmap_type mmap_type;
> > > >
> > > > - if (boot_cpu_has(X86_FEATURE_PAT))
> > > > + if (HAS_LMEM(to_i915(dev)))
> > > > + mmap_type = I915_MMAP_TYPE_TTM;
> > > > + else if (boot_cpu_has(X86_FEATURE_PAT))
> > > > mmap_type = I915_MMAP_TYPE_WC;
> > > > else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
> > > > return -ENODEV;
> > > > @@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> > > > type = I915_MMAP_TYPE_UC;
> > > > break;
> > > >
> > > > + case I915_MMAP_OFFSET_TTM:
> > > > + type = I915_MMAP_TYPE_TTM;
> > > > + break;
> > > > +
> > > > default:
> > > > return -EINVAL;
> > > > }
> > > > @@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> > > > vma->vm_ops = &vm_ops_cpu;
> > > > break;
> > > >
> > > > + case I915_MMAP_TYPE_TTM:
> > > > + GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
> > > > + /* fall-through */
> > > > case I915_MMAP_TYPE_WB:
> > > > vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> > > > vma->vm_ops = &vm_ops_cpu;
> > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > > index ef3de2ae9723..d4c42bcdfeb6 100644
> > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > > @@ -105,6 +105,7 @@ enum i915_mmap_type {
> > > > I915_MMAP_TYPE_WC,
> > > > I915_MMAP_TYPE_WB,
> > > > I915_MMAP_TYPE_UC,
> > > > + I915_MMAP_TYPE_TTM,
> > > > };
> > > >
> > > > struct i915_mmap_offset {
> > > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > > index 1da8bd675e54..27a35d88e5f5 100644
> > > > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > > @@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
> > > > return 0;
> > > > }
> > > >
> > > > +static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
> > > > +{
> > > > + if (HAS_LMEM(i915))
> > > > + return I915_MMAP_TYPE_TTM;
> > > > +
> > > > + return I915_MMAP_TYPE_GTT;
> > > > +}
> > > > +
> > > > static bool assert_mmap_offset(struct drm_i915_private *i915,
> > > > unsigned long size,
> > > > int expected)
> > > > @@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
> > > > if (IS_ERR(obj))
> > > > return expected && expected == PTR_ERR(obj);
> > > >
> > > > - ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > > > + ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > > > i915_gem_object_put(obj);
> > > >
> > > > return ret == expected;
> > > > @@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
> > > > goto out;
> > > > }
> > > >
> > > > - err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > > > + err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > > > if (err) {
> > > > pr_err("Unable to insert object into reclaimed hole\n");
> > > > goto err_obj;
> > > > @@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
> > > >
> > > > static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
> > > > {
> > > > + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> > > > bool no_map;
> > > >
> > > > + if (HAS_LMEM(i915))
> > > > + return type == I915_MMAP_TYPE_TTM;
> > > > + else if (type == I915_MMAP_TYPE_TTM)
> > > > + return false;
> > > > +
> > > > if (type == I915_MMAP_TYPE_GTT &&
> > > > !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
> > > > return false;
> > > > @@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
> > > > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
> > > > if (err == 0)
> > > > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
> > > > + if (err == 0)
> > > > + err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
> > > >
> > > > i915_gem_object_put(obj);
> > > > if (err)
> > > > @@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
> > > > case I915_MMAP_TYPE_WB: return "wb";
> > > > case I915_MMAP_TYPE_WC: return "wc";
> > > > case I915_MMAP_TYPE_UC: return "uc";
> > > > + case I915_MMAP_TYPE_TTM: return "ttm";
> > > > default: return "unknown";
> > > > }
> > > > }
> > > > @@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
> > > > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
> > > > if (err == 0)
> > > > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
> > > > + if (err == 0)
> > > > + err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
> > > >
> > > > i915_gem_object_put(obj);
> > > > if (err)
> > > > @@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
> > > > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
> > > > if (err == 0)
> > > > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
> > > > + if (err == 0)
> > > > + err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
> > > >
> > > > i915_gem_object_put(obj);
> > > > if (err)
> > > > @@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
> > > > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
> > > > if (err == 0)
> > > > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
> > > > + if (err == 0)
> > > > + err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
> > > >
> > > > i915_gem_object_put(obj);
> > > > if (err)
> > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > > index e334a8b14ef2..1610ed40b4b5 100644
> > > > --- a/include/uapi/drm/i915_drm.h
> > > > +++ b/include/uapi/drm/i915_drm.h
> > > > @@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
> > > > __u64 offset;
> > > > };
> > > >
> > > > +/**
> > > > + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> > > > + *
> > > > + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> > > > + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> > > > + *
> > > > + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> > > > + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> > > > + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> > > > + */
> > > > struct drm_i915_gem_mmap_offset {
> > > > - /** Handle for the object being mapped. */
> > > > + /** @handle: Handle for the object being mapped. */
> > > > __u32 handle;
> > > > + /** @pad: Must be zero */
> > > > __u32 pad;
> > > > /**
> > > > - * Fake offset to use for subsequent mmap call
> > > > + * @offset: The fake offset to use for subsequent mmap call
> > > > *
> > > > * This is a fixed-size type for 32/64 compatibility.
> > > > */
> > > > __u64 offset;
> > > >
> > > > /**
> > > > - * Flags for extended behaviour.
> > > > + * @flags: Flags for extended behaviour.
> > > > + *
> > > > + * It is mandatory that one of the `MMAP_OFFSET` types
> > > > + * should be included:
> > > > + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
> > > > + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> > > > + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> > > > + * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
> > > > + *
> > > > + * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
> > > > + * devices without local memory, this caching mode is invalid.
> > > > *
> > > > - * It is mandatory that one of the MMAP_OFFSET types
> > > > - * (GTT, WC, WB, UC, etc) should be included.
> > > > + * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
> > > > + * be used, depending on the object placement. WC will be used
> > > > + * when the object resides in local memory, WB otherwise.
> > > > */
> > > > __u64 flags;
> > > > -#define I915_MMAP_OFFSET_GTT 0
> > > > -#define I915_MMAP_OFFSET_WC 1
> > > > -#define I915_MMAP_OFFSET_WB 2
> > > > -#define I915_MMAP_OFFSET_UC 3
> > > >
> > > > - /*
> > > > - * Zero-terminated chain of extensions.
> > > > +/** Use an mmap for the object by binding to GTT. */
> > > > +#define I915_MMAP_OFFSET_GTT 0
> > > > +/** Use Write-Combined caching. */
> > > > +#define I915_MMAP_OFFSET_WC 1
> > > > +/** Use Write-Back caching. */
> > > > +#define I915_MMAP_OFFSET_WB 2
> > > > +/** Do not use caching when binding this mmap. */
> > > > +#define I915_MMAP_OFFSET_UC 3
> > > > +/** Use the TTM binding, which determines the appropriate caching mode. */
> > > > +#define I915_MMAP_OFFSET_TTM 4
> > >
> > > I'm not sure I like the name here. TTM is an implementation detail,
> > > not a kind of map. I think we want something more like
> > > I915_MMAP_OFFSET_IMPLICIT or something like that. The semantics here,
> > > as far as I can tell, are "the mmap type is based on the object; you
> > > can't change it." On DG1, the mmap type is fixed for all objects. On
> > > integrated, we could have a BO create option for the mmap type but we
> > > don't yet.
> >
> > Yeah it's not a great name, but also we didn't come up with anything
> > substantially better on irc. More ideas:
> > - PREDEFINED
> > - PRESELECTED
> >
> > Note that we want to pick a value here which also makes sense for when we
> > extend GEM_CREATE_EXT to allow you to select the single mmap mode you get
> > at creation time (for igfx cleanup of the uapi). So IMPLICIT isn't the
> > greatest name either, when we'll allow userspace to explicit chose it -
> > just not here anymore.
>
> Yeah, none of them are great. Maybe FIXED? Or PER_BO? Or BO_CREATE?
> Or just BO? I think the semantics we want are "whatever was on the
> BO at create time".
_FIXED sounds like the least horrible one to me.
-Daniel
>
> --Jason
>
> >
> > Anyway, pick a name and we'll paint this bikeshed, I don't care much
> > really. As long as there's kerneldoc :-)
> > -Daniel
> >
> > >
> > > --Jason
> > >
> > > > +
> > > > + /**
> > > > + * @extensions: Zero-terminated chain of extensions.
> > > > *
> > > > * No current extensions defined; mbz.
> > > > */
> > > > --
> > > > 2.31.0
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
@ 2021-07-12 14:38 ` Daniel Vetter
0 siblings, 0 replies; 18+ messages in thread
From: Daniel Vetter @ 2021-07-12 14:38 UTC (permalink / raw)
To: Jason Ekstrand; +Cc: Intel GFX, Maling list - DRI developers
On Mon, Jul 12, 2021 at 09:31:13AM -0500, Jason Ekstrand wrote:
> On Mon, Jul 12, 2021 at 9:12 AM Daniel Vetter <daniel@ffwll.ch> wrote:
> >
> > On Mon, Jul 12, 2021 at 08:47:24AM -0500, Jason Ekstrand wrote:
> > > On Fri, Jul 9, 2021 at 6:41 AM Maarten Lankhorst
> > > <maarten.lankhorst@linux.intel.com> wrote:
> > > >
> > > > This is only used for ttm, and tells userspace that the mapping type is
> > > > ignored. This disables the other type of mmap offsets when discrete
> > > > memory is used, so fix the selftests as well.
> > > >
> > > > Document the struct as well, so it shows up in docbook correctly.
> > > >
> > > > Changes since v1:
> > > > - Add docbook entries.
> > > >
> > > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
> > > > .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> > > > .../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
> > > > include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
> > > > 4 files changed, 82 insertions(+), 14 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > index a90f796e85c0..b34be9e5d094 100644
> > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > @@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
> > > > return -ENODEV;
> > > >
> > > > if (obj->ops->mmap_offset) {
> > > > + if (mmap_type != I915_MMAP_TYPE_TTM)
> > > > + return -ENODEV;
> > > > +
> > > > *offset = obj->ops->mmap_offset(obj);
> > > > return 0;
> > > > }
> > > >
> > > > + if (mmap_type == I915_MMAP_TYPE_TTM)
> > > > + return -ENODEV;
> > > > +
> > > > if (mmap_type != I915_MMAP_TYPE_GTT &&
> > > > !i915_gem_object_has_struct_page(obj) &&
> > > > !i915_gem_object_has_iomem(obj))
> > > > @@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
> > > > {
> > > > enum i915_mmap_type mmap_type;
> > > >
> > > > - if (boot_cpu_has(X86_FEATURE_PAT))
> > > > + if (HAS_LMEM(to_i915(dev)))
> > > > + mmap_type = I915_MMAP_TYPE_TTM;
> > > > + else if (boot_cpu_has(X86_FEATURE_PAT))
> > > > mmap_type = I915_MMAP_TYPE_WC;
> > > > else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
> > > > return -ENODEV;
> > > > @@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> > > > type = I915_MMAP_TYPE_UC;
> > > > break;
> > > >
> > > > + case I915_MMAP_OFFSET_TTM:
> > > > + type = I915_MMAP_TYPE_TTM;
> > > > + break;
> > > > +
> > > > default:
> > > > return -EINVAL;
> > > > }
> > > > @@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> > > > vma->vm_ops = &vm_ops_cpu;
> > > > break;
> > > >
> > > > + case I915_MMAP_TYPE_TTM:
> > > > + GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
> > > > + /* fall-through */
> > > > case I915_MMAP_TYPE_WB:
> > > > vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> > > > vma->vm_ops = &vm_ops_cpu;
> > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > > index ef3de2ae9723..d4c42bcdfeb6 100644
> > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > > @@ -105,6 +105,7 @@ enum i915_mmap_type {
> > > > I915_MMAP_TYPE_WC,
> > > > I915_MMAP_TYPE_WB,
> > > > I915_MMAP_TYPE_UC,
> > > > + I915_MMAP_TYPE_TTM,
> > > > };
> > > >
> > > > struct i915_mmap_offset {
> > > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > > index 1da8bd675e54..27a35d88e5f5 100644
> > > > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > > @@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
> > > > return 0;
> > > > }
> > > >
> > > > +static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
> > > > +{
> > > > + if (HAS_LMEM(i915))
> > > > + return I915_MMAP_TYPE_TTM;
> > > > +
> > > > + return I915_MMAP_TYPE_GTT;
> > > > +}
> > > > +
> > > > static bool assert_mmap_offset(struct drm_i915_private *i915,
> > > > unsigned long size,
> > > > int expected)
> > > > @@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
> > > > if (IS_ERR(obj))
> > > > return expected && expected == PTR_ERR(obj);
> > > >
> > > > - ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > > > + ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > > > i915_gem_object_put(obj);
> > > >
> > > > return ret == expected;
> > > > @@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
> > > > goto out;
> > > > }
> > > >
> > > > - err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > > > + err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > > > if (err) {
> > > > pr_err("Unable to insert object into reclaimed hole\n");
> > > > goto err_obj;
> > > > @@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
> > > >
> > > > static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
> > > > {
> > > > + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> > > > bool no_map;
> > > >
> > > > + if (HAS_LMEM(i915))
> > > > + return type == I915_MMAP_TYPE_TTM;
> > > > + else if (type == I915_MMAP_TYPE_TTM)
> > > > + return false;
> > > > +
> > > > if (type == I915_MMAP_TYPE_GTT &&
> > > > !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
> > > > return false;
> > > > @@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
> > > > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
> > > > if (err == 0)
> > > > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
> > > > + if (err == 0)
> > > > + err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
> > > >
> > > > i915_gem_object_put(obj);
> > > > if (err)
> > > > @@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
> > > > case I915_MMAP_TYPE_WB: return "wb";
> > > > case I915_MMAP_TYPE_WC: return "wc";
> > > > case I915_MMAP_TYPE_UC: return "uc";
> > > > + case I915_MMAP_TYPE_TTM: return "ttm";
> > > > default: return "unknown";
> > > > }
> > > > }
> > > > @@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
> > > > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
> > > > if (err == 0)
> > > > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
> > > > + if (err == 0)
> > > > + err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
> > > >
> > > > i915_gem_object_put(obj);
> > > > if (err)
> > > > @@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
> > > > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
> > > > if (err == 0)
> > > > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
> > > > + if (err == 0)
> > > > + err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
> > > >
> > > > i915_gem_object_put(obj);
> > > > if (err)
> > > > @@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
> > > > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
> > > > if (err == 0)
> > > > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
> > > > + if (err == 0)
> > > > + err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
> > > >
> > > > i915_gem_object_put(obj);
> > > > if (err)
> > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > > index e334a8b14ef2..1610ed40b4b5 100644
> > > > --- a/include/uapi/drm/i915_drm.h
> > > > +++ b/include/uapi/drm/i915_drm.h
> > > > @@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
> > > > __u64 offset;
> > > > };
> > > >
> > > > +/**
> > > > + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> > > > + *
> > > > + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> > > > + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> > > > + *
> > > > + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> > > > + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> > > > + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> > > > + */
> > > > struct drm_i915_gem_mmap_offset {
> > > > - /** Handle for the object being mapped. */
> > > > + /** @handle: Handle for the object being mapped. */
> > > > __u32 handle;
> > > > + /** @pad: Must be zero */
> > > > __u32 pad;
> > > > /**
> > > > - * Fake offset to use for subsequent mmap call
> > > > + * @offset: The fake offset to use for subsequent mmap call
> > > > *
> > > > * This is a fixed-size type for 32/64 compatibility.
> > > > */
> > > > __u64 offset;
> > > >
> > > > /**
> > > > - * Flags for extended behaviour.
> > > > + * @flags: Flags for extended behaviour.
> > > > + *
> > > > + * It is mandatory that one of the `MMAP_OFFSET` types
> > > > + * should be included:
> > > > + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
> > > > + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> > > > + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> > > > + * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
> > > > + *
> > > > + * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
> > > > + * devices without local memory, this caching mode is invalid.
> > > > *
> > > > - * It is mandatory that one of the MMAP_OFFSET types
> > > > - * (GTT, WC, WB, UC, etc) should be included.
> > > > + * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
> > > > + * be used, depending on the object placement. WC will be used
> > > > + * when the object resides in local memory, WB otherwise.
> > > > */
> > > > __u64 flags;
> > > > -#define I915_MMAP_OFFSET_GTT 0
> > > > -#define I915_MMAP_OFFSET_WC 1
> > > > -#define I915_MMAP_OFFSET_WB 2
> > > > -#define I915_MMAP_OFFSET_UC 3
> > > >
> > > > - /*
> > > > - * Zero-terminated chain of extensions.
> > > > +/** Use an mmap for the object by binding to GTT. */
> > > > +#define I915_MMAP_OFFSET_GTT 0
> > > > +/** Use Write-Combined caching. */
> > > > +#define I915_MMAP_OFFSET_WC 1
> > > > +/** Use Write-Back caching. */
> > > > +#define I915_MMAP_OFFSET_WB 2
> > > > +/** Do not use caching when binding this mmap. */
> > > > +#define I915_MMAP_OFFSET_UC 3
> > > > +/** Use the TTM binding, which determines the appropriate caching mode. */
> > > > +#define I915_MMAP_OFFSET_TTM 4
> > >
> > > I'm not sure I like the name here. TTM is an implementation detail,
> > > not a kind of map. I think we want something more like
> > > I915_MMAP_OFFSET_IMPLICIT or something like that. The semantics here,
> > > as far as I can tell, are "the mmap type is based on the object; you
> > > can't change it." On DG1, the mmap type is fixed for all objects. On
> > > integrated, we could have a BO create option for the mmap type but we
> > > don't yet.
> >
> > Yeah it's not a great name, but also we didn't come up with anything
> > substantially better on irc. More ideas:
> > - PREDEFINED
> > - PRESELECTED
> >
> > Note that we want to pick a value here which also makes sense for when we
> > extend GEM_CREATE_EXT to allow you to select the single mmap mode you get
> > at creation time (for igfx cleanup of the uapi). So IMPLICIT isn't the
> > greatest name either, when we'll allow userspace to explicit chose it -
> > just not here anymore.
>
> Yeah, none of them are great. Maybe FIXED? Or PER_BO? Or BO_CREATE?
> Or just BO? I think the semantics we want are "whatever was on the
> BO at create time".
_FIXED sounds like the least horrible one to me.
-Daniel
>
> --Jason
>
> >
> > Anyway, pick a name and we'll paint this bikeshed, I don't care much
> > really. As long as there's kerneldoc :-)
> > -Daniel
> >
> > >
> > > --Jason
> > >
> > > > +
> > > > + /**
> > > > + * @extensions: Zero-terminated chain of extensions.
> > > > *
> > > > * No current extensions defined; mbz.
> > > > */
> > > > --
> > > > 2.31.0
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
2021-07-12 14:38 ` Daniel Vetter
@ 2021-07-12 15:07 ` Jason Ekstrand
-1 siblings, 0 replies; 18+ messages in thread
From: Jason Ekstrand @ 2021-07-12 15:07 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel GFX, Maling list - DRI developers
On Mon, Jul 12, 2021 at 9:38 AM Daniel Vetter <daniel@ffwll.ch> wrote:
>
> On Mon, Jul 12, 2021 at 09:31:13AM -0500, Jason Ekstrand wrote:
> > On Mon, Jul 12, 2021 at 9:12 AM Daniel Vetter <daniel@ffwll.ch> wrote:
> > >
> > > On Mon, Jul 12, 2021 at 08:47:24AM -0500, Jason Ekstrand wrote:
> > > > On Fri, Jul 9, 2021 at 6:41 AM Maarten Lankhorst
> > > > <maarten.lankhorst@linux.intel.com> wrote:
> > > > >
> > > > > This is only used for ttm, and tells userspace that the mapping type is
> > > > > ignored. This disables the other type of mmap offsets when discrete
> > > > > memory is used, so fix the selftests as well.
> > > > >
> > > > > Document the struct as well, so it shows up in docbook correctly.
> > > > >
> > > > > Changes since v1:
> > > > > - Add docbook entries.
> > > > >
> > > > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
> > > > > .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> > > > > .../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
> > > > > include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
> > > > > 4 files changed, 82 insertions(+), 14 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > > index a90f796e85c0..b34be9e5d094 100644
> > > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > > @@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
> > > > > return -ENODEV;
> > > > >
> > > > > if (obj->ops->mmap_offset) {
> > > > > + if (mmap_type != I915_MMAP_TYPE_TTM)
> > > > > + return -ENODEV;
> > > > > +
> > > > > *offset = obj->ops->mmap_offset(obj);
> > > > > return 0;
> > > > > }
> > > > >
> > > > > + if (mmap_type == I915_MMAP_TYPE_TTM)
> > > > > + return -ENODEV;
> > > > > +
> > > > > if (mmap_type != I915_MMAP_TYPE_GTT &&
> > > > > !i915_gem_object_has_struct_page(obj) &&
> > > > > !i915_gem_object_has_iomem(obj))
> > > > > @@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
> > > > > {
> > > > > enum i915_mmap_type mmap_type;
> > > > >
> > > > > - if (boot_cpu_has(X86_FEATURE_PAT))
> > > > > + if (HAS_LMEM(to_i915(dev)))
> > > > > + mmap_type = I915_MMAP_TYPE_TTM;
> > > > > + else if (boot_cpu_has(X86_FEATURE_PAT))
> > > > > mmap_type = I915_MMAP_TYPE_WC;
> > > > > else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
> > > > > return -ENODEV;
> > > > > @@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> > > > > type = I915_MMAP_TYPE_UC;
> > > > > break;
> > > > >
> > > > > + case I915_MMAP_OFFSET_TTM:
> > > > > + type = I915_MMAP_TYPE_TTM;
> > > > > + break;
> > > > > +
> > > > > default:
> > > > > return -EINVAL;
> > > > > }
> > > > > @@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> > > > > vma->vm_ops = &vm_ops_cpu;
> > > > > break;
> > > > >
> > > > > + case I915_MMAP_TYPE_TTM:
> > > > > + GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
> > > > > + /* fall-through */
> > > > > case I915_MMAP_TYPE_WB:
> > > > > vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> > > > > vma->vm_ops = &vm_ops_cpu;
> > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > > > index ef3de2ae9723..d4c42bcdfeb6 100644
> > > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > > > @@ -105,6 +105,7 @@ enum i915_mmap_type {
> > > > > I915_MMAP_TYPE_WC,
> > > > > I915_MMAP_TYPE_WB,
> > > > > I915_MMAP_TYPE_UC,
> > > > > + I915_MMAP_TYPE_TTM,
> > > > > };
> > > > >
> > > > > struct i915_mmap_offset {
> > > > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > > > index 1da8bd675e54..27a35d88e5f5 100644
> > > > > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > > > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > > > @@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
> > > > > return 0;
> > > > > }
> > > > >
> > > > > +static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
> > > > > +{
> > > > > + if (HAS_LMEM(i915))
> > > > > + return I915_MMAP_TYPE_TTM;
> > > > > +
> > > > > + return I915_MMAP_TYPE_GTT;
> > > > > +}
> > > > > +
> > > > > static bool assert_mmap_offset(struct drm_i915_private *i915,
> > > > > unsigned long size,
> > > > > int expected)
> > > > > @@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
> > > > > if (IS_ERR(obj))
> > > > > return expected && expected == PTR_ERR(obj);
> > > > >
> > > > > - ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > > > > + ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > > > > i915_gem_object_put(obj);
> > > > >
> > > > > return ret == expected;
> > > > > @@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
> > > > > goto out;
> > > > > }
> > > > >
> > > > > - err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > > > > + err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > > > > if (err) {
> > > > > pr_err("Unable to insert object into reclaimed hole\n");
> > > > > goto err_obj;
> > > > > @@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
> > > > >
> > > > > static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
> > > > > {
> > > > > + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> > > > > bool no_map;
> > > > >
> > > > > + if (HAS_LMEM(i915))
> > > > > + return type == I915_MMAP_TYPE_TTM;
> > > > > + else if (type == I915_MMAP_TYPE_TTM)
> > > > > + return false;
> > > > > +
> > > > > if (type == I915_MMAP_TYPE_GTT &&
> > > > > !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
> > > > > return false;
> > > > > @@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
> > > > > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
> > > > > if (err == 0)
> > > > > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
> > > > > + if (err == 0)
> > > > > + err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
> > > > >
> > > > > i915_gem_object_put(obj);
> > > > > if (err)
> > > > > @@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
> > > > > case I915_MMAP_TYPE_WB: return "wb";
> > > > > case I915_MMAP_TYPE_WC: return "wc";
> > > > > case I915_MMAP_TYPE_UC: return "uc";
> > > > > + case I915_MMAP_TYPE_TTM: return "ttm";
> > > > > default: return "unknown";
> > > > > }
> > > > > }
> > > > > @@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
> > > > > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
> > > > > if (err == 0)
> > > > > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
> > > > > + if (err == 0)
> > > > > + err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
> > > > >
> > > > > i915_gem_object_put(obj);
> > > > > if (err)
> > > > > @@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
> > > > > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
> > > > > if (err == 0)
> > > > > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
> > > > > + if (err == 0)
> > > > > + err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
> > > > >
> > > > > i915_gem_object_put(obj);
> > > > > if (err)
> > > > > @@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
> > > > > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
> > > > > if (err == 0)
> > > > > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
> > > > > + if (err == 0)
> > > > > + err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
> > > > >
> > > > > i915_gem_object_put(obj);
> > > > > if (err)
> > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > > > index e334a8b14ef2..1610ed40b4b5 100644
> > > > > --- a/include/uapi/drm/i915_drm.h
> > > > > +++ b/include/uapi/drm/i915_drm.h
> > > > > @@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
> > > > > __u64 offset;
> > > > > };
> > > > >
> > > > > +/**
> > > > > + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> > > > > + *
> > > > > + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> > > > > + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> > > > > + *
> > > > > + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> > > > > + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> > > > > + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> > > > > + */
> > > > > struct drm_i915_gem_mmap_offset {
> > > > > - /** Handle for the object being mapped. */
> > > > > + /** @handle: Handle for the object being mapped. */
> > > > > __u32 handle;
> > > > > + /** @pad: Must be zero */
> > > > > __u32 pad;
> > > > > /**
> > > > > - * Fake offset to use for subsequent mmap call
> > > > > + * @offset: The fake offset to use for subsequent mmap call
> > > > > *
> > > > > * This is a fixed-size type for 32/64 compatibility.
> > > > > */
> > > > > __u64 offset;
> > > > >
> > > > > /**
> > > > > - * Flags for extended behaviour.
> > > > > + * @flags: Flags for extended behaviour.
> > > > > + *
> > > > > + * It is mandatory that one of the `MMAP_OFFSET` types
> > > > > + * should be included:
> > > > > + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
> > > > > + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> > > > > + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> > > > > + * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
> > > > > + *
> > > > > + * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
> > > > > + * devices without local memory, this caching mode is invalid.
> > > > > *
> > > > > - * It is mandatory that one of the MMAP_OFFSET types
> > > > > - * (GTT, WC, WB, UC, etc) should be included.
> > > > > + * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
> > > > > + * be used, depending on the object placement. WC will be used
> > > > > + * when the object resides in local memory, WB otherwise.
> > > > > */
> > > > > __u64 flags;
> > > > > -#define I915_MMAP_OFFSET_GTT 0
> > > > > -#define I915_MMAP_OFFSET_WC 1
> > > > > -#define I915_MMAP_OFFSET_WB 2
> > > > > -#define I915_MMAP_OFFSET_UC 3
> > > > >
> > > > > - /*
> > > > > - * Zero-terminated chain of extensions.
> > > > > +/** Use an mmap for the object by binding to GTT. */
> > > > > +#define I915_MMAP_OFFSET_GTT 0
> > > > > +/** Use Write-Combined caching. */
> > > > > +#define I915_MMAP_OFFSET_WC 1
> > > > > +/** Use Write-Back caching. */
> > > > > +#define I915_MMAP_OFFSET_WB 2
> > > > > +/** Do not use caching when binding this mmap. */
> > > > > +#define I915_MMAP_OFFSET_UC 3
> > > > > +/** Use the TTM binding, which determines the appropriate caching mode. */
> > > > > +#define I915_MMAP_OFFSET_TTM 4
> > > >
> > > > I'm not sure I like the name here. TTM is an implementation detail,
> > > > not a kind of map. I think we want something more like
> > > > I915_MMAP_OFFSET_IMPLICIT or something like that. The semantics here,
> > > > as far as I can tell, are "the mmap type is based on the object; you
> > > > can't change it." On DG1, the mmap type is fixed for all objects. On
> > > > integrated, we could have a BO create option for the mmap type but we
> > > > don't yet.
> > >
> > > Yeah it's not a great name, but also we didn't come up with anything
> > > substantially better on irc. More ideas:
> > > - PREDEFINED
> > > - PRESELECTED
> > >
> > > Note that we want to pick a value here which also makes sense for when we
> > > extend GEM_CREATE_EXT to allow you to select the single mmap mode you get
> > > at creation time (for igfx cleanup of the uapi). So IMPLICIT isn't the
> > > greatest name either, when we'll allow userspace to explicit chose it -
> > > just not here anymore.
> >
> > Yeah, none of them are great. Maybe FIXED? Or PER_BO? Or BO_CREATE?
> > Or just BO? I think the semantics we want are "whatever was on the
> > BO at create time".
>
> _FIXED sounds like the least horrible one to me.
Fine with me.
> -Daniel
>
> >
> > --Jason
> >
> > >
> > > Anyway, pick a name and we'll paint this bikeshed, I don't care much
> > > really. As long as there's kerneldoc :-)
> > > -Daniel
> > >
> > > >
> > > > --Jason
> > > >
> > > > > +
> > > > > + /**
> > > > > + * @extensions: Zero-terminated chain of extensions.
> > > > > *
> > > > > * No current extensions defined; mbz.
> > > > > */
> > > > > --
> > > > > 2.31.0
> > > > >
> > > > > _______________________________________________
> > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> > > --
> > > Daniel Vetter
> > > Software Engineer, Intel Corporation
> > > http://blog.ffwll.ch
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH v2] drm/i915: Add TTM offset argument to mmap.
@ 2021-07-12 15:07 ` Jason Ekstrand
0 siblings, 0 replies; 18+ messages in thread
From: Jason Ekstrand @ 2021-07-12 15:07 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel GFX, Maling list - DRI developers
On Mon, Jul 12, 2021 at 9:38 AM Daniel Vetter <daniel@ffwll.ch> wrote:
>
> On Mon, Jul 12, 2021 at 09:31:13AM -0500, Jason Ekstrand wrote:
> > On Mon, Jul 12, 2021 at 9:12 AM Daniel Vetter <daniel@ffwll.ch> wrote:
> > >
> > > On Mon, Jul 12, 2021 at 08:47:24AM -0500, Jason Ekstrand wrote:
> > > > On Fri, Jul 9, 2021 at 6:41 AM Maarten Lankhorst
> > > > <maarten.lankhorst@linux.intel.com> wrote:
> > > > >
> > > > > This is only used for ttm, and tells userspace that the mapping type is
> > > > > ignored. This disables the other type of mmap offsets when discrete
> > > > > memory is used, so fix the selftests as well.
> > > > >
> > > > > Document the struct as well, so it shows up in docbook correctly.
> > > > >
> > > > > Changes since v1:
> > > > > - Add docbook entries.
> > > > >
> > > > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 ++++++-
> > > > > .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> > > > > .../drm/i915/gem/selftests/i915_gem_mman.c | 27 +++++++++-
> > > > > include/uapi/drm/i915_drm.h | 51 +++++++++++++++----
> > > > > 4 files changed, 82 insertions(+), 14 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > > index a90f796e85c0..b34be9e5d094 100644
> > > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > > @@ -679,10 +679,16 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
> > > > > return -ENODEV;
> > > > >
> > > > > if (obj->ops->mmap_offset) {
> > > > > + if (mmap_type != I915_MMAP_TYPE_TTM)
> > > > > + return -ENODEV;
> > > > > +
> > > > > *offset = obj->ops->mmap_offset(obj);
> > > > > return 0;
> > > > > }
> > > > >
> > > > > + if (mmap_type == I915_MMAP_TYPE_TTM)
> > > > > + return -ENODEV;
> > > > > +
> > > > > if (mmap_type != I915_MMAP_TYPE_GTT &&
> > > > > !i915_gem_object_has_struct_page(obj) &&
> > > > > !i915_gem_object_has_iomem(obj))
> > > > > @@ -727,7 +733,9 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
> > > > > {
> > > > > enum i915_mmap_type mmap_type;
> > > > >
> > > > > - if (boot_cpu_has(X86_FEATURE_PAT))
> > > > > + if (HAS_LMEM(to_i915(dev)))
> > > > > + mmap_type = I915_MMAP_TYPE_TTM;
> > > > > + else if (boot_cpu_has(X86_FEATURE_PAT))
> > > > > mmap_type = I915_MMAP_TYPE_WC;
> > > > > else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt))
> > > > > return -ENODEV;
> > > > > @@ -798,6 +806,10 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
> > > > > type = I915_MMAP_TYPE_UC;
> > > > > break;
> > > > >
> > > > > + case I915_MMAP_OFFSET_TTM:
> > > > > + type = I915_MMAP_TYPE_TTM;
> > > > > + break;
> > > > > +
> > > > > default:
> > > > > return -EINVAL;
> > > > > }
> > > > > @@ -968,6 +980,9 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
> > > > > vma->vm_ops = &vm_ops_cpu;
> > > > > break;
> > > > >
> > > > > + case I915_MMAP_TYPE_TTM:
> > > > > + GEM_WARN_ON(mmo->mmap_type == I915_MMAP_TYPE_TTM);
> > > > > + /* fall-through */
> > > > > case I915_MMAP_TYPE_WB:
> > > > > vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
> > > > > vma->vm_ops = &vm_ops_cpu;
> > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > > > index ef3de2ae9723..d4c42bcdfeb6 100644
> > > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > > > @@ -105,6 +105,7 @@ enum i915_mmap_type {
> > > > > I915_MMAP_TYPE_WC,
> > > > > I915_MMAP_TYPE_WB,
> > > > > I915_MMAP_TYPE_UC,
> > > > > + I915_MMAP_TYPE_TTM,
> > > > > };
> > > > >
> > > > > struct i915_mmap_offset {
> > > > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > > > index 1da8bd675e54..27a35d88e5f5 100644
> > > > > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > > > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> > > > > @@ -573,6 +573,14 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
> > > > > return 0;
> > > > > }
> > > > >
> > > > > +static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
> > > > > +{
> > > > > + if (HAS_LMEM(i915))
> > > > > + return I915_MMAP_TYPE_TTM;
> > > > > +
> > > > > + return I915_MMAP_TYPE_GTT;
> > > > > +}
> > > > > +
> > > > > static bool assert_mmap_offset(struct drm_i915_private *i915,
> > > > > unsigned long size,
> > > > > int expected)
> > > > > @@ -585,7 +593,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
> > > > > if (IS_ERR(obj))
> > > > > return expected && expected == PTR_ERR(obj);
> > > > >
> > > > > - ret = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > > > > + ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > > > > i915_gem_object_put(obj);
> > > > >
> > > > > return ret == expected;
> > > > > @@ -689,7 +697,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
> > > > > goto out;
> > > > > }
> > > > >
> > > > > - err = __assign_mmap_offset(obj, I915_MMAP_TYPE_GTT, &offset, NULL);
> > > > > + err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
> > > > > if (err) {
> > > > > pr_err("Unable to insert object into reclaimed hole\n");
> > > > > goto err_obj;
> > > > > @@ -831,8 +839,14 @@ static int wc_check(struct drm_i915_gem_object *obj)
> > > > >
> > > > > static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
> > > > > {
> > > > > + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> > > > > bool no_map;
> > > > >
> > > > > + if (HAS_LMEM(i915))
> > > > > + return type == I915_MMAP_TYPE_TTM;
> > > > > + else if (type == I915_MMAP_TYPE_TTM)
> > > > > + return false;
> > > > > +
> > > > > if (type == I915_MMAP_TYPE_GTT &&
> > > > > !i915_ggtt_has_aperture(&to_i915(obj->base.dev)->ggtt))
> > > > > return false;
> > > > > @@ -970,6 +984,8 @@ static int igt_mmap(void *arg)
> > > > > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
> > > > > if (err == 0)
> > > > > err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
> > > > > + if (err == 0)
> > > > > + err = __igt_mmap(i915, obj, I915_MMAP_TYPE_TTM);
> > > > >
> > > > > i915_gem_object_put(obj);
> > > > > if (err)
> > > > > @@ -987,6 +1003,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
> > > > > case I915_MMAP_TYPE_WB: return "wb";
> > > > > case I915_MMAP_TYPE_WC: return "wc";
> > > > > case I915_MMAP_TYPE_UC: return "uc";
> > > > > + case I915_MMAP_TYPE_TTM: return "ttm";
> > > > > default: return "unknown";
> > > > > }
> > > > > }
> > > > > @@ -1100,6 +1117,8 @@ static int igt_mmap_access(void *arg)
> > > > > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
> > > > > if (err == 0)
> > > > > err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
> > > > > + if (err == 0)
> > > > > + err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_TTM);
> > > > >
> > > > > i915_gem_object_put(obj);
> > > > > if (err)
> > > > > @@ -1241,6 +1260,8 @@ static int igt_mmap_gpu(void *arg)
> > > > > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
> > > > > if (err == 0)
> > > > > err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
> > > > > + if (err == 0)
> > > > > + err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_TTM);
> > > > >
> > > > > i915_gem_object_put(obj);
> > > > > if (err)
> > > > > @@ -1396,6 +1417,8 @@ static int igt_mmap_revoke(void *arg)
> > > > > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
> > > > > if (err == 0)
> > > > > err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
> > > > > + if (err == 0)
> > > > > + err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_TTM);
> > > > >
> > > > > i915_gem_object_put(obj);
> > > > > if (err)
> > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > > > index e334a8b14ef2..1610ed40b4b5 100644
> > > > > --- a/include/uapi/drm/i915_drm.h
> > > > > +++ b/include/uapi/drm/i915_drm.h
> > > > > @@ -849,31 +849,60 @@ struct drm_i915_gem_mmap_gtt {
> > > > > __u64 offset;
> > > > > };
> > > > >
> > > > > +/**
> > > > > + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> > > > > + *
> > > > > + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> > > > > + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> > > > > + *
> > > > > + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> > > > > + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> > > > > + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> > > > > + */
> > > > > struct drm_i915_gem_mmap_offset {
> > > > > - /** Handle for the object being mapped. */
> > > > > + /** @handle: Handle for the object being mapped. */
> > > > > __u32 handle;
> > > > > + /** @pad: Must be zero */
> > > > > __u32 pad;
> > > > > /**
> > > > > - * Fake offset to use for subsequent mmap call
> > > > > + * @offset: The fake offset to use for subsequent mmap call
> > > > > *
> > > > > * This is a fixed-size type for 32/64 compatibility.
> > > > > */
> > > > > __u64 offset;
> > > > >
> > > > > /**
> > > > > - * Flags for extended behaviour.
> > > > > + * @flags: Flags for extended behaviour.
> > > > > + *
> > > > > + * It is mandatory that one of the `MMAP_OFFSET` types
> > > > > + * should be included:
> > > > > + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT.
> > > > > + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> > > > > + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> > > > > + * - `I915_MMAP_OFFSET_TTM`: Use TTM to determine caching based on object placement.
> > > > > + *
> > > > > + * Only on devices with local memory is `I915_MMAP_OFFSET_TTM` valid. On
> > > > > + * devices without local memory, this caching mode is invalid.
> > > > > *
> > > > > - * It is mandatory that one of the MMAP_OFFSET types
> > > > > - * (GTT, WC, WB, UC, etc) should be included.
> > > > > + * As caching mode when specifying `I915_MMAP_OFFSET_TTM`, WC or WB will
> > > > > + * be used, depending on the object placement. WC will be used
> > > > > + * when the object resides in local memory, WB otherwise.
> > > > > */
> > > > > __u64 flags;
> > > > > -#define I915_MMAP_OFFSET_GTT 0
> > > > > -#define I915_MMAP_OFFSET_WC 1
> > > > > -#define I915_MMAP_OFFSET_WB 2
> > > > > -#define I915_MMAP_OFFSET_UC 3
> > > > >
> > > > > - /*
> > > > > - * Zero-terminated chain of extensions.
> > > > > +/** Use an mmap for the object by binding to GTT. */
> > > > > +#define I915_MMAP_OFFSET_GTT 0
> > > > > +/** Use Write-Combined caching. */
> > > > > +#define I915_MMAP_OFFSET_WC 1
> > > > > +/** Use Write-Back caching. */
> > > > > +#define I915_MMAP_OFFSET_WB 2
> > > > > +/** Do not use caching when binding this mmap. */
> > > > > +#define I915_MMAP_OFFSET_UC 3
> > > > > +/** Use the TTM binding, which determines the appropriate caching mode. */
> > > > > +#define I915_MMAP_OFFSET_TTM 4
> > > >
> > > > I'm not sure I like the name here. TTM is an implementation detail,
> > > > not a kind of map. I think we want something more like
> > > > I915_MMAP_OFFSET_IMPLICIT or something like that. The semantics here,
> > > > as far as I can tell, are "the mmap type is based on the object; you
> > > > can't change it." On DG1, the mmap type is fixed for all objects. On
> > > > integrated, we could have a BO create option for the mmap type but we
> > > > don't yet.
> > >
> > > Yeah it's not a great name, but also we didn't come up with anything
> > > substantially better on irc. More ideas:
> > > - PREDEFINED
> > > - PRESELECTED
> > >
> > > Note that we want to pick a value here which also makes sense for when we
> > > extend GEM_CREATE_EXT to allow you to select the single mmap mode you get
> > > at creation time (for igfx cleanup of the uapi). So IMPLICIT isn't the
> > > greatest name either, when we'll allow userspace to explicit chose it -
> > > just not here anymore.
> >
> > Yeah, none of them are great. Maybe FIXED? Or PER_BO? Or BO_CREATE?
> > Or just BO? I think the semantics we want are "whatever was on the
> > BO at create time".
>
> _FIXED sounds like the least horrible one to me.
Fine with me.
> -Daniel
>
> >
> > --Jason
> >
> > >
> > > Anyway, pick a name and we'll paint this bikeshed, I don't care much
> > > really. As long as there's kerneldoc :-)
> > > -Daniel
> > >
> > > >
> > > > --Jason
> > > >
> > > > > +
> > > > > + /**
> > > > > + * @extensions: Zero-terminated chain of extensions.
> > > > > *
> > > > > * No current extensions defined; mbz.
> > > > > */
> > > > > --
> > > > > 2.31.0
> > > > >
> > > > > _______________________________________________
> > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> > > --
> > > Daniel Vetter
> > > Software Engineer, Intel Corporation
> > > http://blog.ffwll.ch
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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