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From: Abel Vesa <abel.vesa@nxp.com>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	kernel@pengutronix.de, patchwork-lst@pengutronix.de
Subject: Re: [PATCH 2/2] clk: imx8mn: use correct mux type for clkout path
Date: Mon, 19 Jul 2021 13:37:14 +0300	[thread overview]
Message-ID: <YPVV2m3n79XtGrQa@ryzen> (raw)
In-Reply-To: <20210628211554.2510238-2-l.stach@pengutronix.de>

On 21-06-28 23:15:54, Lucas Stach wrote:
> The mux in the clkout path needs the current selected parent to
> be enabled for the the switch to work. Use the correct mux type
> to have the clk framework take care of this requirement.
> 
> Fixes: af4df655040 ("clk: imx8mn: add clkout1/2 support")
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

I'm OK with this one too.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  drivers/clk/imx/clk-imx8mn.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index 88f6630cd472..212708e9388e 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -402,10 +402,10 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
>  	hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
>  
> -	hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> +	hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
>  	hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
>  	hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
> -	hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> +	hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
>  	hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
>  	hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
>  
> -- 
> 2.30.2
> 

WARNING: multiple messages have this Message-ID (diff)
From: Abel Vesa <abel.vesa@nxp.com>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	kernel@pengutronix.de, patchwork-lst@pengutronix.de
Subject: Re: [PATCH 2/2] clk: imx8mn: use correct mux type for clkout path
Date: Mon, 19 Jul 2021 13:37:14 +0300	[thread overview]
Message-ID: <YPVV2m3n79XtGrQa@ryzen> (raw)
In-Reply-To: <20210628211554.2510238-2-l.stach@pengutronix.de>

On 21-06-28 23:15:54, Lucas Stach wrote:
> The mux in the clkout path needs the current selected parent to
> be enabled for the the switch to work. Use the correct mux type
> to have the clk framework take care of this requirement.
> 
> Fixes: af4df655040 ("clk: imx8mn: add clkout1/2 support")
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

I'm OK with this one too.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  drivers/clk/imx/clk-imx8mn.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index 88f6630cd472..212708e9388e 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -402,10 +402,10 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
>  	hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
>  
> -	hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> +	hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
>  	hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
>  	hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
> -	hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
> +	hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
>  	hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
>  	hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
>  
> -- 
> 2.30.2
> 

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  reply	other threads:[~2021-07-19 10:37 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-28 21:15 [PATCH 1/2] clk: imx8mm: use correct mux type for clkout path Lucas Stach
2021-06-28 21:15 ` Lucas Stach
2021-06-28 21:15 ` [PATCH 2/2] clk: imx8mn: " Lucas Stach
2021-06-28 21:15   ` Lucas Stach
2021-07-19 10:37   ` Abel Vesa [this message]
2021-07-19 10:37     ` Abel Vesa
2021-07-19 10:36 ` [PATCH 1/2] clk: imx8mm: " Abel Vesa
2021-07-19 10:36   ` Abel Vesa
2021-07-29 10:45 ` Abel Vesa
2021-07-29 10:45   ` Abel Vesa

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