[igt-dev] [PATCH i-g-t 0/8] drm-uapi clean-up

[igt-dev] [PATCH i-g-t 0/8] drm-uapi clean-up

[Rodrigo Vivi]

Patches 1 to 3:
The main motivation of this series is to clean-up the mess
I created with the recent merge of a i915_drm.h coming from
drm-intel-gt-next rather than from drm-next. I'm sorry for that.

Patches 4:
Since I was already there, let me update some of the upstreamed
UAPIs.

Patch 5: Extra sync to drm-next, including all of the patches.

Patches 6 to 8: These might be the controversial ones. While
doing the work above, I decided that we needed to make the
documentation cleaner and more visible so we would avoid further
mistakes. But I'm okay on dropping these patches if there's
any disagreement.

Thanks,
Rodrigo.

Rodrigo Vivi (8):
  tests/i915/gem_pxp: Add LOCAL_ UAPI defines
  Revert "i915_drm.h sync"
  i915_drm.h sync with drm-next
  tests/gem_userptr_blits: Remove LOCAL_
  include/drm-uapi: Sync with drm-next
  README.md: Detail the drm-uapi headers sync.
  include: Introduce linux-uapi for non-drm-uapi files.
  README.md: Accept the i915_drm.h standalone update.

 README.md                                    |  38 +-
 include/drm-uapi/drm.h                       |  14 +-
 include/drm-uapi/drm_fourcc.h                | 115 ++++-
 include/drm-uapi/drm_mode.h                  |  95 ++++-
 include/drm-uapi/i915_drm.h                  |  99 +----
 include/drm-uapi/msm_drm.h                   |  14 +-
 include/drm-uapi/tegra_drm.h                 | 425 ++++++++++++++++++-
 include/drm-uapi/v3d_drm.h                   | 136 ++++++
 include/drm-uapi/vmwgfx_drm.h                |  41 ++
 include/{drm-uapi => linux-uapi}/sync_file.h |   0
 meson.build                                  |   2 +-
 tests/i915/gem_pxp.c                         |  31 +-
 tests/i915/gem_userptr_blits.c               |   7 +-
 13 files changed, 866 insertions(+), 151 deletions(-)
 rename include/{drm-uapi => linux-uapi}/sync_file.h (100%)

-- 
2.31.1

[igt-dev] [PATCH i-g-t 1/8] tests/i915/gem_pxp: Add LOCAL_ UAPI defines

[Rodrigo Vivi]

While the UAPI changes don't propagate to drm-next we should
have that as LOCAL_ ones.

That was my mistake during review and merge since I had
ignored the rules documented at README.md and considered
drm-intel branches would be enough. I'm sorry.

Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 tests/i915/gem_pxp.c | 31 +++++++++++++++++++++----------
 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 79040165..afd4ce4d 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -25,14 +25,25 @@ struct simple_exec_assets {
 	struct intel_bb *ibb;
 };
 
+#define LOCAL_I915_GEM_CREATE_EXT_PROTECTED_CONTENT	1
+#define LOCAL_I915_CONTEXT_PARAM_PROTECTED_CONTENT	0xd
+#define LOCAL_I915_PROTECTED_CONTENT_DEFAULT_SESSION	0xf
+
+struct local_drm_i915_gem_create_ext_protected_content {
+       /** @base: Extension link. See struct i915_user_extension. */
+       struct i915_user_extension base;
+       /** @flags: reserved for future usage, currently MBZ */
+       __u32 flags;
+};
+
 static int create_bo_ext(int i915, uint32_t size, bool protected_is_true, uint32_t *bo_out)
 {
 	int ret;
 	uint64_t size64 = size;
 	struct i915_user_extension *ext = NULL;
 
-	struct drm_i915_gem_create_ext_protected_content protected_ext = {
-		.base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT },
+	struct local_drm_i915_gem_create_ext_protected_content protected_ext = {
+		.base = { .name = LOCAL_I915_GEM_CREATE_EXT_PROTECTED_CONTENT },
 		.flags = 0,
 	};
 
@@ -92,7 +103,7 @@ static int create_ctx_with_params(int i915, bool with_protected_param, bool prot
 			.next_extension = 0,
 		},
 		.param = {
-			.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+			.param = LOCAL_I915_CONTEXT_PARAM_PROTECTED_CONTENT,
 			.value = 0,
 		}
 	};
@@ -143,7 +154,7 @@ static int modify_ctx_param(int i915, uint32_t ctx_id, uint32_t param_mask, bool
 	};
 
 	if (param_mask == CHANGE_PARAM_PROTECTED) {
-		ctx_param.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT;
+		ctx_param.param = LOCAL_I915_CONTEXT_PARAM_PROTECTED_CONTENT;
 		ctx_param.value = (int)param_value;
 	} else if (param_mask == CHANGE_PARAM_RECOVERY) {
 		ctx_param.param = I915_CONTEXT_PARAM_RECOVERABLE;
@@ -161,7 +172,7 @@ static int get_ctx_protected_param(int i915, uint32_t ctx_id)
 
 	struct drm_i915_gem_context_param ctx_param = {
 		.ctx_id = ctx_id,
-		.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+		.param = LOCAL_I915_CONTEXT_PARAM_PROTECTED_CONTENT,
 	};
 
 	ret = igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
@@ -508,7 +519,7 @@ static void __test_render_pxp_src_to_protdest(int i915, uint32_t *outpixels, int
 	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
 	ibb = intel_bb_create_with_context(i915, ctx, 4096);
 	igt_assert(ibb);
-	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, LOCAL_I915_PROTECTED_CONTENT_DEFAULT_SESSION);
 
 	dstbo = alloc_and_fill_dest_buff(i915, true, TSTSURF_SIZE, TSTSURF_INITCOLOR2);
 	dstbuf = intel_buf_create_using_handle(bops, dstbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
@@ -569,7 +580,7 @@ static void test_render_pxp_protsrc_to_protdest(int i915)
 	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
 	ibb = intel_bb_create_with_context(i915, ctx, 4096);
 	igt_assert(ibb);
-	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, LOCAL_I915_PROTECTED_CONTENT_DEFAULT_SESSION);
 
 	dstbo = alloc_and_fill_dest_buff(i915, true, TSTSURF_SIZE, TSTSURF_INITCOLOR2);
 	dstbuf = intel_buf_create_using_handle(bops, dstbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
@@ -603,7 +614,7 @@ static void test_render_pxp_protsrc_to_protdest(int i915)
 	intel_buf_set_pxp(dstbuf2, true);
 	intel_buf_set_pxp(dstbuf, true);/*this time, src is protected*/
 
-	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, LOCAL_I915_PROTECTED_CONTENT_DEFAULT_SESSION);
 
 	gen12_render_copyfunc(ibb, dstbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf2, 0, 0);
 	gem_sync(i915, dstbo2);
@@ -675,7 +686,7 @@ static void test_pxp_dmabuffshare_refcnt(void)
 		igt_assert_eq(get_ctx_protected_param(fd[n], ctx[n]), 1);
 		ibb[n] = intel_bb_create_with_context(fd[n], ctx[n], 4096);
 		intel_bb_set_pxp(ibb[n], true, DISPLAY_APPTYPE,
-				 I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+				 LOCAL_I915_PROTECTED_CONTENT_DEFAULT_SESSION);
 
 		bops[n] = buf_ops_create(fd[n]);
 		if (n == 1)
@@ -1066,7 +1077,7 @@ static void setup_protected_fb(int i915, int width, int height, igt_fb_t *fb, ui
 
 	ibb->pxp.enabled = true;
 	ibb->pxp.apptype = DISPLAY_APPTYPE;
-	ibb->pxp.appid = I915_PROTECTED_CONTENT_DEFAULT_SESSION;
+	ibb->pxp.appid = LOCAL_I915_PROTECTED_CONTENT_DEFAULT_SESSION;
 
 	gen12_render_copyfunc(ibb, srcbuf, 0, 0, fb->width, fb->height, dstbuf, 0, 0);
 
-- 
2.31.1

[igt-dev] [PATCH i-g-t 2/8] Revert "i915_drm.h sync"

[Rodrigo Vivi]

This reverts commit 4d5f8bcd2e35de368fcaa968c127111d9f450247.

That was my mistake during review and merge since I had
ignored the rules documented at README.md and considered
drm-intel branches would be enough. I'm sorry.

Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 include/drm-uapi/i915_drm.h | 147 +-----------------------------------
 1 file changed, 1 insertion(+), 146 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 50c9308b..b9632bb2 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -572,15 +572,6 @@ typedef struct drm_i915_irq_wait {
 #define   I915_SCHEDULER_CAP_PREEMPTION	(1ul << 2)
 #define   I915_SCHEDULER_CAP_SEMAPHORES	(1ul << 3)
 #define   I915_SCHEDULER_CAP_ENGINE_BUSY_STATS	(1ul << 4)
-/*
- * Indicates the 2k user priority levels are statically mapped into 3 buckets as
- * follows:
- *
- * -1k to -1	Low priority
- * 0		Normal priority
- * 1 to 1k	Highest priority
- */
-#define   I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP	(1ul << 5)
 
 #define I915_PARAM_HUC_STATUS		 42
 
@@ -683,9 +674,6 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
 
-/* Query if the kernel supports the I915_USERPTR_PROBE flag. */
-#define I915_PARAM_HAS_USERPTR_PROBE 56
-
 /* Must be kept compact -- no holes and well documented */
 
 typedef struct drm_i915_getparam {
@@ -935,25 +923,6 @@ struct drm_i915_gem_mmap_offset {
  *	- I915_GEM_DOMAIN_GTT: Mappable aperture domain
  *
  * All other domains are rejected.
- *
- * Note that for discrete, starting from DG1, this is no longer supported, and
- * is instead rejected. On such platforms the CPU domain is effectively static,
- * where we also only support a single &drm_i915_gem_mmap_offset cache mode,
- * which can't be set explicitly and instead depends on the object placements,
- * as per the below.
- *
- * Implicit caching rules, starting from DG1:
- *
- *	- If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
- *	  contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
- *	  mapped as write-combined only.
- *
- *	- Everything else is always allocated and mapped as write-back, with the
- *	  guarantee that everything is also coherent with the GPU.
- *
- * Note that this is likely to change in the future again, where we might need
- * more flexibility on future devices, so making this all explicit as part of a
- * new &drm_i915_gem_create_ext extension is probable.
  */
 struct drm_i915_gem_set_domain {
 	/** @handle: Handle for the object. */
@@ -1846,55 +1815,6 @@ struct drm_i915_gem_context_param {
  * attempted to use it, never re-use this context param number.
  */
 #define I915_CONTEXT_PARAM_RINGSIZE	0xc
-
-/*
- * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
- *
- * Mark that the context makes use of protected content, which will result
- * in the context being invalidated when the protected content session is.
- * Given that the protected content session is killed on suspend, the device
- * is kept awake for the lifetime of a protected context, so the user should
- * make sure to dispose of them once done.
- * This flag can only be set at context creation time and, when set to true,
- * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
- * to false. This flag can't be set to true in conjunction with setting the
- * I915_CONTEXT_PARAM_BANNABLE flag to false. Creation example:
- *
- * .. code-block:: C
- *
- *	struct drm_i915_gem_context_create_ext_setparam p_protected = {
- *		.base = {
- *			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
- *		},
- *		.param = {
- *			.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
- *			.value = 1,
- *		}
- *	};
- *	struct drm_i915_gem_context_create_ext_setparam p_norecover = {
- *		.base = {
- *			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
- *			.next_extension = to_user_pointer(&p_protected),
- *		},
- *		.param = {
- *			.param = I915_CONTEXT_PARAM_RECOVERABLE,
- *			.value = 0,
- *		}
- *	};
- *	struct drm_i915_gem_context_create_ext create = {
- *		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
- *		.extensions = to_user_pointer(&p_norecover);
- *	};
- *
- *	ctx_id = gem_context_create_ext(drm_fd, &create);
- *
- * In addition to the normal failure cases, setting this flag during context
- * creation can result in the following errors:
- *
- * -ENODEV: feature not available
- * -EPERM: trying to mark a recoverable or not bannable context as protected
- */
-#define I915_CONTEXT_PARAM_PROTECTED_CONTENT    0xd
 /* Must be kept compact -- no holes and well documented */
 
 	__u64 value;
@@ -2283,29 +2203,12 @@ struct drm_i915_gem_userptr {
 	 * through the GTT. If the HW can't support readonly access, an error is
 	 * returned.
 	 *
-	 * I915_USERPTR_PROBE:
-	 *
-	 * Probe the provided @user_ptr range and validate that the @user_ptr is
-	 * indeed pointing to normal memory and that the range is also valid.
-	 * For example if some garbage address is given to the kernel, then this
-	 * should complain.
-	 *
-	 * Returns -EFAULT if the probe failed.
-	 *
-	 * Note that this doesn't populate the backing pages, and also doesn't
-	 * guarantee that the object will remain valid when the object is
-	 * eventually used.
-	 *
-	 * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE
-	 * returns a non-zero value.
-	 *
 	 * I915_USERPTR_UNSYNCHRONIZED:
 	 *
 	 * NOT USED. Setting this flag will result in an error.
 	 */
 	__u32 flags;
 #define I915_USERPTR_READ_ONLY 0x1
-#define I915_USERPTR_PROBE 0x2
 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
 	/**
 	 * @handle: Returned handle for the object.
@@ -2457,7 +2360,7 @@ struct drm_i915_perf_open_param {
  * Change metrics_set captured by a stream.
  *
  * If the stream is bound to a specific context, the configuration change
- * will performed inline with that context such that it takes effect before
+ * will performed __inline__ with that context such that it takes effect before
  * the next execbuf submission.
  *
  * Returns the previously bound metrics set id, or a negative error code.
@@ -3028,12 +2931,8 @@ struct drm_i915_gem_create_ext {
 	 *
 	 * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
 	 * struct drm_i915_gem_create_ext_memory_regions.
-	 *
-	 * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
-	 * struct drm_i915_gem_create_ext_protected_content.
 	 */
 #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
-#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
 	__u64 extensions;
 };
 
@@ -3091,50 +2990,6 @@ struct drm_i915_gem_create_ext_memory_regions {
 	__u64 regions;
 };
 
-/**
- * struct drm_i915_gem_create_ext_protected_content - The
- * I915_OBJECT_PARAM_PROTECTED_CONTENT extension.
- *
- * If this extension is provided, buffer contents are expected to be protected
- * by PXP encryption and require decryption for scan out and processing. This
- * is only possible on platforms that have PXP enabled, on all other scenarios
- * using this extension will cause the ioctl to fail and return -ENODEV. The
- * flags parameter is reserved for future expansion and must currently be set
- * to zero.
- *
- * The buffer contents are considered invalid after a PXP session teardown.
- *
- * The encryption is guaranteed to be processed correctly only if the object
- * is submitted with a context created using the
- * I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks
- * at submission time on the validity of the objects involved.
- *
- * Below is an example on how to create a protected object:
- *
- * .. code-block:: C
- *
- *      struct drm_i915_gem_create_ext_protected_content protected_ext = {
- *              .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT },
- *              .flags = 0,
- *      };
- *      struct drm_i915_gem_create_ext create_ext = {
- *              .size = PAGE_SIZE,
- *              .extensions = (uintptr_t)&protected_ext,
- *      };
- *
- *      int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
- *      if (err) ...
- */
-struct drm_i915_gem_create_ext_protected_content {
-	/** @base: Extension link. See struct i915_user_extension. */
-	struct i915_user_extension base;
-	/** @flags: reserved for future usage, currently MBZ */
-	__u32 flags;
-};
-
-/* ID of the protected content session managed by i915 when PXP is active */
-#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
-
 #if defined(__cplusplus)
 }
 #endif
-- 
2.31.1

[igt-dev] [PATCH i-g-t 3/8] i915_drm.h sync with drm-next

[Rodrigo Vivi]

Let's do a catch-up on i915_drm.h here.
Only on i915_drm.h for now so we can have a clean
view of the LOCAL_ ones that we need to remove.

Taken from 25fed6b324ac ("Merge tag 'drm-intel-gt-next-2021-08-06-1' of ssh://git.freedesktop.org/git/drm/drm-intel into drm-next")

Cc: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 include/drm-uapi/i915_drm.h | 48 +++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index b9632bb2..c788a1ab 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -572,6 +572,15 @@ typedef struct drm_i915_irq_wait {
 #define   I915_SCHEDULER_CAP_PREEMPTION	(1ul << 2)
 #define   I915_SCHEDULER_CAP_SEMAPHORES	(1ul << 3)
 #define   I915_SCHEDULER_CAP_ENGINE_BUSY_STATS	(1ul << 4)
+/*
+ * Indicates the 2k user priority levels are statically mapped into 3 buckets as
+ * follows:
+ *
+ * -1k to -1	Low priority
+ * 0		Normal priority
+ * 1 to 1k	Highest priority
+ */
+#define   I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP	(1ul << 5)
 
 #define I915_PARAM_HUC_STATUS		 42
 
@@ -674,6 +683,9 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
 
+/* Query if the kernel supports the I915_USERPTR_PROBE flag. */
+#define I915_PARAM_HAS_USERPTR_PROBE 56
+
 /* Must be kept compact -- no holes and well documented */
 
 typedef struct drm_i915_getparam {
@@ -923,6 +935,25 @@ struct drm_i915_gem_mmap_offset {
  *	- I915_GEM_DOMAIN_GTT: Mappable aperture domain
  *
  * All other domains are rejected.
+ *
+ * Note that for discrete, starting from DG1, this is no longer supported, and
+ * is instead rejected. On such platforms the CPU domain is effectively static,
+ * where we also only support a single &drm_i915_gem_mmap_offset cache mode,
+ * which can't be set explicitly and instead depends on the object placements,
+ * as per the below.
+ *
+ * Implicit caching rules, starting from DG1:
+ *
+ *	- If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
+ *	  contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
+ *	  mapped as write-combined only.
+ *
+ *	- Everything else is always allocated and mapped as write-back, with the
+ *	  guarantee that everything is also coherent with the GPU.
+ *
+ * Note that this is likely to change in the future again, where we might need
+ * more flexibility on future devices, so making this all explicit as part of a
+ * new &drm_i915_gem_create_ext extension is probable.
  */
 struct drm_i915_gem_set_domain {
 	/** @handle: Handle for the object. */
@@ -2203,12 +2234,29 @@ struct drm_i915_gem_userptr {
 	 * through the GTT. If the HW can't support readonly access, an error is
 	 * returned.
 	 *
+	 * I915_USERPTR_PROBE:
+	 *
+	 * Probe the provided @user_ptr range and validate that the @user_ptr is
+	 * indeed pointing to normal memory and that the range is also valid.
+	 * For example if some garbage address is given to the kernel, then this
+	 * should complain.
+	 *
+	 * Returns -EFAULT if the probe failed.
+	 *
+	 * Note that this doesn't populate the backing pages, and also doesn't
+	 * guarantee that the object will remain valid when the object is
+	 * eventually used.
+	 *
+	 * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE
+	 * returns a non-zero value.
+	 *
 	 * I915_USERPTR_UNSYNCHRONIZED:
 	 *
 	 * NOT USED. Setting this flag will result in an error.
 	 */
 	__u32 flags;
 #define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_PROBE 0x2
 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
 	/**
 	 * @handle: Returned handle for the object.
-- 
2.31.1

[igt-dev] [PATCH i-g-t 4/8] tests/gem_userptr_blits: Remove LOCAL_

[Rodrigo Vivi]

These UAPIs are upstreamed now.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 tests/i915/gem_userptr_blits.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index 756bd6e4..0d084674 100644
--- a/tests/i915/gem_userptr_blits.c
+++ b/tests/i915/gem_userptr_blits.c
@@ -2151,16 +2151,13 @@ static int userfaultfd(int flags)
 	return syscall(SYS_userfaultfd, flags);
 }
 
-#define LOCAL_I915_PARAM_HAS_USERPTR_PROBE 56
-#define LOCAL_I915_USERPTR_PROBE 0x2
-
 static bool has_userptr_probe(int fd)
 {
 	struct drm_i915_getparam gp;
 	int value = 0;
 
 	memset(&gp, 0, sizeof(gp));
-	gp.param = LOCAL_I915_PARAM_HAS_USERPTR_PROBE;
+	gp.param = I915_PARAM_HAS_USERPTR_PROBE;
 	gp.value = &value;
 
 	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp));
@@ -2222,7 +2219,7 @@ static void test_probe(int fd)
 		}
 
 		igt_assert_eq(__gem_userptr(fd, ptr + PAGE_SIZE, 3*PAGE_SIZE,
-					    0, LOCAL_I915_USERPTR_PROBE, &handle),
+					    0, I915_USERPTR_PROBE, &handle),
 			      expected);
 
 		munmap(ptr, N_PAGES * PAGE_SIZE);
-- 
2.31.1

[igt-dev] [PATCH i-g-t 5/8] include/drm-uapi: Sync with drm-next

[Rodrigo Vivi]

Sync to: 1e3944578b74 ("Merge tag 'amd-drm-next-5.16-2021-09-27' of https://gitlab.freedesktop.org/agd5f/linux into drm-next")

Cc: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 include/drm-uapi/drm.h        |  14 +-
 include/drm-uapi/drm_fourcc.h | 115 ++++++++-
 include/drm-uapi/drm_mode.h   |  95 +++++++-
 include/drm-uapi/msm_drm.h    |  14 +-
 include/drm-uapi/tegra_drm.h  | 425 ++++++++++++++++++++++++++++++++--
 include/drm-uapi/v3d_drm.h    | 136 +++++++++++
 include/drm-uapi/vmwgfx_drm.h |  41 ++++
 7 files changed, 807 insertions(+), 33 deletions(-)

diff --git a/include/drm-uapi/drm.h b/include/drm-uapi/drm.h
index 398c396f..5e54c3aa 100644
--- a/include/drm-uapi/drm.h
+++ b/include/drm-uapi/drm.h
@@ -629,8 +629,8 @@ struct drm_gem_open {
 /**
  * DRM_CAP_VBLANK_HIGH_CRTC
  *
- * If set to 1, the kernel supports specifying a CRTC index in the high bits of
- * &drm_wait_vblank_request.type.
+ * If set to 1, the kernel supports specifying a :ref:`CRTC index<crtc_index>`
+ * in the high bits of &drm_wait_vblank_request.type.
  *
  * Starting kernel version 2.6.39, this capability is always set to 1.
  */
@@ -1044,6 +1044,16 @@ extern "C" {
 #define DRM_IOCTL_MODE_GETPROPBLOB	DRM_IOWR(0xAC, struct drm_mode_get_blob)
 #define DRM_IOCTL_MODE_GETFB		DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
 #define DRM_IOCTL_MODE_ADDFB		DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
+/**
+ * DRM_IOCTL_MODE_RMFB - Remove a framebuffer.
+ *
+ * This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL
+ * argument is a framebuffer object ID.
+ *
+ * Warning: removing a framebuffer currently in-use on an enabled plane will
+ * disable that plane. The CRTC the plane is linked to may also be disabled
+ * (depending on driver capabilities).
+ */
 #define DRM_IOCTL_MODE_RMFB		DRM_IOWR(0xAF, unsigned int)
 #define DRM_IOCTL_MODE_PAGE_FLIP	DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
 #define DRM_IOCTL_MODE_DIRTYFB		DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index cd3ce8a8..91b6a0fd 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -373,6 +373,12 @@ extern "C" {
 
 #define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
 
+#define fourcc_mod_get_vendor(modifier) \
+	(((modifier) >> 56) & 0xff)
+
+#define fourcc_mod_is_vendor(modifier, vendor) \
+	(fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor)
+
 #define fourcc_mod_code(vendor, val) \
 	((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
 
@@ -900,9 +906,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 
 /*
  * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
- * modifiers) denote the category for modifiers. Currently we have only two
- * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
- * different categories.
+ * modifiers) denote the category for modifiers. Currently we have three
+ * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
+ * sixteen different categories.
  */
 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
 	fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
@@ -1017,6 +1023,109 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
  */
 #define AFBC_FORMAT_MOD_USM	(1ULL << 12)
 
+/*
+ * Arm Fixed-Rate Compression (AFRC) modifiers
+ *
+ * AFRC is a proprietary fixed rate image compression protocol and format,
+ * designed to provide guaranteed bandwidth and memory footprint
+ * reductions in graphics and media use-cases.
+ *
+ * AFRC buffers consist of one or more planes, with the same components
+ * and meaning as an uncompressed buffer using the same pixel format.
+ *
+ * Within each plane, the pixel/luma/chroma values are grouped into
+ * "coding unit" blocks which are individually compressed to a
+ * fixed size (in bytes). All coding units within a given plane of a buffer
+ * store the same number of values, and have the same compressed size.
+ *
+ * The coding unit size is configurable, allowing different rates of compression.
+ *
+ * The start of each AFRC buffer plane must be aligned to an alignment granule which
+ * depends on the coding unit size.
+ *
+ * Coding Unit Size   Plane Alignment
+ * ----------------   ---------------
+ * 16 bytes           1024 bytes
+ * 24 bytes           512  bytes
+ * 32 bytes           2048 bytes
+ *
+ * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned
+ * to a multiple of the paging tile dimensions.
+ * The dimensions of each paging tile depend on whether the buffer is optimised for
+ * scanline (SCAN layout) or rotated (ROT layout) access.
+ *
+ * Layout   Paging Tile Width   Paging Tile Height
+ * ------   -----------------   ------------------
+ * SCAN     16 coding units     4 coding units
+ * ROT      8  coding units     8 coding units
+ *
+ * The dimensions of each coding unit depend on the number of components
+ * in the compressed plane and whether the buffer is optimised for
+ * scanline (SCAN layout) or rotated (ROT layout) access.
+ *
+ * Number of Components in Plane   Layout      Coding Unit Width   Coding Unit Height
+ * -----------------------------   ---------   -----------------   ------------------
+ * 1                               SCAN        16 samples          4 samples
+ * Example: 16x4 luma samples in a 'Y' plane
+ *          16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
+ * -----------------------------   ---------   -----------------   ------------------
+ * 1                               ROT         8 samples           8 samples
+ * Example: 8x8 luma samples in a 'Y' plane
+ *          8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
+ * -----------------------------   ---------   -----------------   ------------------
+ * 2                               DONT CARE   8 samples           4 samples
+ * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
+ * -----------------------------   ---------   -----------------   ------------------
+ * 3                               DONT CARE   4 samples           4 samples
+ * Example: 4x4 pixels in an RGB buffer without alpha
+ * -----------------------------   ---------   -----------------   ------------------
+ * 4                               DONT CARE   4 samples           4 samples
+ * Example: 4x4 pixels in an RGB buffer with alpha
+ */
+
+#define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02
+
+#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \
+	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)
+
+/*
+ * AFRC coding unit size modifier.
+ *
+ * Indicates the number of bytes used to store each compressed coding unit for
+ * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance
+ * is the same for both Cb and Cr, which may be stored in separate planes.
+ *
+ * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store
+ * each compressed coding unit in the first plane of the buffer. For RGBA buffers
+ * this is the only plane, while for semi-planar and fully-planar YUV buffers,
+ * this corresponds to the luma plane.
+ *
+ * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store
+ * each compressed coding unit in the second and third planes in the buffer.
+ * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
+ *
+ * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
+ * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero.
+ * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
+ * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified.
+ */
+#define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf
+#define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
+#define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)
+#define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)
+
+#define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)
+#define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
+
+/*
+ * AFRC scanline memory layout.
+ *
+ * Indicates if the buffer uses the scanline-optimised layout
+ * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
+ * The memory layout is the same for all planes.
+ */
+#define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
+
 /*
  * Arm 16x16 Block U-Interleaved modifier
  *
diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h
index 9b6722d4..e4a2570a 100644
--- a/include/drm-uapi/drm_mode.h
+++ b/include/drm-uapi/drm_mode.h
@@ -312,16 +312,48 @@ struct drm_mode_set_plane {
 	__u32 src_w;
 };
 
+/**
+ * struct drm_mode_get_plane - Get plane metadata.
+ *
+ * Userspace can perform a GETPLANE ioctl to retrieve information about a
+ * plane.
+ *
+ * To retrieve the number of formats supported, set @count_format_types to zero
+ * and call the ioctl. @count_format_types will be updated with the value.
+ *
+ * To retrieve these formats, allocate an array with the memory needed to store
+ * @count_format_types formats. Point @format_type_ptr to this array and call
+ * the ioctl again (with @count_format_types still set to the value returned in
+ * the first ioctl call).
+ */
 struct drm_mode_get_plane {
+	/**
+	 * @plane_id: Object ID of the plane whose information should be
+	 * retrieved. Set by caller.
+	 */
 	__u32 plane_id;
 
+	/** @crtc_id: Object ID of the current CRTC. */
 	__u32 crtc_id;
+	/** @fb_id: Object ID of the current fb. */
 	__u32 fb_id;
 
+	/**
+	 * @possible_crtcs: Bitmask of CRTC's compatible with the plane. CRTC's
+	 * are created and they receive an index, which corresponds to their
+	 * position in the bitmask. Bit N corresponds to
+	 * :ref:`CRTC index<crtc_index>` N.
+	 */
 	__u32 possible_crtcs;
+	/** @gamma_size: Never used. */
 	__u32 gamma_size;
 
+	/** @count_format_types: Number of formats. */
 	__u32 count_format_types;
+	/**
+	 * @format_type_ptr: Pointer to ``__u32`` array of formats that are
+	 * supported by the plane. These formats do not require modifiers.
+	 */
 	__u64 format_type_ptr;
 };
 
@@ -509,22 +541,74 @@ struct drm_mode_get_connector {
  */
 #define DRM_MODE_PROP_ATOMIC        0x80000000
 
+/**
+ * struct drm_mode_property_enum - Description for an enum/bitfield entry.
+ * @value: numeric value for this enum entry.
+ * @name: symbolic name for this enum entry.
+ *
+ * See struct drm_property_enum for details.
+ */
 struct drm_mode_property_enum {
 	__u64 value;
 	char name[DRM_PROP_NAME_LEN];
 };
 
+/**
+ * struct drm_mode_get_property - Get property metadata.
+ *
+ * User-space can perform a GETPROPERTY ioctl to retrieve information about a
+ * property. The same property may be attached to multiple objects, see
+ * "Modeset Base Object Abstraction".
+ *
+ * The meaning of the @values_ptr field changes depending on the property type.
+ * See &drm_property.flags for more details.
+ *
+ * The @enum_blob_ptr and @count_enum_blobs fields are only meaningful when the
+ * property has the type &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK. For
+ * backwards compatibility, the kernel will always set @count_enum_blobs to
+ * zero when the property has the type &DRM_MODE_PROP_BLOB. User-space must
+ * ignore these two fields if the property has a different type.
+ *
+ * User-space is expected to retrieve values and enums by performing this ioctl
+ * at least twice: the first time to retrieve the number of elements, the
+ * second time to retrieve the elements themselves.
+ *
+ * To retrieve the number of elements, set @count_values and @count_enum_blobs
+ * to zero, then call the ioctl. @count_values will be updated with the number
+ * of elements. If the property has the type &DRM_MODE_PROP_ENUM or
+ * &DRM_MODE_PROP_BITMASK, @count_enum_blobs will be updated as well.
+ *
+ * To retrieve the elements themselves, allocate an array for @values_ptr and
+ * set @count_values to its capacity. If the property has the type
+ * &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK, allocate an array for
+ * @enum_blob_ptr and set @count_enum_blobs to its capacity. Calling the ioctl
+ * again will fill the arrays.
+ */
 struct drm_mode_get_property {
-	__u64 values_ptr; /* values and blob lengths */
-	__u64 enum_blob_ptr; /* enum and blob id ptrs */
+	/** @values_ptr: Pointer to a ``__u64`` array. */
+	__u64 values_ptr;
+	/** @enum_blob_ptr: Pointer to a struct drm_mode_property_enum array. */
+	__u64 enum_blob_ptr;
 
+	/**
+	 * @prop_id: Object ID of the property which should be retrieved. Set
+	 * by the caller.
+	 */
 	__u32 prop_id;
+	/**
+	 * @flags: ``DRM_MODE_PROP_*`` bitfield. See &drm_property.flags for
+	 * a definition of the flags.
+	 */
 	__u32 flags;
+	/**
+	 * @name: Symbolic property name. User-space should use this field to
+	 * recognize properties.
+	 */
 	char name[DRM_PROP_NAME_LEN];
 
+	/** @count_values: Number of elements in @values_ptr. */
 	__u32 count_values;
-	/* This is only used to count enum values, not blobs. The _blobs is
-	 * simply because of a historical reason, i.e. backwards compat. */
+	/** @count_enum_blobs: Number of elements in @enum_blob_ptr. */
 	__u32 count_enum_blobs;
 };
 
@@ -1026,6 +1110,9 @@ struct drm_mode_destroy_blob {
  * struct drm_mode_create_lease - Create lease
  *
  * Lease mode resources, creating another drm_master.
+ *
+ * The @object_ids array must reference at least one CRTC, one connector and
+ * one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled.
  */
 struct drm_mode_create_lease {
 	/** @object_ids: Pointer to array of object ids (__u32) */
diff --git a/include/drm-uapi/msm_drm.h b/include/drm-uapi/msm_drm.h
index f0758510..6b8fffc2 100644
--- a/include/drm-uapi/msm_drm.h
+++ b/include/drm-uapi/msm_drm.h
@@ -73,11 +73,19 @@ struct drm_msm_timespec {
 #define MSM_PARAM_MAX_FREQ   0x04
 #define MSM_PARAM_TIMESTAMP  0x05
 #define MSM_PARAM_GMEM_BASE  0x06
-#define MSM_PARAM_NR_RINGS   0x07
+#define MSM_PARAM_PRIORITIES 0x07  /* The # of priority levels */
 #define MSM_PARAM_PP_PGTABLE 0x08  /* => 1 for per-process pagetables, else 0 */
 #define MSM_PARAM_FAULTS     0x09
 #define MSM_PARAM_SUSPENDS   0x0a
 
+/* For backwards compat.  The original support for preemption was based on
+ * a single ring per priority level so # of priority levels equals the #
+ * of rings.  With drm/scheduler providing additional levels of priority,
+ * the number of priorities is greater than the # of rings.  The param is
+ * renamed to better reflect this.
+ */
+#define MSM_PARAM_NR_RINGS   MSM_PARAM_PRIORITIES
+
 struct drm_msm_param {
 	__u32 pipe;           /* in, MSM_PIPE_x */
 	__u32 param;          /* in, MSM_PARAM_x */
@@ -304,6 +312,10 @@ struct drm_msm_gem_madvise {
 
 #define MSM_SUBMITQUEUE_FLAGS (0)
 
+/*
+ * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
+ * a lower numeric value is higher priority.
+ */
 struct drm_msm_submitqueue {
 	__u32 flags;   /* in, MSM_SUBMITQUEUE_x */
 	__u32 prio;    /* in, Priority level */
diff --git a/include/drm-uapi/tegra_drm.h b/include/drm-uapi/tegra_drm.h
index 6c07919c..bb1adff0 100644
--- a/include/drm-uapi/tegra_drm.h
+++ b/include/drm-uapi/tegra_drm.h
@@ -1,24 +1,5 @@
-/*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+/* SPDX-License-Identifier: MIT */
+/* Copyright (c) 2012-2020 NVIDIA Corporation */
 
 #ifndef _TEGRA_DRM_H_
 #define _TEGRA_DRM_H_
@@ -29,6 +10,8 @@
 extern "C" {
 #endif
 
+/* Tegra DRM legacy UAPI. Only enabled with STAGING */
+
 #define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
 #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
 
@@ -649,8 +632,8 @@ struct drm_tegra_gem_get_flags {
 #define DRM_TEGRA_SYNCPT_READ		0x02
 #define DRM_TEGRA_SYNCPT_INCR		0x03
 #define DRM_TEGRA_SYNCPT_WAIT		0x04
-#define DRM_TEGRA_OPEN_CHANNEL		0x05
-#define DRM_TEGRA_CLOSE_CHANNEL		0x06
+#define DRM_TEGRA_OPEN_CHANNEL	        0x05
+#define DRM_TEGRA_CLOSE_CHANNEL	        0x06
 #define DRM_TEGRA_GET_SYNCPT		0x07
 #define DRM_TEGRA_SUBMIT		0x08
 #define DRM_TEGRA_GET_SYNCPT_BASE	0x09
@@ -674,6 +657,402 @@ struct drm_tegra_gem_get_flags {
 #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
 #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
 
+/* New Tegra DRM UAPI */
+
+/*
+ * Reported by the driver in the `capabilities` field.
+ *
+ * DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent
+ * with regard to the system memory.
+ */
+#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0)
+
+struct drm_tegra_channel_open {
+	/**
+	 * @host1x_class: [in]
+	 *
+	 * Host1x class of the engine that will be programmed using this
+	 * channel.
+	 */
+	__u32 host1x_class;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @context: [out]
+	 *
+	 * Opaque identifier corresponding to the opened channel.
+	 */
+	__u32 context;
+
+	/**
+	 * @version: [out]
+	 *
+	 * Version of the engine hardware. This can be used by userspace
+	 * to determine how the engine needs to be programmed.
+	 */
+	__u32 version;
+
+	/**
+	 * @capabilities: [out]
+	 *
+	 * Flags describing the hardware capabilities.
+	 */
+	__u32 capabilities;
+	__u32 padding;
+};
+
+struct drm_tegra_channel_close {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to close.
+	 */
+	__u32 context;
+	__u32 padding;
+};
+
+/*
+ * Mapping flags that can be used to influence how the mapping is created.
+ *
+ * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access
+ * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access
+ */
+#define DRM_TEGRA_CHANNEL_MAP_READ  (1 << 0)
+#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1)
+#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \
+					  DRM_TEGRA_CHANNEL_MAP_WRITE)
+
+struct drm_tegra_channel_map {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to which make memory available for.
+	 */
+	__u32 context;
+
+	/**
+	 * @handle: [in]
+	 *
+	 * GEM handle of the memory to map.
+	 */
+	__u32 handle;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @mapping: [out]
+	 *
+	 * Identifier corresponding to the mapping, to be used for
+	 * relocations or unmapping later.
+	 */
+	__u32 mapping;
+};
+
+struct drm_tegra_channel_unmap {
+	/**
+	 * @context: [in]
+	 *
+	 * Channel identifier of the channel to unmap memory from.
+	 */
+	__u32 context;
+
+	/**
+	 * @mapping: [in]
+	 *
+	 * Mapping identifier of the memory mapping to unmap.
+	 */
+	__u32 mapping;
+};
+
+/* Submission */
+
+/**
+ * Specify that bit 39 of the patched-in address should be set to switch
+ * swizzling between Tegra and non-Tegra sector layout on systems that store
+ * surfaces in system memory in non-Tegra sector layout.
+ */
+#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0)
+
+struct drm_tegra_submit_buf {
+	/**
+	 * @mapping: [in]
+	 *
+	 * Identifier of the mapping to use in the submission.
+	 */
+	__u32 mapping;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * Information for relocation patching.
+	 */
+	struct {
+		/**
+		 * @target_offset: [in]
+		 *
+		 * Offset from the start of the mapping of the data whose
+		 * address is to be patched into the gather.
+		 */
+		__u64 target_offset;
+
+		/**
+		 * @gather_offset_words: [in]
+		 *
+		 * Offset in words from the start of the gather data to
+		 * where the address should be patched into.
+		 */
+		__u32 gather_offset_words;
+
+		/**
+		 * @shift: [in]
+		 *
+		 * Number of bits the address should be shifted right before
+		 * patching in.
+		 */
+		__u32 shift;
+	} reloc;
+};
+
+/**
+ * Execute `words` words of Host1x opcodes specified in the `gather_data_ptr`
+ * buffer. Each GATHER_UPTR command uses successive words from the buffer.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR		0
+/**
+ * Wait for a syncpoint to reach a value before continuing with further
+ * commands.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT		1
+/**
+ * Wait for a syncpoint to reach a value before continuing with further
+ * commands. The threshold is calculated relative to the start of the job.
+ */
+#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE	2
+
+struct drm_tegra_submit_cmd_gather_uptr {
+	__u32 words;
+	__u32 reserved[3];
+};
+
+struct drm_tegra_submit_cmd_wait_syncpt {
+	__u32 id;
+	__u32 value;
+	__u32 reserved[2];
+};
+
+struct drm_tegra_submit_cmd {
+	/**
+	 * @type: [in]
+	 *
+	 * Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD*
+	 * defines.
+	 */
+	__u32 type;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	union {
+		struct drm_tegra_submit_cmd_gather_uptr gather_uptr;
+		struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt;
+		__u32 reserved[4];
+	};
+};
+
+struct drm_tegra_submit_syncpt {
+	/**
+	 * @id: [in]
+	 *
+	 * ID of the syncpoint that the job will increment.
+	 */
+	__u32 id;
+
+	/**
+	 * @flags: [in]
+	 *
+	 * Flags.
+	 */
+	__u32 flags;
+
+	/**
+	 * @increments: [in]
+	 *
+	 * Number of times the job will increment this syncpoint.
+	 */
+	__u32 increments;
+
+	/**
+	 * @value: [out]
+	 *
+	 * Value the syncpoint will have once the job has completed all
+	 * its specified syncpoint increments.
+	 *
+	 * Note that the kernel may increment the syncpoint before or after
+	 * the job. These increments are not reflected in this field.
+	 *
+	 * If the job hangs or times out, not all of the increments may
+	 * get executed.
+	 */
+	__u32 value;
+};
+
+struct drm_tegra_channel_submit {
+	/**
+	 * @context: [in]
+	 *
+	 * Identifier of the channel to submit this job to.
+	 */
+	__u32 context;
+
+	/**
+	 * @num_bufs: [in]
+	 *
+	 * Number of elements in the `bufs_ptr` array.
+	 */
+	__u32 num_bufs;
+
+	/**
+	 * @num_cmds: [in]
+	 *
+	 * Number of elements in the `cmds_ptr` array.
+	 */
+	__u32 num_cmds;
+
+	/**
+	 * @gather_data_words: [in]
+	 *
+	 * Number of 32-bit words in the `gather_data_ptr` array.
+	 */
+	__u32 gather_data_words;
+
+	/**
+	 * @bufs_ptr: [in]
+	 *
+	 * Pointer to an array of drm_tegra_submit_buf structures.
+	 */
+	__u64 bufs_ptr;
+
+	/**
+	 * @cmds_ptr: [in]
+	 *
+	 * Pointer to an array of drm_tegra_submit_cmd structures.
+	 */
+	__u64 cmds_ptr;
+
+	/**
+	 * @gather_data_ptr: [in]
+	 *
+	 * Pointer to an array of Host1x opcodes to be used by GATHER_UPTR
+	 * commands.
+	 */
+	__u64 gather_data_ptr;
+
+	/**
+	 * @syncobj_in: [in]
+	 *
+	 * Handle for DRM syncobj that will be waited before submission.
+	 * Ignored if zero.
+	 */
+	__u32 syncobj_in;
+
+	/**
+	 * @syncobj_out: [in]
+	 *
+	 * Handle for DRM syncobj that will have its fence replaced with
+	 * the job's completion fence. Ignored if zero.
+	 */
+	__u32 syncobj_out;
+
+	/**
+	 * @syncpt_incr: [in,out]
+	 *
+	 * Information about the syncpoint the job will increment.
+	 */
+	struct drm_tegra_submit_syncpt syncpt;
+};
+
+struct drm_tegra_syncpoint_allocate {
+	/**
+	 * @id: [out]
+	 *
+	 * ID of allocated syncpoint.
+	 */
+	__u32 id;
+	__u32 padding;
+};
+
+struct drm_tegra_syncpoint_free {
+	/**
+	 * @id: [in]
+	 *
+	 * ID of syncpoint to free.
+	 */
+	__u32 id;
+	__u32 padding;
+};
+
+struct drm_tegra_syncpoint_wait {
+	/**
+	 * @timeout: [in]
+	 *
+	 * Absolute timestamp at which the wait will time out.
+	 */
+	__s64 timeout_ns;
+
+	/**
+	 * @id: [in]
+	 *
+	 * ID of syncpoint to wait on.
+	 */
+	__u32 id;
+
+	/**
+	 * @threshold: [in]
+	 *
+	 * Threshold to wait for.
+	 */
+	__u32 threshold;
+
+	/**
+	 * @value: [out]
+	 *
+	 * Value of the syncpoint upon wait completion.
+	 */
+	__u32 value;
+
+	__u32 padding;
+};
+
+#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open)
+#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close)
+#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map)
+#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap)
+#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit)
+
+#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free)
+#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait)
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/include/drm-uapi/v3d_drm.h b/include/drm-uapi/v3d_drm.h
index 1ce746e2..4104f22f 100644
--- a/include/drm-uapi/v3d_drm.h
+++ b/include/drm-uapi/v3d_drm.h
@@ -38,6 +38,9 @@ extern "C" {
 #define DRM_V3D_GET_BO_OFFSET                     0x05
 #define DRM_V3D_SUBMIT_TFU                        0x06
 #define DRM_V3D_SUBMIT_CSD                        0x07
+#define DRM_V3D_PERFMON_CREATE                    0x08
+#define DRM_V3D_PERFMON_DESTROY                   0x09
+#define DRM_V3D_PERFMON_GET_VALUES                0x0a
 
 #define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
 #define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
@@ -47,6 +50,12 @@ extern "C" {
 #define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
 #define DRM_IOCTL_V3D_SUBMIT_TFU          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
 #define DRM_IOCTL_V3D_SUBMIT_CSD          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
+#define DRM_IOCTL_V3D_PERFMON_CREATE      DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \
+						   struct drm_v3d_perfmon_create)
+#define DRM_IOCTL_V3D_PERFMON_DESTROY     DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \
+						   struct drm_v3d_perfmon_destroy)
+#define DRM_IOCTL_V3D_PERFMON_GET_VALUES  DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \
+						   struct drm_v3d_perfmon_get_values)
 
 #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE             0x01
 
@@ -127,6 +136,11 @@ struct drm_v3d_submit_cl {
 	__u32 bo_handle_count;
 
 	__u32 flags;
+
+	/* ID of the perfmon to attach to this job. 0 means no perfmon. */
+	__u32 perfmon_id;
+
+	__u32 pad;
 };
 
 /**
@@ -195,6 +209,7 @@ enum drm_v3d_param {
 	DRM_V3D_PARAM_SUPPORTS_TFU,
 	DRM_V3D_PARAM_SUPPORTS_CSD,
 	DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
+	DRM_V3D_PARAM_SUPPORTS_PERFMON,
 };
 
 struct drm_v3d_get_param {
@@ -258,6 +273,127 @@ struct drm_v3d_submit_csd {
 	__u32 in_sync;
 	/* Sync object to signal when the CSD job is done. */
 	__u32 out_sync;
+
+	/* ID of the perfmon to attach to this job. 0 means no perfmon. */
+	__u32 perfmon_id;
+};
+
+enum {
+	V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
+	V3D_PERFCNT_FEP_VALID_PRIMS,
+	V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS,
+	V3D_PERFCNT_FEP_VALID_QUADS,
+	V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL,
+	V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL,
+	V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS,
+	V3D_PERFCNT_TLB_QUADS_ZERO_COV,
+	V3D_PERFCNT_TLB_QUADS_NONZERO_COV,
+	V3D_PERFCNT_TLB_QUADS_WRITTEN,
+	V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD,
+	V3D_PERFCNT_PTB_PRIM_CLIP,
+	V3D_PERFCNT_PTB_PRIM_REV,
+	V3D_PERFCNT_QPU_IDLE_CYCLES,
+	V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER,
+	V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG,
+	V3D_PERFCNT_QPU_CYCLES_VALID_INSTR,
+	V3D_PERFCNT_QPU_CYCLES_TMU_STALL,
+	V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL,
+	V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL,
+	V3D_PERFCNT_QPU_IC_HIT,
+	V3D_PERFCNT_QPU_IC_MISS,
+	V3D_PERFCNT_QPU_UC_HIT,
+	V3D_PERFCNT_QPU_UC_MISS,
+	V3D_PERFCNT_TMU_TCACHE_ACCESS,
+	V3D_PERFCNT_TMU_TCACHE_MISS,
+	V3D_PERFCNT_VPM_VDW_STALL,
+	V3D_PERFCNT_VPM_VCD_STALL,
+	V3D_PERFCNT_BIN_ACTIVE,
+	V3D_PERFCNT_RDR_ACTIVE,
+	V3D_PERFCNT_L2T_HITS,
+	V3D_PERFCNT_L2T_MISSES,
+	V3D_PERFCNT_CYCLE_COUNT,
+	V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER,
+	V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT,
+	V3D_PERFCNT_PTB_PRIMS_BINNED,
+	V3D_PERFCNT_AXI_WRITES_WATCH_0,
+	V3D_PERFCNT_AXI_READS_WATCH_0,
+	V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0,
+	V3D_PERFCNT_AXI_READ_STALLS_WATCH_0,
+	V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0,
+	V3D_PERFCNT_AXI_READ_BYTES_WATCH_0,
+	V3D_PERFCNT_AXI_WRITES_WATCH_1,
+	V3D_PERFCNT_AXI_READS_WATCH_1,
+	V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1,
+	V3D_PERFCNT_AXI_READ_STALLS_WATCH_1,
+	V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1,
+	V3D_PERFCNT_AXI_READ_BYTES_WATCH_1,
+	V3D_PERFCNT_TLB_PARTIAL_QUADS,
+	V3D_PERFCNT_TMU_CONFIG_ACCESSES,
+	V3D_PERFCNT_L2T_NO_ID_STALL,
+	V3D_PERFCNT_L2T_COM_QUE_STALL,
+	V3D_PERFCNT_L2T_TMU_WRITES,
+	V3D_PERFCNT_TMU_ACTIVE_CYCLES,
+	V3D_PERFCNT_TMU_STALLED_CYCLES,
+	V3D_PERFCNT_CLE_ACTIVE,
+	V3D_PERFCNT_L2T_TMU_READS,
+	V3D_PERFCNT_L2T_CLE_READS,
+	V3D_PERFCNT_L2T_VCD_READS,
+	V3D_PERFCNT_L2T_TMUCFG_READS,
+	V3D_PERFCNT_L2T_SLC0_READS,
+	V3D_PERFCNT_L2T_SLC1_READS,
+	V3D_PERFCNT_L2T_SLC2_READS,
+	V3D_PERFCNT_L2T_TMU_W_MISSES,
+	V3D_PERFCNT_L2T_TMU_R_MISSES,
+	V3D_PERFCNT_L2T_CLE_MISSES,
+	V3D_PERFCNT_L2T_VCD_MISSES,
+	V3D_PERFCNT_L2T_TMUCFG_MISSES,
+	V3D_PERFCNT_L2T_SLC0_MISSES,
+	V3D_PERFCNT_L2T_SLC1_MISSES,
+	V3D_PERFCNT_L2T_SLC2_MISSES,
+	V3D_PERFCNT_CORE_MEM_WRITES,
+	V3D_PERFCNT_L2T_MEM_WRITES,
+	V3D_PERFCNT_PTB_MEM_WRITES,
+	V3D_PERFCNT_TLB_MEM_WRITES,
+	V3D_PERFCNT_CORE_MEM_READS,
+	V3D_PERFCNT_L2T_MEM_READS,
+	V3D_PERFCNT_PTB_MEM_READS,
+	V3D_PERFCNT_PSE_MEM_READS,
+	V3D_PERFCNT_TLB_MEM_READS,
+	V3D_PERFCNT_GMP_MEM_READS,
+	V3D_PERFCNT_PTB_W_MEM_WORDS,
+	V3D_PERFCNT_TLB_W_MEM_WORDS,
+	V3D_PERFCNT_PSE_R_MEM_WORDS,
+	V3D_PERFCNT_TLB_R_MEM_WORDS,
+	V3D_PERFCNT_TMU_MRU_HITS,
+	V3D_PERFCNT_COMPUTE_ACTIVE,
+	V3D_PERFCNT_NUM,
+};
+
+#define DRM_V3D_MAX_PERF_COUNTERS                 32
+
+struct drm_v3d_perfmon_create {
+	__u32 id;
+	__u32 ncounters;
+	__u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
+};
+
+struct drm_v3d_perfmon_destroy {
+	__u32 id;
+};
+
+/*
+ * Returns the values of the performance counters tracked by this
+ * perfmon (as an array of ncounters u64 values).
+ *
+ * No implicit synchronization is performed, so the user has to
+ * guarantee that any jobs using this perfmon have already been
+ * completed  (probably by blocking on the seqno returned by the
+ * last exec that used the perfmon).
+ */
+struct drm_v3d_perfmon_get_values {
+	__u32 id;
+	__u32 pad;
+	__u64 values_ptr;
 };
 
 #if defined(__cplusplus)
diff --git a/include/drm-uapi/vmwgfx_drm.h b/include/drm-uapi/vmwgfx_drm.h
index 02e91750..9078775f 100644
--- a/include/drm-uapi/vmwgfx_drm.h
+++ b/include/drm-uapi/vmwgfx_drm.h
@@ -72,6 +72,9 @@ extern "C" {
 #define DRM_VMW_GB_SURFACE_CREATE_EXT   27
 #define DRM_VMW_GB_SURFACE_REF_EXT      28
 #define DRM_VMW_MSG                     29
+#define DRM_VMW_MKSSTAT_RESET           30
+#define DRM_VMW_MKSSTAT_ADD             31
+#define DRM_VMW_MKSSTAT_REMOVE          32
 
 /*************************************************************************/
 /**
@@ -1236,6 +1239,44 @@ struct drm_vmw_msg_arg {
 	__u32 receive_len;
 };
 
+/**
+ * struct drm_vmw_mksstat_add_arg
+ *
+ * @stat: Pointer to user-space stat-counters array, page-aligned.
+ * @info: Pointer to user-space counter-infos array, page-aligned.
+ * @strs: Pointer to user-space stat strings, page-aligned.
+ * @stat_len: Length in bytes of stat-counters array.
+ * @info_len: Length in bytes of counter-infos array.
+ * @strs_len: Length in bytes of the stat strings, terminators included.
+ * @description: Pointer to instance descriptor string; will be truncated
+ *               to MKS_GUEST_STAT_INSTANCE_DESC_LENGTH chars.
+ * @id: Output identifier of the produced record; -1 if error.
+ *
+ * Argument to the DRM_VMW_MKSSTAT_ADD ioctl.
+ */
+struct drm_vmw_mksstat_add_arg {
+	__u64 stat;
+	__u64 info;
+	__u64 strs;
+	__u64 stat_len;
+	__u64 info_len;
+	__u64 strs_len;
+	__u64 description;
+	__u64 id;
+};
+
+/**
+ * struct drm_vmw_mksstat_remove_arg
+ *
+ * @id: Identifier of the record being disposed, originally obtained through
+ *      DRM_VMW_MKSSTAT_ADD ioctl.
+ *
+ * Argument to the DRM_VMW_MKSSTAT_REMOVE ioctl.
+ */
+struct drm_vmw_mksstat_remove_arg {
+	__u64 id;
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.31.1

[igt-dev] [PATCH i-g-t 6/8] README.md: Detail the drm-uapi headers sync.

[Rodrigo Vivi]

Let's detail a bit more on how to properly get the headers
properly in a cleaner way. This might help to avoid small
mistakes when syncing uapi headers.

Cc: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 README.md | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/README.md b/README.md
index 6d9e40f3..d71a2fa7 100644
--- a/README.md
+++ b/README.md
@@ -149,7 +149,13 @@ overall structure or indexes you need to reflect the change in
 
 Imported DRM uapi headers from airlied's drm-next branch.
 
-These should be updated all together by executing `make headers_install` from
-that branch of the kernel and then copying the resulting
-`./usr/include/drm/*.h` in and committing with a note of which exact commit
-from airlied's branch was used to generate them.
+These should be updated all together by:
+
+    # From the kernel dir with a drm/drm-next commit checked out:
+    $ make INSTALL_HDR_PATH=<dest-dir> headers_install
+    $ rm -f <igt-dir>/include/drm-uapi/*
+    $ cp <dest-dir>/include/linux/sync_file.h <igt-dir>/include/drm-uapi/
+    $ cp <dest-dir>/include/drm/* <igt-dir>/include/drm-uapi/
+
+Then, commit with a note of which exact commit from airlied's branch
+was used to generate them.
-- 
2.31.1

[igt-dev] [PATCH i-g-t 7/8] include: Introduce linux-uapi for non-drm-uapi files.

[Rodrigo Vivi]

sync_file.h is needed for dma-buf, but it is part of the
linux-uapi include dir.

The patch aims to have a drm-uapi directory that is a pure
copy of the generated drm-uapi include dir.

Cc: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 README.md                                    | 12 +++++++++++-
 include/{drm-uapi => linux-uapi}/sync_file.h |  0
 meson.build                                  |  2 +-
 3 files changed, 12 insertions(+), 2 deletions(-)
 rename include/{drm-uapi => linux-uapi}/sync_file.h (100%)

diff --git a/README.md b/README.md
index d71a2fa7..62bef46d 100644
--- a/README.md
+++ b/README.md
@@ -154,8 +154,18 @@ These should be updated all together by:
     # From the kernel dir with a drm/drm-next commit checked out:
     $ make INSTALL_HDR_PATH=<dest-dir> headers_install
     $ rm -f <igt-dir>/include/drm-uapi/*
-    $ cp <dest-dir>/include/linux/sync_file.h <igt-dir>/include/drm-uapi/
     $ cp <dest-dir>/include/drm/* <igt-dir>/include/drm-uapi/
 
 Then, commit with a note of which exact commit from airlied's branch
 was used to generate them.
+
+### `include/linux-uapi/sync_file.h`
+
+Imported non-DRM uapi headers from airlied's drm-next branch.
+
+    # From the kernel dir with a drm/drm-next commit checked out:
+    $ make INSTALL_HDR_PATH=<destdir> headers_install
+    $ cp <destdir>/include/linux/sync_file.h ~/igt/include/linux-uapi/
+
+Then, commit with a note of which exact commit from airlied's branch
+was used to generate them.
diff --git a/include/drm-uapi/sync_file.h b/include/linux-uapi/sync_file.h
similarity index 100%
rename from include/drm-uapi/sync_file.h
rename to include/linux-uapi/sync_file.h
diff --git a/meson.build b/meson.build
index 06e76189..f9a284d8 100644
--- a/meson.build
+++ b/meson.build
@@ -86,7 +86,7 @@ with_libdrm = get_option('libdrm_drivers')
 
 build_info = ['Build type: ' + get_option('buildtype')]
 
-inc = include_directories('include/drm-uapi', 'lib', 'lib/stubs/syscalls', '.')
+inc = include_directories('include/drm-uapi', 'include/linux-uapi', 'lib', 'lib/stubs/syscalls', '.')
 
 inc_for_gtkdoc = include_directories('lib')
 
-- 
2.31.1

[igt-dev] [PATCH i-g-t 8/8] README.md: Accept the i915_drm.h standalone update.

[Rodrigo Vivi]

Looking to our git log we can see that the most common case
is the update of the single i915_drm.h file.

There are some advantages of doing this standalone update:

1. Make reviews easier without the noise of other headers.
2. Avoid the developer to have to touch other areas that are
   not immediately related to targeted work.

Cc: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 README.md | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/README.md b/README.md
index 62bef46d..66f2bc0f 100644
--- a/README.md
+++ b/README.md
@@ -159,6 +159,20 @@ These should be updated all together by:
 Then, commit with a note of which exact commit from airlied's branch
 was used to generate them.
 
+### `include/drm-uapi/i915_drm.h`
+
+Imported i915_drm.h uapi headers from airlied's drm-next branch.
+
+In some cases updating a single uapi file is needed as our history
+shows. So in this case, it should be done by:
+
+    # From the kernel dir with a drm/drm-next commit checked out:
+    $ make INSTALL_HDR_PATH=<dest-dir> headers_install
+    $ cp <dest-dir>/include/drm/i915_drm.h <igt-dir>/include/drm-uapi/
+
+Then, commit with a note of which exact commit from airlied's branch
+was used to generate it.
+
 ### `include/linux-uapi/sync_file.h`
 
 Imported non-DRM uapi headers from airlied's drm-next branch.
-- 
2.31.1

[igt-dev] ✓ Fi.CI.BAT: success for drm-uapi clean-up

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4552 bytes --]

== Series Details ==

Series: drm-uapi clean-up
URL   : https://patchwork.freedesktop.org/series/95526/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10689 -> IGTPW_6294
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/index.html

Known issues
------------

  Here are the changes found in IGTPW_6294 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-bsw-nick:        NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][2] ([fdo#109271]) +7 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/fi-kbl-soraka/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-r:           [PASS][3] -> [INCOMPLETE][4] ([i915#151] / [i915#92])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/fi-kbl-r/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/fi-kbl-r/igt@i915_pm_rpm@module-reload.html

  * igt@kms_flip@basic-flip-vs-modeset@c-dp1:
    - fi-cfl-8109u:       [PASS][5] -> [FAIL][6] ([i915#4165]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cfl-8109u:       [PASS][7] -> [FAIL][8] ([i915#2546])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html

  * igt@runner@aborted:
    - fi-kbl-r:           NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#1814] / [i915#2722] / [i915#3363])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/fi-kbl-r/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [INCOMPLETE][10] ([i915#2940]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [FAIL][12] ([i915#1372]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#3057]: https://gitlab.freedesktop.org/drm/intel/issues/3057
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3970]: https://gitlab.freedesktop.org/drm/intel/issues/3970
  [i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92


Participating hosts (44 -> 37)
------------------------------

  Missing    (7): fi-ilk-m540 bat-dg1-6 fi-tgl-u2 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 bat-jsl-1 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6233 -> IGTPW_6294

  CI-20190529: 20190529
  CI_DRM_10689: 6e9dcd4e975288c683c9299de5abb64c5e96215f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6294: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/index.html
  IGT_6233: a2e7a4583f0f68218c53cfe7b0ea8cc34b49cae9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/index.html

[-- Attachment #2: Type: text/html, Size: 5341 bytes --]

Re: [igt-dev] [PATCH i-g-t 1/8] tests/i915/gem_pxp: Add LOCAL_ UAPI defines

[Dixit, Ashutosh]

On Wed, 06 Oct 2021 09:14:37 -0700, Rodrigo Vivi wrote:
>
> While the UAPI changes don't propagate to drm-next we should
> have that as LOCAL_ ones.

Please add these in lib/i915/i915_drm_local.h as follows:

/*
 * It is necessary on occasion to add uapi declarations to IGT before they
 * appear in imported kernel uapi headers. This header is provided for this
 * purpose.

 * Early uapi declarations should be added here exactly as they are
 * expected to appear in the kernel uapi headers, i.e. without the LOCAL_
 * or local_ prefix and without any #ifndef's. Attempt should be made to
 * clean these up when kernel uapi headers are sync'd.
 */

>
> That was my mistake during review and merge since I had
> ignored the rules documented at README.md and considered
> drm-intel branches would be enough. I'm sorry.
>
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Cc: Petri Latvala <petri.latvala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Re: [igt-dev] [PATCH i-g-t 1/8] tests/i915/gem_pxp: Add LOCAL_ UAPI defines

[Rodrigo Vivi]

On Wed, Oct 06, 2021 at 10:17:41AM -0700, Dixit, Ashutosh wrote:
> On Wed, 06 Oct 2021 09:14:37 -0700, Rodrigo Vivi wrote:
> >
> > While the UAPI changes don't propagate to drm-next we should
> > have that as LOCAL_ ones.
> 
> Please add these in lib/i915/i915_drm_local.h as follows:

Could we move this file to the include directory and document it
in the README.md along with the uapi sync mention?

> 
> /*
>  * It is necessary on occasion to add uapi declarations to IGT before they
>  * appear in imported kernel uapi headers. This header is provided for this
>  * purpose.
> 
>  * Early uapi declarations should be added here exactly as they are
>  * expected to appear in the kernel uapi headers, i.e. without the LOCAL_
>  * or local_ prefix and without any #ifndef's. Attempt should be made to
>  * clean these up when kernel uapi headers are sync'd.
>  */
> 
> >
> > That was my mistake during review and merge since I had
> > ignored the rules documented at README.md and considered
> > drm-intel branches would be enough. I'm sorry.
> >
> > Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> > Cc: Petri Latvala <petri.latvala@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Re: [igt-dev] [PATCH i-g-t 1/8] tests/i915/gem_pxp: Add LOCAL_ UAPI defines

[Dixit, Ashutosh]

On Wed, 06 Oct 2021 10:25:25 -0700, Rodrigo Vivi wrote:
>
> On Wed, Oct 06, 2021 at 10:17:41AM -0700, Dixit, Ashutosh wrote:
> > On Wed, 06 Oct 2021 09:14:37 -0700, Rodrigo Vivi wrote:
> > >
> > > While the UAPI changes don't propagate to drm-next we should
> > > have that as LOCAL_ ones.
> >
> > Please add these in lib/i915/i915_drm_local.h as follows:
>
> Could we move this file to the include directory and document it
> in the README.md along with the uapi sync mention?

I think that should be fine. Petri: what do you think, since the directory
is supposed to contain "imported" kernel headers?

Anyway, let's add the LOCAL's to this file for now as it says below. Thanks.

>
> >
> > /*
> >  * It is necessary on occasion to add uapi declarations to IGT before they
> >  * appear in imported kernel uapi headers. This header is provided for this
> >  * purpose.
> >
> >  * Early uapi declarations should be added here exactly as they are
> >  * expected to appear in the kernel uapi headers, i.e. without the LOCAL_
> >  * or local_ prefix and without any #ifndef's. Attempt should be made to
> >  * clean these up when kernel uapi headers are sync'd.
> >  */
> >
> > >
> > > That was my mistake during review and merge since I had
> > > ignored the rules documented at README.md and considered
> > > drm-intel branches would be enough. I'm sorry.
> > >
> > > Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> > > Cc: Petri Latvala <petri.latvala@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Re: [igt-dev] [PATCH i-g-t 1/8] tests/i915/gem_pxp: Add LOCAL_ UAPI defines

[Rodrigo Vivi]

On Wed, Oct 06, 2021 at 01:25:28PM -0400, Rodrigo Vivi wrote:
> On Wed, Oct 06, 2021 at 10:17:41AM -0700, Dixit, Ashutosh wrote:
> > On Wed, 06 Oct 2021 09:14:37 -0700, Rodrigo Vivi wrote:
> > >
> > > While the UAPI changes don't propagate to drm-next we should
> > > have that as LOCAL_ ones.
> > 
> > Please add these in lib/i915/i915_drm_local.h as follows:
> 
> Could we move this file to the include directory and document it
> in the README.md along with the uapi sync mention?
> 
> > 
> > /*
> >  * It is necessary on occasion to add uapi declarations to IGT before they
> >  * appear in imported kernel uapi headers. This header is provided for this
> >  * purpose.
> > 
> >  * Early uapi declarations should be added here exactly as they are
> >  * expected to appear in the kernel uapi headers, i.e. without the LOCAL_
> >  * or local_ prefix and without any #ifndef's. Attempt should be made to
> >  * clean these up when kernel uapi headers are sync'd.
> >  */

I'd like to highlight that I have a concern with this approach without
the local_ prefix.

This approach would force anyone that is syncing the header to solve
everyone's else updates.

It gets even worse and uglier when the api in here diverged from the
actually merged upstream. Okay, one can say this is really rare.

I'm okay with a centralized place for the locals... I believe we even
had that in the past. But I don't like the idea of the lack of prefix.

> > 
> > >
> > > That was my mistake during review and merge since I had
> > > ignored the rules documented at README.md and considered
> > > drm-intel branches would be enough. I'm sorry.
> > >
> > > Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> > > Cc: Petri Latvala <petri.latvala@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Re: [igt-dev] [PATCH i-g-t 7/8] include: Introduce linux-uapi for non-drm-uapi files.

[Dixit, Ashutosh]

On Wed, 06 Oct 2021 09:14:43 -0700, Rodrigo Vivi wrote:
>
> sync_file.h is needed for dma-buf, but it is part of the
> linux-uapi include dir.
>
> The patch aims to have a drm-uapi directory that is a pure
> copy of the generated drm-uapi include dir.

But then we cannot add i915_drm_local.h here?

Re: [igt-dev] [PATCH i-g-t 1/8] tests/i915/gem_pxp: Add LOCAL_ UAPI defines

[Teres Alexis, Alan Previn]

Apologies for the IRQ, newbie-question: 

WRT "... Early uapi declarations should be added here exactly as they are 
expected to appear in the kernel uapi headers ", during the initial series reviews 
(pending merge + propagation), I added those definitions / structures into
I915_drm_local.h with additional comments explaining where they belong
in the main header (example: this definition is a new flag param for structure 'foo'),
which is unnecessary once u merge the kernel UAPI in where the context is apparent.

I assume such additional-context would be okay? If so, the exclusion during merge would
Be expected to be manual right? (comparing the delta matched)?

...alan

-----Original Message-----
From: Dixit, Ashutosh <ashutosh.dixit@intel.com> 
Sent: Wednesday, October 6, 2021 10:32 AM
To: Vivi, Rodrigo <rodrigo.vivi@intel.com>
Cc: igt-dev@lists.freedesktop.org; Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>; Latvala, Petri <petri.latvala@intel.com>
Subject: Re: [igt-dev] [PATCH i-g-t 1/8] tests/i915/gem_pxp: Add LOCAL_ UAPI defines

On Wed, 06 Oct 2021 10:25:25 -0700, Rodrigo Vivi wrote:
>
> On Wed, Oct 06, 2021 at 10:17:41AM -0700, Dixit, Ashutosh wrote:
> > On Wed, 06 Oct 2021 09:14:37 -0700, Rodrigo Vivi wrote:
> > >
> > > While the UAPI changes don't propagate to drm-next we should have 
> > > that as LOCAL_ ones.
> >
> > Please add these in lib/i915/i915_drm_local.h as follows:
>
> Could we move this file to the include directory and document it in 
> the README.md along with the uapi sync mention?

I think that should be fine. Petri: what do you think, since the directory is supposed to contain "imported" kernel headers?

Anyway, let's add the LOCAL's to this file for now as it says below. Thanks.

>
> >
> > /*
> >  * It is necessary on occasion to add uapi declarations to IGT 
> > before they
> >  * appear in imported kernel uapi headers. This header is provided 
> > for this
> >  * purpose.
> >
> >  * Early uapi declarations should be added here exactly as they are
> >  * expected to appear in the kernel uapi headers, i.e. without the 
> > LOCAL_
> >  * or local_ prefix and without any #ifndef's. Attempt should be 
> > made to
> >  * clean these up when kernel uapi headers are sync'd.
> >  */
> >
> > >
> > > That was my mistake during review and merge since I had ignored 
> > > the rules documented at README.md and considered drm-intel 
> > > branches would be enough. I'm sorry.
> > >
> > > Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> > > Cc: Petri Latvala <petri.latvala@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Re: [igt-dev] [PATCH i-g-t 7/8] include: Introduce linux-uapi for non-drm-uapi files.

[Vivi, Rodrigo]

On Wed, 2021-10-06 at 10:39 -0700, Dixit, Ashutosh wrote:
> On Wed, 06 Oct 2021 09:14:43 -0700, Rodrigo Vivi wrote:
> > 
> > sync_file.h is needed for dma-buf, but it is part of the
> > linux-uapi include dir.
> > 
> > The patch aims to have a drm-uapi directory that is a pure
> > copy of the generated drm-uapi include dir.
> 
> But then we cannot add i915_drm_local.h here?

I was thinking about another directory like
include/local-uapi/i915_drm_local.h

Re: [igt-dev] [PATCH i-g-t 1/8] tests/i915/gem_pxp: Add LOCAL_ UAPI defines

[Dixit, Ashutosh]

On Wed, 06 Oct 2021 10:37:13 -0700, Rodrigo Vivi wrote:
>
> On Wed, Oct 06, 2021 at 01:25:28PM -0400, Rodrigo Vivi wrote:
> > On Wed, Oct 06, 2021 at 10:17:41AM -0700, Dixit, Ashutosh wrote:
> > > On Wed, 06 Oct 2021 09:14:37 -0700, Rodrigo Vivi wrote:
> > > >
> > > > While the UAPI changes don't propagate to drm-next we should
> > > > have that as LOCAL_ ones.
> > >
> > > Please add these in lib/i915/i915_drm_local.h as follows:
> >
> > Could we move this file to the include directory and document it
> > in the README.md along with the uapi sync mention?
> >
> > >
> > > /*
> > >  * It is necessary on occasion to add uapi declarations to IGT before they
> > >  * appear in imported kernel uapi headers. This header is provided for this
> > >  * purpose.
> > >
> > >  * Early uapi declarations should be added here exactly as they are
> > >  * expected to appear in the kernel uapi headers, i.e. without the LOCAL_
> > >  * or local_ prefix and without any #ifndef's. Attempt should be made to
> > >  * clean these up when kernel uapi headers are sync'd.
> > >  */
>
> I'd like to highlight that I have a concern with this approach without
> the local_ prefix.

See the commit message for bb1c96b29234 where i915_drm_local.h was
introduced for the rationale for this approach.

> This approach would force anyone that is syncing the header to solve
> everyone's else updates.

As long as there are no conflicts (say between i915_drm.h and
i915_drm_local.h) there is no problem since the compiler silently ignores
identical duplicate declarations. If there is a conflict and it is not
clear what to do then the developers will need to communicate and resolve
the conflict. We haven't seen this yet so let's see if this causes problems
and then revisit I think.

> It gets even worse and uglier when the api in here diverged from the
> actually merged upstream. Okay, one can say this is really rare.
>
> I'm okay with a centralized place for the locals... I believe we even
> had that in the past. But I don't like the idea of the lack of prefix.

The thinking was that the lack of local_ or LOCAL_ prefix actually makes it
easier to catch conflicts between what got merged into the kernel and what
was originally added to IGT since the compiler will warn us about it. So
it helps to convert a possible run time failure into a compile time
failure. Anyway I was tired of seeing so many stale LOCAL declarations
lying around so we are trying this out and asking people to use it whenever
we spot this in their patches :)

Re: [igt-dev] [PATCH i-g-t 7/8] include: Introduce linux-uapi for non-drm-uapi files.

[Dixit, Ashutosh]

On Wed, 06 Oct 2021 10:56:24 -0700, Vivi, Rodrigo wrote:
>
> On Wed, 2021-10-06 at 10:39 -0700, Dixit, Ashutosh wrote:
> > On Wed, 06 Oct 2021 09:14:43 -0700, Rodrigo Vivi wrote:
> > >
> > > sync_file.h is needed for dma-buf, but it is part of the
> > > linux-uapi include dir.
> > >
> > > The patch aims to have a drm-uapi directory that is a pure
> > > copy of the generated drm-uapi include dir.
> >
> > But then we cannot add i915_drm_local.h here?
>
> I was thinking about another directory like
> include/local-uapi/i915_drm_local.h

OK, I will post a patch for this and then see what Petri says. Thanks.

Re: [igt-dev] [PATCH i-g-t 1/8] tests/i915/gem_pxp: Add LOCAL_ UAPI defines

[Vivi, Rodrigo]

On Wed, 2021-10-06 at 11:09 -0700, Dixit, Ashutosh wrote:
> On Wed, 06 Oct 2021 10:37:13 -0700, Rodrigo Vivi wrote:
> > 
> > On Wed, Oct 06, 2021 at 01:25:28PM -0400, Rodrigo Vivi wrote:
> > > On Wed, Oct 06, 2021 at 10:17:41AM -0700, Dixit, Ashutosh wrote:
> > > > On Wed, 06 Oct 2021 09:14:37 -0700, Rodrigo Vivi wrote:
> > > > > 
> > > > > While the UAPI changes don't propagate to drm-next we should
> > > > > have that as LOCAL_ ones.
> > > > 
> > > > Please add these in lib/i915/i915_drm_local.h as follows:
> > > 
> > > Could we move this file to the include directory and document it
> > > in the README.md along with the uapi sync mention?
> > > 
> > > > 
> > > > /*
> > > >  * It is necessary on occasion to add uapi declarations to IGT
> > > > before they
> > > >  * appear in imported kernel uapi headers. This header is
> > > > provided for this
> > > >  * purpose.
> > > > 
> > > >  * Early uapi declarations should be added here exactly as they
> > > > are
> > > >  * expected to appear in the kernel uapi headers, i.e. without
> > > > the LOCAL_
> > > >  * or local_ prefix and without any #ifndef's. Attempt should be
> > > > made to
> > > >  * clean these up when kernel uapi headers are sync'd.
> > > >  */
> > 
> > I'd like to highlight that I have a concern with this approach
> > without
> > the local_ prefix.
> 
> See the commit message for bb1c96b29234 where i915_drm_local.h was
> introduced for the rationale for this approach.
> 
> > This approach would force anyone that is syncing the header to solve
> > everyone's else updates.
> 
> As long as there are no conflicts (say between i915_drm.h and
> i915_drm_local.h) there is no problem since the compiler silently
> ignores
> identical duplicate declarations.

I had identical declarations of a struct and it caused conflict for me.
This is why I had to squash the changes of patches 1 to the revert on
the other patch to revert the i915_drm.h:

https://patchwork.freedesktop.org/patch/457774/

That's why I came to vent :)
But anyway, I got the point and I believe it is a good thing overall.

Could you please help with the review of the patch in this link above?


>  If there is a conflict and it is not
> clear what to do then the developers will need to communicate and
> resolve
> the conflict. We haven't seen this yet so let's see if this causes
> problems
> and then revisit I think.
> 
> > It gets even worse and uglier when the api in here diverged from the
> > actually merged upstream. Okay, one can say this is really rare.
> > 
> > I'm okay with a centralized place for the locals... I believe we even
> > had that in the past. But I don't like the idea of the lack of
> > prefix.
> 
> The thinking was that the lack of local_ or LOCAL_ prefix actually
> makes it
> easier to catch conflicts between what got merged into the kernel and
> what
> was originally added to IGT since the compiler will warn us about it.
> So
> it helps to convert a possible run time failure into a compile time
> failure. Anyway I was tired of seeing so many stale LOCAL declarations
> lying around so we are trying this out and asking people to use it
> whenever
> we spot this in their patches :)

[igt-dev] ✗ Fi.CI.IGT: failure for drm-uapi clean-up

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30233 bytes --]

== Series Details ==

Series: drm-uapi clean-up
URL   : https://patchwork.freedesktop.org/series/95526/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10689_full -> IGTPW_6294_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_6294_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_6294_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6294_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-iclb:         NOTRUN -> [SKIP][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb5/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
    - shard-tglb:         NOTRUN -> [SKIP][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb8/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-iclb4/igt@i915_pm_dc@dc9-dpms.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb2/igt@i915_pm_dc@dc9-dpms.html

  
Known issues
------------

  Here are the changes found in IGTPW_6294_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         NOTRUN -> [SKIP][5] ([i915#658]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb5/igt@feature_discovery@psr2.html

  * igt@gem_ctx_persistence@legacy-engines-mixed:
    - shard-snb:          NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +5 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-snb2/igt@gem_ctx_persistence@legacy-engines-mixed.html

  * igt@gem_ctx_shared@q-in-order:
    - shard-snb:          NOTRUN -> [SKIP][7] ([fdo#109271]) +458 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-snb7/igt@gem_ctx_shared@q-in-order.html

  * igt@gem_eio@in-flight-suspend:
    - shard-apl:          [PASS][8] -> [DMESG-WARN][9] ([i915#180]) +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-apl6/igt@gem_eio@in-flight-suspend.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl8/igt@gem_eio@in-flight-suspend.html

  * igt@gem_eio@unwedge-stress:
    - shard-snb:          NOTRUN -> [FAIL][10] ([i915#3354])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-snb2/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][11] -> [FAIL][12] ([i915#2846])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-glk9/igt@gem_exec_fair@basic-deadline.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk8/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][15] ([i915#2842])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][16] ([i915#2842])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk7/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-tglb:         [PASS][17] -> [FAIL][18] ([i915#2842]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-tglb5/igt@gem_exec_fair@basic-pace@bcs0.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb3/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [PASS][19] -> [SKIP][20] ([fdo#109271])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
    - shard-glk:          [PASS][21] -> [FAIL][22] ([i915#2842]) +3 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-glk3/igt@gem_exec_fair@basic-pace@vecs0.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk1/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [PASS][23] -> [FAIL][24] ([i915#2849])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_params@no-blt:
    - shard-tglb:         NOTRUN -> [SKIP][25] ([fdo#109283])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb7/igt@gem_exec_params@no-blt.html

  * igt@gem_exec_whisper@basic-fds:
    - shard-glk:          [PASS][26] -> [DMESG-WARN][27] ([i915#118]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-glk8/igt@gem_exec_whisper@basic-fds.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk3/igt@gem_exec_whisper@basic-fds.html

  * igt@gem_pread@exhaustion:
    - shard-snb:          NOTRUN -> [WARN][28] ([i915#2658])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-snb6/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@create-regular-context-1:
    - shard-tglb:         NOTRUN -> [SKIP][29] ([i915#4270])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb5/igt@gem_pxp@create-regular-context-1.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-kbl:          NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3323])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl7/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@input-checking:
    - shard-snb:          NOTRUN -> [DMESG-WARN][31] ([i915#3002])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-snb6/igt@gem_userptr_blits@input-checking.html

  * igt@gem_userptr_blits@unsync-unmap-after-close:
    - shard-tglb:         NOTRUN -> [SKIP][32] ([i915#3297])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb3/igt@gem_userptr_blits@unsync-unmap-after-close.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-snb:          NOTRUN -> [FAIL][33] ([i915#2724])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-snb5/igt@gem_userptr_blits@vma-merge.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-kbl:          [PASS][34] -> [DMESG-WARN][35] ([i915#180])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen7_exec_parse@chained-batch:
    - shard-iclb:         NOTRUN -> [SKIP][36] ([fdo#109289])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb6/igt@gen7_exec_parse@chained-batch.html
    - shard-tglb:         NOTRUN -> [SKIP][37] ([fdo#109289])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb2/igt@gen7_exec_parse@chained-batch.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [PASS][38] -> [DMESG-WARN][39] ([i915#1436] / [i915#716])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-glk2/igt@gen9_exec_parse@allowed-all.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk3/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([i915#2856]) +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb6/igt@gen9_exec_parse@bb-start-param.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglb:         NOTRUN -> [SKIP][41] ([fdo#109288])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb5/igt@i915_pm_sseu@full-enable.html

  * igt@i915_suspend@debugfs-reader:
    - shard-tglb:         NOTRUN -> [INCOMPLETE][42] ([i915#456])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb7/igt@i915_suspend@debugfs-reader.html

  * igt@kms_big_fb@linear-64bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][43] ([fdo#110725] / [fdo#111614])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb4/igt@kms_big_fb@linear-64bpp-rotate-270.html
    - shard-tglb:         NOTRUN -> [SKIP][44] ([fdo#111614])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb2/igt@kms_big_fb@linear-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-apl:          NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3777]) +3 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-glk:          NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3777]) +1 similar issue
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
    - shard-kbl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3777])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-iclb:         NOTRUN -> [SKIP][48] ([fdo#110723])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
    - shard-tglb:         NOTRUN -> [SKIP][49] ([fdo#111615]) +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#3689]) +8 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb2/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#3886]) +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk5/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
    - shard-tglb:         NOTRUN -> [SKIP][52] ([i915#3689] / [i915#3886])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb2/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#3886]) +3 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
    - shard-iclb:         NOTRUN -> [SKIP][54] ([fdo#109278] / [i915#3886])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#3886]) +5 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl8/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - shard-glk:          NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +5 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk6/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-mode-timings:
    - shard-snb:          NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +18 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-snb5/igt@kms_chamelium@hdmi-mode-timings.html

  * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
    - shard-kbl:          NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +7 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl2/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
    - shard-iclb:         NOTRUN -> [SKIP][59] ([fdo#109284] / [fdo#111827]) +3 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb2/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-b-ctm-0-75:
    - shard-tglb:         NOTRUN -> [SKIP][60] ([fdo#109284] / [fdo#111827]) +7 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb6/igt@kms_color_chamelium@pipe-b-ctm-0-75.html

  * igt@kms_color_chamelium@pipe-c-ctm-0-25:
    - shard-apl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [fdo#111827]) +20 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl2/igt@kms_color_chamelium@pipe-c-ctm-0-25.html

  * igt@kms_color_chamelium@pipe-d-gamma:
    - shard-iclb:         NOTRUN -> [SKIP][62] ([fdo#109278] / [fdo#109284] / [fdo#111827])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb6/igt@kms_color_chamelium@pipe-d-gamma.html

  * igt@kms_content_protection@legacy:
    - shard-apl:          NOTRUN -> [TIMEOUT][63] ([i915#1319])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl6/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding:
    - shard-kbl:          NOTRUN -> [SKIP][64] ([fdo#109271]) +111 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen:
    - shard-iclb:         NOTRUN -> [SKIP][65] ([fdo#109278] / [fdo#109279])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][66] ([i915#3319]) +3 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb8/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][67] ([i915#3359]) +6 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb2/igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][68] ([fdo#109279] / [i915#3359]) +3 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb2/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html

  * igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding:
    - shard-iclb:         NOTRUN -> [SKIP][69] ([fdo#109278]) +9 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb1/igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding.html

  * igt@kms_cursor_crc@pipe-d-cursor-suspend:
    - shard-tglb:         [PASS][70] -> [INCOMPLETE][71] ([i915#2411] / [i915#4211])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-iclb:         NOTRUN -> [SKIP][72] ([fdo#109274] / [fdo#109278])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb4/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
    - shard-tglb:         NOTRUN -> [SKIP][73] ([fdo#111825]) +17 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb1/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@pipe-d-single-bo:
    - shard-kbl:          NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#533])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl1/igt@kms_cursor_legacy@pipe-d-single-bo.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-apl:          NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#533]) +2 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl1/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_dsc@basic-dsc-enable:
    - shard-iclb:         NOTRUN -> [SKIP][76] ([i915#3840])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb2/igt@kms_dsc@basic-dsc-enable.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-iclb:         NOTRUN -> [SKIP][77] ([fdo#109274])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb6/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
    - shard-apl:          NOTRUN -> [DMESG-WARN][78] ([i915#180])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
    - shard-iclb:         [PASS][79] -> [SKIP][80] ([i915#3701])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-iclb:         NOTRUN -> [SKIP][81] ([fdo#109280]) +3 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][82] ([i915#180])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-apl:          NOTRUN -> [FAIL][83] ([fdo#108145] / [i915#265]) +1 similar issue
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][84] ([i915#265]) +1 similar issue
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb:
    - shard-glk:          NOTRUN -> [SKIP][85] ([fdo#109271]) +49 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk6/igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
    - shard-kbl:          NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#658])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
    - shard-tglb:         NOTRUN -> [SKIP][87] ([i915#2920]) +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
    - shard-apl:          NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#658]) +4 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl1/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
    - shard-glk:          NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#658])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk5/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [PASS][90] -> [SKIP][91] ([fdo#109441])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb6/igt@kms_psr@psr2_primary_mmap_gtt.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-tglb:         NOTRUN -> [FAIL][92] ([i915#132] / [i915#3467]) +2 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb1/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         NOTRUN -> [SKIP][93] ([fdo#109441]) +1 similar issue
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_setmode@basic:
    - shard-snb:          NOTRUN -> [FAIL][94] ([i915#31])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-snb6/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          [PASS][95] -> [DMESG-WARN][96] ([i915#180] / [i915#295])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame:
    - shard-iclb:         NOTRUN -> [SKIP][97] ([i915#2530])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb3/igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame.html

  * igt@nouveau_crc@pipe-d-ctx-flip-detection:
    - shard-tglb:         NOTRUN -> [SKIP][98] ([i915#2530]) +4 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb8/igt@nouveau_crc@pipe-d-ctx-flip-detection.html

  * igt@nouveau_crc@pipe-d-source-outp-complete:
    - shard-iclb:         NOTRUN -> [SKIP][99] ([fdo#109278] / [i915#2530])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb3/igt@nouveau_crc@pipe-d-source-outp-complete.html

  * igt@prime_nv_api@i915_nv_import_twice:
    - shard-iclb:         NOTRUN -> [SKIP][100] ([fdo#109291]) +2 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb1/igt@prime_nv_api@i915_nv_import_twice.html

  * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
    - shard-apl:          NOTRUN -> [SKIP][101] ([fdo#109271]) +193 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl3/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html

  * igt@prime_nv_pcopy@test3_1:
    - shard-tglb:         NOTRUN -> [SKIP][102] ([fdo#109291]) +4 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb8/igt@prime_nv_pcopy@test3_1.html

  * igt@sysfs_clients@pidname:
    - shard-apl:          NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#2994])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl2/igt@sysfs_clients@pidname.html

  * igt@sysfs_clients@sema-10:
    - shard-tglb:         NOTRUN -> [SKIP][104] ([i915#2994])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb5/igt@sysfs_clients@sema-10.html
    - shard-kbl:          NOTRUN -> [SKIP][105] ([fdo#109271] / [i915#2994]) +1 similar issue
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl6/igt@sysfs_clients@sema-10.html
    - shard-glk:          NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2994]) +1 similar issue
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk3/igt@sysfs_clients@sema-10.html
    - shard-iclb:         NOTRUN -> [SKIP][107] ([i915#2994])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb1/igt@sysfs_clients@sema-10.html

  
#### Possible fixes ####

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [TIMEOUT][108] ([i915#2369] / [i915#3063] / [i915#3648]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-tglb6/igt@gem_eio@unwedge-stress.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb1/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [FAIL][110] ([i915#2842]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-tglb:         [FAIL][112] ([i915#2842]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-tglb5/igt@gem_exec_fair@basic-pace@rcs0.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb3/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_whisper@basic-contexts-forked-all:
    - shard-glk:          [DMESG-WARN][114] ([i915#118] / [i915#95]) -> [PASS][115] +1 similar issue
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-glk6/igt@gem_exec_whisper@basic-contexts-forked-all.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk2/igt@gem_exec_whisper@basic-contexts-forked-all.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-90:
    - shard-glk:          [FAIL][116] ([i915#1888]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-glk8/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-glk2/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
    - shard-apl:          [SKIP][118] ([fdo#109271]) -> [PASS][119] +8 similar issues
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-apl8/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - shard-apl:          [DMESG-WARN][120] ([i915#203] / [i915#62]) -> [PASS][121] +3 similar issues
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-apl8/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl6/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html

  * igt@kms_flip@flip-vs-suspend@a-edp1:
    - shard-tglb:         [INCOMPLETE][122] ([i915#2411] / [i915#456]) -> [PASS][123] +1 similar issue
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-tglb7/igt@kms_flip@flip-vs-suspend@a-edp1.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-tglb8/igt@kms_flip@flip-vs-suspend@a-edp1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [DMESG-WARN][124] ([i915#180]) -> [PASS][125] +7 similar issues
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
    - shard-iclb:         [SKIP][126] ([i915#3701]) -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html

  * igt@kms_invalid_mode@bad-vtotal:
    - shard-apl:          [DMESG-WARN][128] ([i915#180] / [i915#203] / [i915#62]) -> [PASS][129] +3 similar issues
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-apl8/igt@kms_invalid_mode@bad-vtotal.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl6/igt@kms_invalid_mode@bad-vtotal.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][130] ([fdo#109441]) -> [PASS][131] +1 similar issue
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][132] ([i915#1804] / [i915#2684]) -> [WARN][133] ([i915#2684]) +1 similar issue
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-apl:          [SKIP][134] ([fdo#109271]) -> [SKIP][135] ([fdo#109271] / [i915#3886])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-apl8/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/shard-apl3/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_content_protection@uevent:
    - shard-apl:          [SKIP][136] ([fdo#109271]) -> [FAIL][137] ([i915#2105])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10689/shard-apl8/igt@kms_content_protection@uevent.html

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6294/index.html

[-- Attachment #2: Type: text/html, Size: 33729 bytes --]

Re: [igt-dev] [PATCH i-g-t 1/8] tests/i915/gem_pxp: Add LOCAL_ UAPI defines

[Dixit, Ashutosh]

On Wed, 06 Oct 2021 12:40:01 -0700, Vivi, Rodrigo wrote:
>
> On Wed, 2021-10-06 at 11:09 -0700, Dixit, Ashutosh wrote:
> > On Wed, 06 Oct 2021 10:37:13 -0700, Rodrigo Vivi wrote:
> > >
> > > On Wed, Oct 06, 2021 at 01:25:28PM -0400, Rodrigo Vivi wrote:
> > > > On Wed, Oct 06, 2021 at 10:17:41AM -0700, Dixit, Ashutosh wrote:
> > > > > On Wed, 06 Oct 2021 09:14:37 -0700, Rodrigo Vivi wrote:
> > > > > >
> > > > > > While the UAPI changes don't propagate to drm-next we should
> > > > > > have that as LOCAL_ ones.
> > > > >
> > > > > Please add these in lib/i915/i915_drm_local.h as follows:
> > > >
> > > > Could we move this file to the include directory and document it
> > > > in the README.md along with the uapi sync mention?
> > > >
> > > > >
> > > > > /*  * It is necessary on occasion to add uapi declarations to IGT
> > > > > before they  * appear in imported kernel uapi headers. This
> > > > > header is provided for this  * purpose.
> > > > >
> > > > >  * Early uapi declarations should be added here exactly as they
> > > > > are  * expected to appear in the kernel uapi headers,
> > > > > i.e. without the LOCAL_  * or local_ prefix and without any
> > > > > #ifndef's. Attempt should be made to  * clean these up when
> > > > > kernel uapi headers are sync'd.   */
> > >
> > > I'd like to highlight that I have a concern with this approach
> > > without the local_ prefix.
> >
> > See the commit message for bb1c96b29234 where i915_drm_local.h was
> > introduced for the rationale for this approach.
> >
> > > This approach would force anyone that is syncing the header to solve
> > > everyone's else updates.
> >
> > As long as there are no conflicts (say between i915_drm.h and
> > i915_drm_local.h) there is no problem since the compiler silently
> > ignores identical duplicate declarations.
>
> I had identical declarations of a struct and it caused conflict for me.

You are right, compiler will complain about identical duplicate structs,
just not about identical duplicate #define's :(

Probably not a bad idea since it will force stuff to be deleted from
i915_drm_local.h :)

> This is why I had to squash the changes of patches 1 to the revert on
> the other patch to revert the i915_drm.h:
>
> https://patchwork.freedesktop.org/patch/457774/
>
> That's why I came to vent :)
>
> But anyway, I got the point and I believe it is a good thing overall.
>
> Could you please help with the review of the patch in this link above?
>
> >  If there is a conflict and it is not clear what to do then the
> > developers will need to communicate and resolve the conflict. We
> > haven't seen this yet so let's see if this causes problems and then
> > revisit I think.
> >
> > > It gets even worse and uglier when the api in here diverged from the
> > > actually merged upstream. Okay, one can say this is really rare.
> > >
> > > I'm okay with a centralized place for the locals... I believe we even
> > > had that in the past. But I don't like the idea of the lack of
> > > prefix.
> >
> > The thinking was that the lack of local_ or LOCAL_ prefix actually
> > makes it easier to catch conflicts between what got merged into the
> > kernel and what was originally added to IGT since the compiler will
> > warn us about it.  So it helps to convert a possible run time failure
> > into a compile time failure. Anyway I was tired of seeing so many stale
> > LOCAL declarations lying around so we are trying this out and asking
> > people to use it whenever we spot this in their patches :)
>

Re: [igt-dev] [PATCH i-g-t 1/8] tests/i915/gem_pxp: Add LOCAL_ UAPI defines

[Petri Latvala]

On Wed, Oct 06, 2021 at 10:32:04AM -0700, Dixit, Ashutosh wrote:
> On Wed, 06 Oct 2021 10:25:25 -0700, Rodrigo Vivi wrote:
> >
> > On Wed, Oct 06, 2021 at 10:17:41AM -0700, Dixit, Ashutosh wrote:
> > > On Wed, 06 Oct 2021 09:14:37 -0700, Rodrigo Vivi wrote:
> > > >
> > > > While the UAPI changes don't propagate to drm-next we should
> > > > have that as LOCAL_ ones.
> > >
> > > Please add these in lib/i915/i915_drm_local.h as follows:
> >
> > Could we move this file to the include directory and document it
> > in the README.md along with the uapi sync mention?
> 
> I think that should be fine. Petri: what do you think, since the directory
> is supposed to contain "imported" kernel headers?

Yeah that is fine. The directory is already not a full copy of _all_
drm-uapi headers.

-- 
Petri Latvala


> 
> Anyway, let's add the LOCAL's to this file for now as it says below. Thanks.
> 
> >
> > >
> > > /*
> > >  * It is necessary on occasion to add uapi declarations to IGT before they
> > >  * appear in imported kernel uapi headers. This header is provided for this
> > >  * purpose.
> > >
> > >  * Early uapi declarations should be added here exactly as they are
> > >  * expected to appear in the kernel uapi headers, i.e. without the LOCAL_
> > >  * or local_ prefix and without any #ifndef's. Attempt should be made to
> > >  * clean these up when kernel uapi headers are sync'd.
> > >  */
> > >
> > > >
> > > > That was my mistake during review and merge since I had
> > > > ignored the rules documented at README.md and considered
> > > > drm-intel branches would be enough. I'm sorry.
> > > >
> > > > Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> > > > Cc: Petri Latvala <petri.latvala@intel.com>
> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Re: [igt-dev] [PATCH i-g-t 7/8] include: Introduce linux-uapi for non-drm-uapi files.

[Petri Latvala]

On Wed, Oct 06, 2021 at 11:25:54AM -0700, Dixit, Ashutosh wrote:
> On Wed, 06 Oct 2021 10:56:24 -0700, Vivi, Rodrigo wrote:
> >
> > On Wed, 2021-10-06 at 10:39 -0700, Dixit, Ashutosh wrote:
> > > On Wed, 06 Oct 2021 09:14:43 -0700, Rodrigo Vivi wrote:
> > > >
> > > > sync_file.h is needed for dma-buf, but it is part of the
> > > > linux-uapi include dir.
> > > >
> > > > The patch aims to have a drm-uapi directory that is a pure
> > > > copy of the generated drm-uapi include dir.
> > >
> > > But then we cannot add i915_drm_local.h here?
> >
> > I was thinking about another directory like
> > include/local-uapi/i915_drm_local.h
> 
> OK, I will post a patch for this and then see what Petri says. Thanks.

Ah, I already replied to that earlier email. This looks even cleaner.


-- 
Petri Latvala

Re: [igt-dev] [PATCH i-g-t 6/8] README.md: Detail the drm-uapi headers sync.

[Petri Latvala]

On Wed, Oct 06, 2021 at 12:14:42PM -0400, Rodrigo Vivi wrote:
> Let's detail a bit more on how to properly get the headers
> properly in a cleaner way. This might help to avoid small
> mistakes when syncing uapi headers.
> 
> Cc: Petri Latvala <petri.latvala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


Reviewed-by: Petri Latvala <petri.latvala@intel.com>


> ---
>  README.md | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/README.md b/README.md
> index 6d9e40f3..d71a2fa7 100644
> --- a/README.md
> +++ b/README.md
> @@ -149,7 +149,13 @@ overall structure or indexes you need to reflect the change in
>  
>  Imported DRM uapi headers from airlied's drm-next branch.
>  
> -These should be updated all together by executing `make headers_install` from
> -that branch of the kernel and then copying the resulting
> -`./usr/include/drm/*.h` in and committing with a note of which exact commit
> -from airlied's branch was used to generate them.
> +These should be updated all together by:
> +
> +    # From the kernel dir with a drm/drm-next commit checked out:
> +    $ make INSTALL_HDR_PATH=<dest-dir> headers_install
> +    $ rm -f <igt-dir>/include/drm-uapi/*
> +    $ cp <dest-dir>/include/linux/sync_file.h <igt-dir>/include/drm-uapi/
> +    $ cp <dest-dir>/include/drm/* <igt-dir>/include/drm-uapi/
> +
> +Then, commit with a note of which exact commit from airlied's branch
> +was used to generate them.
> -- 
> 2.31.1
> 

Re: [igt-dev] [PATCH i-g-t 8/8] README.md: Accept the i915_drm.h standalone update.

[Petri Latvala]

On Wed, Oct 06, 2021 at 12:14:44PM -0400, Rodrigo Vivi wrote:
> Looking to our git log we can see that the most common case
> is the update of the single i915_drm.h file.
> 
> There are some advantages of doing this standalone update:
> 
> 1. Make reviews easier without the noise of other headers.
> 2. Avoid the developer to have to touch other areas that are
>    not immediately related to targeted work.
> 
> Cc: Petri Latvala <petri.latvala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Petri Latvala <petri.latvala@intel.com>


> ---
>  README.md | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/README.md b/README.md
> index 62bef46d..66f2bc0f 100644
> --- a/README.md
> +++ b/README.md
> @@ -159,6 +159,20 @@ These should be updated all together by:
>  Then, commit with a note of which exact commit from airlied's branch
>  was used to generate them.
>  
> +### `include/drm-uapi/i915_drm.h`
> +
> +Imported i915_drm.h uapi headers from airlied's drm-next branch.
> +
> +In some cases updating a single uapi file is needed as our history
> +shows. So in this case, it should be done by:
> +
> +    # From the kernel dir with a drm/drm-next commit checked out:
> +    $ make INSTALL_HDR_PATH=<dest-dir> headers_install
> +    $ cp <dest-dir>/include/drm/i915_drm.h <igt-dir>/include/drm-uapi/
> +
> +Then, commit with a note of which exact commit from airlied's branch
> +was used to generate it.
> +
>  ### `include/linux-uapi/sync_file.h`
>  
>  Imported non-DRM uapi headers from airlied's drm-next branch.
> -- 
> 2.31.1
> 

Re: [igt-dev] [PATCH i-g-t 7/8] include: Introduce linux-uapi for non-drm-uapi files.

[Petri Latvala]

On Wed, Oct 06, 2021 at 12:14:43PM -0400, Rodrigo Vivi wrote:
> sync_file.h is needed for dma-buf, but it is part of the
> linux-uapi include dir.
> 
> The patch aims to have a drm-uapi directory that is a pure
> copy of the generated drm-uapi include dir.
> 
> Cc: Petri Latvala <petri.latvala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Petri Latvala <petri.latvala@intel.com>

> ---
>  README.md                                    | 12 +++++++++++-
>  include/{drm-uapi => linux-uapi}/sync_file.h |  0
>  meson.build                                  |  2 +-
>  3 files changed, 12 insertions(+), 2 deletions(-)
>  rename include/{drm-uapi => linux-uapi}/sync_file.h (100%)
> 
> diff --git a/README.md b/README.md
> index d71a2fa7..62bef46d 100644
> --- a/README.md
> +++ b/README.md
> @@ -154,8 +154,18 @@ These should be updated all together by:
>      # From the kernel dir with a drm/drm-next commit checked out:
>      $ make INSTALL_HDR_PATH=<dest-dir> headers_install
>      $ rm -f <igt-dir>/include/drm-uapi/*
> -    $ cp <dest-dir>/include/linux/sync_file.h <igt-dir>/include/drm-uapi/
>      $ cp <dest-dir>/include/drm/* <igt-dir>/include/drm-uapi/
>  
>  Then, commit with a note of which exact commit from airlied's branch
>  was used to generate them.
> +
> +### `include/linux-uapi/sync_file.h`
> +
> +Imported non-DRM uapi headers from airlied's drm-next branch.
> +
> +    # From the kernel dir with a drm/drm-next commit checked out:
> +    $ make INSTALL_HDR_PATH=<destdir> headers_install
> +    $ cp <destdir>/include/linux/sync_file.h ~/igt/include/linux-uapi/
> +
> +Then, commit with a note of which exact commit from airlied's branch
> +was used to generate them.
> diff --git a/include/drm-uapi/sync_file.h b/include/linux-uapi/sync_file.h
> similarity index 100%
> rename from include/drm-uapi/sync_file.h
> rename to include/linux-uapi/sync_file.h
> diff --git a/meson.build b/meson.build
> index 06e76189..f9a284d8 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -86,7 +86,7 @@ with_libdrm = get_option('libdrm_drivers')
>  
>  build_info = ['Build type: ' + get_option('buildtype')]
>  
> -inc = include_directories('include/drm-uapi', 'lib', 'lib/stubs/syscalls', '.')
> +inc = include_directories('include/drm-uapi', 'include/linux-uapi', 'lib', 'lib/stubs/syscalls', '.')
>  
>  inc_for_gtkdoc = include_directories('lib')
>  
> -- 
> 2.31.1
> 

Re: [igt-dev] [PATCH i-g-t 3/8] i915_drm.h sync with drm-next

[Petri Latvala]

On Wed, Oct 06, 2021 at 12:14:39PM -0400, Rodrigo Vivi wrote:
> Let's do a catch-up on i915_drm.h here.
> Only on i915_drm.h for now so we can have a clean
> view of the LOCAL_ ones that we need to remove.
> 
> Taken from 25fed6b324ac ("Merge tag 'drm-intel-gt-next-2021-08-06-1' of ssh://git.freedesktop.org/git/drm/drm-intel into drm-next")
> 
> Cc: Petri Latvala <petri.latvala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Acked-by: Petri Latvala <petri.latvala@intel.com>

> ---
>  include/drm-uapi/i915_drm.h | 48 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index b9632bb2..c788a1ab 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -572,6 +572,15 @@ typedef struct drm_i915_irq_wait {
>  #define   I915_SCHEDULER_CAP_PREEMPTION	(1ul << 2)
>  #define   I915_SCHEDULER_CAP_SEMAPHORES	(1ul << 3)
>  #define   I915_SCHEDULER_CAP_ENGINE_BUSY_STATS	(1ul << 4)
> +/*
> + * Indicates the 2k user priority levels are statically mapped into 3 buckets as
> + * follows:
> + *
> + * -1k to -1	Low priority
> + * 0		Normal priority
> + * 1 to 1k	Highest priority
> + */
> +#define   I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP	(1ul << 5)
>  
>  #define I915_PARAM_HUC_STATUS		 42
>  
> @@ -674,6 +683,9 @@ typedef struct drm_i915_irq_wait {
>   */
>  #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
>  
> +/* Query if the kernel supports the I915_USERPTR_PROBE flag. */
> +#define I915_PARAM_HAS_USERPTR_PROBE 56
> +
>  /* Must be kept compact -- no holes and well documented */
>  
>  typedef struct drm_i915_getparam {
> @@ -923,6 +935,25 @@ struct drm_i915_gem_mmap_offset {
>   *	- I915_GEM_DOMAIN_GTT: Mappable aperture domain
>   *
>   * All other domains are rejected.
> + *
> + * Note that for discrete, starting from DG1, this is no longer supported, and
> + * is instead rejected. On such platforms the CPU domain is effectively static,
> + * where we also only support a single &drm_i915_gem_mmap_offset cache mode,
> + * which can't be set explicitly and instead depends on the object placements,
> + * as per the below.
> + *
> + * Implicit caching rules, starting from DG1:
> + *
> + *	- If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
> + *	  contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
> + *	  mapped as write-combined only.
> + *
> + *	- Everything else is always allocated and mapped as write-back, with the
> + *	  guarantee that everything is also coherent with the GPU.
> + *
> + * Note that this is likely to change in the future again, where we might need
> + * more flexibility on future devices, so making this all explicit as part of a
> + * new &drm_i915_gem_create_ext extension is probable.
>   */
>  struct drm_i915_gem_set_domain {
>  	/** @handle: Handle for the object. */
> @@ -2203,12 +2234,29 @@ struct drm_i915_gem_userptr {
>  	 * through the GTT. If the HW can't support readonly access, an error is
>  	 * returned.
>  	 *
> +	 * I915_USERPTR_PROBE:
> +	 *
> +	 * Probe the provided @user_ptr range and validate that the @user_ptr is
> +	 * indeed pointing to normal memory and that the range is also valid.
> +	 * For example if some garbage address is given to the kernel, then this
> +	 * should complain.
> +	 *
> +	 * Returns -EFAULT if the probe failed.
> +	 *
> +	 * Note that this doesn't populate the backing pages, and also doesn't
> +	 * guarantee that the object will remain valid when the object is
> +	 * eventually used.
> +	 *
> +	 * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE
> +	 * returns a non-zero value.
> +	 *
>  	 * I915_USERPTR_UNSYNCHRONIZED:
>  	 *
>  	 * NOT USED. Setting this flag will result in an error.
>  	 */
>  	__u32 flags;
>  #define I915_USERPTR_READ_ONLY 0x1
> +#define I915_USERPTR_PROBE 0x2
>  #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
>  	/**
>  	 * @handle: Returned handle for the object.
> -- 
> 2.31.1
> 

Re: [igt-dev] [PATCH i-g-t 5/8] include/drm-uapi: Sync with drm-next

[Petri Latvala]

On Wed, Oct 06, 2021 at 12:14:41PM -0400, Rodrigo Vivi wrote:
> Sync to: 1e3944578b74 ("Merge tag 'amd-drm-next-5.16-2021-09-27' of https://gitlab.freedesktop.org/agd5f/linux into drm-next")
> 
> Cc: Petri Latvala <petri.latvala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Acked-by: Petri Latvala <petri.latvala@intel.com>

> ---
>  include/drm-uapi/drm.h        |  14 +-
>  include/drm-uapi/drm_fourcc.h | 115 ++++++++-
>  include/drm-uapi/drm_mode.h   |  95 +++++++-
>  include/drm-uapi/msm_drm.h    |  14 +-
>  include/drm-uapi/tegra_drm.h  | 425 ++++++++++++++++++++++++++++++++--
>  include/drm-uapi/v3d_drm.h    | 136 +++++++++++
>  include/drm-uapi/vmwgfx_drm.h |  41 ++++
>  7 files changed, 807 insertions(+), 33 deletions(-)
> 
> diff --git a/include/drm-uapi/drm.h b/include/drm-uapi/drm.h
> index 398c396f..5e54c3aa 100644
> --- a/include/drm-uapi/drm.h
> +++ b/include/drm-uapi/drm.h
> @@ -629,8 +629,8 @@ struct drm_gem_open {
>  /**
>   * DRM_CAP_VBLANK_HIGH_CRTC
>   *
> - * If set to 1, the kernel supports specifying a CRTC index in the high bits of
> - * &drm_wait_vblank_request.type.
> + * If set to 1, the kernel supports specifying a :ref:`CRTC index<crtc_index>`
> + * in the high bits of &drm_wait_vblank_request.type.
>   *
>   * Starting kernel version 2.6.39, this capability is always set to 1.
>   */
> @@ -1044,6 +1044,16 @@ extern "C" {
>  #define DRM_IOCTL_MODE_GETPROPBLOB	DRM_IOWR(0xAC, struct drm_mode_get_blob)
>  #define DRM_IOCTL_MODE_GETFB		DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
>  #define DRM_IOCTL_MODE_ADDFB		DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
> +/**
> + * DRM_IOCTL_MODE_RMFB - Remove a framebuffer.
> + *
> + * This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL
> + * argument is a framebuffer object ID.
> + *
> + * Warning: removing a framebuffer currently in-use on an enabled plane will
> + * disable that plane. The CRTC the plane is linked to may also be disabled
> + * (depending on driver capabilities).
> + */
>  #define DRM_IOCTL_MODE_RMFB		DRM_IOWR(0xAF, unsigned int)
>  #define DRM_IOCTL_MODE_PAGE_FLIP	DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
>  #define DRM_IOCTL_MODE_DIRTYFB		DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
> diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
> index cd3ce8a8..91b6a0fd 100644
> --- a/include/drm-uapi/drm_fourcc.h
> +++ b/include/drm-uapi/drm_fourcc.h
> @@ -373,6 +373,12 @@ extern "C" {
>  
>  #define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
>  
> +#define fourcc_mod_get_vendor(modifier) \
> +	(((modifier) >> 56) & 0xff)
> +
> +#define fourcc_mod_is_vendor(modifier, vendor) \
> +	(fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor)
> +
>  #define fourcc_mod_code(vendor, val) \
>  	((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
>  
> @@ -900,9 +906,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
>  
>  /*
>   * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
> - * modifiers) denote the category for modifiers. Currently we have only two
> - * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
> - * different categories.
> + * modifiers) denote the category for modifiers. Currently we have three
> + * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
> + * sixteen different categories.
>   */
>  #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
>  	fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
> @@ -1017,6 +1023,109 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
>   */
>  #define AFBC_FORMAT_MOD_USM	(1ULL << 12)
>  
> +/*
> + * Arm Fixed-Rate Compression (AFRC) modifiers
> + *
> + * AFRC is a proprietary fixed rate image compression protocol and format,
> + * designed to provide guaranteed bandwidth and memory footprint
> + * reductions in graphics and media use-cases.
> + *
> + * AFRC buffers consist of one or more planes, with the same components
> + * and meaning as an uncompressed buffer using the same pixel format.
> + *
> + * Within each plane, the pixel/luma/chroma values are grouped into
> + * "coding unit" blocks which are individually compressed to a
> + * fixed size (in bytes). All coding units within a given plane of a buffer
> + * store the same number of values, and have the same compressed size.
> + *
> + * The coding unit size is configurable, allowing different rates of compression.
> + *
> + * The start of each AFRC buffer plane must be aligned to an alignment granule which
> + * depends on the coding unit size.
> + *
> + * Coding Unit Size   Plane Alignment
> + * ----------------   ---------------
> + * 16 bytes           1024 bytes
> + * 24 bytes           512  bytes
> + * 32 bytes           2048 bytes
> + *
> + * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned
> + * to a multiple of the paging tile dimensions.
> + * The dimensions of each paging tile depend on whether the buffer is optimised for
> + * scanline (SCAN layout) or rotated (ROT layout) access.
> + *
> + * Layout   Paging Tile Width   Paging Tile Height
> + * ------   -----------------   ------------------
> + * SCAN     16 coding units     4 coding units
> + * ROT      8  coding units     8 coding units
> + *
> + * The dimensions of each coding unit depend on the number of components
> + * in the compressed plane and whether the buffer is optimised for
> + * scanline (SCAN layout) or rotated (ROT layout) access.
> + *
> + * Number of Components in Plane   Layout      Coding Unit Width   Coding Unit Height
> + * -----------------------------   ---------   -----------------   ------------------
> + * 1                               SCAN        16 samples          4 samples
> + * Example: 16x4 luma samples in a 'Y' plane
> + *          16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
> + * -----------------------------   ---------   -----------------   ------------------
> + * 1                               ROT         8 samples           8 samples
> + * Example: 8x8 luma samples in a 'Y' plane
> + *          8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
> + * -----------------------------   ---------   -----------------   ------------------
> + * 2                               DONT CARE   8 samples           4 samples
> + * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
> + * -----------------------------   ---------   -----------------   ------------------
> + * 3                               DONT CARE   4 samples           4 samples
> + * Example: 4x4 pixels in an RGB buffer without alpha
> + * -----------------------------   ---------   -----------------   ------------------
> + * 4                               DONT CARE   4 samples           4 samples
> + * Example: 4x4 pixels in an RGB buffer with alpha
> + */
> +
> +#define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02
> +
> +#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \
> +	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)
> +
> +/*
> + * AFRC coding unit size modifier.
> + *
> + * Indicates the number of bytes used to store each compressed coding unit for
> + * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance
> + * is the same for both Cb and Cr, which may be stored in separate planes.
> + *
> + * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store
> + * each compressed coding unit in the first plane of the buffer. For RGBA buffers
> + * this is the only plane, while for semi-planar and fully-planar YUV buffers,
> + * this corresponds to the luma plane.
> + *
> + * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store
> + * each compressed coding unit in the second and third planes in the buffer.
> + * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
> + *
> + * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
> + * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero.
> + * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
> + * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified.
> + */
> +#define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf
> +#define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
> +#define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)
> +#define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)
> +
> +#define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)
> +#define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
> +
> +/*
> + * AFRC scanline memory layout.
> + *
> + * Indicates if the buffer uses the scanline-optimised layout
> + * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
> + * The memory layout is the same for all planes.
> + */
> +#define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
> +
>  /*
>   * Arm 16x16 Block U-Interleaved modifier
>   *
> diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h
> index 9b6722d4..e4a2570a 100644
> --- a/include/drm-uapi/drm_mode.h
> +++ b/include/drm-uapi/drm_mode.h
> @@ -312,16 +312,48 @@ struct drm_mode_set_plane {
>  	__u32 src_w;
>  };
>  
> +/**
> + * struct drm_mode_get_plane - Get plane metadata.
> + *
> + * Userspace can perform a GETPLANE ioctl to retrieve information about a
> + * plane.
> + *
> + * To retrieve the number of formats supported, set @count_format_types to zero
> + * and call the ioctl. @count_format_types will be updated with the value.
> + *
> + * To retrieve these formats, allocate an array with the memory needed to store
> + * @count_format_types formats. Point @format_type_ptr to this array and call
> + * the ioctl again (with @count_format_types still set to the value returned in
> + * the first ioctl call).
> + */
>  struct drm_mode_get_plane {
> +	/**
> +	 * @plane_id: Object ID of the plane whose information should be
> +	 * retrieved. Set by caller.
> +	 */
>  	__u32 plane_id;
>  
> +	/** @crtc_id: Object ID of the current CRTC. */
>  	__u32 crtc_id;
> +	/** @fb_id: Object ID of the current fb. */
>  	__u32 fb_id;
>  
> +	/**
> +	 * @possible_crtcs: Bitmask of CRTC's compatible with the plane. CRTC's
> +	 * are created and they receive an index, which corresponds to their
> +	 * position in the bitmask. Bit N corresponds to
> +	 * :ref:`CRTC index<crtc_index>` N.
> +	 */
>  	__u32 possible_crtcs;
> +	/** @gamma_size: Never used. */
>  	__u32 gamma_size;
>  
> +	/** @count_format_types: Number of formats. */
>  	__u32 count_format_types;
> +	/**
> +	 * @format_type_ptr: Pointer to ``__u32`` array of formats that are
> +	 * supported by the plane. These formats do not require modifiers.
> +	 */
>  	__u64 format_type_ptr;
>  };
>  
> @@ -509,22 +541,74 @@ struct drm_mode_get_connector {
>   */
>  #define DRM_MODE_PROP_ATOMIC        0x80000000
>  
> +/**
> + * struct drm_mode_property_enum - Description for an enum/bitfield entry.
> + * @value: numeric value for this enum entry.
> + * @name: symbolic name for this enum entry.
> + *
> + * See struct drm_property_enum for details.
> + */
>  struct drm_mode_property_enum {
>  	__u64 value;
>  	char name[DRM_PROP_NAME_LEN];
>  };
>  
> +/**
> + * struct drm_mode_get_property - Get property metadata.
> + *
> + * User-space can perform a GETPROPERTY ioctl to retrieve information about a
> + * property. The same property may be attached to multiple objects, see
> + * "Modeset Base Object Abstraction".
> + *
> + * The meaning of the @values_ptr field changes depending on the property type.
> + * See &drm_property.flags for more details.
> + *
> + * The @enum_blob_ptr and @count_enum_blobs fields are only meaningful when the
> + * property has the type &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK. For
> + * backwards compatibility, the kernel will always set @count_enum_blobs to
> + * zero when the property has the type &DRM_MODE_PROP_BLOB. User-space must
> + * ignore these two fields if the property has a different type.
> + *
> + * User-space is expected to retrieve values and enums by performing this ioctl
> + * at least twice: the first time to retrieve the number of elements, the
> + * second time to retrieve the elements themselves.
> + *
> + * To retrieve the number of elements, set @count_values and @count_enum_blobs
> + * to zero, then call the ioctl. @count_values will be updated with the number
> + * of elements. If the property has the type &DRM_MODE_PROP_ENUM or
> + * &DRM_MODE_PROP_BITMASK, @count_enum_blobs will be updated as well.
> + *
> + * To retrieve the elements themselves, allocate an array for @values_ptr and
> + * set @count_values to its capacity. If the property has the type
> + * &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK, allocate an array for
> + * @enum_blob_ptr and set @count_enum_blobs to its capacity. Calling the ioctl
> + * again will fill the arrays.
> + */
>  struct drm_mode_get_property {
> -	__u64 values_ptr; /* values and blob lengths */
> -	__u64 enum_blob_ptr; /* enum and blob id ptrs */
> +	/** @values_ptr: Pointer to a ``__u64`` array. */
> +	__u64 values_ptr;
> +	/** @enum_blob_ptr: Pointer to a struct drm_mode_property_enum array. */
> +	__u64 enum_blob_ptr;
>  
> +	/**
> +	 * @prop_id: Object ID of the property which should be retrieved. Set
> +	 * by the caller.
> +	 */
>  	__u32 prop_id;
> +	/**
> +	 * @flags: ``DRM_MODE_PROP_*`` bitfield. See &drm_property.flags for
> +	 * a definition of the flags.
> +	 */
>  	__u32 flags;
> +	/**
> +	 * @name: Symbolic property name. User-space should use this field to
> +	 * recognize properties.
> +	 */
>  	char name[DRM_PROP_NAME_LEN];
>  
> +	/** @count_values: Number of elements in @values_ptr. */
>  	__u32 count_values;
> -	/* This is only used to count enum values, not blobs. The _blobs is
> -	 * simply because of a historical reason, i.e. backwards compat. */
> +	/** @count_enum_blobs: Number of elements in @enum_blob_ptr. */
>  	__u32 count_enum_blobs;
>  };
>  
> @@ -1026,6 +1110,9 @@ struct drm_mode_destroy_blob {
>   * struct drm_mode_create_lease - Create lease
>   *
>   * Lease mode resources, creating another drm_master.
> + *
> + * The @object_ids array must reference at least one CRTC, one connector and
> + * one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled.
>   */
>  struct drm_mode_create_lease {
>  	/** @object_ids: Pointer to array of object ids (__u32) */
> diff --git a/include/drm-uapi/msm_drm.h b/include/drm-uapi/msm_drm.h
> index f0758510..6b8fffc2 100644
> --- a/include/drm-uapi/msm_drm.h
> +++ b/include/drm-uapi/msm_drm.h
> @@ -73,11 +73,19 @@ struct drm_msm_timespec {
>  #define MSM_PARAM_MAX_FREQ   0x04
>  #define MSM_PARAM_TIMESTAMP  0x05
>  #define MSM_PARAM_GMEM_BASE  0x06
> -#define MSM_PARAM_NR_RINGS   0x07
> +#define MSM_PARAM_PRIORITIES 0x07  /* The # of priority levels */
>  #define MSM_PARAM_PP_PGTABLE 0x08  /* => 1 for per-process pagetables, else 0 */
>  #define MSM_PARAM_FAULTS     0x09
>  #define MSM_PARAM_SUSPENDS   0x0a
>  
> +/* For backwards compat.  The original support for preemption was based on
> + * a single ring per priority level so # of priority levels equals the #
> + * of rings.  With drm/scheduler providing additional levels of priority,
> + * the number of priorities is greater than the # of rings.  The param is
> + * renamed to better reflect this.
> + */
> +#define MSM_PARAM_NR_RINGS   MSM_PARAM_PRIORITIES
> +
>  struct drm_msm_param {
>  	__u32 pipe;           /* in, MSM_PIPE_x */
>  	__u32 param;          /* in, MSM_PARAM_x */
> @@ -304,6 +312,10 @@ struct drm_msm_gem_madvise {
>  
>  #define MSM_SUBMITQUEUE_FLAGS (0)
>  
> +/*
> + * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
> + * a lower numeric value is higher priority.
> + */
>  struct drm_msm_submitqueue {
>  	__u32 flags;   /* in, MSM_SUBMITQUEUE_x */
>  	__u32 prio;    /* in, Priority level */
> diff --git a/include/drm-uapi/tegra_drm.h b/include/drm-uapi/tegra_drm.h
> index 6c07919c..bb1adff0 100644
> --- a/include/drm-uapi/tegra_drm.h
> +++ b/include/drm-uapi/tegra_drm.h
> @@ -1,24 +1,5 @@
> -/*
> - * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - */
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright (c) 2012-2020 NVIDIA Corporation */
>  
>  #ifndef _TEGRA_DRM_H_
>  #define _TEGRA_DRM_H_
> @@ -29,6 +10,8 @@
>  extern "C" {
>  #endif
>  
> +/* Tegra DRM legacy UAPI. Only enabled with STAGING */
> +
>  #define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
>  #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
>  
> @@ -649,8 +632,8 @@ struct drm_tegra_gem_get_flags {
>  #define DRM_TEGRA_SYNCPT_READ		0x02
>  #define DRM_TEGRA_SYNCPT_INCR		0x03
>  #define DRM_TEGRA_SYNCPT_WAIT		0x04
> -#define DRM_TEGRA_OPEN_CHANNEL		0x05
> -#define DRM_TEGRA_CLOSE_CHANNEL		0x06
> +#define DRM_TEGRA_OPEN_CHANNEL	        0x05
> +#define DRM_TEGRA_CLOSE_CHANNEL	        0x06
>  #define DRM_TEGRA_GET_SYNCPT		0x07
>  #define DRM_TEGRA_SUBMIT		0x08
>  #define DRM_TEGRA_GET_SYNCPT_BASE	0x09
> @@ -674,6 +657,402 @@ struct drm_tegra_gem_get_flags {
>  #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
>  #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
>  
> +/* New Tegra DRM UAPI */
> +
> +/*
> + * Reported by the driver in the `capabilities` field.
> + *
> + * DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent
> + * with regard to the system memory.
> + */
> +#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0)
> +
> +struct drm_tegra_channel_open {
> +	/**
> +	 * @host1x_class: [in]
> +	 *
> +	 * Host1x class of the engine that will be programmed using this
> +	 * channel.
> +	 */
> +	__u32 host1x_class;
> +
> +	/**
> +	 * @flags: [in]
> +	 *
> +	 * Flags.
> +	 */
> +	__u32 flags;
> +
> +	/**
> +	 * @context: [out]
> +	 *
> +	 * Opaque identifier corresponding to the opened channel.
> +	 */
> +	__u32 context;
> +
> +	/**
> +	 * @version: [out]
> +	 *
> +	 * Version of the engine hardware. This can be used by userspace
> +	 * to determine how the engine needs to be programmed.
> +	 */
> +	__u32 version;
> +
> +	/**
> +	 * @capabilities: [out]
> +	 *
> +	 * Flags describing the hardware capabilities.
> +	 */
> +	__u32 capabilities;
> +	__u32 padding;
> +};
> +
> +struct drm_tegra_channel_close {
> +	/**
> +	 * @context: [in]
> +	 *
> +	 * Identifier of the channel to close.
> +	 */
> +	__u32 context;
> +	__u32 padding;
> +};
> +
> +/*
> + * Mapping flags that can be used to influence how the mapping is created.
> + *
> + * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access
> + * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access
> + */
> +#define DRM_TEGRA_CHANNEL_MAP_READ  (1 << 0)
> +#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1)
> +#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \
> +					  DRM_TEGRA_CHANNEL_MAP_WRITE)
> +
> +struct drm_tegra_channel_map {
> +	/**
> +	 * @context: [in]
> +	 *
> +	 * Identifier of the channel to which make memory available for.
> +	 */
> +	__u32 context;
> +
> +	/**
> +	 * @handle: [in]
> +	 *
> +	 * GEM handle of the memory to map.
> +	 */
> +	__u32 handle;
> +
> +	/**
> +	 * @flags: [in]
> +	 *
> +	 * Flags.
> +	 */
> +	__u32 flags;
> +
> +	/**
> +	 * @mapping: [out]
> +	 *
> +	 * Identifier corresponding to the mapping, to be used for
> +	 * relocations or unmapping later.
> +	 */
> +	__u32 mapping;
> +};
> +
> +struct drm_tegra_channel_unmap {
> +	/**
> +	 * @context: [in]
> +	 *
> +	 * Channel identifier of the channel to unmap memory from.
> +	 */
> +	__u32 context;
> +
> +	/**
> +	 * @mapping: [in]
> +	 *
> +	 * Mapping identifier of the memory mapping to unmap.
> +	 */
> +	__u32 mapping;
> +};
> +
> +/* Submission */
> +
> +/**
> + * Specify that bit 39 of the patched-in address should be set to switch
> + * swizzling between Tegra and non-Tegra sector layout on systems that store
> + * surfaces in system memory in non-Tegra sector layout.
> + */
> +#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0)
> +
> +struct drm_tegra_submit_buf {
> +	/**
> +	 * @mapping: [in]
> +	 *
> +	 * Identifier of the mapping to use in the submission.
> +	 */
> +	__u32 mapping;
> +
> +	/**
> +	 * @flags: [in]
> +	 *
> +	 * Flags.
> +	 */
> +	__u32 flags;
> +
> +	/**
> +	 * Information for relocation patching.
> +	 */
> +	struct {
> +		/**
> +		 * @target_offset: [in]
> +		 *
> +		 * Offset from the start of the mapping of the data whose
> +		 * address is to be patched into the gather.
> +		 */
> +		__u64 target_offset;
> +
> +		/**
> +		 * @gather_offset_words: [in]
> +		 *
> +		 * Offset in words from the start of the gather data to
> +		 * where the address should be patched into.
> +		 */
> +		__u32 gather_offset_words;
> +
> +		/**
> +		 * @shift: [in]
> +		 *
> +		 * Number of bits the address should be shifted right before
> +		 * patching in.
> +		 */
> +		__u32 shift;
> +	} reloc;
> +};
> +
> +/**
> + * Execute `words` words of Host1x opcodes specified in the `gather_data_ptr`
> + * buffer. Each GATHER_UPTR command uses successive words from the buffer.
> + */
> +#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR		0
> +/**
> + * Wait for a syncpoint to reach a value before continuing with further
> + * commands.
> + */
> +#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT		1
> +/**
> + * Wait for a syncpoint to reach a value before continuing with further
> + * commands. The threshold is calculated relative to the start of the job.
> + */
> +#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE	2
> +
> +struct drm_tegra_submit_cmd_gather_uptr {
> +	__u32 words;
> +	__u32 reserved[3];
> +};
> +
> +struct drm_tegra_submit_cmd_wait_syncpt {
> +	__u32 id;
> +	__u32 value;
> +	__u32 reserved[2];
> +};
> +
> +struct drm_tegra_submit_cmd {
> +	/**
> +	 * @type: [in]
> +	 *
> +	 * Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD*
> +	 * defines.
> +	 */
> +	__u32 type;
> +
> +	/**
> +	 * @flags: [in]
> +	 *
> +	 * Flags.
> +	 */
> +	__u32 flags;
> +
> +	union {
> +		struct drm_tegra_submit_cmd_gather_uptr gather_uptr;
> +		struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt;
> +		__u32 reserved[4];
> +	};
> +};
> +
> +struct drm_tegra_submit_syncpt {
> +	/**
> +	 * @id: [in]
> +	 *
> +	 * ID of the syncpoint that the job will increment.
> +	 */
> +	__u32 id;
> +
> +	/**
> +	 * @flags: [in]
> +	 *
> +	 * Flags.
> +	 */
> +	__u32 flags;
> +
> +	/**
> +	 * @increments: [in]
> +	 *
> +	 * Number of times the job will increment this syncpoint.
> +	 */
> +	__u32 increments;
> +
> +	/**
> +	 * @value: [out]
> +	 *
> +	 * Value the syncpoint will have once the job has completed all
> +	 * its specified syncpoint increments.
> +	 *
> +	 * Note that the kernel may increment the syncpoint before or after
> +	 * the job. These increments are not reflected in this field.
> +	 *
> +	 * If the job hangs or times out, not all of the increments may
> +	 * get executed.
> +	 */
> +	__u32 value;
> +};
> +
> +struct drm_tegra_channel_submit {
> +	/**
> +	 * @context: [in]
> +	 *
> +	 * Identifier of the channel to submit this job to.
> +	 */
> +	__u32 context;
> +
> +	/**
> +	 * @num_bufs: [in]
> +	 *
> +	 * Number of elements in the `bufs_ptr` array.
> +	 */
> +	__u32 num_bufs;
> +
> +	/**
> +	 * @num_cmds: [in]
> +	 *
> +	 * Number of elements in the `cmds_ptr` array.
> +	 */
> +	__u32 num_cmds;
> +
> +	/**
> +	 * @gather_data_words: [in]
> +	 *
> +	 * Number of 32-bit words in the `gather_data_ptr` array.
> +	 */
> +	__u32 gather_data_words;
> +
> +	/**
> +	 * @bufs_ptr: [in]
> +	 *
> +	 * Pointer to an array of drm_tegra_submit_buf structures.
> +	 */
> +	__u64 bufs_ptr;
> +
> +	/**
> +	 * @cmds_ptr: [in]
> +	 *
> +	 * Pointer to an array of drm_tegra_submit_cmd structures.
> +	 */
> +	__u64 cmds_ptr;
> +
> +	/**
> +	 * @gather_data_ptr: [in]
> +	 *
> +	 * Pointer to an array of Host1x opcodes to be used by GATHER_UPTR
> +	 * commands.
> +	 */
> +	__u64 gather_data_ptr;
> +
> +	/**
> +	 * @syncobj_in: [in]
> +	 *
> +	 * Handle for DRM syncobj that will be waited before submission.
> +	 * Ignored if zero.
> +	 */
> +	__u32 syncobj_in;
> +
> +	/**
> +	 * @syncobj_out: [in]
> +	 *
> +	 * Handle for DRM syncobj that will have its fence replaced with
> +	 * the job's completion fence. Ignored if zero.
> +	 */
> +	__u32 syncobj_out;
> +
> +	/**
> +	 * @syncpt_incr: [in,out]
> +	 *
> +	 * Information about the syncpoint the job will increment.
> +	 */
> +	struct drm_tegra_submit_syncpt syncpt;
> +};
> +
> +struct drm_tegra_syncpoint_allocate {
> +	/**
> +	 * @id: [out]
> +	 *
> +	 * ID of allocated syncpoint.
> +	 */
> +	__u32 id;
> +	__u32 padding;
> +};
> +
> +struct drm_tegra_syncpoint_free {
> +	/**
> +	 * @id: [in]
> +	 *
> +	 * ID of syncpoint to free.
> +	 */
> +	__u32 id;
> +	__u32 padding;
> +};
> +
> +struct drm_tegra_syncpoint_wait {
> +	/**
> +	 * @timeout: [in]
> +	 *
> +	 * Absolute timestamp at which the wait will time out.
> +	 */
> +	__s64 timeout_ns;
> +
> +	/**
> +	 * @id: [in]
> +	 *
> +	 * ID of syncpoint to wait on.
> +	 */
> +	__u32 id;
> +
> +	/**
> +	 * @threshold: [in]
> +	 *
> +	 * Threshold to wait for.
> +	 */
> +	__u32 threshold;
> +
> +	/**
> +	 * @value: [out]
> +	 *
> +	 * Value of the syncpoint upon wait completion.
> +	 */
> +	__u32 value;
> +
> +	__u32 padding;
> +};
> +
> +#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open)
> +#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close)
> +#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map)
> +#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap)
> +#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit)
> +
> +#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate)
> +#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free)
> +#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait)
> +
>  #if defined(__cplusplus)
>  }
>  #endif
> diff --git a/include/drm-uapi/v3d_drm.h b/include/drm-uapi/v3d_drm.h
> index 1ce746e2..4104f22f 100644
> --- a/include/drm-uapi/v3d_drm.h
> +++ b/include/drm-uapi/v3d_drm.h
> @@ -38,6 +38,9 @@ extern "C" {
>  #define DRM_V3D_GET_BO_OFFSET                     0x05
>  #define DRM_V3D_SUBMIT_TFU                        0x06
>  #define DRM_V3D_SUBMIT_CSD                        0x07
> +#define DRM_V3D_PERFMON_CREATE                    0x08
> +#define DRM_V3D_PERFMON_DESTROY                   0x09
> +#define DRM_V3D_PERFMON_GET_VALUES                0x0a
>  
>  #define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
>  #define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
> @@ -47,6 +50,12 @@ extern "C" {
>  #define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
>  #define DRM_IOCTL_V3D_SUBMIT_TFU          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
>  #define DRM_IOCTL_V3D_SUBMIT_CSD          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
> +#define DRM_IOCTL_V3D_PERFMON_CREATE      DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \
> +						   struct drm_v3d_perfmon_create)
> +#define DRM_IOCTL_V3D_PERFMON_DESTROY     DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \
> +						   struct drm_v3d_perfmon_destroy)
> +#define DRM_IOCTL_V3D_PERFMON_GET_VALUES  DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \
> +						   struct drm_v3d_perfmon_get_values)
>  
>  #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE             0x01
>  
> @@ -127,6 +136,11 @@ struct drm_v3d_submit_cl {
>  	__u32 bo_handle_count;
>  
>  	__u32 flags;
> +
> +	/* ID of the perfmon to attach to this job. 0 means no perfmon. */
> +	__u32 perfmon_id;
> +
> +	__u32 pad;
>  };
>  
>  /**
> @@ -195,6 +209,7 @@ enum drm_v3d_param {
>  	DRM_V3D_PARAM_SUPPORTS_TFU,
>  	DRM_V3D_PARAM_SUPPORTS_CSD,
>  	DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
> +	DRM_V3D_PARAM_SUPPORTS_PERFMON,
>  };
>  
>  struct drm_v3d_get_param {
> @@ -258,6 +273,127 @@ struct drm_v3d_submit_csd {
>  	__u32 in_sync;
>  	/* Sync object to signal when the CSD job is done. */
>  	__u32 out_sync;
> +
> +	/* ID of the perfmon to attach to this job. 0 means no perfmon. */
> +	__u32 perfmon_id;
> +};
> +
> +enum {
> +	V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
> +	V3D_PERFCNT_FEP_VALID_PRIMS,
> +	V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS,
> +	V3D_PERFCNT_FEP_VALID_QUADS,
> +	V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL,
> +	V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL,
> +	V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS,
> +	V3D_PERFCNT_TLB_QUADS_ZERO_COV,
> +	V3D_PERFCNT_TLB_QUADS_NONZERO_COV,
> +	V3D_PERFCNT_TLB_QUADS_WRITTEN,
> +	V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD,
> +	V3D_PERFCNT_PTB_PRIM_CLIP,
> +	V3D_PERFCNT_PTB_PRIM_REV,
> +	V3D_PERFCNT_QPU_IDLE_CYCLES,
> +	V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER,
> +	V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG,
> +	V3D_PERFCNT_QPU_CYCLES_VALID_INSTR,
> +	V3D_PERFCNT_QPU_CYCLES_TMU_STALL,
> +	V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL,
> +	V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL,
> +	V3D_PERFCNT_QPU_IC_HIT,
> +	V3D_PERFCNT_QPU_IC_MISS,
> +	V3D_PERFCNT_QPU_UC_HIT,
> +	V3D_PERFCNT_QPU_UC_MISS,
> +	V3D_PERFCNT_TMU_TCACHE_ACCESS,
> +	V3D_PERFCNT_TMU_TCACHE_MISS,
> +	V3D_PERFCNT_VPM_VDW_STALL,
> +	V3D_PERFCNT_VPM_VCD_STALL,
> +	V3D_PERFCNT_BIN_ACTIVE,
> +	V3D_PERFCNT_RDR_ACTIVE,
> +	V3D_PERFCNT_L2T_HITS,
> +	V3D_PERFCNT_L2T_MISSES,
> +	V3D_PERFCNT_CYCLE_COUNT,
> +	V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER,
> +	V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT,
> +	V3D_PERFCNT_PTB_PRIMS_BINNED,
> +	V3D_PERFCNT_AXI_WRITES_WATCH_0,
> +	V3D_PERFCNT_AXI_READS_WATCH_0,
> +	V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0,
> +	V3D_PERFCNT_AXI_READ_STALLS_WATCH_0,
> +	V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0,
> +	V3D_PERFCNT_AXI_READ_BYTES_WATCH_0,
> +	V3D_PERFCNT_AXI_WRITES_WATCH_1,
> +	V3D_PERFCNT_AXI_READS_WATCH_1,
> +	V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1,
> +	V3D_PERFCNT_AXI_READ_STALLS_WATCH_1,
> +	V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1,
> +	V3D_PERFCNT_AXI_READ_BYTES_WATCH_1,
> +	V3D_PERFCNT_TLB_PARTIAL_QUADS,
> +	V3D_PERFCNT_TMU_CONFIG_ACCESSES,
> +	V3D_PERFCNT_L2T_NO_ID_STALL,
> +	V3D_PERFCNT_L2T_COM_QUE_STALL,
> +	V3D_PERFCNT_L2T_TMU_WRITES,
> +	V3D_PERFCNT_TMU_ACTIVE_CYCLES,
> +	V3D_PERFCNT_TMU_STALLED_CYCLES,
> +	V3D_PERFCNT_CLE_ACTIVE,
> +	V3D_PERFCNT_L2T_TMU_READS,
> +	V3D_PERFCNT_L2T_CLE_READS,
> +	V3D_PERFCNT_L2T_VCD_READS,
> +	V3D_PERFCNT_L2T_TMUCFG_READS,
> +	V3D_PERFCNT_L2T_SLC0_READS,
> +	V3D_PERFCNT_L2T_SLC1_READS,
> +	V3D_PERFCNT_L2T_SLC2_READS,
> +	V3D_PERFCNT_L2T_TMU_W_MISSES,
> +	V3D_PERFCNT_L2T_TMU_R_MISSES,
> +	V3D_PERFCNT_L2T_CLE_MISSES,
> +	V3D_PERFCNT_L2T_VCD_MISSES,
> +	V3D_PERFCNT_L2T_TMUCFG_MISSES,
> +	V3D_PERFCNT_L2T_SLC0_MISSES,
> +	V3D_PERFCNT_L2T_SLC1_MISSES,
> +	V3D_PERFCNT_L2T_SLC2_MISSES,
> +	V3D_PERFCNT_CORE_MEM_WRITES,
> +	V3D_PERFCNT_L2T_MEM_WRITES,
> +	V3D_PERFCNT_PTB_MEM_WRITES,
> +	V3D_PERFCNT_TLB_MEM_WRITES,
> +	V3D_PERFCNT_CORE_MEM_READS,
> +	V3D_PERFCNT_L2T_MEM_READS,
> +	V3D_PERFCNT_PTB_MEM_READS,
> +	V3D_PERFCNT_PSE_MEM_READS,
> +	V3D_PERFCNT_TLB_MEM_READS,
> +	V3D_PERFCNT_GMP_MEM_READS,
> +	V3D_PERFCNT_PTB_W_MEM_WORDS,
> +	V3D_PERFCNT_TLB_W_MEM_WORDS,
> +	V3D_PERFCNT_PSE_R_MEM_WORDS,
> +	V3D_PERFCNT_TLB_R_MEM_WORDS,
> +	V3D_PERFCNT_TMU_MRU_HITS,
> +	V3D_PERFCNT_COMPUTE_ACTIVE,
> +	V3D_PERFCNT_NUM,
> +};
> +
> +#define DRM_V3D_MAX_PERF_COUNTERS                 32
> +
> +struct drm_v3d_perfmon_create {
> +	__u32 id;
> +	__u32 ncounters;
> +	__u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
> +};
> +
> +struct drm_v3d_perfmon_destroy {
> +	__u32 id;
> +};
> +
> +/*
> + * Returns the values of the performance counters tracked by this
> + * perfmon (as an array of ncounters u64 values).
> + *
> + * No implicit synchronization is performed, so the user has to
> + * guarantee that any jobs using this perfmon have already been
> + * completed  (probably by blocking on the seqno returned by the
> + * last exec that used the perfmon).
> + */
> +struct drm_v3d_perfmon_get_values {
> +	__u32 id;
> +	__u32 pad;
> +	__u64 values_ptr;
>  };
>  
>  #if defined(__cplusplus)
> diff --git a/include/drm-uapi/vmwgfx_drm.h b/include/drm-uapi/vmwgfx_drm.h
> index 02e91750..9078775f 100644
> --- a/include/drm-uapi/vmwgfx_drm.h
> +++ b/include/drm-uapi/vmwgfx_drm.h
> @@ -72,6 +72,9 @@ extern "C" {
>  #define DRM_VMW_GB_SURFACE_CREATE_EXT   27
>  #define DRM_VMW_GB_SURFACE_REF_EXT      28
>  #define DRM_VMW_MSG                     29
> +#define DRM_VMW_MKSSTAT_RESET           30
> +#define DRM_VMW_MKSSTAT_ADD             31
> +#define DRM_VMW_MKSSTAT_REMOVE          32
>  
>  /*************************************************************************/
>  /**
> @@ -1236,6 +1239,44 @@ struct drm_vmw_msg_arg {
>  	__u32 receive_len;
>  };
>  
> +/**
> + * struct drm_vmw_mksstat_add_arg
> + *
> + * @stat: Pointer to user-space stat-counters array, page-aligned.
> + * @info: Pointer to user-space counter-infos array, page-aligned.
> + * @strs: Pointer to user-space stat strings, page-aligned.
> + * @stat_len: Length in bytes of stat-counters array.
> + * @info_len: Length in bytes of counter-infos array.
> + * @strs_len: Length in bytes of the stat strings, terminators included.
> + * @description: Pointer to instance descriptor string; will be truncated
> + *               to MKS_GUEST_STAT_INSTANCE_DESC_LENGTH chars.
> + * @id: Output identifier of the produced record; -1 if error.
> + *
> + * Argument to the DRM_VMW_MKSSTAT_ADD ioctl.
> + */
> +struct drm_vmw_mksstat_add_arg {
> +	__u64 stat;
> +	__u64 info;
> +	__u64 strs;
> +	__u64 stat_len;
> +	__u64 info_len;
> +	__u64 strs_len;
> +	__u64 description;
> +	__u64 id;
> +};
> +
> +/**
> + * struct drm_vmw_mksstat_remove_arg
> + *
> + * @id: Identifier of the record being disposed, originally obtained through
> + *      DRM_VMW_MKSSTAT_ADD ioctl.
> + *
> + * Argument to the DRM_VMW_MKSSTAT_REMOVE ioctl.
> + */
> +struct drm_vmw_mksstat_remove_arg {
> +	__u64 id;
> +};
> +
>  #if defined(__cplusplus)
>  }
>  #endif
> -- 
> 2.31.1
> 

Re: [igt-dev] [PATCH i-g-t 4/8] tests/gem_userptr_blits: Remove LOCAL_

[Petri Latvala]

On Wed, Oct 06, 2021 at 12:14:40PM -0400, Rodrigo Vivi wrote:
> These UAPIs are upstreamed now.
> 
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Petri Latvala <petri.latvala@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Petri Latvala <petri.latvala@intel.com>

> ---
>  tests/i915/gem_userptr_blits.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
> index 756bd6e4..0d084674 100644
> --- a/tests/i915/gem_userptr_blits.c
> +++ b/tests/i915/gem_userptr_blits.c
> @@ -2151,16 +2151,13 @@ static int userfaultfd(int flags)
>  	return syscall(SYS_userfaultfd, flags);
>  }
>  
> -#define LOCAL_I915_PARAM_HAS_USERPTR_PROBE 56
> -#define LOCAL_I915_USERPTR_PROBE 0x2
> -
>  static bool has_userptr_probe(int fd)
>  {
>  	struct drm_i915_getparam gp;
>  	int value = 0;
>  
>  	memset(&gp, 0, sizeof(gp));
> -	gp.param = LOCAL_I915_PARAM_HAS_USERPTR_PROBE;
> +	gp.param = I915_PARAM_HAS_USERPTR_PROBE;
>  	gp.value = &value;
>  
>  	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp));
> @@ -2222,7 +2219,7 @@ static void test_probe(int fd)
>  		}
>  
>  		igt_assert_eq(__gem_userptr(fd, ptr + PAGE_SIZE, 3*PAGE_SIZE,
> -					    0, LOCAL_I915_USERPTR_PROBE, &handle),
> +					    0, I915_USERPTR_PROBE, &handle),
>  			      expected);
>  
>  		munmap(ptr, N_PAGES * PAGE_SIZE);
> -- 
> 2.31.1
> 

Re: [igt-dev] [PATCH i-g-t 8/8] README.md: Accept the i915_drm.h standalone update.

[Rodrigo Vivi]

On Thu, Oct 07, 2021 at 11:27:22AM +0300, Petri Latvala wrote:
> On Wed, Oct 06, 2021 at 12:14:44PM -0400, Rodrigo Vivi wrote:
> > Looking to our git log we can see that the most common case
> > is the update of the single i915_drm.h file.
> > 
> > There are some advantages of doing this standalone update:
> > 
> > 1. Make reviews easier without the noise of other headers.
> > 2. Avoid the developer to have to touch other areas that are
> >    not immediately related to targeted work.
> > 
> > Cc: Petri Latvala <petri.latvala@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> Reviewed-by: Petri Latvala <petri.latvala@intel.com>

Thank you. Pushed the remaining patches just now.

> 
> 
> > ---
> >  README.md | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> > 
> > diff --git a/README.md b/README.md
> > index 62bef46d..66f2bc0f 100644
> > --- a/README.md
> > +++ b/README.md
> > @@ -159,6 +159,20 @@ These should be updated all together by:
> >  Then, commit with a note of which exact commit from airlied's branch
> >  was used to generate them.
> >  
> > +### `include/drm-uapi/i915_drm.h`
> > +
> > +Imported i915_drm.h uapi headers from airlied's drm-next branch.
> > +
> > +In some cases updating a single uapi file is needed as our history
> > +shows. So in this case, it should be done by:
> > +
> > +    # From the kernel dir with a drm/drm-next commit checked out:
> > +    $ make INSTALL_HDR_PATH=<dest-dir> headers_install
> > +    $ cp <dest-dir>/include/drm/i915_drm.h <igt-dir>/include/drm-uapi/
> > +
> > +Then, commit with a note of which exact commit from airlied's branch
> > +was used to generate it.
> > +
> >  ### `include/linux-uapi/sync_file.h`
> >  
> >  Imported non-DRM uapi headers from airlied's drm-next branch.
> > -- 
> > 2.31.1
> >