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* [PATCH] drm/i915: Stop using I915_TILING_* in client blit selftest
@ 2021-10-01  0:58 ` Matt Roper
  0 siblings, 0 replies; 8+ messages in thread
From: Matt Roper @ 2021-10-01  0:58 UTC (permalink / raw)
  To: intel-gfx
  Cc: dri-devel, Matt Roper, Ville Syrjälä, Stanislav Lisovskiy

The I915_TILING_* definitions in the uapi header are intended solely for
tiling modes that are visible to the old de-tiling fence ioctls.  Since
modern hardware does not support de-tiling fences, we should not add new
definitions for new tiling types going forward.  However we do want the
client blit selftest to eventually cover other new tiling modes (such as
Tile4), so switch it to using its own enum of tiling modes.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../i915/gem/selftests/i915_gem_client_blt.c  | 29 ++++++++++++-------
 include/uapi/drm/i915_drm.h                   |  6 ++++
 2 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index ecbcbb86ae1e..8402ed925a69 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -17,13 +17,20 @@
 #include "huge_gem_object.h"
 #include "mock_context.h"
 
+enum client_tiling {
+	CLIENT_TILING_LINEAR,
+	CLIENT_TILING_X,
+	CLIENT_TILING_Y,
+	CLIENT_NUM_TILING_TYPES
+};
+
 #define WIDTH 512
 #define HEIGHT 32
 
 struct blit_buffer {
 	struct i915_vma *vma;
 	u32 start_val;
-	u32 tiling;
+	enum client_tiling tiling;
 };
 
 struct tiled_blits {
@@ -53,9 +60,9 @@ static int prepare_blit(const struct tiled_blits *t,
 	*cs++ = MI_LOAD_REGISTER_IMM(1);
 	*cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
 	cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
-	if (src->tiling == I915_TILING_Y)
+	if (src->tiling == CLIENT_TILING_Y)
 		cmd |= BCS_SRC_Y;
-	if (dst->tiling == I915_TILING_Y)
+	if (dst->tiling == CLIENT_TILING_Y)
 		cmd |= BCS_DST_Y;
 	*cs++ = cmd;
 
@@ -172,7 +179,7 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
 
 		t->buffers[i].vma = vma;
 		t->buffers[i].tiling =
-			i915_prandom_u32_max_state(I915_TILING_Y + 1, prng);
+			i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
 	}
 
 	return 0;
@@ -197,17 +204,17 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
 static u64 tiled_offset(const struct intel_gt *gt,
 			u64 v,
 			unsigned int stride,
-			unsigned int tiling)
+			enum client_tiling tiling)
 {
 	unsigned int swizzle;
 	u64 x, y;
 
-	if (tiling == I915_TILING_NONE)
+	if (tiling == CLIENT_TILING_LINEAR)
 		return v;
 
 	y = div64_u64_rem(v, stride, &x);
 
-	if (tiling == I915_TILING_X) {
+	if (tiling == CLIENT_TILING_X) {
 		v = div64_u64_rem(y, 8, &y) * stride * 8;
 		v += y * 512;
 		v += div64_u64_rem(x, 512, &x) << 12;
@@ -244,12 +251,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
 	return v;
 }
 
-static const char *repr_tiling(int tiling)
+static const char *repr_tiling(enum client_tiling tiling)
 {
 	switch (tiling) {
-	case I915_TILING_NONE: return "linear";
-	case I915_TILING_X: return "X";
-	case I915_TILING_Y: return "Y";
+	case CLIENT_TILING_LINEAR: return "linear";
+	case CLIENT_TILING_X: return "X";
+	case CLIENT_TILING_Y: return "Y";
 	default: return "unknown";
 	}
 }
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index bde5860b3686..00311a63068e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1522,6 +1522,12 @@ struct drm_i915_gem_caching {
 #define I915_TILING_NONE	0
 #define I915_TILING_X		1
 #define I915_TILING_Y		2
+/*
+ * Do not add new tiling types here.  The I915_TILING_* values are for
+ * de-tiling fence registers that no longer exist on modern platforms.  Although
+ * the hardware may support new types of tiling in general (e.g., Tile4), we
+ * do not need to add them to the uapi that is specific to now-defunct ioctls.
+ */
 #define I915_TILING_LAST	I915_TILING_Y
 
 #define I915_BIT_6_SWIZZLE_NONE		0
-- 
2.33.0


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [Intel-gfx] [PATCH] drm/i915: Stop using I915_TILING_* in client blit selftest
@ 2021-10-01  0:58 ` Matt Roper
  0 siblings, 0 replies; 8+ messages in thread
From: Matt Roper @ 2021-10-01  0:58 UTC (permalink / raw)
  To: intel-gfx
  Cc: dri-devel, Matt Roper, Ville Syrjälä, Stanislav Lisovskiy

The I915_TILING_* definitions in the uapi header are intended solely for
tiling modes that are visible to the old de-tiling fence ioctls.  Since
modern hardware does not support de-tiling fences, we should not add new
definitions for new tiling types going forward.  However we do want the
client blit selftest to eventually cover other new tiling modes (such as
Tile4), so switch it to using its own enum of tiling modes.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../i915/gem/selftests/i915_gem_client_blt.c  | 29 ++++++++++++-------
 include/uapi/drm/i915_drm.h                   |  6 ++++
 2 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index ecbcbb86ae1e..8402ed925a69 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -17,13 +17,20 @@
 #include "huge_gem_object.h"
 #include "mock_context.h"
 
+enum client_tiling {
+	CLIENT_TILING_LINEAR,
+	CLIENT_TILING_X,
+	CLIENT_TILING_Y,
+	CLIENT_NUM_TILING_TYPES
+};
+
 #define WIDTH 512
 #define HEIGHT 32
 
 struct blit_buffer {
 	struct i915_vma *vma;
 	u32 start_val;
-	u32 tiling;
+	enum client_tiling tiling;
 };
 
 struct tiled_blits {
@@ -53,9 +60,9 @@ static int prepare_blit(const struct tiled_blits *t,
 	*cs++ = MI_LOAD_REGISTER_IMM(1);
 	*cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
 	cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
-	if (src->tiling == I915_TILING_Y)
+	if (src->tiling == CLIENT_TILING_Y)
 		cmd |= BCS_SRC_Y;
-	if (dst->tiling == I915_TILING_Y)
+	if (dst->tiling == CLIENT_TILING_Y)
 		cmd |= BCS_DST_Y;
 	*cs++ = cmd;
 
@@ -172,7 +179,7 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
 
 		t->buffers[i].vma = vma;
 		t->buffers[i].tiling =
-			i915_prandom_u32_max_state(I915_TILING_Y + 1, prng);
+			i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
 	}
 
 	return 0;
@@ -197,17 +204,17 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
 static u64 tiled_offset(const struct intel_gt *gt,
 			u64 v,
 			unsigned int stride,
-			unsigned int tiling)
+			enum client_tiling tiling)
 {
 	unsigned int swizzle;
 	u64 x, y;
 
-	if (tiling == I915_TILING_NONE)
+	if (tiling == CLIENT_TILING_LINEAR)
 		return v;
 
 	y = div64_u64_rem(v, stride, &x);
 
-	if (tiling == I915_TILING_X) {
+	if (tiling == CLIENT_TILING_X) {
 		v = div64_u64_rem(y, 8, &y) * stride * 8;
 		v += y * 512;
 		v += div64_u64_rem(x, 512, &x) << 12;
@@ -244,12 +251,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
 	return v;
 }
 
-static const char *repr_tiling(int tiling)
+static const char *repr_tiling(enum client_tiling tiling)
 {
 	switch (tiling) {
-	case I915_TILING_NONE: return "linear";
-	case I915_TILING_X: return "X";
-	case I915_TILING_Y: return "Y";
+	case CLIENT_TILING_LINEAR: return "linear";
+	case CLIENT_TILING_X: return "X";
+	case CLIENT_TILING_Y: return "Y";
 	default: return "unknown";
 	}
 }
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index bde5860b3686..00311a63068e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1522,6 +1522,12 @@ struct drm_i915_gem_caching {
 #define I915_TILING_NONE	0
 #define I915_TILING_X		1
 #define I915_TILING_Y		2
+/*
+ * Do not add new tiling types here.  The I915_TILING_* values are for
+ * de-tiling fence registers that no longer exist on modern platforms.  Although
+ * the hardware may support new types of tiling in general (e.g., Tile4), we
+ * do not need to add them to the uapi that is specific to now-defunct ioctls.
+ */
 #define I915_TILING_LAST	I915_TILING_Y
 
 #define I915_BIT_6_SWIZZLE_NONE		0
-- 
2.33.0


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Stop using I915_TILING_* in client blit selftest
  2021-10-01  0:58 ` [Intel-gfx] " Matt Roper
  (?)
@ 2021-10-01  1:48 ` Patchwork
  -1 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2021-10-01  1:48 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 4088 bytes --]

== Series Details ==

Series: drm/i915: Stop using I915_TILING_* in client blit selftest
URL   : https://patchwork.freedesktop.org/series/95308/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10670 -> Patchwork_21212
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/index.html

Known issues
------------

  Here are the changes found in Patchwork_21212 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@query-info:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][1] ([fdo#109315])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/fi-tgl-1115g4/igt@amdgpu/amd_basic@query-info.html

  * igt@amdgpu/amd_cs_nop@nop-gfx0:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][2] ([fdo#109315] / [i915#2575]) +16 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/fi-tgl-1115g4/igt@amdgpu/amd_cs_nop@nop-gfx0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html

  * igt@i915_pm_backlight@basic-brightness:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][4] ([i915#1155])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][5] ([fdo#111827]) +8 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][6] ([i915#4103]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][7] ([fdo#109285])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_psr@primary_mmap_gtt:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][8] ([i915#1072]) +3 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html

  * igt@prime_vgem@basic-userptr:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][9] ([i915#3301])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html

  
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103


Participating hosts (32 -> 28)
------------------------------

  Additional (1): fi-tgl-1115g4 
  Missing    (5): bat-dg1-6 fi-bsw-cyan bat-adlp-4 bat-jsl-2 bat-jsl-1 


Build changes
-------------

  * Linux: CI_DRM_10670 -> Patchwork_21212

  CI-20190529: 20190529
  CI_DRM_10670: 3d3b1ccf805891e2b05ba21cb98790aa0cfa48a8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6228: 22643ce4014a0b2dc52ce7916b2f657e2a7757c3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21212: 7d31c572692bf78a138df127d58b67052c16a859 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7d31c572692b drm/i915: Stop using I915_TILING_* in client blit selftest

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/index.html

[-- Attachment #2: Type: text/html, Size: 4979 bytes --]

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Stop using I915_TILING_* in client blit selftest
  2021-10-01  0:58 ` [Intel-gfx] " Matt Roper
  (?)
  (?)
@ 2021-10-01  7:16 ` Patchwork
  -1 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2021-10-01  7:16 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 30281 bytes --]

== Series Details ==

Series: drm/i915: Stop using I915_TILING_* in client blit selftest
URL   : https://patchwork.freedesktop.org/series/95308/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10670_full -> Patchwork_21212_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_21212_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-apl:          NOTRUN -> [DMESG-WARN][1] ([i915#3002])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl7/igt@gem_create@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
    - shard-apl:          [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-apl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl8/igt@gem_ctx_isolation@preservation-s3@bcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
    - shard-kbl:          [PASS][4] -> [FAIL][5] ([i915#2842])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-kbl7/igt@gem_exec_fair@basic-none@rcs0.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-kbl3/igt@gem_exec_fair@basic-none@rcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-apl:          [PASS][6] -> [FAIL][7] ([i915#2842] / [i915#3468])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl8/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
    - shard-glk:          [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [PASS][12] -> [SKIP][13] ([fdo#109271])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_params@no-blt:
    - shard-tglb:         NOTRUN -> [SKIP][14] ([fdo#109283]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@gem_exec_params@no-blt.html

  * igt@gem_exec_params@secure-non-master:
    - shard-tglb:         NOTRUN -> [SKIP][15] ([fdo#112283])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb8/igt@gem_exec_params@secure-non-master.html

  * igt@gem_pread@exhaustion:
    - shard-apl:          NOTRUN -> [WARN][16] ([i915#2658]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl2/igt@gem_pread@exhaustion.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-apl:          NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3323])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-tglb:         NOTRUN -> [SKIP][18] ([i915#3323])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-apl:          NOTRUN -> [FAIL][19] ([i915#3318])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl2/igt@gem_userptr_blits@vma-merge.html

  * igt@gen7_exec_parse@load-register-reg:
    - shard-tglb:         NOTRUN -> [SKIP][20] ([fdo#109289])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb8/igt@gen7_exec_parse@load-register-reg.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][21] -> [FAIL][22] ([i915#454])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-iclb8/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-tglb:         NOTRUN -> [WARN][23] ([i915#2681])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb8/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - shard-apl:          NOTRUN -> [SKIP][24] ([fdo#109271]) +268 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl2/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([i915#2411] / [i915#456] / [i915#750])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-tglb2/igt@i915_pm_rpm@system-suspend-execbuf.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][27] ([fdo#111614])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb8/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3777])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-tglb:         NOTRUN -> [SKIP][29] ([fdo#111615]) +2 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-skl:          NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3777])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl5/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886]) +11 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl2/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) +2 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl5/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-kbl2/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-random-ccs-data-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([i915#3689]) +5 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb8/igt@kms_ccs@pipe-c-random-ccs-data-yf_tiled_ccs.html

  * igt@kms_chamelium@hdmi-audio-edid:
    - shard-tglb:         NOTRUN -> [SKIP][35] ([fdo#109284] / [fdo#111827]) +5 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@kms_chamelium@hdmi-audio-edid.html

  * igt@kms_chamelium@vga-frame-dump:
    - shard-skl:          NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl5/igt@kms_chamelium@vga-frame-dump.html

  * igt@kms_chamelium@vga-hpd:
    - shard-apl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +21 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl6/igt@kms_chamelium@vga-hpd.html

  * igt@kms_color@pipe-a-ctm-0-25:
    - shard-skl:          [PASS][38] -> [DMESG-WARN][39] ([i915#1982]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl10/igt@kms_color@pipe-a-ctm-0-25.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl7/igt@kms_color@pipe-a-ctm-0-25.html

  * igt@kms_color_chamelium@pipe-c-ctm-max:
    - shard-kbl:          NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-kbl2/igt@kms_color_chamelium@pipe-c-ctm-max.html

  * igt@kms_concurrent@pipe-c:
    - shard-tglb:         NOTRUN -> [FAIL][41] ([i915#1385])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@kms_concurrent@pipe-c.html

  * igt@kms_content_protection@type1:
    - shard-tglb:         NOTRUN -> [SKIP][42] ([fdo#111828])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
    - shard-apl:          NOTRUN -> [FAIL][43] ([i915#3444])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x32-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][44] ([i915#3319]) +2 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-32x32-offscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-max-size-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][45] ([i915#3359]) +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-max-size-onscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-512x512-random:
    - shard-tglb:         NOTRUN -> [SKIP][46] ([fdo#109279] / [i915#3359]) +1 similar issue
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-512x512-random.html
    - shard-skl:          NOTRUN -> [SKIP][47] ([fdo#109271]) +34 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-512x512-random.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [PASS][48] -> [FAIL][49] ([i915#2346])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [PASS][50] -> [FAIL][51] ([i915#2346] / [i915#533])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][52] -> [FAIL][53] ([i915#79])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-skl:          [PASS][54] -> [FAIL][55] ([i915#79]) +2 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [PASS][56] -> [DMESG-WARN][57] ([i915#180]) +8 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-skl:          [PASS][58] -> [FAIL][59] ([i915#2122])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
    - shard-skl:          NOTRUN -> [FAIL][60] ([i915#2122])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl5/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
    - shard-iclb:         [PASS][61] -> [SKIP][62] ([i915#3701])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt:
    - shard-tglb:         NOTRUN -> [SKIP][63] ([fdo#111825]) +18 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][64] -> [FAIL][65] ([i915#1188]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-tglb:         NOTRUN -> [SKIP][66] ([i915#1187])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#533]) +5 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [PASS][68] -> [INCOMPLETE][69] ([i915#155] / [i915#794])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-apl:          NOTRUN -> [DMESG-WARN][70] ([i915#180])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-apl:          NOTRUN -> [FAIL][71] ([fdo#108145] / [i915#265]) +2 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][72] -> [FAIL][73] ([fdo#108145] / [i915#265])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][74] ([i915#265])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-skl:          NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
    - shard-tglb:         NOTRUN -> [SKIP][76] ([fdo#112054])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2733])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@cursor-plane-update-sf:
    - shard-tglb:         NOTRUN -> [SKIP][78] ([i915#2920]) +1 similar issue
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@kms_psr2_sf@cursor-plane-update-sf.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
    - shard-kbl:          NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#658]) +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-kbl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html

  * igt@kms_psr2_su@page_flip:
    - shard-apl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658]) +6 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl3/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_dpms:
    - shard-tglb:         NOTRUN -> [FAIL][81] ([i915#132] / [i915#3467])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb8/igt@kms_psr@psr2_dpms.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][82] -> [SKIP][83] ([fdo#109441]) +4 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_psr@suspend:
    - shard-skl:          [PASS][84] -> [INCOMPLETE][85] ([i915#198])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl8/igt@kms_psr@suspend.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl1/igt@kms_psr@suspend.html

  * igt@kms_vblank@pipe-d-query-forked-busy:
    - shard-kbl:          NOTRUN -> [SKIP][86] ([fdo#109271]) +43 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-kbl2/igt@kms_vblank@pipe-d-query-forked-busy.html

  * igt@kms_writeback@writeback-check-output:
    - shard-kbl:          NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2437])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-kbl2/igt@kms_writeback@writeback-check-output.html

  * igt@nouveau_crc@pipe-a-ctx-flip-detection:
    - shard-tglb:         NOTRUN -> [SKIP][88] ([i915#2530]) +1 similar issue
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb8/igt@nouveau_crc@pipe-a-ctx-flip-detection.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [PASS][89] -> [FAIL][90] ([i915#1542])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl4/igt@perf@polling-parameterized.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl1/igt@perf@polling-parameterized.html
    - shard-tglb:         [PASS][91] -> [FAIL][92] ([i915#1542])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-tglb3/igt@perf@polling-parameterized.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb2/igt@perf@polling-parameterized.html

  * igt@prime_nv_test@i915_blt_fill_nv_read:
    - shard-tglb:         NOTRUN -> [SKIP][93] ([fdo#109291]) +2 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb8/igt@prime_nv_test@i915_blt_fill_nv_read.html

  * igt@sysfs_clients@fair-3:
    - shard-tglb:         NOTRUN -> [SKIP][94] ([i915#2994])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb7/igt@sysfs_clients@fair-3.html

  * igt@sysfs_clients@recycle-many:
    - shard-apl:          NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2994]) +5 similar issues
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl3/igt@sysfs_clients@recycle-many.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [FAIL][96] ([i915#2846]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-glk9/igt@gem_exec_fair@basic-deadline.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-glk7/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [FAIL][98] ([i915#2842]) -> [PASS][99] +2 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          [FAIL][100] ([i915#2842]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-glk3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-glk6/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-iclb:         [FAIL][102] ([i915#2842]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-iclb2/igt@gem_exec_fair@basic-pace@rcs0.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-iclb7/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-kbl:          [FAIL][104] ([i915#2842]) -> [PASS][105] +1 similar issue
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-kbl:          [DMESG-WARN][106] ([i915#180]) -> [PASS][107] +1 similar issue
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-kbl1/igt@gem_exec_suspend@basic-s3.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-kbl2/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][108] ([i915#2190]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-tglb7/igt@gem_huc_copy@huc-copy.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb2/igt@gem_huc_copy@huc-copy.html

  * igt@gem_workarounds@suspend-resume:
    - shard-tglb:         [INCOMPLETE][110] ([i915#456]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-tglb7/igt@gem_workarounds@suspend-resume.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-tglb8/igt@gem_workarounds@suspend-resume.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-apl:          [DMESG-WARN][112] ([i915#180]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-apl6/igt@gem_workarounds@suspend-resume-fd.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl2/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-skl:          [DMESG-WARN][114] ([i915#1436] / [i915#716]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl6/igt@gen9_exec_parse@allowed-single.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl6/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_suspend@debugfs-reader:
    - shard-skl:          [INCOMPLETE][116] ([i915#198] / [i915#4173]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl2/igt@i915_suspend@debugfs-reader.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl5/igt@i915_suspend@debugfs-reader.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-0:
    - shard-glk:          [DMESG-WARN][118] ([i915#118] / [i915#95]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-glk4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-glk4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html

  * igt@kms_color@pipe-b-ctm-0-5:
    - shard-skl:          [DMESG-WARN][120] ([i915#1982]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl3/igt@kms_color@pipe-b-ctm-0-5.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl3/igt@kms_color@pipe-b-ctm-0-5.html

  * igt@kms_flip@plain-flip-fb-recreate@b-edp1:
    - shard-skl:          [FAIL][122] ([i915#2122]) -> [PASS][123] +1 similar issue
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [FAIL][124] ([i915#1188]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][126] ([fdo#108145] / [i915#265]) -> [PASS][127] +1 similar issue
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][128] ([fdo#109441]) -> [PASS][129] +3 similar issues
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          [DMESG-WARN][130] ([i915#180] / [i915#295]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@perf@polling-parameterized:
    - shard-glk:          [FAIL][132] ([i915#1542]) -> [PASS][133]
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-glk4/igt@perf@polling-parameterized.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-glk1/igt@perf@polling-parameterized.html

  * igt@perf@polling-small-buf:
    - shard-skl:          [FAIL][134] ([i915#1722]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl6/igt@perf@polling-small-buf.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl6/igt@perf@polling-small-buf.html

  * igt@sysfs_heartbeat_interval@precise@vecs0:
    - shard-apl:          [FAIL][136] ([i915#1755]) -> [PASS][137]
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-apl8/igt@sysfs_heartbeat_interval@precise@vecs0.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-apl1/igt@sysfs_heartbeat_interval@precise@vecs0.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][138] ([i915#2684]) -> [WARN][139] ([i915#1804] / [i915#2684])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-iclb3/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][140] ([i915#1804] / [i915#2684]) -> [WARN][141] ([i915#2684])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_big_fb@linear-32bpp-rotate-0:
    - shard-glk:          [DMESG-WARN][142] ([i915#118] / [i915#95]) -> [DMESG-WARN][143] ([i915#118] / [i915#1982] / [i915#95])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-0.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-glk9/igt@kms_big_fb@linear-32bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-skl:          [FAIL][144] ([i915#3743]) -> [FAIL][145] ([i915#3722])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
    - shard-iclb:         [SKIP][146] ([i915#2920]) -

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21212/index.html

[-- Attachment #2: Type: text/html, Size: 33528 bytes --]

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH] drm/i915: Stop using I915_TILING_* in client blit selftest
  2021-10-01  0:58 ` [Intel-gfx] " Matt Roper
@ 2021-10-08  9:49   ` Ville Syrjälä
  -1 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjälä @ 2021-10-08  9:49 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx, dri-devel, Stanislav Lisovskiy

On Thu, Sep 30, 2021 at 05:58:16PM -0700, Matt Roper wrote:
> The I915_TILING_* definitions in the uapi header are intended solely for
> tiling modes that are visible to the old de-tiling fence ioctls.  Since
> modern hardware does not support de-tiling fences, we should not add new
> definitions for new tiling types going forward.  However we do want the
> client blit selftest to eventually cover other new tiling modes (such as
> Tile4), so switch it to using its own enum of tiling modes.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../i915/gem/selftests/i915_gem_client_blt.c  | 29 ++++++++++++-------
>  include/uapi/drm/i915_drm.h                   |  6 ++++
>  2 files changed, 24 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> index ecbcbb86ae1e..8402ed925a69 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> @@ -17,13 +17,20 @@
>  #include "huge_gem_object.h"
>  #include "mock_context.h"
>  
> +enum client_tiling {
> +	CLIENT_TILING_LINEAR,
> +	CLIENT_TILING_X,
> +	CLIENT_TILING_Y,
> +	CLIENT_NUM_TILING_TYPES
> +};
> +
>  #define WIDTH 512
>  #define HEIGHT 32
>  
>  struct blit_buffer {
>  	struct i915_vma *vma;
>  	u32 start_val;
> -	u32 tiling;
> +	enum client_tiling tiling;
>  };
>  
>  struct tiled_blits {
> @@ -53,9 +60,9 @@ static int prepare_blit(const struct tiled_blits *t,
>  	*cs++ = MI_LOAD_REGISTER_IMM(1);
>  	*cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
>  	cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
> -	if (src->tiling == I915_TILING_Y)
> +	if (src->tiling == CLIENT_TILING_Y)
>  		cmd |= BCS_SRC_Y;
> -	if (dst->tiling == I915_TILING_Y)
> +	if (dst->tiling == CLIENT_TILING_Y)
>  		cmd |= BCS_DST_Y;
>  	*cs++ = cmd;
>  
> @@ -172,7 +179,7 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
>  
>  		t->buffers[i].vma = vma;
>  		t->buffers[i].tiling =
> -			i915_prandom_u32_max_state(I915_TILING_Y + 1, prng);
> +			i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
>  	}
>  
>  	return 0;
> @@ -197,17 +204,17 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
>  static u64 tiled_offset(const struct intel_gt *gt,
>  			u64 v,
>  			unsigned int stride,
> -			unsigned int tiling)
> +			enum client_tiling tiling)
>  {
>  	unsigned int swizzle;
>  	u64 x, y;
>  
> -	if (tiling == I915_TILING_NONE)
> +	if (tiling == CLIENT_TILING_LINEAR)
>  		return v;
>  
>  	y = div64_u64_rem(v, stride, &x);
>  
> -	if (tiling == I915_TILING_X) {
> +	if (tiling == CLIENT_TILING_X) {
>  		v = div64_u64_rem(y, 8, &y) * stride * 8;
>  		v += y * 512;
>  		v += div64_u64_rem(x, 512, &x) << 12;
> @@ -244,12 +251,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
>  	return v;
>  }
>  
> -static const char *repr_tiling(int tiling)
> +static const char *repr_tiling(enum client_tiling tiling)
>  {
>  	switch (tiling) {
> -	case I915_TILING_NONE: return "linear";
> -	case I915_TILING_X: return "X";
> -	case I915_TILING_Y: return "Y";
> +	case CLIENT_TILING_LINEAR: return "linear";
> +	case CLIENT_TILING_X: return "X";
> +	case CLIENT_TILING_Y: return "Y";
>  	default: return "unknown";
>  	}
>  }
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index bde5860b3686..00311a63068e 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1522,6 +1522,12 @@ struct drm_i915_gem_caching {
>  #define I915_TILING_NONE	0
>  #define I915_TILING_X		1
>  #define I915_TILING_Y		2
> +/*
> + * Do not add new tiling types here.  The I915_TILING_* values are for
> + * de-tiling fence registers that no longer exist on modern platforms.  Although
> + * the hardware may support new types of tiling in general (e.g., Tile4), we
> + * do not need to add them to the uapi that is specific to now-defunct ioctls.
> + */
>  #define I915_TILING_LAST	I915_TILING_Y

I think we should split this one into a separate patch to give it
some visibility. The people who care about gem uapi seem to be in
some kind of early winter hibernation and no one read this.

Apart from that
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  
>  #define I915_BIT_6_SWIZZLE_NONE		0
> -- 
> 2.33.0

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Stop using I915_TILING_* in client blit selftest
@ 2021-10-08  9:49   ` Ville Syrjälä
  0 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjälä @ 2021-10-08  9:49 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx, dri-devel, Stanislav Lisovskiy

On Thu, Sep 30, 2021 at 05:58:16PM -0700, Matt Roper wrote:
> The I915_TILING_* definitions in the uapi header are intended solely for
> tiling modes that are visible to the old de-tiling fence ioctls.  Since
> modern hardware does not support de-tiling fences, we should not add new
> definitions for new tiling types going forward.  However we do want the
> client blit selftest to eventually cover other new tiling modes (such as
> Tile4), so switch it to using its own enum of tiling modes.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../i915/gem/selftests/i915_gem_client_blt.c  | 29 ++++++++++++-------
>  include/uapi/drm/i915_drm.h                   |  6 ++++
>  2 files changed, 24 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> index ecbcbb86ae1e..8402ed925a69 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> @@ -17,13 +17,20 @@
>  #include "huge_gem_object.h"
>  #include "mock_context.h"
>  
> +enum client_tiling {
> +	CLIENT_TILING_LINEAR,
> +	CLIENT_TILING_X,
> +	CLIENT_TILING_Y,
> +	CLIENT_NUM_TILING_TYPES
> +};
> +
>  #define WIDTH 512
>  #define HEIGHT 32
>  
>  struct blit_buffer {
>  	struct i915_vma *vma;
>  	u32 start_val;
> -	u32 tiling;
> +	enum client_tiling tiling;
>  };
>  
>  struct tiled_blits {
> @@ -53,9 +60,9 @@ static int prepare_blit(const struct tiled_blits *t,
>  	*cs++ = MI_LOAD_REGISTER_IMM(1);
>  	*cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
>  	cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
> -	if (src->tiling == I915_TILING_Y)
> +	if (src->tiling == CLIENT_TILING_Y)
>  		cmd |= BCS_SRC_Y;
> -	if (dst->tiling == I915_TILING_Y)
> +	if (dst->tiling == CLIENT_TILING_Y)
>  		cmd |= BCS_DST_Y;
>  	*cs++ = cmd;
>  
> @@ -172,7 +179,7 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
>  
>  		t->buffers[i].vma = vma;
>  		t->buffers[i].tiling =
> -			i915_prandom_u32_max_state(I915_TILING_Y + 1, prng);
> +			i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
>  	}
>  
>  	return 0;
> @@ -197,17 +204,17 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
>  static u64 tiled_offset(const struct intel_gt *gt,
>  			u64 v,
>  			unsigned int stride,
> -			unsigned int tiling)
> +			enum client_tiling tiling)
>  {
>  	unsigned int swizzle;
>  	u64 x, y;
>  
> -	if (tiling == I915_TILING_NONE)
> +	if (tiling == CLIENT_TILING_LINEAR)
>  		return v;
>  
>  	y = div64_u64_rem(v, stride, &x);
>  
> -	if (tiling == I915_TILING_X) {
> +	if (tiling == CLIENT_TILING_X) {
>  		v = div64_u64_rem(y, 8, &y) * stride * 8;
>  		v += y * 512;
>  		v += div64_u64_rem(x, 512, &x) << 12;
> @@ -244,12 +251,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
>  	return v;
>  }
>  
> -static const char *repr_tiling(int tiling)
> +static const char *repr_tiling(enum client_tiling tiling)
>  {
>  	switch (tiling) {
> -	case I915_TILING_NONE: return "linear";
> -	case I915_TILING_X: return "X";
> -	case I915_TILING_Y: return "Y";
> +	case CLIENT_TILING_LINEAR: return "linear";
> +	case CLIENT_TILING_X: return "X";
> +	case CLIENT_TILING_Y: return "Y";
>  	default: return "unknown";
>  	}
>  }
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index bde5860b3686..00311a63068e 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1522,6 +1522,12 @@ struct drm_i915_gem_caching {
>  #define I915_TILING_NONE	0
>  #define I915_TILING_X		1
>  #define I915_TILING_Y		2
> +/*
> + * Do not add new tiling types here.  The I915_TILING_* values are for
> + * de-tiling fence registers that no longer exist on modern platforms.  Although
> + * the hardware may support new types of tiling in general (e.g., Tile4), we
> + * do not need to add them to the uapi that is specific to now-defunct ioctls.
> + */
>  #define I915_TILING_LAST	I915_TILING_Y

I think we should split this one into a separate patch to give it
some visibility. The people who care about gem uapi seem to be in
some kind of early winter hibernation and no one read this.

Apart from that
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  
>  #define I915_BIT_6_SWIZZLE_NONE		0
> -- 
> 2.33.0

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH] drm/i915: Stop using I915_TILING_* in client blit selftest
  2021-10-08  9:49   ` [Intel-gfx] " Ville Syrjälä
@ 2021-10-12 21:43     ` Matt Roper
  -1 siblings, 0 replies; 8+ messages in thread
From: Matt Roper @ 2021-10-12 21:43 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx, dri-devel, Stanislav Lisovskiy

On Fri, Oct 08, 2021 at 12:49:57PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 30, 2021 at 05:58:16PM -0700, Matt Roper wrote:
> > The I915_TILING_* definitions in the uapi header are intended solely for
> > tiling modes that are visible to the old de-tiling fence ioctls.  Since
> > modern hardware does not support de-tiling fences, we should not add new
> > definitions for new tiling types going forward.  However we do want the
> > client blit selftest to eventually cover other new tiling modes (such as
> > Tile4), so switch it to using its own enum of tiling modes.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  .../i915/gem/selftests/i915_gem_client_blt.c  | 29 ++++++++++++-------
> >  include/uapi/drm/i915_drm.h                   |  6 ++++
> >  2 files changed, 24 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > index ecbcbb86ae1e..8402ed925a69 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > @@ -17,13 +17,20 @@
> >  #include "huge_gem_object.h"
> >  #include "mock_context.h"
> >  
> > +enum client_tiling {
> > +	CLIENT_TILING_LINEAR,
> > +	CLIENT_TILING_X,
> > +	CLIENT_TILING_Y,
> > +	CLIENT_NUM_TILING_TYPES
> > +};
> > +
> >  #define WIDTH 512
> >  #define HEIGHT 32
> >  
> >  struct blit_buffer {
> >  	struct i915_vma *vma;
> >  	u32 start_val;
> > -	u32 tiling;
> > +	enum client_tiling tiling;
> >  };
> >  
> >  struct tiled_blits {
> > @@ -53,9 +60,9 @@ static int prepare_blit(const struct tiled_blits *t,
> >  	*cs++ = MI_LOAD_REGISTER_IMM(1);
> >  	*cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
> >  	cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
> > -	if (src->tiling == I915_TILING_Y)
> > +	if (src->tiling == CLIENT_TILING_Y)
> >  		cmd |= BCS_SRC_Y;
> > -	if (dst->tiling == I915_TILING_Y)
> > +	if (dst->tiling == CLIENT_TILING_Y)
> >  		cmd |= BCS_DST_Y;
> >  	*cs++ = cmd;
> >  
> > @@ -172,7 +179,7 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
> >  
> >  		t->buffers[i].vma = vma;
> >  		t->buffers[i].tiling =
> > -			i915_prandom_u32_max_state(I915_TILING_Y + 1, prng);
> > +			i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
> >  	}
> >  
> >  	return 0;
> > @@ -197,17 +204,17 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
> >  static u64 tiled_offset(const struct intel_gt *gt,
> >  			u64 v,
> >  			unsigned int stride,
> > -			unsigned int tiling)
> > +			enum client_tiling tiling)
> >  {
> >  	unsigned int swizzle;
> >  	u64 x, y;
> >  
> > -	if (tiling == I915_TILING_NONE)
> > +	if (tiling == CLIENT_TILING_LINEAR)
> >  		return v;
> >  
> >  	y = div64_u64_rem(v, stride, &x);
> >  
> > -	if (tiling == I915_TILING_X) {
> > +	if (tiling == CLIENT_TILING_X) {
> >  		v = div64_u64_rem(y, 8, &y) * stride * 8;
> >  		v += y * 512;
> >  		v += div64_u64_rem(x, 512, &x) << 12;
> > @@ -244,12 +251,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
> >  	return v;
> >  }
> >  
> > -static const char *repr_tiling(int tiling)
> > +static const char *repr_tiling(enum client_tiling tiling)
> >  {
> >  	switch (tiling) {
> > -	case I915_TILING_NONE: return "linear";
> > -	case I915_TILING_X: return "X";
> > -	case I915_TILING_Y: return "Y";
> > +	case CLIENT_TILING_LINEAR: return "linear";
> > +	case CLIENT_TILING_X: return "X";
> > +	case CLIENT_TILING_Y: return "Y";
> >  	default: return "unknown";
> >  	}
> >  }
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index bde5860b3686..00311a63068e 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -1522,6 +1522,12 @@ struct drm_i915_gem_caching {
> >  #define I915_TILING_NONE	0
> >  #define I915_TILING_X		1
> >  #define I915_TILING_Y		2
> > +/*
> > + * Do not add new tiling types here.  The I915_TILING_* values are for
> > + * de-tiling fence registers that no longer exist on modern platforms.  Although
> > + * the hardware may support new types of tiling in general (e.g., Tile4), we
> > + * do not need to add them to the uapi that is specific to now-defunct ioctls.
> > + */
> >  #define I915_TILING_LAST	I915_TILING_Y
> 
> I think we should split this one into a separate patch to give it
> some visibility. The people who care about gem uapi seem to be in
> some kind of early winter hibernation and no one read this.
> 
> Apart from that
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thanks.  I dropped the comment here and pushed the rest of the patch.
I'll re-send the uapi header comment separately to increase visibility.


Matt

> 
> >  
> >  #define I915_BIT_6_SWIZZLE_NONE		0
> > -- 
> > 2.33.0
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Stop using I915_TILING_* in client blit selftest
@ 2021-10-12 21:43     ` Matt Roper
  0 siblings, 0 replies; 8+ messages in thread
From: Matt Roper @ 2021-10-12 21:43 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx, dri-devel, Stanislav Lisovskiy

On Fri, Oct 08, 2021 at 12:49:57PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 30, 2021 at 05:58:16PM -0700, Matt Roper wrote:
> > The I915_TILING_* definitions in the uapi header are intended solely for
> > tiling modes that are visible to the old de-tiling fence ioctls.  Since
> > modern hardware does not support de-tiling fences, we should not add new
> > definitions for new tiling types going forward.  However we do want the
> > client blit selftest to eventually cover other new tiling modes (such as
> > Tile4), so switch it to using its own enum of tiling modes.
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  .../i915/gem/selftests/i915_gem_client_blt.c  | 29 ++++++++++++-------
> >  include/uapi/drm/i915_drm.h                   |  6 ++++
> >  2 files changed, 24 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > index ecbcbb86ae1e..8402ed925a69 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > @@ -17,13 +17,20 @@
> >  #include "huge_gem_object.h"
> >  #include "mock_context.h"
> >  
> > +enum client_tiling {
> > +	CLIENT_TILING_LINEAR,
> > +	CLIENT_TILING_X,
> > +	CLIENT_TILING_Y,
> > +	CLIENT_NUM_TILING_TYPES
> > +};
> > +
> >  #define WIDTH 512
> >  #define HEIGHT 32
> >  
> >  struct blit_buffer {
> >  	struct i915_vma *vma;
> >  	u32 start_val;
> > -	u32 tiling;
> > +	enum client_tiling tiling;
> >  };
> >  
> >  struct tiled_blits {
> > @@ -53,9 +60,9 @@ static int prepare_blit(const struct tiled_blits *t,
> >  	*cs++ = MI_LOAD_REGISTER_IMM(1);
> >  	*cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
> >  	cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
> > -	if (src->tiling == I915_TILING_Y)
> > +	if (src->tiling == CLIENT_TILING_Y)
> >  		cmd |= BCS_SRC_Y;
> > -	if (dst->tiling == I915_TILING_Y)
> > +	if (dst->tiling == CLIENT_TILING_Y)
> >  		cmd |= BCS_DST_Y;
> >  	*cs++ = cmd;
> >  
> > @@ -172,7 +179,7 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
> >  
> >  		t->buffers[i].vma = vma;
> >  		t->buffers[i].tiling =
> > -			i915_prandom_u32_max_state(I915_TILING_Y + 1, prng);
> > +			i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
> >  	}
> >  
> >  	return 0;
> > @@ -197,17 +204,17 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
> >  static u64 tiled_offset(const struct intel_gt *gt,
> >  			u64 v,
> >  			unsigned int stride,
> > -			unsigned int tiling)
> > +			enum client_tiling tiling)
> >  {
> >  	unsigned int swizzle;
> >  	u64 x, y;
> >  
> > -	if (tiling == I915_TILING_NONE)
> > +	if (tiling == CLIENT_TILING_LINEAR)
> >  		return v;
> >  
> >  	y = div64_u64_rem(v, stride, &x);
> >  
> > -	if (tiling == I915_TILING_X) {
> > +	if (tiling == CLIENT_TILING_X) {
> >  		v = div64_u64_rem(y, 8, &y) * stride * 8;
> >  		v += y * 512;
> >  		v += div64_u64_rem(x, 512, &x) << 12;
> > @@ -244,12 +251,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
> >  	return v;
> >  }
> >  
> > -static const char *repr_tiling(int tiling)
> > +static const char *repr_tiling(enum client_tiling tiling)
> >  {
> >  	switch (tiling) {
> > -	case I915_TILING_NONE: return "linear";
> > -	case I915_TILING_X: return "X";
> > -	case I915_TILING_Y: return "Y";
> > +	case CLIENT_TILING_LINEAR: return "linear";
> > +	case CLIENT_TILING_X: return "X";
> > +	case CLIENT_TILING_Y: return "Y";
> >  	default: return "unknown";
> >  	}
> >  }
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index bde5860b3686..00311a63068e 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -1522,6 +1522,12 @@ struct drm_i915_gem_caching {
> >  #define I915_TILING_NONE	0
> >  #define I915_TILING_X		1
> >  #define I915_TILING_Y		2
> > +/*
> > + * Do not add new tiling types here.  The I915_TILING_* values are for
> > + * de-tiling fence registers that no longer exist on modern platforms.  Although
> > + * the hardware may support new types of tiling in general (e.g., Tile4), we
> > + * do not need to add them to the uapi that is specific to now-defunct ioctls.
> > + */
> >  #define I915_TILING_LAST	I915_TILING_Y
> 
> I think we should split this one into a separate patch to give it
> some visibility. The people who care about gem uapi seem to be in
> some kind of early winter hibernation and no one read this.
> 
> Apart from that
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Thanks.  I dropped the comment here and pushed the rest of the patch.
I'll re-send the uapi header comment separately to increase visibility.


Matt

> 
> >  
> >  #define I915_BIT_6_SWIZZLE_NONE		0
> > -- 
> > 2.33.0
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2021-10-12 21:43 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-01  0:58 [PATCH] drm/i915: Stop using I915_TILING_* in client blit selftest Matt Roper
2021-10-01  0:58 ` [Intel-gfx] " Matt Roper
2021-10-01  1:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-10-01  7:16 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-10-08  9:49 ` [PATCH] " Ville Syrjälä
2021-10-08  9:49   ` [Intel-gfx] " Ville Syrjälä
2021-10-12 21:43   ` Matt Roper
2021-10-12 21:43     ` [Intel-gfx] " Matt Roper

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