From: "Ville Syrjälä" <ville.syrjala@linux.intel.com> To: Jani Nikula <jani.nikula@intel.com> Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: Re: [PATCH 2/3] drm/dp: reuse the 8b/10b link training delay helpers Date: Thu, 14 Oct 2021 18:43:28 +0300 [thread overview] Message-ID: <YWhQIAh5f8cUjVbc@intel.com> (raw) In-Reply-To: <20211014150059.28957-2-jani.nikula@intel.com> On Thu, Oct 14, 2021 at 06:00:58PM +0300, Jani Nikula wrote: > Reuse the 8b/10b link training delay helpers. Functionally this skips > the check for invalid values for DPCD 1.4 and later at clock recovery > delay (as it's a fixed delay and bypasses the rd_interval) but the same > value will be checked and invalid values reported at channel > equalization. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/drm_dp_helper.c | 30 ++++++++++-------------------- > 1 file changed, 10 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index f7ebf5974fa7..ada0a1ff262d 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -284,35 +284,25 @@ EXPORT_SYMBOL(drm_dp_read_channel_eq_delay); > void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > - unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > - DP_TRAINING_AUX_RD_MASK; > + u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > + DP_TRAINING_AUX_RD_MASK; > + int delay_us; > > - if (rd_interval > 4) > - drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n", > - aux->name, rd_interval); > - > - if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) > - rd_interval = 100; > + if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) > + delay_us = 100; > else > - rd_interval *= 4 * USEC_PER_MSEC; > + delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval); > > - usleep_range(rd_interval, rd_interval * 2); > + usleep_range(delay_us, delay_us * 2); > } > EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); > > static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > - unsigned long rd_interval) > + u8 rd_interval) > { > - if (rd_interval > 4) > - drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n", > - aux->name, rd_interval); > - > - if (rd_interval == 0) > - rd_interval = 400; > - else > - rd_interval *= 4 * USEC_PER_MSEC; > + int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval); > > - usleep_range(rd_interval, rd_interval * 2); > + usleep_range(delay_us, delay_us * 2); > } > > void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > -- > 2.30.2 -- Ville Syrjälä Intel
WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com> To: Jani Nikula <jani.nikula@intel.com> Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 2/3] drm/dp: reuse the 8b/10b link training delay helpers Date: Thu, 14 Oct 2021 18:43:28 +0300 [thread overview] Message-ID: <YWhQIAh5f8cUjVbc@intel.com> (raw) In-Reply-To: <20211014150059.28957-2-jani.nikula@intel.com> On Thu, Oct 14, 2021 at 06:00:58PM +0300, Jani Nikula wrote: > Reuse the 8b/10b link training delay helpers. Functionally this skips > the check for invalid values for DPCD 1.4 and later at clock recovery > delay (as it's a fixed delay and bypasses the rd_interval) but the same > value will be checked and invalid values reported at channel > equalization. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/drm_dp_helper.c | 30 ++++++++++-------------------- > 1 file changed, 10 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index f7ebf5974fa7..ada0a1ff262d 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -284,35 +284,25 @@ EXPORT_SYMBOL(drm_dp_read_channel_eq_delay); > void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > - unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > - DP_TRAINING_AUX_RD_MASK; > + u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > + DP_TRAINING_AUX_RD_MASK; > + int delay_us; > > - if (rd_interval > 4) > - drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n", > - aux->name, rd_interval); > - > - if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) > - rd_interval = 100; > + if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) > + delay_us = 100; > else > - rd_interval *= 4 * USEC_PER_MSEC; > + delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval); > > - usleep_range(rd_interval, rd_interval * 2); > + usleep_range(delay_us, delay_us * 2); > } > EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); > > static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > - unsigned long rd_interval) > + u8 rd_interval) > { > - if (rd_interval > 4) > - drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n", > - aux->name, rd_interval); > - > - if (rd_interval == 0) > - rd_interval = 400; > - else > - rd_interval *= 4 * USEC_PER_MSEC; > + int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval); > > - usleep_range(rd_interval, rd_interval * 2); > + usleep_range(delay_us, delay_us * 2); > } > > void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > -- > 2.30.2 -- Ville Syrjälä Intel
next prev parent reply other threads:[~2021-10-14 15:43 UTC|newest] Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-14 15:00 [PATCH 1/3] drm/dp: add helpers to read link training delays Jani Nikula 2021-10-14 15:00 ` [Intel-gfx] " Jani Nikula 2021-10-14 15:00 ` [PATCH 2/3] drm/dp: reuse the 8b/10b link training delay helpers Jani Nikula 2021-10-14 15:00 ` [Intel-gfx] " Jani Nikula 2021-10-14 15:43 ` Ville Syrjälä [this message] 2021-10-14 15:43 ` Ville Syrjälä 2021-10-14 15:00 ` [PATCH 3/3] drm/i915/dp: use new " Jani Nikula 2021-10-14 15:00 ` [Intel-gfx] " Jani Nikula 2021-10-19 15:38 ` Jani Nikula 2021-10-19 15:38 ` [Intel-gfx] " Jani Nikula 2021-10-14 22:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/dp: add helpers to read link training delays Patchwork 2021-10-14 23:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-10-15 4:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-10-15 15:21 ` [PATCH 1/3] " Jani Nikula 2021-10-15 15:21 ` [Intel-gfx] " Jani Nikula 2021-10-18 8:41 ` Maxime Ripard 2021-10-18 8:41 ` [Intel-gfx] " Maxime Ripard 2021-10-19 12:39 ` Jani Nikula 2021-10-19 12:39 ` [Intel-gfx] " Jani Nikula
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