[Intel-gfx] [PATCH 00/20] drm/i915: Fix up DP DFP 4:2:0 handling more

[Intel-gfx] [PATCH 00/20] drm/i915: Fix up DP DFP 4:2:0 handling more

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we're failing to respect the sink's max TMDS clock
in the DP HDMI DFP code, and exceeding them means the sink
won't show a picture [1]. So let's improve the situation by
checking those limits, and generally fixing up a bunch things
in the deep color/4:2:0 related stuff for both native HDMI
and DP HDMI DFPs.

The end result is fairly unified apporach to this stuff on
both sides of the aisle. There's probably more we could try
to abstract to share even more code. But that will need a lot
of actual thought so leave it for later.

The high level algorithm is basically now:
for_each(respect TMDS clock limits, disrespect TMDS clock limits)
	for_each(YCbCr 4:2:0 only, RGB 4:4:4, YCbCr 4:2:0 also)
		for_each(12bpc,10bpc,8bpc)
			compute_and_check_the_things
with some obvious tweaks for HDMI vs. DP specifics.

[1] https://gitlab.freedesktop.org/drm/intel/-/issues/4095

Ville Syrjälä (20):
  drm/i915/hdmi: Split intel_hdmi_bpc_possible() to source vs. sink pair
  drm/i915/hdmi: Introduce intel_hdmi_is_ycbr420()
  drm/i915/hdmi: Introduce intel_hdmi_tmds_clock()
  drm/i915/hdmi: Unify "4:2:0 also" logic between .mode_valid() and
    .compute_config()
  drm/i915/hdmi: Extract intel_hdmi_output_format()
  drm/i915/hdmi: Clean up TMDS clock limit exceeding user mode handling
  drm/i915/hdmi: Simplify intel_hdmi_mode_clock_valid()
  drm/i915/dp: Reuse intel_hdmi_tmds_clock()
  drm/i915/dp: Extract intel_dp_tmds_clock_valid()
  drm/i915/dp: Respect the sink's max TMDS clock when dealing with
    DP->HDMI DFPs
  drm/i915/dp: Extract intel_dp_has_audio()
  drm/i915/dp: s/intel_dp_hdmi_ycbcr420/intel_dp_is_ycbcr420/
  drm/i915/dp: Reorder intel_dp_compute_config() a bit
  drm/i915/dp: Pass around intel_connector rather than drm_connector
  drm/i915/dp: Make intel_dp_output_format() usable for "4:2:0 also"
    modes
  drm/i915/dp: Rework HDMI DFP TMDS clock handling
  drm/i915/dp: Add support for "4:2:0 also" modes for DP
  drm/i915/dp: Duplicate native HDMI TMDS clock limit handling for DP
    HDMI DFPs
  drm/i915/dp: Fix DFP rgb->ycbcr conversion matrix
  drm/i915/dp: Disable DFP RGB->YCbCr conversion for now

 drivers/gpu/drm/i915/display/intel_dp.c   | 339 +++++++++++++---------
 drivers/gpu/drm/i915/display/intel_hdmi.c | 220 ++++++++------
 drivers/gpu/drm/i915/display/intel_hdmi.h |   5 +-
 3 files changed, 342 insertions(+), 222 deletions(-)

-- 
2.32.0

[Intel-gfx] [PATCH 01/20] drm/i915/hdmi: Split intel_hdmi_bpc_possible() to source vs. sink pair

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_hdmi_bpc_possible() is used by the DP code as well where
the native HDMI source limits do not apply. So let's split this
into a pair of functions: one for the source vs. one for the sink.

This is basically reverting some of commit 41828125acd6 ("drm/i915:
Move platform checks into intel_hdmi_bpc_possible()") slightly,
but in a nicer form. I guess I forgot at the time that the DP side
uses this too.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 38 ++++++++++++++++-------
 1 file changed, 26 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index d2e61f6c6e08..d7196494cc27 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1873,18 +1873,29 @@ static int intel_hdmi_port_clock(int clock, int bpc)
 	return clock * bpc / 8;
 }
 
-static bool intel_hdmi_bpc_possible(struct drm_connector *connector,
-				    int bpc, bool has_hdmi_sink, bool ycbcr420_output)
+static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
+{
+	switch (bpc) {
+	case 12:
+		return !HAS_GMCH(i915);
+	case 10:
+		return DISPLAY_VER(i915) >= 11;
+	case 8:
+		return true;
+	default:
+		MISSING_CASE(bpc);
+		return false;
+	}
+}
+
+static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
+					 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
 {
-	struct drm_i915_private *i915 = to_i915(connector->dev);
 	const struct drm_display_info *info = &connector->display_info;
 	const struct drm_hdmi_info *hdmi = &info->hdmi;
 
 	switch (bpc) {
 	case 12:
-		if (HAS_GMCH(i915))
-			return false;
-
 		if (!has_hdmi_sink)
 			return false;
 
@@ -1893,9 +1904,6 @@ static bool intel_hdmi_bpc_possible(struct drm_connector *connector,
 		else
 			return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36;
 	case 10:
-		if (DISPLAY_VER(i915) < 11)
-			return false;
-
 		if (!has_hdmi_sink)
 			return false;
 
@@ -1915,6 +1923,7 @@ static enum drm_mode_status
 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
 			    bool has_hdmi_sink, bool ycbcr420_output)
 {
+	struct drm_i915_private *i915 = to_i915(connector->dev);
 	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
 	enum drm_mode_status status;
 
@@ -1927,13 +1936,15 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
 
 	/* if we can't do 8bpc we may still be able to do 12bpc */
 	if (status != MODE_OK &&
-	    intel_hdmi_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output))
+	    intel_hdmi_source_bpc_possible(i915, 12) &&
+	    intel_hdmi_sink_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output))
 		status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12),
 					       true, has_hdmi_sink);
 
 	/* if we can't do 8,12bpc we may still be able to do 10bpc */
 	if (status != MODE_OK &&
-	    intel_hdmi_bpc_possible(connector, 10, has_hdmi_sink, ycbcr420_output))
+	    intel_hdmi_source_bpc_possible(i915, 10) &&
+	    intel_hdmi_sink_bpc_possible(connector, 10, has_hdmi_sink, ycbcr420_output))
 		status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10),
 					       true, has_hdmi_sink);
 
@@ -1999,7 +2010,7 @@ bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
 		if (connector_state->crtc != crtc_state->uapi.crtc)
 			continue;
 
-		if (!intel_hdmi_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
+		if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
 			return false;
 	}
 
@@ -2014,6 +2025,9 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
 
+	if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
+		return false;
+
 	/*
 	 * HDMI deep color affects the clocks, so it's only possible
 	 * when not cloning with other encoder types.
-- 
2.32.0

[Intel-gfx] [PATCH 02/20] drm/i915/hdmi: Introduce intel_hdmi_is_ycbr420()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Introduce a small helper which given the crtc state tells us
whether we're output YCbCr 4:2:0 or not. For native HDMI this
is rather simple as we just look at the output_format. But I
think the helper is beneficial since with DP HDMI DFPs we're
going to need a more complex variant, and I want to unify the
DP and HDMI sides of that as much as possible.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index d7196494cc27..37ce8a621973 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1799,6 +1799,11 @@ static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
 		READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
 }
 
+static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
+{
+	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
+}
+
 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
 				 bool respect_downstream_limits,
 				 bool has_hdmi_sink)
@@ -2036,7 +2041,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
 		return false;
 
 	/* Display Wa_1405510057:icl,ehl */
-	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
+	if (intel_hdmi_is_ycbcr420(crtc_state) &&
 	    bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
 	    (adjusted_mode->crtc_hblank_end -
 	     adjusted_mode->crtc_hblank_start) % 8 == 2)
@@ -2044,8 +2049,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
 
 	return intel_hdmi_deep_color_possible(crtc_state, bpc,
 					      crtc_state->has_hdmi_sink,
-					      crtc_state->output_format ==
-					      INTEL_OUTPUT_FORMAT_YCBCR420);
+					      intel_hdmi_is_ycbcr420(crtc_state));
 }
 
 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
@@ -2079,7 +2083,7 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
 		clock *= 2;
 
 	/* YCBCR420 TMDS rate requirement is half the pixel clock */
-	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+	if (intel_hdmi_is_ycbcr420(crtc_state))
 		clock /= 2;
 
 	bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
@@ -2176,7 +2180,7 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
 
 	ret = intel_hdmi_compute_clock(encoder, crtc_state);
 	if (ret) {
-		if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
+		if (!intel_hdmi_is_ycbcr420(crtc_state) &&
 		    connector->ycbcr_420_allowed &&
 		    drm_mode_is_420_also(&connector->display_info, adjusted_mode)) {
 			crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
@@ -2221,7 +2225,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
 	if (ret)
 		return ret;
 
-	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+	if (intel_hdmi_is_ycbcr420(pipe_config)) {
 		ret = intel_panel_fitting(pipe_config, conn_state);
 		if (ret)
 			return ret;
-- 
2.32.0

[Intel-gfx] [PATCH 03/20] drm/i915/hdmi: Introduce intel_hdmi_tmds_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename intel_hdmi_port_clock() into intel_hdmi_tmds_clock(), and
move the 4:2:0 TMDS clock halving into intel_hdmi_tmds_clock() so
the callers don't have to worry about such details.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 25 +++++++++++------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 37ce8a621973..e97c83535965 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1868,8 +1868,12 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
 	return MODE_OK;
 }
 
-static int intel_hdmi_port_clock(int clock, int bpc)
+static int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
 {
+	/* YCBCR420 TMDS rate requirement is half the pixel clock */
+	if (ycbcr420_output)
+		clock /= 2;
+
 	/*
 	 * Need to adjust the port link by:
 	 *  1.5x for 12bpc
@@ -1932,25 +1936,22 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
 	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
 	enum drm_mode_status status;
 
-	if (ycbcr420_output)
-		clock /= 2;
-
 	/* check if we can do 8bpc */
-	status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
+	status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 8, ycbcr420_output),
 				       true, has_hdmi_sink);
 
 	/* if we can't do 8bpc we may still be able to do 12bpc */
 	if (status != MODE_OK &&
 	    intel_hdmi_source_bpc_possible(i915, 12) &&
 	    intel_hdmi_sink_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output))
-		status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12),
+		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 12, ycbcr420_output),
 					       true, has_hdmi_sink);
 
 	/* if we can't do 8,12bpc we may still be able to do 10bpc */
 	if (status != MODE_OK &&
 	    intel_hdmi_source_bpc_possible(i915, 10) &&
 	    intel_hdmi_sink_bpc_possible(connector, 10, has_hdmi_sink, ycbcr420_output))
-		status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10),
+		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 10, ycbcr420_output),
 					       true, has_hdmi_sink);
 
 	return status;
@@ -2057,12 +2058,13 @@ static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
 				  int clock)
 {
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+	bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
 	int bpc;
 
 	for (bpc = 12; bpc >= 10; bpc -= 2) {
 		if (hdmi_deep_color_possible(crtc_state, bpc) &&
 		    hdmi_port_clock_valid(intel_hdmi,
-					  intel_hdmi_port_clock(clock, bpc),
+					  intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output),
 					  true, crtc_state->has_hdmi_sink) == MODE_OK)
 			return bpc;
 	}
@@ -2082,13 +2084,10 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 		clock *= 2;
 
-	/* YCBCR420 TMDS rate requirement is half the pixel clock */
-	if (intel_hdmi_is_ycbcr420(crtc_state))
-		clock /= 2;
-
 	bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
 
-	crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
+	crtc_state->port_clock = intel_hdmi_tmds_clock(clock, bpc,
+						       intel_hdmi_is_ycbcr420(crtc_state));
 
 	/*
 	 * pipe_bpp could already be below 8bpc due to
-- 
2.32.0

[Intel-gfx] [PATCH 04/20] drm/i915/hdmi: Unify "4:2:0 also" logic between .mode_valid() and .compute_config()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently .mode_valid() and .compute_config() have their "4:2:0 also"
logic inverted. Unify things so that we use the same logic on both
sides.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index e97c83535965..18e7ef125827 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2179,12 +2179,13 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
 
 	ret = intel_hdmi_compute_clock(encoder, crtc_state);
 	if (ret) {
-		if (!intel_hdmi_is_ycbcr420(crtc_state) &&
-		    connector->ycbcr_420_allowed &&
-		    drm_mode_is_420_also(&connector->display_info, adjusted_mode)) {
-			crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
-			ret = intel_hdmi_compute_clock(encoder, crtc_state);
-		}
+		if (intel_hdmi_is_ycbcr420(crtc_state) ||
+		    !connector->ycbcr_420_allowed ||
+		    !drm_mode_is_420_also(&connector->display_info, adjusted_mode))
+			return ret;
+
+		crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+		ret = intel_hdmi_compute_clock(encoder, crtc_state);
 	}
 
 	return ret;
-- 
2.32.0

[Intel-gfx] [PATCH 05/20] drm/i915/hdmi: Extract intel_hdmi_output_format()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reorganize the HDMI 4:2:0 handling a bit by introducing
intel_hdmi_output_format(). We already have the DP counterpart
and I want to unify the 4:2:0 handling across both a bit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 35 ++++++++++++++---------
 1 file changed, 22 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 18e7ef125827..7e6af959bf83 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2157,34 +2157,43 @@ static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
 		return intel_conn_state->force_audio == HDMI_AUDIO_ON;
 }
 
+static enum intel_output_format
+intel_hdmi_output_format(struct intel_connector *connector,
+			 bool ycbcr_420_output)
+{
+	if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
+		return INTEL_OUTPUT_FORMAT_YCBCR420;
+	else
+		return INTEL_OUTPUT_FORMAT_RGB;
+}
+
 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
 					    struct intel_crtc_state *crtc_state,
 					    const struct drm_connector_state *conn_state)
 {
-	struct drm_connector *connector = conn_state->connector;
-	struct drm_i915_private *i915 = to_i915(connector->dev);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	const struct drm_display_info *info = &connector->base.display_info;
+	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
 	int ret;
-	bool ycbcr_420_only;
 
-	ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, adjusted_mode);
-	if (connector->ycbcr_420_allowed && ycbcr_420_only) {
-		crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
-	} else {
-		if (!connector->ycbcr_420_allowed && ycbcr_420_only)
-			drm_dbg_kms(&i915->drm,
-				    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
+	crtc_state->output_format = intel_hdmi_output_format(connector, ycbcr_420_only);
+
+	if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
+		drm_dbg_kms(&i915->drm,
+			    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
 		crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
 	}
 
 	ret = intel_hdmi_compute_clock(encoder, crtc_state);
 	if (ret) {
 		if (intel_hdmi_is_ycbcr420(crtc_state) ||
-		    !connector->ycbcr_420_allowed ||
-		    !drm_mode_is_420_also(&connector->display_info, adjusted_mode))
+		    !connector->base.ycbcr_420_allowed ||
+		    !drm_mode_is_420_also(info, adjusted_mode))
 			return ret;
 
-		crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+		crtc_state->output_format = intel_hdmi_output_format(connector, true);
 		ret = intel_hdmi_compute_clock(encoder, crtc_state);
 	}
 
-- 
2.32.0

[Intel-gfx] [PATCH 06/20] drm/i915/hdmi: Clean up TMDS clock limit exceeding user mode handling

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we just use all the hdmi_deep_color_possible() stuff
to compute whether deep color is possible, and leave the 8bpc
case to do its own thing. That doesn't mesh super well with 4:2:0
handling because we might end up going for 8bpc RGB without
considering that it's essentially illegal and we could instead
go for a legal 4:2:0 config.

So let's run through all the clock checks even for 8bpc first.
If we've fully exhausted all options only then do we re-run
the computation for 8bpc while ignoring the downstream TMDS
clock limits. This will guarantee that if there's a config
that respects all limits we will find it, and if there is not
we still allow the user to override the mode manually.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c   | 13 ++--
 drivers/gpu/drm/i915/display/intel_hdmi.c | 92 +++++++++++++----------
 drivers/gpu/drm/i915/display/intel_hdmi.h |  4 +-
 3 files changed, 62 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9d8132dd4cc5..5cc99ffc1841 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1097,14 +1097,13 @@ static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
 	return true;
 }
 
-static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
-					      const struct intel_crtc_state *crtc_state,
-					      int bpc)
+static bool intel_dp_hdmi_bpc_possible(struct intel_dp *intel_dp,
+				       const struct intel_crtc_state *crtc_state,
+				       int bpc)
 {
 
-	return intel_hdmi_deep_color_possible(crtc_state, bpc,
-					      intel_dp->has_hdmi_sink,
-					      intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
+	return intel_hdmi_bpc_possible(crtc_state, bpc, intel_dp->has_hdmi_sink,
+				       intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
 		intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
 }
 
@@ -1122,7 +1121,7 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp,
 
 	if (intel_dp->dfp.min_tmds_clock) {
 		for (; bpc >= 10; bpc -= 2) {
-			if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
+			if (intel_dp_hdmi_bpc_possible(intel_dp, crtc_state, bpc))
 				break;
 		}
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7e6af959bf83..b5af986b2778 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2001,17 +2001,14 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
 	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
 }
 
-bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
-				    int bpc, bool has_hdmi_sink, bool ycbcr420_output)
+bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
+			     int bpc, bool has_hdmi_sink, bool ycbcr420_output)
 {
 	struct drm_atomic_state *state = crtc_state->uapi.state;
 	struct drm_connector_state *connector_state;
 	struct drm_connector *connector;
 	int i;
 
-	if (crtc_state->pipe_bpp < bpc * 3)
-		return false;
-
 	for_each_new_connector_in_state(state, connector, connector_state, i) {
 		if (connector_state->crtc != crtc_state->uapi.crtc)
 			continue;
@@ -2023,8 +2020,7 @@ bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
 	return true;
 }
 
-static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
-				     int bpc)
+static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
 {
 	struct drm_i915_private *dev_priv =
 		to_i915(crtc_state->uapi.crtc->dev);
@@ -2038,7 +2034,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
 	 * HDMI deep color affects the clocks, so it's only possible
 	 * when not cloning with other encoder types.
 	 */
-	if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
+	if (bpc > 8 && crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
 		return false;
 
 	/* Display Wa_1405510057:icl,ehl */
@@ -2048,35 +2044,50 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
 	     adjusted_mode->crtc_hblank_start) % 8 == 2)
 		return false;
 
-	return intel_hdmi_deep_color_possible(crtc_state, bpc,
-					      crtc_state->has_hdmi_sink,
-					      intel_hdmi_is_ycbcr420(crtc_state));
+	return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
+				       intel_hdmi_is_ycbcr420(crtc_state));
 }
 
 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
 				  struct intel_crtc_state *crtc_state,
-				  int clock)
+				  int clock, bool respect_downstream_limits)
 {
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
 	int bpc;
 
-	for (bpc = 12; bpc >= 10; bpc -= 2) {
-		if (hdmi_deep_color_possible(crtc_state, bpc) &&
-		    hdmi_port_clock_valid(intel_hdmi,
-					  intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output),
-					  true, crtc_state->has_hdmi_sink) == MODE_OK)
+	/*
+	 * pipe_bpp could already be below 8bpc due to FDI
+	 * bandwidth constraints. HDMI minimum is 8bpc however.
+	 */
+	bpc = max(crtc_state->pipe_bpp / 3, 8);
+
+	/*
+	 * We will never exceed downstream TMDS clock limits while
+	 * attempting deep color. If the user insists on forcing an
+	 * out of spec mode they will have to be satisfied with 8bpc.
+	 */
+	if (!respect_downstream_limits)
+		bpc = 8;
+
+	for (; bpc >= 8; bpc -= 2) {
+		int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
+
+		if (hdmi_bpc_possible(crtc_state, bpc) &&
+		    hdmi_port_clock_valid(intel_hdmi, tmds_clock,
+					  respect_downstream_limits,
+					  crtc_state->has_hdmi_sink) == MODE_OK)
 			return bpc;
 	}
 
-	return 8;
+	return -EINVAL;
 }
 
 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
-				    struct intel_crtc_state *crtc_state)
+				    struct intel_crtc_state *crtc_state,
+				    bool respect_downstream_limits)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
 	int bpc, clock = adjusted_mode->crtc_clock;
@@ -2084,31 +2095,25 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 		clock *= 2;
 
-	bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
+	bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
+				     respect_downstream_limits);
+	if (bpc < 0)
+		return bpc;
 
-	crtc_state->port_clock = intel_hdmi_tmds_clock(clock, bpc,
-						       intel_hdmi_is_ycbcr420(crtc_state));
+	crtc_state->port_clock =
+		intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
 
 	/*
 	 * pipe_bpp could already be below 8bpc due to
 	 * FDI bandwidth constraints. We shouldn't bump it
-	 * back up to 8bpc in that case.
+	 * back up to the HDMI minimum 8bpc in that case.
 	 */
-	if (crtc_state->pipe_bpp > bpc * 3)
-		crtc_state->pipe_bpp = bpc * 3;
+	crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
 
 	drm_dbg_kms(&i915->drm,
 		    "picking %d bpc for HDMI output (pipe bpp: %d)\n",
 		    bpc, crtc_state->pipe_bpp);
 
-	if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
-				  false, crtc_state->has_hdmi_sink) != MODE_OK) {
-		drm_dbg_kms(&i915->drm,
-			    "unsupported HDMI clock (%d kHz), rejecting mode\n",
-			    crtc_state->port_clock);
-		return -EINVAL;
-	}
-
 	return 0;
 }
 
@@ -2169,7 +2174,8 @@ intel_hdmi_output_format(struct intel_connector *connector,
 
 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
 					    struct intel_crtc_state *crtc_state,
-					    const struct drm_connector_state *conn_state)
+					    const struct drm_connector_state *conn_state,
+					    bool respect_downstream_limits)
 {
 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
@@ -2186,7 +2192,7 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
 		crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
 	}
 
-	ret = intel_hdmi_compute_clock(encoder, crtc_state);
+	ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
 	if (ret) {
 		if (intel_hdmi_is_ycbcr420(crtc_state) ||
 		    !connector->base.ycbcr_420_allowed ||
@@ -2194,7 +2200,7 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
 			return ret;
 
 		crtc_state->output_format = intel_hdmi_output_format(connector, true);
-		ret = intel_hdmi_compute_clock(encoder, crtc_state);
+		ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
 	}
 
 	return ret;
@@ -2230,9 +2236,19 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
 	pipe_config->has_audio =
 		intel_hdmi_has_audio(encoder, pipe_config, conn_state);
 
-	ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state);
+	/*
+	 * Try to respect downstream TMDS clock limits first, if
+	 * that fails assume the user might know something we don't.
+	 */
+	ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
 	if (ret)
+		ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
+	if (ret) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "unsupported HDMI clock (%d kHz), rejecting mode\n",
+			    pipe_config->hw.adjusted_mode.crtc_clock);
 		return ret;
+	}
 
 	if (intel_hdmi_is_ycbcr420(pipe_config)) {
 		ret = intel_panel_fitting(pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index b43a180d007e..ee144db67e66 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -45,8 +45,8 @@ void intel_read_infoframe(struct intel_encoder *encoder,
 			  union hdmi_infoframe *frame);
 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state);
-bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, int bpc,
-				    bool has_hdmi_sink, bool ycbcr420_output);
+bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
+			     int bpc, bool has_hdmi_sink, bool ycbcr420_output);
 int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
 			   int num_slices, int output_format, bool hdmi_all_bpp,
 			   int hdmi_max_chunk_bytes);
-- 
2.32.0

[Intel-gfx] [PATCH 07/20] drm/i915/hdmi: Simplify intel_hdmi_mode_clock_valid()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Just loop over the possible bpc values instead of
using an ugly if construct.

A slight change in behaviour is that we now call
intel_hdmi_{source,sink}_bpc_possible() even for 8bpc,
but that is fine since 8bpc is always supported.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 37 +++++++++++++----------
 1 file changed, 21 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b5af986b2778..c6586d10a9d0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1934,25 +1934,30 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
 {
 	struct drm_i915_private *i915 = to_i915(connector->dev);
 	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
-	enum drm_mode_status status;
+	enum drm_mode_status status = MODE_OK;
+	int bpc;
 
-	/* check if we can do 8bpc */
-	status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 8, ycbcr420_output),
-				       true, has_hdmi_sink);
+	/*
+	 * Try all color depths since valid port clock range
+	 * can have holes. Any mode that can be used with at
+	 * least one color depth is accepted.
+	 */
+	for (bpc = 12; bpc >= 8; bpc -= 2) {
+		int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
 
-	/* if we can't do 8bpc we may still be able to do 12bpc */
-	if (status != MODE_OK &&
-	    intel_hdmi_source_bpc_possible(i915, 12) &&
-	    intel_hdmi_sink_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output))
-		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 12, ycbcr420_output),
-					       true, has_hdmi_sink);
+		if (!intel_hdmi_source_bpc_possible(i915, bpc))
+			continue;
 
-	/* if we can't do 8,12bpc we may still be able to do 10bpc */
-	if (status != MODE_OK &&
-	    intel_hdmi_source_bpc_possible(i915, 10) &&
-	    intel_hdmi_sink_bpc_possible(connector, 10, has_hdmi_sink, ycbcr420_output))
-		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 10, ycbcr420_output),
-					       true, has_hdmi_sink);
+		if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
+			continue;
+
+		status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
+		if (status == MODE_OK)
+			return MODE_OK;
+	}
+
+	/* can never happen */
+	drm_WARN_ON(&i915->drm, status == MODE_OK);
 
 	return status;
 }
-- 
2.32.0

[Intel-gfx] [PATCH 08/20] drm/i915/dp: Reuse intel_hdmi_tmds_clock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reuse intel_hdmi_tmds_clock() for DP->HDMI TMDS clock calculations.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c   | 20 +++++---------------
 drivers/gpu/drm/i915/display/intel_hdmi.c |  2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.h |  1 +
 3 files changed, 7 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5cc99ffc1841..45e4bf54e1de 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -814,9 +814,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 		return MODE_CLOCK_HIGH;
 
 	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
-	tmds_clock = target_clock;
-	if (drm_mode_is_420_only(info, mode))
-		tmds_clock /= 2;
+	tmds_clock = intel_hdmi_tmds_clock(target_clock, 8,
+					   drm_mode_is_420_only(info, mode));
 
 	if (intel_dp->dfp.min_tmds_clock &&
 	    tmds_clock < intel_dp->dfp.min_tmds_clock)
@@ -1070,21 +1069,12 @@ static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
 		 intel_dp->dfp.ycbcr_444_to_420);
 }
 
-static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
-				    const struct intel_crtc_state *crtc_state, int bpc)
-{
-	int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
-
-	if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
-		clock /= 2;
-
-	return clock;
-}
-
 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
 					   const struct intel_crtc_state *crtc_state, int bpc)
 {
-	int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
+	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
+	int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
+					       intel_dp_hdmi_ycbcr420(intel_dp, crtc_state));
 
 	if (intel_dp->dfp.min_tmds_clock &&
 	    tmds_clock < intel_dp->dfp.min_tmds_clock)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c6586d10a9d0..f1d42279a2df 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1868,7 +1868,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
 	return MODE_OK;
 }
 
-static int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
+int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
 {
 	/* YCBCR420 TMDS rate requirement is half the pixel clock */
 	if (ycbcr420_output)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index ee144db67e66..d892cbff0da0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -47,6 +47,7 @@ bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state);
 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
 			     int bpc, bool has_hdmi_sink, bool ycbcr420_output);
+int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output);
 int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
 			   int num_slices, int output_format, bool hdmi_all_bpp,
 			   int hdmi_max_chunk_bytes);
-- 
2.32.0

[Intel-gfx] [PATCH 09/20] drm/i915/dp: Extract intel_dp_tmds_clock_valid()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We're currently duplicating the DFP min/max TMDS clock checks
in .mode_valid() and .compute_config(). Extract a helper suitable
for both use cases.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 59 +++++++++++--------------
 1 file changed, 26 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 45e4bf54e1de..b3b8e74fac9c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -781,6 +781,25 @@ static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 	return hdisplay == 4096 && !HAS_DDI(dev_priv);
 }
 
+static enum drm_mode_status
+intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
+			  int clock, int bpc, bool ycbcr420_output)
+{
+	int tmds_clock;
+
+	tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
+
+	if (intel_dp->dfp.min_tmds_clock &&
+	    tmds_clock < intel_dp->dfp.min_tmds_clock)
+		return MODE_CLOCK_LOW;
+
+	if (intel_dp->dfp.max_tmds_clock &&
+	    tmds_clock > intel_dp->dfp.max_tmds_clock)
+		return MODE_CLOCK_HIGH;
+
+	return MODE_OK;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 			       const struct drm_display_mode *mode,
@@ -788,7 +807,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 {
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	const struct drm_display_info *info = &connector->base.display_info;
-	int tmds_clock;
 
 	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
 	if (intel_dp->dfp.pcon_max_frl_bw) {
@@ -814,17 +832,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 		return MODE_CLOCK_HIGH;
 
 	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
-	tmds_clock = intel_hdmi_tmds_clock(target_clock, 8,
-					   drm_mode_is_420_only(info, mode));
-
-	if (intel_dp->dfp.min_tmds_clock &&
-	    tmds_clock < intel_dp->dfp.min_tmds_clock)
-		return MODE_CLOCK_LOW;
-	if (intel_dp->dfp.max_tmds_clock &&
-	    tmds_clock > intel_dp->dfp.max_tmds_clock)
-		return MODE_CLOCK_HIGH;
-
-	return MODE_OK;
+	return intel_dp_tmds_clock_valid(intel_dp, target_clock, 8,
+					 drm_mode_is_420_only(info, mode));
 }
 
 static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
@@ -1069,32 +1078,16 @@ static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
 		 intel_dp->dfp.ycbcr_444_to_420);
 }
 
-static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
-					   const struct intel_crtc_state *crtc_state, int bpc)
-{
-	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
-	int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
-					       intel_dp_hdmi_ycbcr420(intel_dp, crtc_state));
-
-	if (intel_dp->dfp.min_tmds_clock &&
-	    tmds_clock < intel_dp->dfp.min_tmds_clock)
-		return false;
-
-	if (intel_dp->dfp.max_tmds_clock &&
-	    tmds_clock > intel_dp->dfp.max_tmds_clock)
-		return false;
-
-	return true;
-}
-
 static bool intel_dp_hdmi_bpc_possible(struct intel_dp *intel_dp,
 				       const struct intel_crtc_state *crtc_state,
 				       int bpc)
 {
+	bool ycbcr420_output = intel_dp_hdmi_ycbcr420(intel_dp, crtc_state);
+	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
 
-	return intel_hdmi_bpc_possible(crtc_state, bpc, intel_dp->has_hdmi_sink,
-				       intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
-		intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
+	return intel_hdmi_bpc_possible(crtc_state, bpc,
+				       intel_dp->has_hdmi_sink, ycbcr420_output) &&
+		intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output) == MODE_OK;
 }
 
 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
-- 
2.32.0

[Intel-gfx] [PATCH 10/20] drm/i915/dp: Respect the sink's max TMDS clock when dealing with DP->HDMI DFPs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we only look at the DFPs max TMDS clock limit when
considering whether the mode is valid, or whether we can do
deep color. The sink's max TMDS clock limit may be lower than
the DFPs, so we need to account for it as well.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4095
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b3b8e74fac9c..84270f9573ba 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -781,20 +781,34 @@ static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 	return hdisplay == 4096 && !HAS_DDI(dev_priv);
 }
 
+static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
+{
+	struct intel_connector *connector = intel_dp->attached_connector;
+	const struct drm_display_info *info = &connector->base.display_info;
+	int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
+
+	/* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
+	if (max_tmds_clock && info->max_tmds_clock)
+		max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
+
+	return max_tmds_clock;
+}
+
 static enum drm_mode_status
 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
 			  int clock, int bpc, bool ycbcr420_output)
 {
-	int tmds_clock;
+	int tmds_clock, min_tmds_clock, max_tmds_clock;
 
 	tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
 
-	if (intel_dp->dfp.min_tmds_clock &&
-	    tmds_clock < intel_dp->dfp.min_tmds_clock)
+	min_tmds_clock = intel_dp->dfp.min_tmds_clock;
+	max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
+
+	if (min_tmds_clock && tmds_clock < min_tmds_clock)
 		return MODE_CLOCK_LOW;
 
-	if (intel_dp->dfp.max_tmds_clock &&
-	    tmds_clock > intel_dp->dfp.max_tmds_clock)
+	if (max_tmds_clock && tmds_clock > max_tmds_clock)
 		return MODE_CLOCK_HIGH;
 
 	return MODE_OK;
-- 
2.32.0

[Intel-gfx] [PATCH 11/20] drm/i915/dp: Extract intel_dp_has_audio()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Declutter intel_dp_compute_config() a bit by moving the
has_audio computation into a helper. HDMI already does the same thing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 30 ++++++++++++++++---------
 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 84270f9573ba..145f0e4a8a4b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1731,6 +1731,24 @@ intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
 		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
+static bool intel_dp_has_audio(struct intel_encoder *encoder,
+			       const struct intel_crtc_state *crtc_state,
+			       const struct drm_connector_state *conn_state)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	const struct intel_digital_connector_state *intel_conn_state =
+		to_intel_digital_connector_state(conn_state);
+
+	if (!intel_dp_port_has_audio(i915, encoder->port))
+		return false;
+
+	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
+		return intel_dp->has_audio;
+	else
+		return intel_conn_state->force_audio == HDMI_AUDIO_ON;
+}
+
 int
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config,
@@ -1739,14 +1757,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-	enum port port = encoder->port;
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
-	struct intel_digital_connector_state *intel_conn_state =
-		to_intel_digital_connector_state(conn_state);
 	bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
 	int ret = 0, output_bpp;
 
-	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
+	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
 		pipe_config->has_pch_encoder = true;
 
 	pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
@@ -1758,12 +1773,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 			return ret;
 	}
 
-	if (!intel_dp_port_has_audio(dev_priv, port))
-		pipe_config->has_audio = false;
-	else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
-		pipe_config->has_audio = intel_dp->has_audio;
-	else
-		pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
+	pipe_config->has_audio = intel_dp_has_audio(encoder, pipe_config, conn_state);
 
 	if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 		ret = intel_panel_compute_config(intel_connector, adjusted_mode);
-- 
2.32.0

[Intel-gfx] [PATCH 12/20] drm/i915/dp: s/intel_dp_hdmi_ycbcr420/intel_dp_is_ycbcr420/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_dp_hdmi_ycbcr420() does account for native DP 4:2:0
output as well, so lets rename it a bit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 145f0e4a8a4b..2440a6a2e4fc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1084,8 +1084,8 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
 		drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
 }
 
-static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
-				   const struct intel_crtc_state *crtc_state)
+static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state)
 {
 	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 		(crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
@@ -1096,7 +1096,7 @@ static bool intel_dp_hdmi_bpc_possible(struct intel_dp *intel_dp,
 				       const struct intel_crtc_state *crtc_state,
 				       int bpc)
 {
-	bool ycbcr420_output = intel_dp_hdmi_ycbcr420(intel_dp, crtc_state);
+	bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
 	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
 
 	return intel_hdmi_bpc_possible(crtc_state, bpc,
-- 
2.32.0

[Intel-gfx] [PATCH 13/20] drm/i915/dp: Reorder intel_dp_compute_config() a bit

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Consolidate the double pfit call, and reorder things so that
intel_dp_output_format() and intel_dp_compute_link_config() are
back-to-back. They are intimately related, and will need to be
called twice to properly handle the "4:2:0 also" modes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 23 ++++++++++-------------
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2440a6a2e4fc..de2b3d33a726 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1764,25 +1764,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
 		pipe_config->has_pch_encoder = true;
 
-	pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
-							    adjusted_mode);
-
-	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
-		ret = intel_panel_fitting(pipe_config, conn_state);
-		if (ret)
-			return ret;
-	}
-
 	pipe_config->has_audio = intel_dp_has_audio(encoder, pipe_config, conn_state);
 
 	if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 		ret = intel_panel_compute_config(intel_connector, adjusted_mode);
 		if (ret)
 			return ret;
-
-		ret = intel_panel_fitting(pipe_config, conn_state);
-		if (ret)
-			return ret;
 	}
 
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -1798,10 +1785,20 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
 		return -EINVAL;
 
+	pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
+							    adjusted_mode);
+
 	ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
 	if (ret < 0)
 		return ret;
 
+	if ((intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) ||
+	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+		ret = intel_panel_fitting(pipe_config, conn_state);
+		if (ret)
+			return ret;
+	}
+
 	pipe_config->limited_color_range =
 		intel_dp_limited_color_range(pipe_config, conn_state);
 
-- 
2.32.0

[Intel-gfx] [PATCH 14/20] drm/i915/dp: Pass around intel_connector rather than drm_connector

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Prefer to use intel_connector over drm_connector. Also clean
up the related variable names a bit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 38 ++++++++++++-------------
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index de2b3d33a726..d378aeee3287 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -711,13 +711,13 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 }
 
 static enum intel_output_format
-intel_dp_output_format(struct drm_connector *connector,
+intel_dp_output_format(struct intel_connector *connector,
 		       const struct drm_display_mode *mode)
 {
-	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
-	const struct drm_display_info *info = &connector->display_info;
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
+	const struct drm_display_info *info = &connector->base.display_info;
 
-	if (!connector->ycbcr_420_allowed ||
+	if (!connector->base.ycbcr_420_allowed ||
 	    !drm_mode_is_420_only(info, mode))
 		return INTEL_OUTPUT_FORMAT_RGB;
 
@@ -753,7 +753,7 @@ static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 }
 
 static int
-intel_dp_mode_min_output_bpp(struct drm_connector *connector,
+intel_dp_mode_min_output_bpp(struct intel_connector *connector,
 			     const struct drm_display_mode *mode)
 {
 	enum intel_output_format output_format =
@@ -826,7 +826,7 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 	if (intel_dp->dfp.pcon_max_frl_bw) {
 		int target_bw;
 		int max_frl_bw;
-		int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
+		int bpp = intel_dp_mode_min_output_bpp(connector, mode);
 
 		target_bw = bpp * target_clock;
 
@@ -862,13 +862,13 @@ static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
 }
 
 static enum drm_mode_status
-intel_dp_mode_valid(struct drm_connector *connector,
+intel_dp_mode_valid(struct drm_connector *_connector,
 		    struct drm_display_mode *mode)
 {
-	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
-	struct intel_connector *intel_connector = to_intel_connector(connector);
-	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
-	struct drm_i915_private *dev_priv = to_i915(connector->dev);
+	struct intel_connector *connector = to_intel_connector(_connector);
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
+	struct drm_display_mode *fixed_mode = connector->panel.fixed_mode;
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	int target_clock = mode->clock;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
 	int max_dotclk = dev_priv->max_dotclk_freq;
@@ -884,7 +884,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 		return MODE_H_ILLEGAL;
 
 	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
-		status = intel_panel_mode_valid(intel_connector, mode);
+		status = intel_panel_mode_valid(connector, mode);
 		if (status != MODE_OK)
 			return status;
 
@@ -958,8 +958,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	if (mode_rate > max_rate && !dsc)
 		return MODE_CLOCK_HIGH;
 
-	status = intel_dp_mode_valid_downstream(intel_connector,
-						mode, target_clock);
+	status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
 	if (status != MODE_OK)
 		return status;
 
@@ -1757,7 +1756,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-	struct intel_connector *intel_connector = intel_dp->attached_connector;
+	struct intel_connector *connector = intel_dp->attached_connector;
 	bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
 	int ret = 0, output_bpp;
 
@@ -1766,8 +1765,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	pipe_config->has_audio = intel_dp_has_audio(encoder, pipe_config, conn_state);
 
-	if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
-		ret = intel_panel_compute_config(intel_connector, adjusted_mode);
+	if (intel_dp_is_edp(intel_dp) && connector->panel.fixed_mode) {
+		ret = intel_panel_compute_config(connector, adjusted_mode);
 		if (ret)
 			return ret;
 	}
@@ -1785,14 +1784,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
 		return -EINVAL;
 
-	pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
-							    adjusted_mode);
+	pipe_config->output_format = intel_dp_output_format(connector, adjusted_mode);
 
 	ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
 	if (ret < 0)
 		return ret;
 
-	if ((intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) ||
+	if ((intel_dp_is_edp(intel_dp) && connector->panel.fixed_mode) ||
 	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
 		ret = intel_panel_fitting(pipe_config, conn_state);
 		if (ret)
-- 
2.32.0

[Intel-gfx] [PATCH 15/20] drm/i915/dp: Make intel_dp_output_format() usable for "4:2:0 also" modes

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Hoist the drm_mode_is_420_only() from intel_dp_output_format()
into the caller. This will allow intel_dp_output_format() to be
reused for "4:2:0 also" modes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d378aeee3287..ff2dc22966fa 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -712,13 +712,11 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 
 static enum intel_output_format
 intel_dp_output_format(struct intel_connector *connector,
-		       const struct drm_display_mode *mode)
+		       bool ycbcr_420_output)
 {
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
-	const struct drm_display_info *info = &connector->base.display_info;
 
-	if (!connector->base.ycbcr_420_allowed ||
-	    !drm_mode_is_420_only(info, mode))
+	if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
 		return INTEL_OUTPUT_FORMAT_RGB;
 
 	if (intel_dp->dfp.rgb_to_ycbcr &&
@@ -756,8 +754,9 @@ static int
 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
 			     const struct drm_display_mode *mode)
 {
+	const struct drm_display_info *info = &connector->base.display_info;
 	enum intel_output_format output_format =
-		intel_dp_output_format(connector, mode);
+		intel_dp_output_format(connector, drm_mode_is_420_only(info, mode));
 
 	return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 }
@@ -1757,6 +1756,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct intel_connector *connector = intel_dp->attached_connector;
+	const struct drm_display_info *info = &connector->base.display_info;
 	bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
 	int ret = 0, output_bpp;
 
@@ -1784,7 +1784,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
 		return -EINVAL;
 
-	pipe_config->output_format = intel_dp_output_format(connector, adjusted_mode);
+	pipe_config->output_format =
+		intel_dp_output_format(connector, drm_mode_is_420_only(info, adjusted_mode));
 
 	ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
 	if (ret < 0)
-- 
2.32.0

[Intel-gfx] [PATCH 16/20] drm/i915/dp: Rework HDMI DFP TMDS clock handling

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rework the HDMI DFP TMDS clock checks to also check at 8bpc.
Previously we only checked the deep color cases. But I suppose
a sink could potentially declare "4:2:0 also" modes that only
actually fit within its own limits when using 4:2:0. Even if
that is too nuts to be real there is no real harm in running
through the full checks for everything.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 35 ++++++++++++++++++-------
 1 file changed, 25 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ff2dc22966fa..08aab7856f99 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1090,16 +1090,28 @@ static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
 		 intel_dp->dfp.ycbcr_444_to_420);
 }
 
-static bool intel_dp_hdmi_bpc_possible(struct intel_dp *intel_dp,
-				       const struct intel_crtc_state *crtc_state,
-				       int bpc)
+static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state,
+				     int bpc)
 {
 	bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
 	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
 
-	return intel_hdmi_bpc_possible(crtc_state, bpc,
-				       intel_dp->has_hdmi_sink, ycbcr420_output) &&
-		intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output) == MODE_OK;
+	/*
+	 * Current bpc could already be below 8bpc due to
+	 * FDI bandwidth constraints or other limits.
+	 * HDMI minimum is 8bpc however.
+	 */
+	bpc = max(bpc, 8);
+
+	for (; bpc >= 8; bpc -= 2) {
+		if (intel_hdmi_bpc_possible(crtc_state, bpc,
+					    intel_dp->has_hdmi_sink, ycbcr420_output) &&
+		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output) == MODE_OK)
+			return bpc;
+	}
+
+	return -EINVAL;
 }
 
 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
@@ -1115,10 +1127,13 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp,
 		bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
 
 	if (intel_dp->dfp.min_tmds_clock) {
-		for (; bpc >= 10; bpc -= 2) {
-			if (intel_dp_hdmi_bpc_possible(intel_dp, crtc_state, bpc))
-				break;
-		}
+		int max_hdmi_bpc;
+
+		max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc);
+		if (max_hdmi_bpc < 0)
+			return 0;
+
+		bpc = min(bpc, max_hdmi_bpc);
 	}
 
 	bpp = bpc * 3;
-- 
2.32.0

[Intel-gfx] [PATCH 17/20] drm/i915/dp: Add support for "4:2:0 also" modes for DP

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we only support "4:2:0 also" modes on native HDMI.
Extend that support for DP as well.

With all the HDMI DFP TMDS clock handling sorted out this
is now going to work for both native DP and DP->HDMI
converters. As with native HDMI we first check if RGB
output is possible, and if not we try YCbCr 4:2:0 instead.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 67 ++++++++++++++++++++++---
 1 file changed, 59 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 08aab7856f99..2fa3e3013978 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -820,6 +820,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 {
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	const struct drm_display_info *info = &connector->base.display_info;
+	enum drm_mode_status status;
+	bool ycbcr_420_only;
 
 	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
 	if (intel_dp->dfp.pcon_max_frl_bw) {
@@ -844,9 +846,25 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 	    target_clock > intel_dp->dfp.max_dotclock)
 		return MODE_CLOCK_HIGH;
 
+	ycbcr_420_only = drm_mode_is_420_only(info, mode);
+
 	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
-	return intel_dp_tmds_clock_valid(intel_dp, target_clock, 8,
-					 drm_mode_is_420_only(info, mode));
+	status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
+					   8, ycbcr_420_only);
+
+	if (status != MODE_OK) {
+		if (ycbcr_420_only ||
+		    !connector->base.ycbcr_420_allowed ||
+		    !drm_mode_is_420_also(info, mode))
+			return status;
+
+		status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
+						   8, true);
+		if (status != MODE_OK)
+			return status;
+	}
+
+	return MODE_OK;
 }
 
 static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
@@ -1762,6 +1780,43 @@ static bool intel_dp_has_audio(struct intel_encoder *encoder,
 		return intel_conn_state->force_audio == HDMI_AUDIO_ON;
 }
 
+static int
+intel_dp_compute_output_format(struct intel_encoder *encoder,
+			       struct intel_crtc_state *crtc_state,
+			       struct drm_connector_state *conn_state)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct intel_connector *connector = intel_dp->attached_connector;
+	const struct drm_display_info *info = &connector->base.display_info;
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	bool ycbcr_420_only;
+	int ret;
+
+	ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
+
+	crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
+
+	if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
+		drm_dbg_kms(&i915->drm,
+			    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
+		crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
+	}
+
+	ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state);
+	if (ret) {
+		if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
+		    !connector->base.ycbcr_420_allowed ||
+		    !drm_mode_is_420_also(info, adjusted_mode))
+			return ret;
+
+		crtc_state->output_format = intel_dp_output_format(connector, true);
+		ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state);
+	}
+
+	return ret;
+}
+
 int
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config,
@@ -1771,7 +1826,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct intel_connector *connector = intel_dp->attached_connector;
-	const struct drm_display_info *info = &connector->base.display_info;
 	bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
 	int ret = 0, output_bpp;
 
@@ -1799,11 +1853,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
 		return -EINVAL;
 
-	pipe_config->output_format =
-		intel_dp_output_format(connector, drm_mode_is_420_only(info, adjusted_mode));
-
-	ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
-	if (ret < 0)
+	ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state);
+	if (ret)
 		return ret;
 
 	if ((intel_dp_is_edp(intel_dp) && connector->panel.fixed_mode) ||
-- 
2.32.0

[Intel-gfx] [PATCH 18/20] drm/i915/dp: Duplicate native HDMI TMDS clock limit handling for DP HDMI DFPs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

With native HDMI we allow the user to override the mode with
something that may not respect the downstream (sink,dual-mode adapter)
TMDS clock limits. Let's reuse the same logic for DP HDMI DFPs
so that behaviour is more or less uniform.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 51 ++++++++++++++++++-------
 1 file changed, 38 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2fa3e3013978..dfd3ab385b0f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -795,10 +795,14 @@ static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
 
 static enum drm_mode_status
 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
-			  int clock, int bpc, bool ycbcr420_output)
+			  int clock, int bpc, bool ycbcr420_output,
+			  bool respect_downstream_limits)
 {
 	int tmds_clock, min_tmds_clock, max_tmds_clock;
 
+	if (!respect_downstream_limits)
+		return MODE_OK;
+
 	tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
 
 	min_tmds_clock = intel_dp->dfp.min_tmds_clock;
@@ -850,7 +854,7 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 
 	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 	status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
-					   8, ycbcr_420_only);
+					   8, ycbcr_420_only, true);
 
 	if (status != MODE_OK) {
 		if (ycbcr_420_only ||
@@ -859,7 +863,7 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
 			return status;
 
 		status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
-						   8, true);
+						   8, true, true);
 		if (status != MODE_OK)
 			return status;
 	}
@@ -1110,7 +1114,7 @@ static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
 
 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
 				     const struct intel_crtc_state *crtc_state,
-				     int bpc)
+				     int bpc, bool respect_downstream_limits)
 {
 	bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
 	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
@@ -1122,10 +1126,19 @@ static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
 	 */
 	bpc = max(bpc, 8);
 
+	/*
+	 * We will never exceed downstream TMDS clock limits while
+	 * attempting deep color. If the user insists on forcing an
+	 * out of spec mode they will have to be satisfied with 8bpc.
+	 */
+	if (!respect_downstream_limits)
+		bpc = 8;
+
 	for (; bpc >= 8; bpc -= 2) {
 		if (intel_hdmi_bpc_possible(crtc_state, bpc,
 					    intel_dp->has_hdmi_sink, ycbcr420_output) &&
-		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output) == MODE_OK)
+		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output,
+					      respect_downstream_limits) == MODE_OK)
 			return bpc;
 	}
 
@@ -1133,7 +1146,8 @@ static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
 }
 
 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
-			    const struct intel_crtc_state *crtc_state)
+			    const struct intel_crtc_state *crtc_state,
+			    bool respect_downstream_limits)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
@@ -1147,7 +1161,8 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp,
 	if (intel_dp->dfp.min_tmds_clock) {
 		int max_hdmi_bpc;
 
-		max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc);
+		max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
+							 respect_downstream_limits);
 		if (max_hdmi_bpc < 0)
 			return 0;
 
@@ -1466,7 +1481,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 static int
 intel_dp_compute_link_config(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config,
-			     struct drm_connector_state *conn_state)
+			     struct drm_connector_state *conn_state,
+			     bool respect_downstream_limits)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	const struct drm_display_mode *adjusted_mode =
@@ -1489,7 +1505,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
 
 	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
-	limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
+	limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
 
 	if (intel_dp->use_max_params) {
 		/*
@@ -1783,7 +1799,8 @@ static bool intel_dp_has_audio(struct intel_encoder *encoder,
 static int
 intel_dp_compute_output_format(struct intel_encoder *encoder,
 			       struct intel_crtc_state *crtc_state,
-			       struct drm_connector_state *conn_state)
+			       struct drm_connector_state *conn_state,
+			       bool respect_downstream_limits)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -1803,7 +1820,8 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
 		crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
 	}
 
-	ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state);
+	ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
+					   respect_downstream_limits);
 	if (ret) {
 		if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
 		    !connector->base.ycbcr_420_allowed ||
@@ -1811,7 +1829,8 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
 			return ret;
 
 		crtc_state->output_format = intel_dp_output_format(connector, true);
-		ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state);
+		ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
+						   respect_downstream_limits);
 	}
 
 	return ret;
@@ -1853,7 +1872,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
 		return -EINVAL;
 
-	ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state);
+	/*
+	 * Try to respect downstream TMDS clock limits first, if
+	 * that fails assume the user might know something we don't.
+	 */
+	ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
+	if (ret)
+		ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
 	if (ret)
 		return ret;
 
-- 
2.32.0

[Intel-gfx] [PATCH 19/20] drm/i915/dp: Fix DFP rgb->ycbcr conversion matrix

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Our YCbCr output is always supposed to be limited range BT.709.
That's what we send with native HDMI. The conn_state->colorspace
stuff is entirely independent of that and is not supposed to alter
the generated output in any way. If we want a way to do that then
we need a new proprty for it.

Make it so that the RGB->YCbCr conversion when performed by the
DPF will match the BT.709 we would transmit with native HDMI.

Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 38 ++-----------------------
 1 file changed, 3 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index dfd3ab385b0f..29b12456c461 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2456,38 +2456,8 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
 			    "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
 			    enabledisable(intel_dp->dfp.ycbcr_444_to_420));
 
-	tmp = 0;
-	if (intel_dp->dfp.rgb_to_ycbcr) {
-		bool bt2020, bt709;
-
-		/*
-		 * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only
-		 * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default.
-		 *
-		 */
-		tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE;
-
-		bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
-								   intel_dp->downstream_ports,
-								   DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
-		bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
-								  intel_dp->downstream_ports,
-								  DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
-		switch (crtc_state->infoframes.vsc.colorimetry) {
-		case DP_COLORIMETRY_BT2020_RGB:
-		case DP_COLORIMETRY_BT2020_YCC:
-			if (bt2020)
-				tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE;
-			break;
-		case DP_COLORIMETRY_BT709_YCC:
-		case DP_COLORIMETRY_XVYCC_709:
-			if (bt709)
-				tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE;
-			break;
-		default:
-			break;
-		}
-	}
+	tmp = intel_dp->dfp.rgb_to_ycbcr ?
+		DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
 
 	if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
 		drm_dbg_kms(&i915->drm,
@@ -4290,9 +4260,7 @@ intel_dp_update_420(struct intel_dp *intel_dp)
 							intel_dp->downstream_ports);
 	rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
 								 intel_dp->downstream_ports,
-								 DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
-								 DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
-								 DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
+								 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
 
 	if (DISPLAY_VER(i915) >= 11) {
 		/* Let PCON convert from RGB->YCbCr if possible */
-- 
2.32.0

[Intel-gfx] [PATCH 20/20] drm/i915/dp: Disable DFP RGB->YCbCr conversion for now

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We lack sufficient state tracking to figure out whether
we want the DFP to perform the RGB->YCbCr conversion for us
or not. So currently we are blindly just enabling that all the
time when supported by the DFP. That is nonsense. So until
we imporve our state tracking for this just disable the feature.

Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 29b12456c461..3e2a29b589a9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1107,6 +1107,7 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
 static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
 				 const struct intel_crtc_state *crtc_state)
 {
+	/* FIXME see intel_dp_update_420() regarding rgb_to_ycbcr */
 	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 		(crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
 		 intel_dp->dfp.ycbcr_444_to_420);
@@ -2456,6 +2457,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
 			    "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
 			    enabledisable(intel_dp->dfp.ycbcr_444_to_420));
 
+	/* FIXME see intel_dp_update_420() regarding rgb_to_ycbcr */
 	tmp = intel_dp->dfp.rgb_to_ycbcr ?
 		DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
 
@@ -4261,6 +4263,14 @@ intel_dp_update_420(struct intel_dp *intel_dp)
 	rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
 								 intel_dp->downstream_ports,
 								 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
+	/*
+	 * FIXME need to actually track whether we're really
+	 * going to be doing the RGB->YCbCr connversion or not.
+	 * We can't tell by simply looking at intel_dp->dfp.rgb_to_ycbcr.
+	 * Readout is going to annoying due to having to read that
+	 * state from external hardware that may vanish at any time :(
+	 */
+	rgb_to_ycbcr = false;
 
 	if (DISPLAY_VER(i915) >= 11) {
 		/* Let PCON convert from RGB->YCbCr if possible */
-- 
2.32.0

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix up DP DFP 4:2:0 handling more

[Patchwork]

== Series Details ==

Series: drm/i915: Fix up DP DFP 4:2:0 handling more
URL   : https://patchwork.freedesktop.org/series/95881/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
da10a92856b4 drm/i915/hdmi: Split intel_hdmi_bpc_possible() to source vs. sink pair
070dfafd959a drm/i915/hdmi: Introduce intel_hdmi_is_ycbr420()
7d2c8095b108 drm/i915/hdmi: Introduce intel_hdmi_tmds_clock()
-:50: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#50: FILE: drivers/gpu/drm/i915/display/intel_hdmi.c:1947:
+		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 12, ycbcr420_output),

-:58: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#58: FILE: drivers/gpu/drm/i915/display/intel_hdmi.c:1954:
+		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 10, ycbcr420_output),

total: 0 errors, 2 warnings, 0 checks, 70 lines checked
2f30c6c7e076 drm/i915/hdmi: Unify "4:2:0 also" logic between .mode_valid() and .compute_config()
cfdd62a9b76f drm/i915/hdmi: Extract intel_hdmi_output_format()
5300f80e58b7 drm/i915/hdmi: Clean up TMDS clock limit exceeding user mode handling
c1aab421454c drm/i915/hdmi: Simplify intel_hdmi_mode_clock_valid()
a2ebf755d8ec drm/i915/dp: Reuse intel_hdmi_tmds_clock()
b20dd4ac5782 drm/i915/dp: Extract intel_dp_tmds_clock_valid()
3c125fcf5842 drm/i915/dp: Respect the sink's max TMDS clock when dealing with DP->HDMI DFPs
04ab0ef5104e drm/i915/dp: Extract intel_dp_has_audio()
759fa68f70a0 drm/i915/dp: s/intel_dp_hdmi_ycbcr420/intel_dp_is_ycbcr420/
77d2c530f843 drm/i915/dp: Reorder intel_dp_compute_config() a bit
d1f3604570ee drm/i915/dp: Pass around intel_connector rather than drm_connector
86076600d89d drm/i915/dp: Make intel_dp_output_format() usable for "4:2:0 also" modes
ec45d7b88657 drm/i915/dp: Rework HDMI DFP TMDS clock handling
4fa9d8219ec9 drm/i915/dp: Add support for "4:2:0 also" modes for DP
691f4682d81c drm/i915/dp: Duplicate native HDMI TMDS clock limit handling for DP HDMI DFPs
5cb79817652f drm/i915/dp: Fix DFP rgb->ycbcr conversion matrix
87eef2b6e776 drm/i915/dp: Disable DFP RGB->YCbCr conversion for now

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix up DP DFP 4:2:0 handling more

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5493 bytes --]

== Series Details ==

Series: drm/i915: Fix up DP DFP 4:2:0 handling more
URL   : https://patchwork.freedesktop.org/series/95881/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10743 -> Patchwork_21355
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/index.html

Known issues
------------

  Here are the changes found in Patchwork_21355 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [PASS][1] -> [INCOMPLETE][2] ([i915#3921])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@prime_vgem@basic-userptr:
    - fi-pnv-d510:        NOTRUN -> [SKIP][3] ([fdo#109271]) +48 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/fi-pnv-d510/igt@prime_vgem@basic-userptr.html

  
#### Possible fixes ####

  * igt@gem_exec_parallel@engines@userptr:
    - fi-pnv-d510:        [INCOMPLETE][4] ([i915#299]) -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/fi-pnv-d510/igt@gem_exec_parallel@engines@userptr.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/fi-pnv-d510/igt@gem_exec_parallel@engines@userptr.html

  * igt@kms_flip@basic-flip-vs-modeset@c-dp1:
    - fi-cfl-8109u:       [FAIL][6] ([i915#4165]) -> [PASS][7] +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html

  * igt@kms_flip@basic-plain-flip@c-dp2:
    - fi-cfl-8109u:       [DMESG-WARN][8] ([i915#295]) -> [PASS][9] +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp2.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp2.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cml-u2:          [DMESG-WARN][10] ([i915#4269]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html

  
#### Warnings ####

  * igt@kms_flip@basic-plain-flip@c-dp1:
    - fi-cfl-8109u:       [DMESG-WARN][12] ([i915#295]) -> [FAIL][13] ([i915#4165])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#299]: https://gitlab.freedesktop.org/drm/intel/issues/299
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269


Participating hosts (39 -> 34)
------------------------------

  Missing    (5): fi-jsl-1 fi-bdw-5557u bat-dg1-6 fi-hsw-4200u fi-bsw-cyan 


Build changes
-------------

  * Linux: CI_DRM_10743 -> Patchwork_21355

  CI-20190529: 20190529
  CI_DRM_10743: 12c88a23f431212268d7d4d16d313f1d8661c7e5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6250: 3c2ac88757f0d0ac9450487d314fcaceebc8bc26 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21355: 87eef2b6e776be70f6074713edc4f492afa4bb38 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

87eef2b6e776 drm/i915/dp: Disable DFP RGB->YCbCr conversion for now
5cb79817652f drm/i915/dp: Fix DFP rgb->ycbcr conversion matrix
691f4682d81c drm/i915/dp: Duplicate native HDMI TMDS clock limit handling for DP HDMI DFPs
4fa9d8219ec9 drm/i915/dp: Add support for "4:2:0 also" modes for DP
ec45d7b88657 drm/i915/dp: Rework HDMI DFP TMDS clock handling
86076600d89d drm/i915/dp: Make intel_dp_output_format() usable for "4:2:0 also" modes
d1f3604570ee drm/i915/dp: Pass around intel_connector rather than drm_connector
77d2c530f843 drm/i915/dp: Reorder intel_dp_compute_config() a bit
759fa68f70a0 drm/i915/dp: s/intel_dp_hdmi_ycbcr420/intel_dp_is_ycbcr420/
04ab0ef5104e drm/i915/dp: Extract intel_dp_has_audio()
3c125fcf5842 drm/i915/dp: Respect the sink's max TMDS clock when dealing with DP->HDMI DFPs
b20dd4ac5782 drm/i915/dp: Extract intel_dp_tmds_clock_valid()
a2ebf755d8ec drm/i915/dp: Reuse intel_hdmi_tmds_clock()
c1aab421454c drm/i915/hdmi: Simplify intel_hdmi_mode_clock_valid()
5300f80e58b7 drm/i915/hdmi: Clean up TMDS clock limit exceeding user mode handling
cfdd62a9b76f drm/i915/hdmi: Extract intel_hdmi_output_format()
2f30c6c7e076 drm/i915/hdmi: Unify "4:2:0 also" logic between .mode_valid() and .compute_config()
7d2c8095b108 drm/i915/hdmi: Introduce intel_hdmi_tmds_clock()
070dfafd959a drm/i915/hdmi: Introduce intel_hdmi_is_ycbr420()
da10a92856b4 drm/i915/hdmi: Split intel_hdmi_bpc_possible() to source vs. sink pair

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/index.html

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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix up DP DFP 4:2:0 handling more

[Patchwork]

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== Series Details ==

Series: drm/i915: Fix up DP DFP 4:2:0 handling more
URL   : https://patchwork.freedesktop.org/series/95881/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10743_full -> Patchwork_21355_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_21355_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21355_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_21355_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_bw@linear-tiling-3-displays-1920x1080p:
    - shard-apl:          NOTRUN -> [DMESG-FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-apl2/igt@kms_bw@linear-tiling-3-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-3-displays-2560x1440p:
    - shard-skl:          NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl2/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html

  
#### Warnings ####

  * igt@kms_bw@linear-tiling-2-displays-1920x1080p:
    - shard-kbl:          [DMESG-FAIL][3] ([i915#4298]) -> [DMESG-FAIL][4] +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-kbl2/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-kbl7/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
    - shard-iclb:         [DMESG-FAIL][5] ([i915#4298]) -> [DMESG-FAIL][6] +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-iclb2/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-iclb2/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-2-displays-3840x2160p:
    - shard-skl:          [DMESG-FAIL][7] ([i915#4298]) -> [DMESG-FAIL][8] +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-skl3/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl3/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-4-displays-1920x1080p:
    - shard-apl:          [DMESG-FAIL][9] ([i915#4298]) -> [DMESG-FAIL][10] +3 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-apl2/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-apl3/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html

  
Known issues
------------

  Here are the changes found in Patchwork_21355_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-apl:          NOTRUN -> [DMESG-WARN][11] ([i915#3002])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-apl8/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@engines-hostile@vecs0:
    - shard-apl:          [PASS][12] -> [FAIL][13] ([i915#2410])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-apl7/igt@gem_ctx_persistence@engines-hostile@vecs0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-apl7/igt@gem_ctx_persistence@engines-hostile@vecs0.html

  * igt@gem_ctx_persistence@idempotent:
    - shard-snb:          NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1099]) +3 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-snb6/igt@gem_ctx_persistence@idempotent.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [PASS][15] -> [TIMEOUT][16] ([i915#2369] / [i915#3063] / [i915#3648])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-tglb6/igt@gem_eio@unwedge-stress.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb6/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][17] ([i915#2842])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-kbl:          [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-kbl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-kbl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-kbl:          NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2190])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-kbl6/igt@gem_huc_copy@huc-copy.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([i915#644])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-skl7/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl7/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_pread@exhaustion:
    - shard-snb:          NOTRUN -> [WARN][23] ([i915#2658])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-snb7/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-glk:          NOTRUN -> [WARN][24] ([i915#2658])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-glk6/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - shard-tglb:         NOTRUN -> [SKIP][25] ([i915#4270]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@gem_pxp@regular-baseline-src-copy-readible.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][26] ([i915#3297]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb6/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-skl:          NOTRUN -> [FAIL][27] ([i915#3318])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl2/igt@gem_userptr_blits@vma-merge.html

  * igt@gen3_mixed_blits:
    - shard-tglb:         NOTRUN -> [SKIP][28] ([fdo#109289])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@gen3_mixed_blits.html

  * igt@gen3_render_tiledy_blits:
    - shard-iclb:         NOTRUN -> [SKIP][29] ([fdo#109289])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-iclb3/igt@gen3_render_tiledy_blits.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-tglb:         NOTRUN -> [SKIP][30] ([i915#2856]) +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_pm_backlight@fade_with_suspend:
    - shard-tglb:         [PASS][31] -> [INCOMPLETE][32] ([i915#456])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-tglb1/igt@i915_pm_backlight@fade_with_suspend.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb7/igt@i915_pm_backlight@fade_with_suspend.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][33] ([i915#4281])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#111644] / [i915#1397] / [i915#2411])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb2/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-tglb:         NOTRUN -> [SKIP][35] ([fdo#109506] / [i915#2411])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          [PASS][36] -> [INCOMPLETE][37] ([i915#3921])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-snb5/igt@i915_selftest@live@hangcheck.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-snb6/igt@i915_selftest@live@hangcheck.html

  * igt@i915_suspend@forcewake:
    - shard-apl:          [PASS][38] -> [DMESG-WARN][39] ([i915#180])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-apl8/igt@i915_suspend@forcewake.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-apl3/igt@i915_suspend@forcewake.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([i915#3826])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][41] ([fdo#111614]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb6/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-glk:          NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3777])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-glk6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
    - shard-tglb:         NOTRUN -> [SKIP][43] ([fdo#111615]) +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb2/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3777]) +1 similar issue
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-apl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_joiner@basic:
    - shard-tglb:         NOTRUN -> [SKIP][45] ([i915#2705])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb2/igt@kms_big_joiner@basic.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3886]) +2 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl2/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][47] ([fdo#109271]) +36 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-glk6/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][48] ([i915#3689] / [i915#3886]) +1 similar issue
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886]) +3 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-apl2/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#3886]) +2 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-glk6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][51] ([i915#3689]) +9 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb2/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html

  * igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][52] ([fdo#109278])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-iclb3/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-tglb:         NOTRUN -> [SKIP][53] ([i915#3742])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium@hdmi-audio:
    - shard-glk:          NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-glk6/igt@kms_chamelium@hdmi-audio.html

  * igt@kms_chamelium@vga-hpd-for-each-pipe:
    - shard-skl:          NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl9/igt@kms_chamelium@vga-hpd-for-each-pipe.html

  * igt@kms_color_chamelium@pipe-c-ctm-0-25:
    - shard-apl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-apl8/igt@kms_color_chamelium@pipe-c-ctm-0-25.html

  * igt@kms_color_chamelium@pipe-c-ctm-negative:
    - shard-kbl:          NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-kbl6/igt@kms_color_chamelium@pipe-c-ctm-negative.html

  * igt@kms_color_chamelium@pipe-d-ctm-0-5:
    - shard-snb:          NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +14 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-snb6/igt@kms_color_chamelium@pipe-d-ctm-0-5.html

  * igt@kms_color_chamelium@pipe-d-ctm-max:
    - shard-tglb:         NOTRUN -> [SKIP][59] ([fdo#109284] / [fdo#111827]) +8 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb6/igt@kms_color_chamelium@pipe-d-ctm-max.html

  * igt@kms_content_protection@legacy:
    - shard-tglb:         NOTRUN -> [SKIP][60] ([fdo#111828])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x10-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][61] ([i915#3359]) +4 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-32x10-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-512x512-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][62] ([fdo#109279] / [i915#3359]) +1 similar issue
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-512x512-rapid-movement.html

  * igt@kms_cursor_crc@pipe-d-cursor-suspend:
    - shard-tglb:         [PASS][63] -> [INCOMPLETE][64] ([i915#2411] / [i915#4211])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
    - shard-iclb:         NOTRUN -> [SKIP][65] ([fdo#109274] / [fdo#109278])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-iclb3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-glk:          NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#533])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-glk6/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
    - shard-apl:          NOTRUN -> [SKIP][67] ([fdo#109271]) +76 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-apl8/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend@a-edp1:
    - shard-tglb:         [PASS][68] -> [INCOMPLETE][69] ([i915#2411] / [i915#456])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-tglb2/igt@kms_flip@flip-vs-suspend@a-edp1.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb7/igt@kms_flip@flip-vs-suspend@a-edp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
    - shard-skl:          [PASS][70] -> [FAIL][71] ([i915#2122]) +1 similar issue
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
    - shard-snb:          NOTRUN -> [SKIP][72] ([fdo#109271]) +300 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-snb6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html

  * igt@kms_frontbuffer_tracking@fbc-farfromfence-mmap-gtt:
    - shard-skl:          NOTRUN -> [SKIP][73] ([fdo#109271]) +37 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl2/igt@kms_frontbuffer_tracking@fbc-farfromfence-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
    - shard-kbl:          NOTRUN -> [SKIP][74] ([fdo#109271]) +32 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-kbl6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-pwrite:
    - shard-tglb:         NOTRUN -> [SKIP][75] ([fdo#111825]) +16 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-pwrite.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][76] -> [FAIL][77] ([i915#1188]) +1 similar issue
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][78] ([i915#1187])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb6/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
    - shard-kbl:          NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#533])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-kbl6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-glk:          NOTRUN -> [FAIL][80] ([i915#265])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-glk6/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_lowres@pipe-b-tiling-none:
    - shard-tglb:         NOTRUN -> [SKIP][81] ([i915#3536])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb2/igt@kms_plane_lowres@pipe-b-tiling-none.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
    - shard-glk:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#658]) +1 similar issue
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-glk6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
    - shard-apl:          NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#658])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-apl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
    - shard-skl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
    - shard-kbl:          NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#658]) +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-kbl6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-tglb:         NOTRUN -> [SKIP][86] ([i915#1911])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-tglb:         NOTRUN -> [FAIL][87] ([i915#132] / [i915#3467])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame:
    - shard-tglb:         NOTRUN -> [SKIP][88] ([i915#2530]) +1 similar issue
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb2/igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame.html

  * igt@prime_nv_api@i915_self_import_to_different_fd:
    - shard-tglb:         NOTRUN -> [SKIP][89] ([fdo#109291]) +2 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@prime_nv_api@i915_self_import_to_different_fd.html

  * igt@prime_vgem@fence-read-hang:
    - shard-tglb:         NOTRUN -> [SKIP][90] ([fdo#109295])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb2/igt@prime_vgem@fence-read-hang.html

  * igt@sysfs_clients@fair-0:
    - shard-skl:          NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2994])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl2/igt@sysfs_clients@fair-0.html

  * igt@sysfs_clients@sema-10:
    - shard-glk:          NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#2994])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-glk6/igt@sysfs_clients@sema-10.html

  * igt@sysfs_clients@sema-25:
    - shard-apl:          NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#2994])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-apl8/igt@sysfs_clients@sema-25.html

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-contexts-immediate:
    - shard-iclb:         [TIMEOUT][94] ([i915#3070]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-iclb1/igt@gem_eio@in-flight-contexts-immediate.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-iclb3/igt@gem_eio@in-flight-contexts-immediate.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [FAIL][96] ([i915#2842]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-glk:          [FAIL][98] ([i915#2842] / [i915#3468]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-glk1/igt@gem_exec_fair@basic-none@vecs0.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-glk4/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          [FAIL][100] ([i915#2842]) -> [PASS][101] +2 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][102] ([i915#454]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-iclb6/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_suspend@debugfs-reader:
    - shard-tglb:         [INCOMPLETE][104] ([i915#456]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-tglb7/igt@i915_suspend@debugfs-reader.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb2/igt@i915_suspend@debugfs-reader.html

  * igt@i915_suspend@forcewake:
    - shard-skl:          [INCOMPLETE][106] ([i915#636]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-skl3/igt@i915_suspend@forcewake.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl2/igt@i915_suspend@forcewake.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [FAIL][108] ([i915#2346]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-edp1:
    - shard-skl:          [FAIL][110] ([i915#2122]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-skl7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-edp1.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1:
    - shard-kbl:          [FAIL][112] ([i915#79]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-kbl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-kbl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-skl:          [FAIL][114] ([i915#79]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-kbl:          [DMESG-WARN][116] ([i915#180]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][118] ([fdo#108145] / [i915#265]) -> [PASS][119] +1 similar issue
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
    - shard-tglb:         [INCOMPLETE][120] ([i915#2828] / [i915#456]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-tglb7/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb1/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html

  * igt@perf@polling-small-buf:
    - shard-skl:          [FAIL][122] ([i915#1722]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-skl2/igt@perf@polling-small-buf.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl9/igt@perf@polling-small-buf.html

  
#### Warnings ####

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         [FAIL][124] ([i915#2842]) -> [FAIL][125] ([i915#2852])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-iclb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-iclb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-tglb:         [SKIP][126] ([i915#2848]) -> [FAIL][127] ([i915#2842])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-tglb8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb8/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-tglb:         [FAIL][128] ([i915#2851]) -> [FAIL][129] ([i915#2842])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-tglb6/igt@gem_exec_fair@basic-pace@rcs0.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb3/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][130] ([i915#2684]) -> [WARN][131] ([i915#1804] / [i915#2684]) +1 similar issue
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-tglb:         [WARN][132] ([i915#2681] / [i915#2684]) -> [FAIL][133] ([i915#2681] / [i915#3591])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-tglb6/igt@i915_pm_rc6_residency@rc6-idle.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-tglb3/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-skl:          [FAIL][134] ([i915#3722]) -> [FAIL][135] ([i915#3743])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10743/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/shard-skl

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21355/index.html

[-- Attachment #2: Type: text/html, Size: 33618 bytes --]

Re: [Intel-gfx] [PATCH 03/20] drm/i915/hdmi: Introduce intel_hdmi_tmds_clock()

[Jani Nikula]

On Fri, 15 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename intel_hdmi_port_clock() into intel_hdmi_tmds_clock(), and
> move the 4:2:0 TMDS clock halving into intel_hdmi_tmds_clock() so
> the callers don't have to worry about such details.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 25 +++++++++++------------
>  1 file changed, 12 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 37ce8a621973..e97c83535965 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1868,8 +1868,12 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
>  	return MODE_OK;
>  }
>  
> -static int intel_hdmi_port_clock(int clock, int bpc)
> +static int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
>  {
> +	/* YCBCR420 TMDS rate requirement is half the pixel clock */
> +	if (ycbcr420_output)
> +		clock /= 2;
> +
>  	/*
>  	 * Need to adjust the port link by:
>  	 *  1.5x for 12bpc
> @@ -1932,25 +1936,22 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
>  	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
>  	enum drm_mode_status status;
>  
> -	if (ycbcr420_output)
> -		clock /= 2;
> -
>  	/* check if we can do 8bpc */
> -	status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
> +	status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 8, ycbcr420_output),
>  				       true, has_hdmi_sink);
>  
>  	/* if we can't do 8bpc we may still be able to do 12bpc */
>  	if (status != MODE_OK &&
>  	    intel_hdmi_source_bpc_possible(i915, 12) &&
>  	    intel_hdmi_sink_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output))
> -		status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12),
> +		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 12, ycbcr420_output),
>  					       true, has_hdmi_sink);
>  
>  	/* if we can't do 8,12bpc we may still be able to do 10bpc */
>  	if (status != MODE_OK &&
>  	    intel_hdmi_source_bpc_possible(i915, 10) &&
>  	    intel_hdmi_sink_bpc_possible(connector, 10, has_hdmi_sink, ycbcr420_output))
> -		status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10),
> +		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 10, ycbcr420_output),
>  					       true, has_hdmi_sink);
>  
>  	return status;
> @@ -2057,12 +2058,13 @@ static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
>  				  int clock)
>  {
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
> +	bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
>  	int bpc;
>  
>  	for (bpc = 12; bpc >= 10; bpc -= 2) {
>  		if (hdmi_deep_color_possible(crtc_state, bpc) &&
>  		    hdmi_port_clock_valid(intel_hdmi,
> -					  intel_hdmi_port_clock(clock, bpc),
> +					  intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output),

Does not having the clock /= 2 here mean the check was bogus before this
patch?

BR,
Jani.


>  					  true, crtc_state->has_hdmi_sink) == MODE_OK)
>  			return bpc;
>  	}
> @@ -2082,13 +2084,10 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
>  		clock *= 2;
>  
> -	/* YCBCR420 TMDS rate requirement is half the pixel clock */
> -	if (intel_hdmi_is_ycbcr420(crtc_state))
> -		clock /= 2;
> -
>  	bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
>  
> -	crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
> +	crtc_state->port_clock = intel_hdmi_tmds_clock(clock, bpc,
> +						       intel_hdmi_is_ycbcr420(crtc_state));
>  
>  	/*
>  	 * pipe_bpp could already be below 8bpc due to

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 03/20] drm/i915/hdmi: Introduce intel_hdmi_tmds_clock()

[Ville Syrjälä]

On Tue, Oct 19, 2021 at 09:16:33PM +0300, Jani Nikula wrote:
> On Fri, 15 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Rename intel_hdmi_port_clock() into intel_hdmi_tmds_clock(), and
> > move the 4:2:0 TMDS clock halving into intel_hdmi_tmds_clock() so
> > the callers don't have to worry about such details.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_hdmi.c | 25 +++++++++++------------
> >  1 file changed, 12 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 37ce8a621973..e97c83535965 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -1868,8 +1868,12 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> >  	return MODE_OK;
> >  }
> >  
> > -static int intel_hdmi_port_clock(int clock, int bpc)
> > +static int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
> >  {
> > +	/* YCBCR420 TMDS rate requirement is half the pixel clock */
> > +	if (ycbcr420_output)
> > +		clock /= 2;
> > +
> >  	/*
> >  	 * Need to adjust the port link by:
> >  	 *  1.5x for 12bpc
> > @@ -1932,25 +1936,22 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
> >  	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
> >  	enum drm_mode_status status;
> >  
> > -	if (ycbcr420_output)
> > -		clock /= 2;
> > -
> >  	/* check if we can do 8bpc */
> > -	status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
> > +	status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 8, ycbcr420_output),
> >  				       true, has_hdmi_sink);
> >  
> >  	/* if we can't do 8bpc we may still be able to do 12bpc */
> >  	if (status != MODE_OK &&
> >  	    intel_hdmi_source_bpc_possible(i915, 12) &&
> >  	    intel_hdmi_sink_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output))
> > -		status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12),
> > +		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 12, ycbcr420_output),
> >  					       true, has_hdmi_sink);
> >  
> >  	/* if we can't do 8,12bpc we may still be able to do 10bpc */
> >  	if (status != MODE_OK &&
> >  	    intel_hdmi_source_bpc_possible(i915, 10) &&
> >  	    intel_hdmi_sink_bpc_possible(connector, 10, has_hdmi_sink, ycbcr420_output))
> > -		status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10),
> > +		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 10, ycbcr420_output),
> >  					       true, has_hdmi_sink);
> >  
> >  	return status;
> > @@ -2057,12 +2058,13 @@ static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
> >  				  int clock)
> >  {
> >  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
> > +	bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
> >  	int bpc;
> >  
> >  	for (bpc = 12; bpc >= 10; bpc -= 2) {
> >  		if (hdmi_deep_color_possible(crtc_state, bpc) &&
> >  		    hdmi_port_clock_valid(intel_hdmi,
> > -					  intel_hdmi_port_clock(clock, bpc),
> > +					  intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output),
> 
> Does not having the clock /= 2 here mean the check was bogus before this
> patch?

Previously the /2 was done by the caller (intel_hdmi_compute_clock()).
So nothing should be different here.

> 
> BR,
> Jani.
> 
> 
> >  					  true, crtc_state->has_hdmi_sink) == MODE_OK)
> >  			return bpc;
> >  	}
> > @@ -2082,13 +2084,10 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
> >  	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
> >  		clock *= 2;
> >  
> > -	/* YCBCR420 TMDS rate requirement is half the pixel clock */
> > -	if (intel_hdmi_is_ycbcr420(crtc_state))
> > -		clock /= 2;
> > -
> >  	bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
> >  
> > -	crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
> > +	crtc_state->port_clock = intel_hdmi_tmds_clock(clock, bpc,
> > +						       intel_hdmi_is_ycbcr420(crtc_state));
> >  
> >  	/*
> >  	 * pipe_bpp could already be below 8bpc due to
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 05/20] drm/i915/hdmi: Extract intel_hdmi_output_format()

[Jani Nikula]

On Fri, 15 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reorganize the HDMI 4:2:0 handling a bit by introducing
> intel_hdmi_output_format(). We already have the DP counterpart
> and I want to unify the 4:2:0 handling across both a bit.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Patches 1-5,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 35 ++++++++++++++---------
>  1 file changed, 22 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 18e7ef125827..7e6af959bf83 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2157,34 +2157,43 @@ static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
>  		return intel_conn_state->force_audio == HDMI_AUDIO_ON;
>  }
>  
> +static enum intel_output_format
> +intel_hdmi_output_format(struct intel_connector *connector,
> +			 bool ycbcr_420_output)
> +{
> +	if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
> +		return INTEL_OUTPUT_FORMAT_YCBCR420;
> +	else
> +		return INTEL_OUTPUT_FORMAT_RGB;
> +}
> +
>  static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
>  					    struct intel_crtc_state *crtc_state,
>  					    const struct drm_connector_state *conn_state)
>  {
> -	struct drm_connector *connector = conn_state->connector;
> -	struct drm_i915_private *i915 = to_i915(connector->dev);
> +	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	const struct drm_display_info *info = &connector->base.display_info;
> +	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
>  	int ret;
> -	bool ycbcr_420_only;
>  
> -	ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, adjusted_mode);
> -	if (connector->ycbcr_420_allowed && ycbcr_420_only) {
> -		crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> -	} else {
> -		if (!connector->ycbcr_420_allowed && ycbcr_420_only)
> -			drm_dbg_kms(&i915->drm,
> -				    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
> +	crtc_state->output_format = intel_hdmi_output_format(connector, ycbcr_420_only);
> +
> +	if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
> +		drm_dbg_kms(&i915->drm,
> +			    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
>  		crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
>  	}
>  
>  	ret = intel_hdmi_compute_clock(encoder, crtc_state);
>  	if (ret) {
>  		if (intel_hdmi_is_ycbcr420(crtc_state) ||
> -		    !connector->ycbcr_420_allowed ||
> -		    !drm_mode_is_420_also(&connector->display_info, adjusted_mode))
> +		    !connector->base.ycbcr_420_allowed ||
> +		    !drm_mode_is_420_also(info, adjusted_mode))
>  			return ret;
>  
> -		crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> +		crtc_state->output_format = intel_hdmi_output_format(connector, true);
>  		ret = intel_hdmi_compute_clock(encoder, crtc_state);
>  	}

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 00/20] drm/i915: Fix up DP DFP 4:2:0 handling more

[Nautiyal, Ankit K]

Hi Ville,

Thanks for the patch and getting a unified approach for DP, HDMI and DFP 
for YCbCr420 output.

I am trying to have 8k@60 YUV420 via an HDMI2.1 PCON, without having to 
use PCONs Color conversion capability,

but running into different issues, and failing miserably. I think this 
patch series will help get there.

There are a couple of queries and suggestions I have regarding the big 
joiner and DSC, which I'll reply to the patches.

I will also try to test these on the setup I have available.

Thanks & Regards,

Ankit

On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently we're failing to respect the sink's max TMDS clock
> in the DP HDMI DFP code, and exceeding them means the sink
> won't show a picture [1]. So let's improve the situation by
> checking those limits, and generally fixing up a bunch things
> in the deep color/4:2:0 related stuff for both native HDMI
> and DP HDMI DFPs.
>
> The end result is fairly unified apporach to this stuff on
> both sides of the aisle. There's probably more we could try
> to abstract to share even more code. But that will need a lot
> of actual thought so leave it for later.
>
> The high level algorithm is basically now:
> for_each(respect TMDS clock limits, disrespect TMDS clock limits)
> 	for_each(YCbCr 4:2:0 only, RGB 4:4:4, YCbCr 4:2:0 also)
> 		for_each(12bpc,10bpc,8bpc)
> 			compute_and_check_the_things
> with some obvious tweaks for HDMI vs. DP specifics.
>
> [1] https://gitlab.freedesktop.org/drm/intel/-/issues/4095
>
> Ville Syrjälä (20):
>    drm/i915/hdmi: Split intel_hdmi_bpc_possible() to source vs. sink pair
>    drm/i915/hdmi: Introduce intel_hdmi_is_ycbr420()
>    drm/i915/hdmi: Introduce intel_hdmi_tmds_clock()
>    drm/i915/hdmi: Unify "4:2:0 also" logic between .mode_valid() and
>      .compute_config()
>    drm/i915/hdmi: Extract intel_hdmi_output_format()
>    drm/i915/hdmi: Clean up TMDS clock limit exceeding user mode handling
>    drm/i915/hdmi: Simplify intel_hdmi_mode_clock_valid()
>    drm/i915/dp: Reuse intel_hdmi_tmds_clock()
>    drm/i915/dp: Extract intel_dp_tmds_clock_valid()
>    drm/i915/dp: Respect the sink's max TMDS clock when dealing with
>      DP->HDMI DFPs
>    drm/i915/dp: Extract intel_dp_has_audio()
>    drm/i915/dp: s/intel_dp_hdmi_ycbcr420/intel_dp_is_ycbcr420/
>    drm/i915/dp: Reorder intel_dp_compute_config() a bit
>    drm/i915/dp: Pass around intel_connector rather than drm_connector
>    drm/i915/dp: Make intel_dp_output_format() usable for "4:2:0 also"
>      modes
>    drm/i915/dp: Rework HDMI DFP TMDS clock handling
>    drm/i915/dp: Add support for "4:2:0 also" modes for DP
>    drm/i915/dp: Duplicate native HDMI TMDS clock limit handling for DP
>      HDMI DFPs
>    drm/i915/dp: Fix DFP rgb->ycbcr conversion matrix
>    drm/i915/dp: Disable DFP RGB->YCbCr conversion for now
>
>   drivers/gpu/drm/i915/display/intel_dp.c   | 339 +++++++++++++---------
>   drivers/gpu/drm/i915/display/intel_hdmi.c | 220 ++++++++------
>   drivers/gpu/drm/i915/display/intel_hdmi.h |   5 +-
>   3 files changed, 342 insertions(+), 222 deletions(-)
>

Re: [Intel-gfx] [PATCH 13/20] drm/i915/dp: Reorder intel_dp_compute_config() a bit

[Nautiyal, Ankit K]

On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Consolidate the double pfit call, and reorder things so that
> intel_dp_output_format() and intel_dp_compute_link_config() are
> back-to-back. They are intimately related, and will need to be
> called twice to properly handle the "4:2:0 also" modes.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_dp.c | 23 ++++++++++-------------
>   1 file changed, 10 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2440a6a2e4fc..de2b3d33a726 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1764,25 +1764,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
>   		pipe_config->has_pch_encoder = true;
>   
> -	pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
> -							    adjusted_mode);
> -
> -	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
> -		ret = intel_panel_fitting(pipe_config, conn_state);
> -		if (ret)
> -			return ret;
> -	}
> -
>   	pipe_config->has_audio = intel_dp_has_audio(encoder, pipe_config, conn_state);
>   
>   	if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
>   		ret = intel_panel_compute_config(intel_connector, adjusted_mode);
>   		if (ret)
>   			return ret;
> -
> -		ret = intel_panel_fitting(pipe_config, conn_state);
> -		if (ret)
> -			return ret;
>   	}
>   
>   	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> @@ -1798,10 +1785,20 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
>   		return -EINVAL;
>   
> +	pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
> +							    adjusted_mode);
> +
>   	ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
>   	if (ret < 0)
>   		return ret;
>   
> +	if ((intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) ||
> +	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
> +		ret = intel_panel_fitting(pipe_config, conn_state);

Panel fitting code will perhaps need handling for Big joiner.

In case of bigjoiner, we might need to set the pch_pfit->dest width 
halved, otherwise we might have scaler width going out of bound.

Now that we already have pipe_config->bigjoiner set, we can use it in 
pch_panel_fitting( ) to tweak dest width.

Something like 
https://github.com/aknautiyal/drm-tip/commit/c15060be2eca81738f8f0d3431e04215777edfc9

Regards,

Ankit

> +		if (ret)
> +			return ret;
> +	}
> +
>   	pipe_config->limited_color_range =
>   		intel_dp_limited_color_range(pipe_config, conn_state);
>   

Re: [Intel-gfx] [PATCH 20/20] drm/i915/dp: Disable DFP RGB->YCbCr conversion for now

[Nautiyal, Ankit K]

On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We lack sufficient state tracking to figure out whether
> we want the DFP to perform the RGB->YCbCr conversion for us
> or not. So currently we are blindly just enabling that all the
> time when supported by the DFP. That is nonsense. So until
> we imporve our state tracking for this just disable the feature.
>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 29b12456c461..3e2a29b589a9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1107,6 +1107,7 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
>   static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
>   				 const struct intel_crtc_state *crtc_state)
>   {
> +	/* FIXME see intel_dp_update_420() regarding rgb_to_ycbcr */
>   	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>   		(crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
>   		 intel_dp->dfp.ycbcr_444_to_420);
> @@ -2456,6 +2457,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>   			    "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
>   			    enabledisable(intel_dp->dfp.ycbcr_444_to_420));
>   
> +	/* FIXME see intel_dp_update_420() regarding rgb_to_ycbcr */
>   	tmp = intel_dp->dfp.rgb_to_ycbcr ?
>   		DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
>   
> @@ -4261,6 +4263,14 @@ intel_dp_update_420(struct intel_dp *intel_dp)
>   	rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
>   								 intel_dp->downstream_ports,
>   								 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
> +	/*
> +	 * FIXME need to actually track whether we're really
> +	 * going to be doing the RGB->YCbCr connversion or not.
> +	 * We can't tell by simply looking at intel_dp->dfp.rgb_to_ycbcr.
> +	 * Readout is going to annoying due to having to read that
> +	 * state from external hardware that may vanish at any time :(
> +	 */


Hmm right. Do you have any suggestion what should be the better place 
for defining the policy for using DFPs CSC or use our own HW, in case of 
YCbCr 420 output?

Also, IIUC, this might need consideration for higher modes with DSC1.1 
H/w that do not support compression for YCbCr420.

In that case we might need to either use RGB compressed output and ask 
for DFPs CSC for conversion to 444 and then down sampling to 420.

Regards,

Ankit

> +	rgb_to_ycbcr = false;
>   
>   	if (DISPLAY_VER(i915) >= 11) {
>   		/* Let PCON convert from RGB->YCbCr if possible */

Re: [Intel-gfx] [PATCH 13/20] drm/i915/dp: Reorder intel_dp_compute_config() a bit

[Ville Syrjälä]

On Wed, Oct 27, 2021 at 12:36:17PM +0530, Nautiyal, Ankit K wrote:
> 
> On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Consolidate the double pfit call, and reorder things so that
> > intel_dp_output_format() and intel_dp_compute_link_config() are
> > back-to-back. They are intimately related, and will need to be
> > called twice to properly handle the "4:2:0 also" modes.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_dp.c | 23 ++++++++++-------------
> >   1 file changed, 10 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 2440a6a2e4fc..de2b3d33a726 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1764,25 +1764,12 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> >   	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
> >   		pipe_config->has_pch_encoder = true;
> >   
> > -	pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
> > -							    adjusted_mode);
> > -
> > -	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
> > -		ret = intel_panel_fitting(pipe_config, conn_state);
> > -		if (ret)
> > -			return ret;
> > -	}
> > -
> >   	pipe_config->has_audio = intel_dp_has_audio(encoder, pipe_config, conn_state);
> >   
> >   	if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
> >   		ret = intel_panel_compute_config(intel_connector, adjusted_mode);
> >   		if (ret)
> >   			return ret;
> > -
> > -		ret = intel_panel_fitting(pipe_config, conn_state);
> > -		if (ret)
> > -			return ret;
> >   	}
> >   
> >   	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> > @@ -1798,10 +1785,20 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> >   	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
> >   		return -EINVAL;
> >   
> > +	pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
> > +							    adjusted_mode);
> > +
> >   	ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
> >   	if (ret < 0)
> >   		return ret;
> >   
> > +	if ((intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) ||
> > +	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
> > +		ret = intel_panel_fitting(pipe_config, conn_state);
> 
> Panel fitting code will perhaps need handling for Big joiner.
> 
> In case of bigjoiner, we might need to set the pch_pfit->dest width 
> halved, otherwise we might have scaler width going out of bound.

Yes pfit vs. bigjoiner is known to be 100% broken.

> 
> Now that we already have pipe_config->bigjoiner set, we can use it in 
> pch_panel_fitting( ) to tweak dest width.
> 
> Something like 
> https://github.com/aknautiyal/drm-tip/commit/c15060be2eca81738f8f0d3431e04215777edfc9

Hmm. I gues that would be sufficient for the fullscreen case.
And we should probably just -EINVAL the other cases for now.

Actually doing borders correctly with bigjoiner would involve
doing this after/during the bigjoiner state copy.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 20/20] drm/i915/dp: Disable DFP RGB->YCbCr conversion for now

[Ville Syrjälä]

On Wed, Oct 27, 2021 at 12:57:37PM +0530, Nautiyal, Ankit K wrote:
> 
> On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We lack sufficient state tracking to figure out whether
> > we want the DFP to perform the RGB->YCbCr conversion for us
> > or not. So currently we are blindly just enabling that all the
> > time when supported by the DFP. That is nonsense. So until
> > we imporve our state tracking for this just disable the feature.
> >
> > Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > Cc: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 29b12456c461..3e2a29b589a9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1107,6 +1107,7 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> >   static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
> >   				 const struct intel_crtc_state *crtc_state)
> >   {
> > +	/* FIXME see intel_dp_update_420() regarding rgb_to_ycbcr */
> >   	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> >   		(crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
> >   		 intel_dp->dfp.ycbcr_444_to_420);
> > @@ -2456,6 +2457,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
> >   			    "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
> >   			    enabledisable(intel_dp->dfp.ycbcr_444_to_420));
> >   
> > +	/* FIXME see intel_dp_update_420() regarding rgb_to_ycbcr */
> >   	tmp = intel_dp->dfp.rgb_to_ycbcr ?
> >   		DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
> >   
> > @@ -4261,6 +4263,14 @@ intel_dp_update_420(struct intel_dp *intel_dp)
> >   	rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
> >   								 intel_dp->downstream_ports,
> >   								 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
> > +	/*
> > +	 * FIXME need to actually track whether we're really
> > +	 * going to be doing the RGB->YCbCr connversion or not.
> > +	 * We can't tell by simply looking at intel_dp->dfp.rgb_to_ycbcr.
> > +	 * Readout is going to annoying due to having to read that
> > +	 * state from external hardware that may vanish at any time :(
> > +	 */
> 
> 
> Hmm right. Do you have any suggestion what should be the better place 
> for defining the policy for using DFPs CSC or use our own HW, in case of 
> YCbCr 420 output?

One idea that came to mind was just adding some kind of
sink_format thing into the crtc_state, and computing that appropriately
during .compute_config(). But as mentioned the readout part is going to
be annoying. Maybe we just won't have readout for it.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 09/20] drm/i915/dp: Extract intel_dp_tmds_clock_valid()

[Nautiyal, Ankit K]

On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We're currently duplicating the DFP min/max TMDS clock checks
> in .mode_valid() and .compute_config(). Extract a helper suitable
> for both use cases.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_dp.c | 59 +++++++++++--------------
>   1 file changed, 26 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 45e4bf54e1de..b3b8e74fac9c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -781,6 +781,25 @@ static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
>   	return hdisplay == 4096 && !HAS_DDI(dev_priv);
>   }
>   
> +static enum drm_mode_status
> +intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
> +			  int clock, int bpc, bool ycbcr420_output)
> +{
> +	int tmds_clock;
> +
> +	tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
> +
> +	if (intel_dp->dfp.min_tmds_clock &&
> +	    tmds_clock < intel_dp->dfp.min_tmds_clock)
> +		return MODE_CLOCK_LOW;
> +
> +	if (intel_dp->dfp.max_tmds_clock &&
> +	    tmds_clock > intel_dp->dfp.max_tmds_clock)
> +		return MODE_CLOCK_HIGH;
> +
> +	return MODE_OK;
> +}


This looks good to me, a common helper to check if the tmds clock 
calculated for the the bpc selected and 420 format is within the limits 
of the DFP tmds limitations.

There are however some HDMI2.1 protocol converters that support higher 
mode with Fixed Rate Link (where the TMDS clock lane is used as an 
additional lane with hdmi2.1 sinks)

In that case, we would need to skip the tmds check, as the TMDS clock 
will not be sufficient for modes that can be supported with FRL mode, 
and all those higher modes will get pruned.

These PCONs will have additional fields in DPCD caps for maximum FRL 
rate in Gbps (stored in dfp->max_frl_rate), which we can use to check if 
the mode rate would be supported, if FRL mode is used.

I was wondering if we add a similar check for this case or add another 
argument to this function "is_frl_mode" and have the bw check there.


Regards,

Ankit



> +
>   static enum drm_mode_status
>   intel_dp_mode_valid_downstream(struct intel_connector *connector,
>   			       const struct drm_display_mode *mode,
> @@ -788,7 +807,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
>   {
>   	struct intel_dp *intel_dp = intel_attached_dp(connector);
>   	const struct drm_display_info *info = &connector->base.display_info;
> -	int tmds_clock;
>   
>   	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
>   	if (intel_dp->dfp.pcon_max_frl_bw) {
> @@ -814,17 +832,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
>   		return MODE_CLOCK_HIGH;
>   
>   	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
> -	tmds_clock = intel_hdmi_tmds_clock(target_clock, 8,
> -					   drm_mode_is_420_only(info, mode));
> -
> -	if (intel_dp->dfp.min_tmds_clock &&
> -	    tmds_clock < intel_dp->dfp.min_tmds_clock)
> -		return MODE_CLOCK_LOW;
> -	if (intel_dp->dfp.max_tmds_clock &&
> -	    tmds_clock > intel_dp->dfp.max_tmds_clock)
> -		return MODE_CLOCK_HIGH;
> -
> -	return MODE_OK;
> +	return intel_dp_tmds_clock_valid(intel_dp, target_clock, 8,
> +					 drm_mode_is_420_only(info, mode));
>   }
>   
>   static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
> @@ -1069,32 +1078,16 @@ static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
>   		 intel_dp->dfp.ycbcr_444_to_420);
>   }
>   
> -static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
> -					   const struct intel_crtc_state *crtc_state, int bpc)
> -{
> -	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
> -	int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
> -					       intel_dp_hdmi_ycbcr420(intel_dp, crtc_state));
> -
> -	if (intel_dp->dfp.min_tmds_clock &&
> -	    tmds_clock < intel_dp->dfp.min_tmds_clock)
> -		return false;
> -
> -	if (intel_dp->dfp.max_tmds_clock &&
> -	    tmds_clock > intel_dp->dfp.max_tmds_clock)
> -		return false;
> -
> -	return true;
> -}
> -
>   static bool intel_dp_hdmi_bpc_possible(struct intel_dp *intel_dp,
>   				       const struct intel_crtc_state *crtc_state,
>   				       int bpc)
>   {
> +	bool ycbcr420_output = intel_dp_hdmi_ycbcr420(intel_dp, crtc_state);
> +	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
>   
> -	return intel_hdmi_bpc_possible(crtc_state, bpc, intel_dp->has_hdmi_sink,
> -				       intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
> -		intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
> +	return intel_hdmi_bpc_possible(crtc_state, bpc,
> +				       intel_dp->has_hdmi_sink, ycbcr420_output) &&
> +		intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output) == MODE_OK;
>   }
>   
>   static int intel_dp_max_bpp(struct intel_dp *intel_dp,

Re: [Intel-gfx] [PATCH 20/20] drm/i915/dp: Disable DFP RGB->YCbCr conversion for now

[Nautiyal, Ankit K]

On 10/27/2021 2:24 PM, Ville Syrjälä wrote:
> On Wed, Oct 27, 2021 at 12:57:37PM +0530, Nautiyal, Ankit K wrote:
>> On 10/15/2021 7:09 PM, Ville Syrjala wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> We lack sufficient state tracking to figure out whether
>>> we want the DFP to perform the RGB->YCbCr conversion for us
>>> or not. So currently we are blindly just enabling that all the
>>> time when supported by the DFP. That is nonsense. So until
>>> we imporve our state tracking for this just disable the feature.
>>>
>>> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> Cc: Uma Shankar <uma.shankar@intel.com>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++++
>>>    1 file changed, 10 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 29b12456c461..3e2a29b589a9 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -1107,6 +1107,7 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
>>>    static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
>>>    				 const struct intel_crtc_state *crtc_state)
>>>    {
>>> +	/* FIXME see intel_dp_update_420() regarding rgb_to_ycbcr */
>>>    	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>>>    		(crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
>>>    		 intel_dp->dfp.ycbcr_444_to_420);
>>> @@ -2456,6 +2457,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>>>    			    "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
>>>    			    enabledisable(intel_dp->dfp.ycbcr_444_to_420));
>>>    
>>> +	/* FIXME see intel_dp_update_420() regarding rgb_to_ycbcr */
>>>    	tmp = intel_dp->dfp.rgb_to_ycbcr ?
>>>    		DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
>>>    
>>> @@ -4261,6 +4263,14 @@ intel_dp_update_420(struct intel_dp *intel_dp)
>>>    	rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
>>>    								 intel_dp->downstream_ports,
>>>    								 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
>>> +	/*
>>> +	 * FIXME need to actually track whether we're really
>>> +	 * going to be doing the RGB->YCbCr connversion or not.
>>> +	 * We can't tell by simply looking at intel_dp->dfp.rgb_to_ycbcr.
>>> +	 * Readout is going to annoying due to having to read that
>>> +	 * state from external hardware that may vanish at any time :(
>>> +	 */
>>
>> Hmm right. Do you have any suggestion what should be the better place
>> for defining the policy for using DFPs CSC or use our own HW, in case of
>> YCbCr 420 output?
> One idea that came to mind was just adding some kind of
> sink_format thing into the crtc_state, and computing that appropriately
> during .compute_config(). But as mentioned the readout part is going to
> be annoying. Maybe we just won't have readout for it.

Agreed.

As mentioned in the FIX ME, lets have dfp->rgb_to_ycbcr only to capture 
that the dfp supports conversion.

and dfp->ycbcr_444_420 to capture that it supports 444_420.

Whether we need to program the DPCD to avail these support can be 
captured in another member to crtc_state->dp_dfp_444_420, and 
crtc_state->dp_dfp_rgb_ycbcr based on crtc_state->sink_format.

We can fill these members, during compute_config along with dsc 
considerations.

These can then be used in dp_configure_protocol_converter().

Regards,

Ankit

Re: [Intel-gfx] [PATCH 09/20] drm/i915/dp: Extract intel_dp_tmds_clock_valid()

[Ville Syrjälä]

On Fri, Dec 10, 2021 at 10:50:09AM +0530, Nautiyal, Ankit K wrote:
> 
> On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We're currently duplicating the DFP min/max TMDS clock checks
> > in .mode_valid() and .compute_config(). Extract a helper suitable
> > for both use cases.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_dp.c | 59 +++++++++++--------------
> >   1 file changed, 26 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 45e4bf54e1de..b3b8e74fac9c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -781,6 +781,25 @@ static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
> >   	return hdisplay == 4096 && !HAS_DDI(dev_priv);
> >   }
> >   
> > +static enum drm_mode_status
> > +intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
> > +			  int clock, int bpc, bool ycbcr420_output)
> > +{
> > +	int tmds_clock;
> > +
> > +	tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
> > +
> > +	if (intel_dp->dfp.min_tmds_clock &&
> > +	    tmds_clock < intel_dp->dfp.min_tmds_clock)
> > +		return MODE_CLOCK_LOW;
> > +
> > +	if (intel_dp->dfp.max_tmds_clock &&
> > +	    tmds_clock > intel_dp->dfp.max_tmds_clock)
> > +		return MODE_CLOCK_HIGH;
> > +
> > +	return MODE_OK;
> > +}
> 
> 
> This looks good to me, a common helper to check if the tmds clock 
> calculated for the the bpc selected and 420 format is within the limits 
> of the DFP tmds limitations.
> 
> There are however some HDMI2.1 protocol converters that support higher 
> mode with Fixed Rate Link (where the TMDS clock lane is used as an 
> additional lane with hdmi2.1 sinks)
> 
> In that case, we would need to skip the tmds check, as the TMDS clock 
> will not be sufficient for modes that can be supported with FRL mode, 
> and all those higher modes will get pruned.
> 
> These PCONs will have additional fields in DPCD caps for maximum FRL 
> rate in Gbps (stored in dfp->max_frl_rate), which we can use to check if 
> the mode rate would be supported, if FRL mode is used.
> 
> I was wondering if we add a similar check for this case or add another 
> argument to this function "is_frl_mode" and have the bw check there.

I guess we should pull the FRL stuff into its own helper functions,
assuming there is something that can be shared between .mode_valid()
and .compute_config().

But looking at the FRL code it looks a bit sketchy. It doesn't seem
to account for any link bandwidth overhead from the 16b18b encoding
or whatever else overhead there is (the spec seems to have quite a
lot to say on this topic). Also it uses intel_dp_mode_min_output_bpp()
for the bandwidth calculation which seems wrong.
intel_dp_mode_min_output_bpp() deals with the DP side of the link
where min bpc can be as low as 6, but for the HDMI side min bpc
is always 8.

So looks to me like there's a bunch of stuff that needs fixing here.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 06/20] drm/i915/hdmi: Clean up TMDS clock limit exceeding user mode handling

[Lisovskiy, Stanislav]

On Fri, Oct 15, 2021 at 04:39:07PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we just use all the hdmi_deep_color_possible() stuff
> to compute whether deep color is possible, and leave the 8bpc
> case to do its own thing. That doesn't mesh super well with 4:2:0
> handling because we might end up going for 8bpc RGB without
> considering that it's essentially illegal and we could instead
> go for a legal 4:2:0 config.
> 
> So let's run through all the clock checks even for 8bpc first.
> If we've fully exhausted all options only then do we re-run
> the computation for 8bpc while ignoring the downstream TMDS
> clock limits. This will guarantee that if there's a config
> that respects all limits we will find it, and if there is not
> we still allow the user to override the mode manually.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c   | 13 ++--
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 92 +++++++++++++----------
>  drivers/gpu/drm/i915/display/intel_hdmi.h |  4 +-
>  3 files changed, 62 insertions(+), 47 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9d8132dd4cc5..5cc99ffc1841 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1097,14 +1097,13 @@ static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
>  	return true;
>  }
>  
> -static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
> -					      const struct intel_crtc_state *crtc_state,
> -					      int bpc)
> +static bool intel_dp_hdmi_bpc_possible(struct intel_dp *intel_dp,
> +				       const struct intel_crtc_state *crtc_state,
> +				       int bpc)
>  {
>  
> -	return intel_hdmi_deep_color_possible(crtc_state, bpc,
> -					      intel_dp->has_hdmi_sink,
> -					      intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
> +	return intel_hdmi_bpc_possible(crtc_state, bpc, intel_dp->has_hdmi_sink,
> +				       intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
>  		intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
>  }
>  
> @@ -1122,7 +1121,7 @@ static int intel_dp_max_bpp(struct intel_dp *intel_dp,
>  
>  	if (intel_dp->dfp.min_tmds_clock) {
>  		for (; bpc >= 10; bpc -= 2) {
> -			if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
> +			if (intel_dp_hdmi_bpc_possible(intel_dp, crtc_state, bpc))
>  				break;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 7e6af959bf83..b5af986b2778 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2001,17 +2001,14 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
>  	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
>  }
>  
> -bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
> -				    int bpc, bool has_hdmi_sink, bool ycbcr420_output)
> +bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
> +			     int bpc, bool has_hdmi_sink, bool ycbcr420_output)
>  {
>  	struct drm_atomic_state *state = crtc_state->uapi.state;
>  	struct drm_connector_state *connector_state;
>  	struct drm_connector *connector;
>  	int i;
>  
> -	if (crtc_state->pipe_bpp < bpc * 3)
> -		return false;
> -
>  	for_each_new_connector_in_state(state, connector, connector_state, i) {
>  		if (connector_state->crtc != crtc_state->uapi.crtc)
>  			continue;
> @@ -2023,8 +2020,7 @@ bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
>  	return true;
>  }
>  
> -static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
> -				     int bpc)
> +static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
>  {
>  	struct drm_i915_private *dev_priv =
>  		to_i915(crtc_state->uapi.crtc->dev);
> @@ -2038,7 +2034,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
>  	 * HDMI deep color affects the clocks, so it's only possible
>  	 * when not cloning with other encoder types.
>  	 */
> -	if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
> +	if (bpc > 8 && crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
>  		return false;
>  
>  	/* Display Wa_1405510057:icl,ehl */
> @@ -2048,35 +2044,50 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
>  	     adjusted_mode->crtc_hblank_start) % 8 == 2)
>  		return false;
>  
> -	return intel_hdmi_deep_color_possible(crtc_state, bpc,
> -					      crtc_state->has_hdmi_sink,
> -					      intel_hdmi_is_ycbcr420(crtc_state));
> +	return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
> +				       intel_hdmi_is_ycbcr420(crtc_state));
>  }
>  
>  static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
>  				  struct intel_crtc_state *crtc_state,
> -				  int clock)
> +				  int clock, bool respect_downstream_limits)
>  {
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>  	bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
>  	int bpc;
>  
> -	for (bpc = 12; bpc >= 10; bpc -= 2) {
> -		if (hdmi_deep_color_possible(crtc_state, bpc) &&
> -		    hdmi_port_clock_valid(intel_hdmi,
> -					  intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output),
> -					  true, crtc_state->has_hdmi_sink) == MODE_OK)
> +	/*
> +	 * pipe_bpp could already be below 8bpc due to FDI
> +	 * bandwidth constraints. HDMI minimum is 8bpc however.
> +	 */
> +	bpc = max(crtc_state->pipe_bpp / 3, 8);
> +
> +	/*
> +	 * We will never exceed downstream TMDS clock limits while
> +	 * attempting deep color. If the user insists on forcing an
> +	 * out of spec mode they will have to be satisfied with 8bpc.
> +	 */
> +	if (!respect_downstream_limits)
> +		bpc = 8;
> +
> +	for (; bpc >= 8; bpc -= 2) {
> +		int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
> +
> +		if (hdmi_bpc_possible(crtc_state, bpc) &&
> +		    hdmi_port_clock_valid(intel_hdmi, tmds_clock,
> +					  respect_downstream_limits,
> +					  crtc_state->has_hdmi_sink) == MODE_OK)
>  			return bpc;
>  	}
>  
> -	return 8;
> +	return -EINVAL;
>  }
>  
>  static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
> -				    struct intel_crtc_state *crtc_state)
> +				    struct intel_crtc_state *crtc_state,
> +				    bool respect_downstream_limits)
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> -	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
>  	int bpc, clock = adjusted_mode->crtc_clock;
> @@ -2084,31 +2095,25 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
>  		clock *= 2;
>  
> -	bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
> +	bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
> +				     respect_downstream_limits);
> +	if (bpc < 0)
> +		return bpc;
>  
> -	crtc_state->port_clock = intel_hdmi_tmds_clock(clock, bpc,
> -						       intel_hdmi_is_ycbcr420(crtc_state));
> +	crtc_state->port_clock =
> +		intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
>  
>  	/*
>  	 * pipe_bpp could already be below 8bpc due to
>  	 * FDI bandwidth constraints. We shouldn't bump it
> -	 * back up to 8bpc in that case.
> +	 * back up to the HDMI minimum 8bpc in that case.
>  	 */
> -	if (crtc_state->pipe_bpp > bpc * 3)
> -		crtc_state->pipe_bpp = bpc * 3;
> +	crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
>  
>  	drm_dbg_kms(&i915->drm,
>  		    "picking %d bpc for HDMI output (pipe bpp: %d)\n",
>  		    bpc, crtc_state->pipe_bpp);
>  
> -	if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
> -				  false, crtc_state->has_hdmi_sink) != MODE_OK) {
> -		drm_dbg_kms(&i915->drm,
> -			    "unsupported HDMI clock (%d kHz), rejecting mode\n",
> -			    crtc_state->port_clock);
> -		return -EINVAL;
> -	}
> -
>  	return 0;
>  }
>  
> @@ -2169,7 +2174,8 @@ intel_hdmi_output_format(struct intel_connector *connector,
>  
>  static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
>  					    struct intel_crtc_state *crtc_state,
> -					    const struct drm_connector_state *conn_state)
> +					    const struct drm_connector_state *conn_state,
> +					    bool respect_downstream_limits)
>  {
>  	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> @@ -2186,7 +2192,7 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
>  		crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
>  	}
>  
> -	ret = intel_hdmi_compute_clock(encoder, crtc_state);
> +	ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
>  	if (ret) {
>  		if (intel_hdmi_is_ycbcr420(crtc_state) ||
>  		    !connector->base.ycbcr_420_allowed ||
> @@ -2194,7 +2200,7 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
>  			return ret;
>  
>  		crtc_state->output_format = intel_hdmi_output_format(connector, true);
> -		ret = intel_hdmi_compute_clock(encoder, crtc_state);
> +		ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
>  	}
>  
>  	return ret;
> @@ -2230,9 +2236,19 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
>  	pipe_config->has_audio =
>  		intel_hdmi_has_audio(encoder, pipe_config, conn_state);
>  
> -	ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state);
> +	/*
> +	 * Try to respect downstream TMDS clock limits first, if
> +	 * that fails assume the user might know something we don't.
> +	 */
> +	ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
>  	if (ret)
> +		ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
> +	if (ret) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "unsupported HDMI clock (%d kHz), rejecting mode\n",
> +			    pipe_config->hw.adjusted_mode.crtc_clock);
>  		return ret;
> +	}
>  
>  	if (intel_hdmi_is_ycbcr420(pipe_config)) {
>  		ret = intel_panel_fitting(pipe_config, conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
> index b43a180d007e..ee144db67e66 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
> @@ -45,8 +45,8 @@ void intel_read_infoframe(struct intel_encoder *encoder,
>  			  union hdmi_infoframe *frame);
>  bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
>  				    const struct drm_connector_state *conn_state);
> -bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, int bpc,
> -				    bool has_hdmi_sink, bool ycbcr420_output);
> +bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
> +			     int bpc, bool has_hdmi_sink, bool ycbcr420_output);
>  int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
>  			   int num_slices, int output_format, bool hdmi_all_bpp,
>  			   int hdmi_max_chunk_bytes);
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 07/20] drm/i915/hdmi: Simplify intel_hdmi_mode_clock_valid()

[Nautiyal, Ankit K]

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LGTM

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä<ville.syrjala@linux.intel.com>
>
> Just loop over the possible bpc values instead of
> using an ugly if construct.
>
> A slight change in behaviour is that we now call
> intel_hdmi_{source,sink}_bpc_possible() even for 8bpc,
> but that is fine since 8bpc is always supported.
>
> Signed-off-by: Ville Syrjälä<ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_hdmi.c | 37 +++++++++++++----------
>   1 file changed, 21 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index b5af986b2778..c6586d10a9d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1934,25 +1934,30 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
>   {
>   	struct drm_i915_private *i915 = to_i915(connector->dev);
>   	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
> -	enum drm_mode_status status;
> +	enum drm_mode_status status = MODE_OK;
> +	int bpc;
>   
> -	/* check if we can do 8bpc */
> -	status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 8, ycbcr420_output),
> -				       true, has_hdmi_sink);
> +	/*
> +	 * Try all color depths since valid port clock range
> +	 * can have holes. Any mode that can be used with at
> +	 * least one color depth is accepted.
> +	 */
> +	for (bpc = 12; bpc >= 8; bpc -= 2) {
> +		int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
>   
> -	/* if we can't do 8bpc we may still be able to do 12bpc */
> -	if (status != MODE_OK &&
> -	    intel_hdmi_source_bpc_possible(i915, 12) &&
> -	    intel_hdmi_sink_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output))
> -		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 12, ycbcr420_output),
> -					       true, has_hdmi_sink);
> +		if (!intel_hdmi_source_bpc_possible(i915, bpc))
> +			continue;
>   
> -	/* if we can't do 8,12bpc we may still be able to do 10bpc */
> -	if (status != MODE_OK &&
> -	    intel_hdmi_source_bpc_possible(i915, 10) &&
> -	    intel_hdmi_sink_bpc_possible(connector, 10, has_hdmi_sink, ycbcr420_output))
> -		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 10, ycbcr420_output),
> -					       true, has_hdmi_sink);
> +		if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
> +			continue;
> +
> +		status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
> +		if (status == MODE_OK)
> +			return MODE_OK;
> +	}
> +
> +	/* can never happen */
> +	drm_WARN_ON(&i915->drm, status == MODE_OK);
>   
>   	return status;
>   }

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Re: [Intel-gfx] [PATCH 08/20] drm/i915/dp: Reuse intel_hdmi_tmds_clock()

[Nautiyal, Ankit K]

LGTM

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reuse intel_hdmi_tmds_clock() for DP->HDMI TMDS clock calculations.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_dp.c   | 20 +++++---------------
>   drivers/gpu/drm/i915/display/intel_hdmi.c |  2 +-
>   drivers/gpu/drm/i915/display/intel_hdmi.h |  1 +
>   3 files changed, 7 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5cc99ffc1841..45e4bf54e1de 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -814,9 +814,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
>   		return MODE_CLOCK_HIGH;
>   
>   	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
> -	tmds_clock = target_clock;
> -	if (drm_mode_is_420_only(info, mode))
> -		tmds_clock /= 2;
> +	tmds_clock = intel_hdmi_tmds_clock(target_clock, 8,
> +					   drm_mode_is_420_only(info, mode));
>   
>   	if (intel_dp->dfp.min_tmds_clock &&
>   	    tmds_clock < intel_dp->dfp.min_tmds_clock)
> @@ -1070,21 +1069,12 @@ static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
>   		 intel_dp->dfp.ycbcr_444_to_420);
>   }
>   
> -static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
> -				    const struct intel_crtc_state *crtc_state, int bpc)
> -{
> -	int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
> -
> -	if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
> -		clock /= 2;
> -
> -	return clock;
> -}
> -
>   static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
>   					   const struct intel_crtc_state *crtc_state, int bpc)
>   {
> -	int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
> +	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
> +	int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
> +					       intel_dp_hdmi_ycbcr420(intel_dp, crtc_state));
>   
>   	if (intel_dp->dfp.min_tmds_clock &&
>   	    tmds_clock < intel_dp->dfp.min_tmds_clock)
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index c6586d10a9d0..f1d42279a2df 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1868,7 +1868,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
>   	return MODE_OK;
>   }
>   
> -static int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
> +int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
>   {
>   	/* YCBCR420 TMDS rate requirement is half the pixel clock */
>   	if (ycbcr420_output)
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
> index ee144db67e66..d892cbff0da0 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
> @@ -47,6 +47,7 @@ bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
>   				    const struct drm_connector_state *conn_state);
>   bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
>   			     int bpc, bool has_hdmi_sink, bool ycbcr420_output);
> +int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output);
>   int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
>   			   int num_slices, int output_format, bool hdmi_all_bpp,
>   			   int hdmi_max_chunk_bytes);