* Sparsely populated TTM bos
@ 2021-11-19 14:28 ` Thomas Hellström
0 siblings, 0 replies; 6+ messages in thread
From: Thomas Hellström @ 2021-11-19 14:28 UTC (permalink / raw)
To: Christian König
Cc: Daniel Vetter, Intel Graphics Development, DRI Development
Hi, Christian,
We have an upcoming use-case in i915 where one solution would be
sparsely populated TTM bos.
We had that at one point where ttm_tt pages were allocated on demand,
but this time we'd rather be looking at multiple struct ttm_resources
per bo and those resources could be from different managers.
There might theoretically be other ways we can handle this use-case but
I wanted to check with you whether this is something AMD is already
looking into and if not, your general opinion.
Thanks,
Thomas
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] Sparsely populated TTM bos
@ 2021-11-19 14:28 ` Thomas Hellström
0 siblings, 0 replies; 6+ messages in thread
From: Thomas Hellström @ 2021-11-19 14:28 UTC (permalink / raw)
To: Christian König
Cc: Daniel Vetter, Intel Graphics Development, DRI Development
Hi, Christian,
We have an upcoming use-case in i915 where one solution would be
sparsely populated TTM bos.
We had that at one point where ttm_tt pages were allocated on demand,
but this time we'd rather be looking at multiple struct ttm_resources
per bo and those resources could be from different managers.
There might theoretically be other ways we can handle this use-case but
I wanted to check with you whether this is something AMD is already
looking into and if not, your general opinion.
Thanks,
Thomas
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Sparsely populated TTM bos
2021-11-19 14:28 ` [Intel-gfx] " Thomas Hellström
@ 2021-11-19 16:35 ` Christian König
-1 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2021-11-19 16:35 UTC (permalink / raw)
To: Thomas Hellström
Cc: Daniel Vetter, Intel Graphics Development, DRI Development
Hi Thomas,
Am 19.11.21 um 15:28 schrieb Thomas Hellström:
> Hi, Christian,
>
> We have an upcoming use-case in i915 where one solution would be
> sparsely populated TTM bos.
>
> We had that at one point where ttm_tt pages were allocated on demand,
> but this time we'd rather be looking at multiple struct ttm_resources
> per bo and those resources could be from different managers.
>
> There might theoretically be other ways we can handle this use-case
> but I wanted to check with you whether this is something AMD is
> already looking into and if not, your general opinion.
oh, yes I've looked into this as well a very long time ago.
At that point the basic blocker was that we couldn't have different
cache setting for the same VMA, but I think that's fixed by now.
Another thing is that you essentially need to move the LRU handling into
the resource like I already planned to do anyway.
Regards,
Christian.
>
> Thanks,
> Thomas
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] Sparsely populated TTM bos
@ 2021-11-19 16:35 ` Christian König
0 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2021-11-19 16:35 UTC (permalink / raw)
To: Thomas Hellström
Cc: Daniel Vetter, Intel Graphics Development, DRI Development
Hi Thomas,
Am 19.11.21 um 15:28 schrieb Thomas Hellström:
> Hi, Christian,
>
> We have an upcoming use-case in i915 where one solution would be
> sparsely populated TTM bos.
>
> We had that at one point where ttm_tt pages were allocated on demand,
> but this time we'd rather be looking at multiple struct ttm_resources
> per bo and those resources could be from different managers.
>
> There might theoretically be other ways we can handle this use-case
> but I wanted to check with you whether this is something AMD is
> already looking into and if not, your general opinion.
oh, yes I've looked into this as well a very long time ago.
At that point the basic blocker was that we couldn't have different
cache setting for the same VMA, but I think that's fixed by now.
Another thing is that you essentially need to move the LRU handling into
the resource like I already planned to do anyway.
Regards,
Christian.
>
> Thanks,
> Thomas
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Sparsely populated TTM bos
2021-11-19 16:35 ` [Intel-gfx] " Christian König
@ 2021-11-19 17:06 ` Daniel Vetter
-1 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2021-11-19 17:06 UTC (permalink / raw)
To: Christian König
Cc: Thomas Hellström, Intel Graphics Development,
DRI Development, Daniel Vetter
On Fri, Nov 19, 2021 at 05:35:53PM +0100, Christian König wrote:
> Hi Thomas,
>
> Am 19.11.21 um 15:28 schrieb Thomas Hellström:
> > Hi, Christian,
> >
> > We have an upcoming use-case in i915 where one solution would be
> > sparsely populated TTM bos.
> >
> > We had that at one point where ttm_tt pages were allocated on demand,
> > but this time we'd rather be looking at multiple struct ttm_resources
> > per bo and those resources could be from different managers.
> >
> > There might theoretically be other ways we can handle this use-case but
> > I wanted to check with you whether this is something AMD is already
> > looking into and if not, your general opinion.
>
> oh, yes I've looked into this as well a very long time ago.
>
> At that point the basic blocker was that we couldn't have different cache
> setting for the same VMA, but I think that's fixed by now.
I think for cpu mmap we might just disallow them. Or we just migrate them
back into so that cpu access is always done in the same (or at least a
compatible) cache domain.
We can't really talk yet about what this thing is for, but "entire ttm_bo
cpu mmap must have same caching mode" shouldn't be a real limitation for
what we want to do here.
> Another thing is that you essentially need to move the LRU handling into the
> resource like I already planned to do anyway.
Yeah, hence why I suggested going ttm_bo : ttm_resource 1:N might be a
good idea in general, and we could piggy-pack on top of this. If you're
all on board then I guess we'll try to prototype something and maybe if
you're bored we could resurrect some of the patches to move lru/dma_resv
and whatever else from ttm_bo to ttm_resource? Just to see how much this
would impact.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] Sparsely populated TTM bos
@ 2021-11-19 17:06 ` Daniel Vetter
0 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2021-11-19 17:06 UTC (permalink / raw)
To: Christian König
Cc: Thomas Hellström, Intel Graphics Development,
DRI Development, Daniel Vetter
On Fri, Nov 19, 2021 at 05:35:53PM +0100, Christian König wrote:
> Hi Thomas,
>
> Am 19.11.21 um 15:28 schrieb Thomas Hellström:
> > Hi, Christian,
> >
> > We have an upcoming use-case in i915 where one solution would be
> > sparsely populated TTM bos.
> >
> > We had that at one point where ttm_tt pages were allocated on demand,
> > but this time we'd rather be looking at multiple struct ttm_resources
> > per bo and those resources could be from different managers.
> >
> > There might theoretically be other ways we can handle this use-case but
> > I wanted to check with you whether this is something AMD is already
> > looking into and if not, your general opinion.
>
> oh, yes I've looked into this as well a very long time ago.
>
> At that point the basic blocker was that we couldn't have different cache
> setting for the same VMA, but I think that's fixed by now.
I think for cpu mmap we might just disallow them. Or we just migrate them
back into so that cpu access is always done in the same (or at least a
compatible) cache domain.
We can't really talk yet about what this thing is for, but "entire ttm_bo
cpu mmap must have same caching mode" shouldn't be a real limitation for
what we want to do here.
> Another thing is that you essentially need to move the LRU handling into the
> resource like I already planned to do anyway.
Yeah, hence why I suggested going ttm_bo : ttm_resource 1:N might be a
good idea in general, and we could piggy-pack on top of this. If you're
all on board then I guess we'll try to prototype something and maybe if
you're bored we could resurrect some of the patches to move lru/dma_resv
and whatever else from ttm_bo to ttm_resource? Just to see how much this
would impact.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-11-19 17:06 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-19 14:28 Sparsely populated TTM bos Thomas Hellström
2021-11-19 14:28 ` [Intel-gfx] " Thomas Hellström
2021-11-19 16:35 ` Christian König
2021-11-19 16:35 ` [Intel-gfx] " Christian König
2021-11-19 17:06 ` Daniel Vetter
2021-11-19 17:06 ` [Intel-gfx] " Daniel Vetter
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