[PATCH 1/3] dt-bindings: arm: pmu: Document Denver and Carmel PMUs

[PATCH 1/3] dt-bindings: arm: pmu: Document Denver and Carmel PMUs

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Add compatible strings for the NVIDIA Denver and Carmel PMUs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml
index e17ac049e890..c6447dc86076 100644
--- a/Documentation/devicetree/bindings/arm/pmu.yaml
+++ b/Documentation/devicetree/bindings/arm/pmu.yaml
@@ -48,6 +48,8 @@ properties:
           - arm,neoverse-n1-pmu
           - brcm,vulcan-pmu
           - cavium,thunder-pmu
+          - nvidia,denver-pmu
+          - nvidia,carmel-pmu
           - qcom,krait-pmu
           - qcom,scorpion-pmu
           - qcom,scorpion-mp-pmu
-- 
2.33.1

[PATCH 1/3] dt-bindings: arm: pmu: Document Denver and Carmel PMUs

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Add compatible strings for the NVIDIA Denver and Carmel PMUs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml
index e17ac049e890..c6447dc86076 100644
--- a/Documentation/devicetree/bindings/arm/pmu.yaml
+++ b/Documentation/devicetree/bindings/arm/pmu.yaml
@@ -48,6 +48,8 @@ properties:
           - arm,neoverse-n1-pmu
           - brcm,vulcan-pmu
           - cavium,thunder-pmu
+          - nvidia,denver-pmu
+          - nvidia,carmel-pmu
           - qcom,krait-pmu
           - qcom,scorpion-pmu
           - qcom,scorpion-mp-pmu
-- 
2.33.1


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[PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Add support for the NVIDIA Denver and Carmel PMUs using the generic
PMUv3 event map for now.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index b4044469527e..8c8cf369c450 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
 				       armv8_vulcan_map_event);
 }
 
+static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
+				       armv8_pmuv3_map_event);
+}
+
+static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
+				       armv8_pmuv3_map_event);
+}
+
 static const struct of_device_id armv8_pmu_of_device_ids[] = {
 	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},
 	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},
@@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
 	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
 	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
 	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
+	{.compatible = "nvidia,denver-pmu",	.data = armv8_denver_pmu_init},
+	{.compatible = "nvidia,carmel-pmu",	.data = armv8_carmel_pmu_init},
 	{},
 };
 
-- 
2.33.1

[PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Add support for the NVIDIA Denver and Carmel PMUs using the generic
PMUv3 event map for now.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index b4044469527e..8c8cf369c450 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
 				       armv8_vulcan_map_event);
 }
 
+static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
+				       armv8_pmuv3_map_event);
+}
+
+static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
+				       armv8_pmuv3_map_event);
+}
+
 static const struct of_device_id armv8_pmu_of_device_ids[] = {
 	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},
 	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},
@@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
 	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
 	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
 	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
+	{.compatible = "nvidia,denver-pmu",	.data = armv8_denver_pmu_init},
+	{.compatible = "nvidia,carmel-pmu",	.data = armv8_carmel_pmu_init},
 	{},
 };
 
-- 
2.33.1


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[PATCH 3/3] arm64: tegra: Drop arm,armv8-pmuv3 compatible string

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The arm,armv8-pmuv3 compatible string is meant to be used only for
software models and not silicon chips. Drop them and use silicon-
specific compatible strings instead.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++--
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 5f8132884be0..eb739ffbdfce 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1892,14 +1892,14 @@ L2_A57: l2-cache1 {
 	};
 
 	pmu_denver {
-		compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
+		compatible = "nvidia,denver-pmu";
 		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-affinity = <&denver_0 &denver_1>;
 	};
 
 	pmu_a57 {
-		compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+		compatible = "arm,cortex-a57-pmu";
 		interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 8d29b7fdb044..a0025b1c425f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -2687,7 +2687,7 @@ l3c: l3-cache {
 	};
 
 	pmu {
-		compatible = "arm,armv8-pmuv3";
+		compatible = "nvidia,carmel-pmu";
 		interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.33.1

[PATCH 3/3] arm64: tegra: Drop arm,armv8-pmuv3 compatible string

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The arm,armv8-pmuv3 compatible string is meant to be used only for
software models and not silicon chips. Drop them and use silicon-
specific compatible strings instead.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++--
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 5f8132884be0..eb739ffbdfce 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1892,14 +1892,14 @@ L2_A57: l2-cache1 {
 	};
 
 	pmu_denver {
-		compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3";
+		compatible = "nvidia,denver-pmu";
 		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-affinity = <&denver_0 &denver_1>;
 	};
 
 	pmu_a57 {
-		compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+		compatible = "arm,cortex-a57-pmu";
 		interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 8d29b7fdb044..a0025b1c425f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -2687,7 +2687,7 @@ l3c: l3-cache {
 	};
 
 	pmu {
-		compatible = "arm,armv8-pmuv3";
+		compatible = "nvidia,carmel-pmu";
 		interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.33.1


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Re: [PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs

[Mark Rutland]

On Tue, Dec 07, 2021 at 04:07:45PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Add support for the NVIDIA Denver and Carmel PMUs using the generic
> PMUv3 event map for now.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index b4044469527e..8c8cf369c450 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
>  				       armv8_vulcan_map_event);
>  }
>  
> +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
> +				       armv8_pmuv3_map_event);
> +}
> +
> +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
> +				       armv8_pmuv3_map_event);
> +}
> +
>  static const struct of_device_id armv8_pmu_of_device_ids[] = {
>  	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},
>  	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},
> @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
>  	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
>  	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
>  	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
> +	{.compatible = "nvidia,denver-pmu",	.data = armv8_denver_pmu_init},
> +	{.compatible = "nvidia,carmel-pmu",	.data = armv8_carmel_pmu_init},

Super trivial nit, but could we please organise this alphabetically (i.e. with carmel first?)

With that:

Acked-by: Mark Rutland <mark.rutland@arm.com>

I see now that we messed up the order of "cavium,thunder-pmu" and
"brcm,vulcan-pmu", but otherwise this is ordered, and it's be nice to keep it
that way. I can fix the order of those two in a separate patch.

Thanks,
Mark.

>  	{},
>  };
>  
> -- 
> 2.33.1
> 

Re: [PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs

[Mark Rutland]

On Tue, Dec 07, 2021 at 04:07:45PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Add support for the NVIDIA Denver and Carmel PMUs using the generic
> PMUv3 event map for now.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index b4044469527e..8c8cf369c450 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
>  				       armv8_vulcan_map_event);
>  }
>  
> +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
> +				       armv8_pmuv3_map_event);
> +}
> +
> +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
> +{
> +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
> +				       armv8_pmuv3_map_event);
> +}
> +
>  static const struct of_device_id armv8_pmu_of_device_ids[] = {
>  	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},
>  	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},
> @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
>  	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
>  	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
>  	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
> +	{.compatible = "nvidia,denver-pmu",	.data = armv8_denver_pmu_init},
> +	{.compatible = "nvidia,carmel-pmu",	.data = armv8_carmel_pmu_init},

Super trivial nit, but could we please organise this alphabetically (i.e. with carmel first?)

With that:

Acked-by: Mark Rutland <mark.rutland@arm.com>

I see now that we messed up the order of "cavium,thunder-pmu" and
"brcm,vulcan-pmu", but otherwise this is ordered, and it's be nice to keep it
that way. I can fix the order of those two in a separate patch.

Thanks,
Mark.

>  	{},
>  };
>  
> -- 
> 2.33.1
> 

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Re: [PATCH 1/3] dt-bindings: arm: pmu: Document Denver and Carmel PMUs

[Rob Herring]

On Tue, 07 Dec 2021 16:07:44 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Add compatible strings for the NVIDIA Denver and Carmel PMUs.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/1564747


arm-pmu: compatible: Additional items are not allowed ('arm,armv8-pmuv3' was unexpected)
	arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dt.yaml
	arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dt.yaml
	arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dt.yaml
	arch/arm/boot/dts/bcm2711-rpi-400.dt.yaml
	arch/arm/boot/dts/bcm2711-rpi-4-b.dt.yaml
	arch/arm/boot/dts/bcm2711-rpi-cm4-io.dt.yaml

arm-pmu: compatible: ['arm,cortex-a72-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dt.yaml
	arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dt.yaml
	arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dt.yaml
	arch/arm/boot/dts/bcm2711-rpi-400.dt.yaml
	arch/arm/boot/dts/bcm2711-rpi-4-b.dt.yaml
	arch/arm/boot/dts/bcm2711-rpi-cm4-io.dt.yaml

pmu@40089000: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+'
	arch/arm/boot/dts/vf500-colibri-eval-v3.dt.yaml
	arch/arm/boot/dts/vf610-bk4.dt.yaml
	arch/arm/boot/dts/vf610-colibri-eval-v3.dt.yaml
	arch/arm/boot/dts/vf610-cosmic.dt.yaml
	arch/arm/boot/dts/vf610-twr.dt.yaml
	arch/arm/boot/dts/vf610-zii-cfu1.dt.yaml
	arch/arm/boot/dts/vf610-zii-dev-rev-b.dt.yaml
	arch/arm/boot/dts/vf610-zii-dev-rev-c.dt.yaml
	arch/arm/boot/dts/vf610-zii-scu4-aib.dt.yaml
	arch/arm/boot/dts/vf610-zii-spb4.dt.yaml
	arch/arm/boot/dts/vf610-zii-ssmb-dtu.dt.yaml
	arch/arm/boot/dts/vf610-zii-ssmb-spu3.dt.yaml

pmu@54000000: 'reg', 'ti,hwmods' do not match any of the regexes: 'pinctrl-[0-9]+'
	arch/arm/boot/dts/am3517-craneboard.dt.yaml
	arch/arm/boot/dts/am3517-evm.dt.yaml
	arch/arm/boot/dts/am3517_mt_ventoux.dt.yaml
	arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dt.yaml
	arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dt.yaml
	arch/arm/boot/dts/omap3430-sdp.dt.yaml
	arch/arm/boot/dts/omap3-beagle.dt.yaml
	arch/arm/boot/dts/omap3-beagle-xm-ab.dt.yaml
	arch/arm/boot/dts/omap3-beagle-xm.dt.yaml
	arch/arm/boot/dts/omap3-cm-t3517.dt.yaml
	arch/arm/boot/dts/omap3-cm-t3530.dt.yaml
	arch/arm/boot/dts/omap3-cm-t3730.dt.yaml
	arch/arm/boot/dts/omap3-devkit8000.dt.yaml
	arch/arm/boot/dts/omap3-devkit8000-lcd43.dt.yaml
	arch/arm/boot/dts/omap3-devkit8000-lcd70.dt.yaml
	arch/arm/boot/dts/omap3-echo.dt.yaml
	arch/arm/boot/dts/omap3-evm-37xx.dt.yaml
	arch/arm/boot/dts/omap3-evm.dt.yaml
	arch/arm/boot/dts/omap3-gta04a3.dt.yaml
	arch/arm/boot/dts/omap3-gta04a4.dt.yaml
	arch/arm/boot/dts/omap3-gta04a5.dt.yaml
	arch/arm/boot/dts/omap3-gta04a5one.dt.yaml
	arch/arm/boot/dts/omap3-ha.dt.yaml
	arch/arm/boot/dts/omap3-ha-lcd.dt.yaml
	arch/arm/boot/dts/omap3-igep0020.dt.yaml
	arch/arm/boot/dts/omap3-igep0020-rev-f.dt.yaml
	arch/arm/boot/dts/omap3-igep0030.dt.yaml
	arch/arm/boot/dts/omap3-igep0030-rev-g.dt.yaml
	arch/arm/boot/dts/omap3-ldp.dt.yaml
	arch/arm/boot/dts/omap3-lilly-dbb056.dt.yaml
	arch/arm/boot/dts/omap3-n900.dt.yaml
	arch/arm/boot/dts/omap3-n950.dt.yaml
	arch/arm/boot/dts/omap3-n9.dt.yaml
	arch/arm/boot/dts/omap3-overo-alto35.dt.yaml
	arch/arm/boot/dts/omap3-overo-chestnut43.dt.yaml
	arch/arm/boot/dts/omap3-overo-gallop43.dt.yaml
	arch/arm/boot/dts/omap3-overo-palo35.dt.yaml
	arch/arm/boot/dts/omap3-overo-palo43.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-alto35.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-chestnut43.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-gallop43.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-palo35.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-palo43.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-summit.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-tobi.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-tobiduo.dt.yaml
	arch/arm/boot/dts/omap3-overo-summit.dt.yaml
	arch/arm/boot/dts/omap3-overo-tobi.dt.yaml
	arch/arm/boot/dts/omap3-overo-tobiduo.dt.yaml
	arch/arm/boot/dts/omap3-pandora-1ghz.dt.yaml
	arch/arm/boot/dts/omap3-pandora-600mhz.dt.yaml
	arch/arm/boot/dts/omap3-sbc-t3517.dt.yaml
	arch/arm/boot/dts/omap3-sbc-t3530.dt.yaml
	arch/arm/boot/dts/omap3-sbc-t3730.dt.yaml
	arch/arm/boot/dts/omap3-sniper.dt.yaml
	arch/arm/boot/dts/omap3-thunder.dt.yaml
	arch/arm/boot/dts/omap3-zoom3.dt.yaml

pmu_a57: compatible: Additional items are not allowed ('arm,armv8-pmuv3' was unexpected)
	arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dt.yaml
	arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml

pmu_a57: compatible: ['arm,cortex-a57-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dt.yaml
	arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml

pmu: compatible: Additional items are not allowed ('arm,armv8-pmuv3' was unexpected)
	arch/arm64/boot/dts/apm/apm-mustang.dt.yaml
	arch/arm64/boot/dts/cavium/thunder2-99xx.dt.yaml
	arch/arm64/boot/dts/cavium/thunder-88xx.dt.yaml
	arch/arm64/boot/dts/sprd/sp9860g-1h10.dt.yaml
	arch/arm64/boot/dts/synaptics/berlin4ct-dmp.dt.yaml
	arch/arm64/boot/dts/synaptics/berlin4ct-stb.dt.yaml

pmu: compatible: ['apm,potenza-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/apm/apm-mustang.dt.yaml

pmu: compatible: ['arm,cortex-a53-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/sprd/sp9860g-1h10.dt.yaml
	arch/arm64/boot/dts/synaptics/berlin4ct-dmp.dt.yaml
	arch/arm64/boot/dts/synaptics/berlin4ct-stb.dt.yaml

pmu: compatible: ['brcm,vulcan-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/cavium/thunder2-99xx.dt.yaml

pmu: compatible: ['cavium,thunder-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/cavium/thunder-88xx.dt.yaml

pmu_denver: compatible: Additional items are not allowed ('arm,armv8-pmuv3' was unexpected)
	arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dt.yaml
	arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml

pmu_denver: compatible: ['nvidia,denver-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dt.yaml
	arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml

pmu@f8891000: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+'
	arch/arm/boot/dts/zynq-cc108.dt.yaml
	arch/arm/boot/dts/zynq-ebaz4205.dt.yaml
	arch/arm/boot/dts/zynq-microzed.dt.yaml
	arch/arm/boot/dts/zynq-parallella.dt.yaml
	arch/arm/boot/dts/zynq-zc702.dt.yaml
	arch/arm/boot/dts/zynq-zc706.dt.yaml
	arch/arm/boot/dts/zynq-zc770-xm010.dt.yaml
	arch/arm/boot/dts/zynq-zc770-xm011.dt.yaml
	arch/arm/boot/dts/zynq-zc770-xm012.dt.yaml
	arch/arm/boot/dts/zynq-zc770-xm013.dt.yaml
	arch/arm/boot/dts/zynq-zed.dt.yaml
	arch/arm/boot/dts/zynq-zturn.dt.yaml
	arch/arm/boot/dts/zynq-zturn-v5.dt.yaml
	arch/arm/boot/dts/zynq-zybo.dt.yaml
	arch/arm/boot/dts/zynq-zybo-z7.dt.yaml

pmu@ff111000: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+'
	arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dt.yaml
	arch/arm/boot/dts/socfpga_arria10_socdk_nand.dt.yaml
	arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dt.yaml
	arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dt.yaml
	arch/arm/boot/dts/socfpga_arria5_socdk.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_socdk.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_sockit.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_socrates.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_sodia.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dt.yaml
	arch/arm/boot/dts/socfpga_vt.dt.yaml

Re: [PATCH 1/3] dt-bindings: arm: pmu: Document Denver and Carmel PMUs

[Rob Herring]

On Tue, 07 Dec 2021 16:07:44 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Add compatible strings for the NVIDIA Denver and Carmel PMUs.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/1564747


arm-pmu: compatible: Additional items are not allowed ('arm,armv8-pmuv3' was unexpected)
	arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dt.yaml
	arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dt.yaml
	arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dt.yaml
	arch/arm/boot/dts/bcm2711-rpi-400.dt.yaml
	arch/arm/boot/dts/bcm2711-rpi-4-b.dt.yaml
	arch/arm/boot/dts/bcm2711-rpi-cm4-io.dt.yaml

arm-pmu: compatible: ['arm,cortex-a72-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dt.yaml
	arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dt.yaml
	arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dt.yaml
	arch/arm/boot/dts/bcm2711-rpi-400.dt.yaml
	arch/arm/boot/dts/bcm2711-rpi-4-b.dt.yaml
	arch/arm/boot/dts/bcm2711-rpi-cm4-io.dt.yaml

pmu@40089000: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+'
	arch/arm/boot/dts/vf500-colibri-eval-v3.dt.yaml
	arch/arm/boot/dts/vf610-bk4.dt.yaml
	arch/arm/boot/dts/vf610-colibri-eval-v3.dt.yaml
	arch/arm/boot/dts/vf610-cosmic.dt.yaml
	arch/arm/boot/dts/vf610-twr.dt.yaml
	arch/arm/boot/dts/vf610-zii-cfu1.dt.yaml
	arch/arm/boot/dts/vf610-zii-dev-rev-b.dt.yaml
	arch/arm/boot/dts/vf610-zii-dev-rev-c.dt.yaml
	arch/arm/boot/dts/vf610-zii-scu4-aib.dt.yaml
	arch/arm/boot/dts/vf610-zii-spb4.dt.yaml
	arch/arm/boot/dts/vf610-zii-ssmb-dtu.dt.yaml
	arch/arm/boot/dts/vf610-zii-ssmb-spu3.dt.yaml

pmu@54000000: 'reg', 'ti,hwmods' do not match any of the regexes: 'pinctrl-[0-9]+'
	arch/arm/boot/dts/am3517-craneboard.dt.yaml
	arch/arm/boot/dts/am3517-evm.dt.yaml
	arch/arm/boot/dts/am3517_mt_ventoux.dt.yaml
	arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dt.yaml
	arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dt.yaml
	arch/arm/boot/dts/omap3430-sdp.dt.yaml
	arch/arm/boot/dts/omap3-beagle.dt.yaml
	arch/arm/boot/dts/omap3-beagle-xm-ab.dt.yaml
	arch/arm/boot/dts/omap3-beagle-xm.dt.yaml
	arch/arm/boot/dts/omap3-cm-t3517.dt.yaml
	arch/arm/boot/dts/omap3-cm-t3530.dt.yaml
	arch/arm/boot/dts/omap3-cm-t3730.dt.yaml
	arch/arm/boot/dts/omap3-devkit8000.dt.yaml
	arch/arm/boot/dts/omap3-devkit8000-lcd43.dt.yaml
	arch/arm/boot/dts/omap3-devkit8000-lcd70.dt.yaml
	arch/arm/boot/dts/omap3-echo.dt.yaml
	arch/arm/boot/dts/omap3-evm-37xx.dt.yaml
	arch/arm/boot/dts/omap3-evm.dt.yaml
	arch/arm/boot/dts/omap3-gta04a3.dt.yaml
	arch/arm/boot/dts/omap3-gta04a4.dt.yaml
	arch/arm/boot/dts/omap3-gta04a5.dt.yaml
	arch/arm/boot/dts/omap3-gta04a5one.dt.yaml
	arch/arm/boot/dts/omap3-ha.dt.yaml
	arch/arm/boot/dts/omap3-ha-lcd.dt.yaml
	arch/arm/boot/dts/omap3-igep0020.dt.yaml
	arch/arm/boot/dts/omap3-igep0020-rev-f.dt.yaml
	arch/arm/boot/dts/omap3-igep0030.dt.yaml
	arch/arm/boot/dts/omap3-igep0030-rev-g.dt.yaml
	arch/arm/boot/dts/omap3-ldp.dt.yaml
	arch/arm/boot/dts/omap3-lilly-dbb056.dt.yaml
	arch/arm/boot/dts/omap3-n900.dt.yaml
	arch/arm/boot/dts/omap3-n950.dt.yaml
	arch/arm/boot/dts/omap3-n9.dt.yaml
	arch/arm/boot/dts/omap3-overo-alto35.dt.yaml
	arch/arm/boot/dts/omap3-overo-chestnut43.dt.yaml
	arch/arm/boot/dts/omap3-overo-gallop43.dt.yaml
	arch/arm/boot/dts/omap3-overo-palo35.dt.yaml
	arch/arm/boot/dts/omap3-overo-palo43.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-alto35.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-chestnut43.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-gallop43.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-palo35.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-palo43.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-summit.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-tobi.dt.yaml
	arch/arm/boot/dts/omap3-overo-storm-tobiduo.dt.yaml
	arch/arm/boot/dts/omap3-overo-summit.dt.yaml
	arch/arm/boot/dts/omap3-overo-tobi.dt.yaml
	arch/arm/boot/dts/omap3-overo-tobiduo.dt.yaml
	arch/arm/boot/dts/omap3-pandora-1ghz.dt.yaml
	arch/arm/boot/dts/omap3-pandora-600mhz.dt.yaml
	arch/arm/boot/dts/omap3-sbc-t3517.dt.yaml
	arch/arm/boot/dts/omap3-sbc-t3530.dt.yaml
	arch/arm/boot/dts/omap3-sbc-t3730.dt.yaml
	arch/arm/boot/dts/omap3-sniper.dt.yaml
	arch/arm/boot/dts/omap3-thunder.dt.yaml
	arch/arm/boot/dts/omap3-zoom3.dt.yaml

pmu_a57: compatible: Additional items are not allowed ('arm,armv8-pmuv3' was unexpected)
	arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dt.yaml
	arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml

pmu_a57: compatible: ['arm,cortex-a57-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dt.yaml
	arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml

pmu: compatible: Additional items are not allowed ('arm,armv8-pmuv3' was unexpected)
	arch/arm64/boot/dts/apm/apm-mustang.dt.yaml
	arch/arm64/boot/dts/cavium/thunder2-99xx.dt.yaml
	arch/arm64/boot/dts/cavium/thunder-88xx.dt.yaml
	arch/arm64/boot/dts/sprd/sp9860g-1h10.dt.yaml
	arch/arm64/boot/dts/synaptics/berlin4ct-dmp.dt.yaml
	arch/arm64/boot/dts/synaptics/berlin4ct-stb.dt.yaml

pmu: compatible: ['apm,potenza-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/apm/apm-mustang.dt.yaml

pmu: compatible: ['arm,cortex-a53-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/sprd/sp9860g-1h10.dt.yaml
	arch/arm64/boot/dts/synaptics/berlin4ct-dmp.dt.yaml
	arch/arm64/boot/dts/synaptics/berlin4ct-stb.dt.yaml

pmu: compatible: ['brcm,vulcan-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/cavium/thunder2-99xx.dt.yaml

pmu: compatible: ['cavium,thunder-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/cavium/thunder-88xx.dt.yaml

pmu_denver: compatible: Additional items are not allowed ('arm,armv8-pmuv3' was unexpected)
	arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dt.yaml
	arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml

pmu_denver: compatible: ['nvidia,denver-pmu', 'arm,armv8-pmuv3'] is too long
	arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dt.yaml
	arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml

pmu@f8891000: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+'
	arch/arm/boot/dts/zynq-cc108.dt.yaml
	arch/arm/boot/dts/zynq-ebaz4205.dt.yaml
	arch/arm/boot/dts/zynq-microzed.dt.yaml
	arch/arm/boot/dts/zynq-parallella.dt.yaml
	arch/arm/boot/dts/zynq-zc702.dt.yaml
	arch/arm/boot/dts/zynq-zc706.dt.yaml
	arch/arm/boot/dts/zynq-zc770-xm010.dt.yaml
	arch/arm/boot/dts/zynq-zc770-xm011.dt.yaml
	arch/arm/boot/dts/zynq-zc770-xm012.dt.yaml
	arch/arm/boot/dts/zynq-zc770-xm013.dt.yaml
	arch/arm/boot/dts/zynq-zed.dt.yaml
	arch/arm/boot/dts/zynq-zturn.dt.yaml
	arch/arm/boot/dts/zynq-zturn-v5.dt.yaml
	arch/arm/boot/dts/zynq-zybo.dt.yaml
	arch/arm/boot/dts/zynq-zybo-z7.dt.yaml

pmu@ff111000: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+'
	arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dt.yaml
	arch/arm/boot/dts/socfpga_arria10_socdk_nand.dt.yaml
	arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dt.yaml
	arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dt.yaml
	arch/arm/boot/dts/socfpga_arria5_socdk.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_socdk.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_sockit.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_socrates.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_sodia.dt.yaml
	arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dt.yaml
	arch/arm/boot/dts/socfpga_vt.dt.yaml


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Re: [PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 2576 bytes --]

On Tue, Dec 07, 2021 at 04:03:25PM +0000, Mark Rutland wrote:
> On Tue, Dec 07, 2021 at 04:07:45PM +0100, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > Add support for the NVIDIA Denver and Carmel PMUs using the generic
> > PMUv3 event map for now.
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> > 
> > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> > index b4044469527e..8c8cf369c450 100644
> > --- a/arch/arm64/kernel/perf_event.c
> > +++ b/arch/arm64/kernel/perf_event.c
> > @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
> >  				       armv8_vulcan_map_event);
> >  }
> >  
> > +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
> > +{
> > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
> > +				       armv8_pmuv3_map_event);
> > +}
> > +
> > +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
> > +{
> > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
> > +				       armv8_pmuv3_map_event);
> > +}
> > +
> >  static const struct of_device_id armv8_pmu_of_device_ids[] = {
> >  	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},
> >  	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},
> > @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
> >  	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
> >  	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
> >  	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
> > +	{.compatible = "nvidia,denver-pmu",	.data = armv8_denver_pmu_init},
> > +	{.compatible = "nvidia,carmel-pmu",	.data = armv8_carmel_pmu_init},
> 
> Super trivial nit, but could we please organise this alphabetically (i.e. with carmel first?)
> 
> With that:
> 
> Acked-by: Mark Rutland <mark.rutland@arm.com>
> 
> I see now that we messed up the order of "cavium,thunder-pmu" and
> "brcm,vulcan-pmu", but otherwise this is ordered, and it's be nice to keep it
> that way. I can fix the order of those two in a separate patch.

I ordered this chronologically (Denver for Tegra186 and Carmel for
Tegra194), which seemed a bit more natural, but I can reorder this
alphabetically if you prefer.

Would Will be the right person to pick this up or should I take it
through the Tegra tree and then ARM SoC?

Thanks,
Thierry

[-- Attachment #2: signature.asc --]
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Re: [PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 2576 bytes --]

On Tue, Dec 07, 2021 at 04:03:25PM +0000, Mark Rutland wrote:
> On Tue, Dec 07, 2021 at 04:07:45PM +0100, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > Add support for the NVIDIA Denver and Carmel PMUs using the generic
> > PMUv3 event map for now.
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> > 
> > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> > index b4044469527e..8c8cf369c450 100644
> > --- a/arch/arm64/kernel/perf_event.c
> > +++ b/arch/arm64/kernel/perf_event.c
> > @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
> >  				       armv8_vulcan_map_event);
> >  }
> >  
> > +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
> > +{
> > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
> > +				       armv8_pmuv3_map_event);
> > +}
> > +
> > +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
> > +{
> > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
> > +				       armv8_pmuv3_map_event);
> > +}
> > +
> >  static const struct of_device_id armv8_pmu_of_device_ids[] = {
> >  	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},
> >  	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},
> > @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
> >  	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
> >  	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
> >  	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
> > +	{.compatible = "nvidia,denver-pmu",	.data = armv8_denver_pmu_init},
> > +	{.compatible = "nvidia,carmel-pmu",	.data = armv8_carmel_pmu_init},
> 
> Super trivial nit, but could we please organise this alphabetically (i.e. with carmel first?)
> 
> With that:
> 
> Acked-by: Mark Rutland <mark.rutland@arm.com>
> 
> I see now that we messed up the order of "cavium,thunder-pmu" and
> "brcm,vulcan-pmu", but otherwise this is ordered, and it's be nice to keep it
> that way. I can fix the order of those two in a separate patch.

I ordered this chronologically (Denver for Tegra186 and Carmel for
Tegra194), which seemed a bit more natural, but I can reorder this
alphabetically if you prefer.

Would Will be the right person to pick this up or should I take it
through the Tegra tree and then ARM SoC?

Thanks,
Thierry

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Re: [PATCH 1/3] dt-bindings: arm: pmu: Document Denver and Carmel PMUs

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1313 bytes --]

On Wed, Dec 08, 2021 at 07:44:28AM -0600, Rob Herring wrote:
> On Tue, 07 Dec 2021 16:07:44 +0100, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > Add compatible strings for the NVIDIA Denver and Carmel PMUs.
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> 
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
> 
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
> 
> Full log is available here: https://patchwork.ozlabs.org/patch/1564747

Yikes, that's a lot of warnings. I've got local patches to fix up the
Tegra-specific ones, but I could look at fixing up the others as well,
provided that you or anyone else aren't looking at this yet.

On that note: do you know of a simple trick to get the dtbs_check target
to run on all DTB files? The only way I've found so far is to manually
select all Kconfig options that would enable a specific subset, but it'd
be great if we could just run the checks on all irrespective of .config.

Thierry

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Re: [PATCH 1/3] dt-bindings: arm: pmu: Document Denver and Carmel PMUs

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 1313 bytes --]

On Wed, Dec 08, 2021 at 07:44:28AM -0600, Rob Herring wrote:
> On Tue, 07 Dec 2021 16:07:44 +0100, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > Add compatible strings for the NVIDIA Denver and Carmel PMUs.
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> 
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
> 
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
> 
> Full log is available here: https://patchwork.ozlabs.org/patch/1564747

Yikes, that's a lot of warnings. I've got local patches to fix up the
Tegra-specific ones, but I could look at fixing up the others as well,
provided that you or anyone else aren't looking at this yet.

On that note: do you know of a simple trick to get the dtbs_check target
to run on all DTB files? The only way I've found so far is to manually
select all Kconfig options that would enable a specific subset, but it'd
be great if we could just run the checks on all irrespective of .config.

Thierry

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Re: [PATCH 1/3] dt-bindings: arm: pmu: Document Denver and Carmel PMUs

[Rob Herring]

On Wed, Dec 8, 2021 at 8:41 AM Thierry Reding <thierry.reding@gmail.com> wrote:
>
> On Wed, Dec 08, 2021 at 07:44:28AM -0600, Rob Herring wrote:
> > On Tue, 07 Dec 2021 16:07:44 +0100, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > >
> > > Add compatible strings for the NVIDIA Denver and Carmel PMUs.
> > >
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > >  Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++
> > >  1 file changed, 2 insertions(+)
> > >
> >
> > Running 'make dtbs_check' with the schema in this patch gives the
> > following warnings. Consider if they are expected or the schema is
> > incorrect. These may not be new warnings.
> >
> > Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> > This will change in the future.
> >
> > Full log is available here: https://patchwork.ozlabs.org/patch/1564747
>
> Yikes, that's a lot of warnings. I've got local patches to fix up the
> Tegra-specific ones, but I could look at fixing up the others as well,
> provided that you or anyone else aren't looking at this yet.

I sent it because I saw the tegra ones.

> On that note: do you know of a simple trick to get the dtbs_check target
> to run on all DTB files? The only way I've found so far is to manually
> select all Kconfig options that would enable a specific subset, but it'd
> be great if we could just run the checks on all irrespective of .config.

Yes, there's a config option hidden behind COMPILE_TEST. I just use
allmodconfig/allyesconfig when I want to do that.

Rob

Re: [PATCH 1/3] dt-bindings: arm: pmu: Document Denver and Carmel PMUs

[Rob Herring]

On Wed, Dec 8, 2021 at 8:41 AM Thierry Reding <thierry.reding@gmail.com> wrote:
>
> On Wed, Dec 08, 2021 at 07:44:28AM -0600, Rob Herring wrote:
> > On Tue, 07 Dec 2021 16:07:44 +0100, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > >
> > > Add compatible strings for the NVIDIA Denver and Carmel PMUs.
> > >
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > >  Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++
> > >  1 file changed, 2 insertions(+)
> > >
> >
> > Running 'make dtbs_check' with the schema in this patch gives the
> > following warnings. Consider if they are expected or the schema is
> > incorrect. These may not be new warnings.
> >
> > Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> > This will change in the future.
> >
> > Full log is available here: https://patchwork.ozlabs.org/patch/1564747
>
> Yikes, that's a lot of warnings. I've got local patches to fix up the
> Tegra-specific ones, but I could look at fixing up the others as well,
> provided that you or anyone else aren't looking at this yet.

I sent it because I saw the tegra ones.

> On that note: do you know of a simple trick to get the dtbs_check target
> to run on all DTB files? The only way I've found so far is to manually
> select all Kconfig options that would enable a specific subset, but it'd
> be great if we could just run the checks on all irrespective of .config.

Yes, there's a config option hidden behind COMPILE_TEST. I just use
allmodconfig/allyesconfig when I want to do that.

Rob

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Re: [PATCH 1/3] dt-bindings: arm: pmu: Document Denver and Carmel PMUs

[Rob Herring]

On Tue, 07 Dec 2021 16:07:44 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Add compatible strings for the NVIDIA Denver and Carmel PMUs.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Given the other compatible string additions I picked up, I applied this 
one too.

Rob

Re: [PATCH 1/3] dt-bindings: arm: pmu: Document Denver and Carmel PMUs

[Rob Herring]

On Tue, 07 Dec 2021 16:07:44 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Add compatible strings for the NVIDIA Denver and Carmel PMUs.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Given the other compatible string additions I picked up, I applied this 
one too.

Rob

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Re: [PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs

[Will Deacon]

On Wed, Dec 08, 2021 at 03:36:02PM +0100, Thierry Reding wrote:
> On Tue, Dec 07, 2021 at 04:03:25PM +0000, Mark Rutland wrote:
> > On Tue, Dec 07, 2021 at 04:07:45PM +0100, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > > 
> > > Add support for the NVIDIA Denver and Carmel PMUs using the generic
> > > PMUv3 event map for now.
> > > 
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > >  arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
> > >  1 file changed, 14 insertions(+)
> > > 
> > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> > > index b4044469527e..8c8cf369c450 100644
> > > --- a/arch/arm64/kernel/perf_event.c
> > > +++ b/arch/arm64/kernel/perf_event.c
> > > @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
> > >  				       armv8_vulcan_map_event);
> > >  }
> > >  
> > > +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
> > > +{
> > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
> > > +				       armv8_pmuv3_map_event);
> > > +}
> > > +
> > > +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
> > > +{
> > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
> > > +				       armv8_pmuv3_map_event);
> > > +}
> > > +
> > >  static const struct of_device_id armv8_pmu_of_device_ids[] = {
> > >  	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},
> > >  	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},
> > > @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
> > >  	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
> > >  	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
> > >  	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
> > > +	{.compatible = "nvidia,denver-pmu",	.data = armv8_denver_pmu_init},
> > > +	{.compatible = "nvidia,carmel-pmu",	.data = armv8_carmel_pmu_init},
> > 
> > Super trivial nit, but could we please organise this alphabetically (i.e. with carmel first?)
> > 
> > With that:
> > 
> > Acked-by: Mark Rutland <mark.rutland@arm.com>
> > 
> > I see now that we messed up the order of "cavium,thunder-pmu" and
> > "brcm,vulcan-pmu", but otherwise this is ordered, and it's be nice to keep it
> > that way. I can fix the order of those two in a separate patch.
> 
> I ordered this chronologically (Denver for Tegra186 and Carmel for
> Tegra194), which seemed a bit more natural, but I can reorder this
> alphabetically if you prefer.
> 
> Would Will be the right person to pick this up or should I take it
> through the Tegra tree and then ARM SoC?

Sorry, I missed this somehow. I've got some perf patches pending already, so
it would be easiest for me to take this one directly (and then I can apply
Robin's stuff on top). Is that ok?

Will

Re: [PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs

[Will Deacon]

On Wed, Dec 08, 2021 at 03:36:02PM +0100, Thierry Reding wrote:
> On Tue, Dec 07, 2021 at 04:03:25PM +0000, Mark Rutland wrote:
> > On Tue, Dec 07, 2021 at 04:07:45PM +0100, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > > 
> > > Add support for the NVIDIA Denver and Carmel PMUs using the generic
> > > PMUv3 event map for now.
> > > 
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > >  arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
> > >  1 file changed, 14 insertions(+)
> > > 
> > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> > > index b4044469527e..8c8cf369c450 100644
> > > --- a/arch/arm64/kernel/perf_event.c
> > > +++ b/arch/arm64/kernel/perf_event.c
> > > @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
> > >  				       armv8_vulcan_map_event);
> > >  }
> > >  
> > > +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
> > > +{
> > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
> > > +				       armv8_pmuv3_map_event);
> > > +}
> > > +
> > > +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
> > > +{
> > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
> > > +				       armv8_pmuv3_map_event);
> > > +}
> > > +
> > >  static const struct of_device_id armv8_pmu_of_device_ids[] = {
> > >  	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},
> > >  	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},
> > > @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
> > >  	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
> > >  	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
> > >  	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
> > > +	{.compatible = "nvidia,denver-pmu",	.data = armv8_denver_pmu_init},
> > > +	{.compatible = "nvidia,carmel-pmu",	.data = armv8_carmel_pmu_init},
> > 
> > Super trivial nit, but could we please organise this alphabetically (i.e. with carmel first?)
> > 
> > With that:
> > 
> > Acked-by: Mark Rutland <mark.rutland@arm.com>
> > 
> > I see now that we messed up the order of "cavium,thunder-pmu" and
> > "brcm,vulcan-pmu", but otherwise this is ordered, and it's be nice to keep it
> > that way. I can fix the order of those two in a separate patch.
> 
> I ordered this chronologically (Denver for Tegra186 and Carmel for
> Tegra194), which seemed a bit more natural, but I can reorder this
> alphabetically if you prefer.
> 
> Would Will be the right person to pick this up or should I take it
> through the Tegra tree and then ARM SoC?

Sorry, I missed this somehow. I've got some perf patches pending already, so
it would be easiest for me to take this one directly (and then I can apply
Robin's stuff on top). Is that ok?

Will

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Re: [PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 3332 bytes --]

On Tue, Dec 14, 2021 at 12:33:53PM +0000, Will Deacon wrote:
> On Wed, Dec 08, 2021 at 03:36:02PM +0100, Thierry Reding wrote:
> > On Tue, Dec 07, 2021 at 04:03:25PM +0000, Mark Rutland wrote:
> > > On Tue, Dec 07, 2021 at 04:07:45PM +0100, Thierry Reding wrote:
> > > > From: Thierry Reding <treding@nvidia.com>
> > > > 
> > > > Add support for the NVIDIA Denver and Carmel PMUs using the generic
> > > > PMUv3 event map for now.
> > > > 
> > > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > > ---
> > > >  arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
> > > >  1 file changed, 14 insertions(+)
> > > > 
> > > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> > > > index b4044469527e..8c8cf369c450 100644
> > > > --- a/arch/arm64/kernel/perf_event.c
> > > > +++ b/arch/arm64/kernel/perf_event.c
> > > > @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
> > > >  				       armv8_vulcan_map_event);
> > > >  }
> > > >  
> > > > +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
> > > > +{
> > > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
> > > > +				       armv8_pmuv3_map_event);
> > > > +}
> > > > +
> > > > +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
> > > > +{
> > > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
> > > > +				       armv8_pmuv3_map_event);
> > > > +}
> > > > +
> > > >  static const struct of_device_id armv8_pmu_of_device_ids[] = {
> > > >  	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},
> > > >  	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},
> > > > @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
> > > >  	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
> > > >  	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
> > > >  	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
> > > > +	{.compatible = "nvidia,denver-pmu",	.data = armv8_denver_pmu_init},
> > > > +	{.compatible = "nvidia,carmel-pmu",	.data = armv8_carmel_pmu_init},
> > > 
> > > Super trivial nit, but could we please organise this alphabetically (i.e. with carmel first?)
> > > 
> > > With that:
> > > 
> > > Acked-by: Mark Rutland <mark.rutland@arm.com>
> > > 
> > > I see now that we messed up the order of "cavium,thunder-pmu" and
> > > "brcm,vulcan-pmu", but otherwise this is ordered, and it's be nice to keep it
> > > that way. I can fix the order of those two in a separate patch.
> > 
> > I ordered this chronologically (Denver for Tegra186 and Carmel for
> > Tegra194), which seemed a bit more natural, but I can reorder this
> > alphabetically if you prefer.
> > 
> > Would Will be the right person to pick this up or should I take it
> > through the Tegra tree and then ARM SoC?
> 
> Sorry, I missed this somehow. I've got some perf patches pending already, so
> it would be easiest for me to take this one directly (and then I can apply
> Robin's stuff on top). Is that ok?

Sure, works for me. Do you still want me to address Mark's comment
regarding the sorting order (chronological vs. alphabetical)? It wasn't
clear to me if Mark still wanted that after my explanation.

Thierry

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Re: [PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 3332 bytes --]

On Tue, Dec 14, 2021 at 12:33:53PM +0000, Will Deacon wrote:
> On Wed, Dec 08, 2021 at 03:36:02PM +0100, Thierry Reding wrote:
> > On Tue, Dec 07, 2021 at 04:03:25PM +0000, Mark Rutland wrote:
> > > On Tue, Dec 07, 2021 at 04:07:45PM +0100, Thierry Reding wrote:
> > > > From: Thierry Reding <treding@nvidia.com>
> > > > 
> > > > Add support for the NVIDIA Denver and Carmel PMUs using the generic
> > > > PMUv3 event map for now.
> > > > 
> > > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > > ---
> > > >  arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
> > > >  1 file changed, 14 insertions(+)
> > > > 
> > > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> > > > index b4044469527e..8c8cf369c450 100644
> > > > --- a/arch/arm64/kernel/perf_event.c
> > > > +++ b/arch/arm64/kernel/perf_event.c
> > > > @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
> > > >  				       armv8_vulcan_map_event);
> > > >  }
> > > >  
> > > > +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
> > > > +{
> > > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
> > > > +				       armv8_pmuv3_map_event);
> > > > +}
> > > > +
> > > > +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
> > > > +{
> > > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
> > > > +				       armv8_pmuv3_map_event);
> > > > +}
> > > > +
> > > >  static const struct of_device_id armv8_pmu_of_device_ids[] = {
> > > >  	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},
> > > >  	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},
> > > > @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
> > > >  	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
> > > >  	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
> > > >  	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
> > > > +	{.compatible = "nvidia,denver-pmu",	.data = armv8_denver_pmu_init},
> > > > +	{.compatible = "nvidia,carmel-pmu",	.data = armv8_carmel_pmu_init},
> > > 
> > > Super trivial nit, but could we please organise this alphabetically (i.e. with carmel first?)
> > > 
> > > With that:
> > > 
> > > Acked-by: Mark Rutland <mark.rutland@arm.com>
> > > 
> > > I see now that we messed up the order of "cavium,thunder-pmu" and
> > > "brcm,vulcan-pmu", but otherwise this is ordered, and it's be nice to keep it
> > > that way. I can fix the order of those two in a separate patch.
> > 
> > I ordered this chronologically (Denver for Tegra186 and Carmel for
> > Tegra194), which seemed a bit more natural, but I can reorder this
> > alphabetically if you prefer.
> > 
> > Would Will be the right person to pick this up or should I take it
> > through the Tegra tree and then ARM SoC?
> 
> Sorry, I missed this somehow. I've got some perf patches pending already, so
> it would be easiest for me to take this one directly (and then I can apply
> Robin's stuff on top). Is that ok?

Sure, works for me. Do you still want me to address Mark's comment
regarding the sorting order (chronological vs. alphabetical)? It wasn't
clear to me if Mark still wanted that after my explanation.

Thierry

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Re: [PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs

[Will Deacon]

On Tue, Dec 14, 2021 at 03:28:40PM +0100, Thierry Reding wrote:
> On Tue, Dec 14, 2021 at 12:33:53PM +0000, Will Deacon wrote:
> > On Wed, Dec 08, 2021 at 03:36:02PM +0100, Thierry Reding wrote:
> > > On Tue, Dec 07, 2021 at 04:03:25PM +0000, Mark Rutland wrote:
> > > > On Tue, Dec 07, 2021 at 04:07:45PM +0100, Thierry Reding wrote:
> > > > > From: Thierry Reding <treding@nvidia.com>
> > > > > 
> > > > > Add support for the NVIDIA Denver and Carmel PMUs using the generic
> > > > > PMUv3 event map for now.
> > > > > 
> > > > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > > > ---
> > > > >  arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
> > > > >  1 file changed, 14 insertions(+)
> > > > > 
> > > > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> > > > > index b4044469527e..8c8cf369c450 100644
> > > > > --- a/arch/arm64/kernel/perf_event.c
> > > > > +++ b/arch/arm64/kernel/perf_event.c
> > > > > @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
> > > > >  				       armv8_vulcan_map_event);
> > > > >  }
> > > > >  
> > > > > +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
> > > > > +{
> > > > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
> > > > > +				       armv8_pmuv3_map_event);
> > > > > +}
> > > > > +
> > > > > +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
> > > > > +{
> > > > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
> > > > > +				       armv8_pmuv3_map_event);
> > > > > +}
> > > > > +
> > > > >  static const struct of_device_id armv8_pmu_of_device_ids[] = {
> > > > >  	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},
> > > > >  	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},
> > > > > @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
> > > > >  	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
> > > > >  	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
> > > > >  	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
> > > > > +	{.compatible = "nvidia,denver-pmu",	.data = armv8_denver_pmu_init},
> > > > > +	{.compatible = "nvidia,carmel-pmu",	.data = armv8_carmel_pmu_init},
> > > > 
> > > > Super trivial nit, but could we please organise this alphabetically (i.e. with carmel first?)
> > > > 
> > > > With that:
> > > > 
> > > > Acked-by: Mark Rutland <mark.rutland@arm.com>
> > > > 
> > > > I see now that we messed up the order of "cavium,thunder-pmu" and
> > > > "brcm,vulcan-pmu", but otherwise this is ordered, and it's be nice to keep it
> > > > that way. I can fix the order of those two in a separate patch.
> > > 
> > > I ordered this chronologically (Denver for Tegra186 and Carmel for
> > > Tegra194), which seemed a bit more natural, but I can reorder this
> > > alphabetically if you prefer.
> > > 
> > > Would Will be the right person to pick this up or should I take it
> > > through the Tegra tree and then ARM SoC?
> > 
> > Sorry, I missed this somehow. I've got some perf patches pending already, so
> > it would be easiest for me to take this one directly (and then I can apply
> > Robin's stuff on top). Is that ok?
> 
> Sure, works for me. Do you still want me to address Mark's comment
> regarding the sorting order (chronological vs. alphabetical)? It wasn't
> clear to me if Mark still wanted that after my explanation.

No need -- Robin's picked this into his series:

https://lore.kernel.org/r/5f0f69d47acca78a9e479501aa4d8b429e23cf11.1639490264.git.robin.murphy@arm.com

so now I just need to pick that lot up.

Thanks!

Will

Re: [PATCH 2/3] arm64: perf: Support Denver and Carmel PMUs

[Will Deacon]

On Tue, Dec 14, 2021 at 03:28:40PM +0100, Thierry Reding wrote:
> On Tue, Dec 14, 2021 at 12:33:53PM +0000, Will Deacon wrote:
> > On Wed, Dec 08, 2021 at 03:36:02PM +0100, Thierry Reding wrote:
> > > On Tue, Dec 07, 2021 at 04:03:25PM +0000, Mark Rutland wrote:
> > > > On Tue, Dec 07, 2021 at 04:07:45PM +0100, Thierry Reding wrote:
> > > > > From: Thierry Reding <treding@nvidia.com>
> > > > > 
> > > > > Add support for the NVIDIA Denver and Carmel PMUs using the generic
> > > > > PMUv3 event map for now.
> > > > > 
> > > > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > > > ---
> > > > >  arch/arm64/kernel/perf_event.c | 14 ++++++++++++++
> > > > >  1 file changed, 14 insertions(+)
> > > > > 
> > > > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> > > > > index b4044469527e..8c8cf369c450 100644
> > > > > --- a/arch/arm64/kernel/perf_event.c
> > > > > +++ b/arch/arm64/kernel/perf_event.c
> > > > > @@ -1247,6 +1247,18 @@ static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
> > > > >  				       armv8_vulcan_map_event);
> > > > >  }
> > > > >  
> > > > > +static int armv8_denver_pmu_init(struct arm_pmu *cpu_pmu)
> > > > > +{
> > > > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_denver",
> > > > > +				       armv8_pmuv3_map_event);
> > > > > +}
> > > > > +
> > > > > +static int armv8_carmel_pmu_init(struct arm_pmu *cpu_pmu)
> > > > > +{
> > > > > +	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_nvidia_carmel",
> > > > > +				       armv8_pmuv3_map_event);
> > > > > +}
> > > > > +
> > > > >  static const struct of_device_id armv8_pmu_of_device_ids[] = {
> > > > >  	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},
> > > > >  	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},
> > > > > @@ -1265,6 +1277,8 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
> > > > >  	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
> > > > >  	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
> > > > >  	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
> > > > > +	{.compatible = "nvidia,denver-pmu",	.data = armv8_denver_pmu_init},
> > > > > +	{.compatible = "nvidia,carmel-pmu",	.data = armv8_carmel_pmu_init},
> > > > 
> > > > Super trivial nit, but could we please organise this alphabetically (i.e. with carmel first?)
> > > > 
> > > > With that:
> > > > 
> > > > Acked-by: Mark Rutland <mark.rutland@arm.com>
> > > > 
> > > > I see now that we messed up the order of "cavium,thunder-pmu" and
> > > > "brcm,vulcan-pmu", but otherwise this is ordered, and it's be nice to keep it
> > > > that way. I can fix the order of those two in a separate patch.
> > > 
> > > I ordered this chronologically (Denver for Tegra186 and Carmel for
> > > Tegra194), which seemed a bit more natural, but I can reorder this
> > > alphabetically if you prefer.
> > > 
> > > Would Will be the right person to pick this up or should I take it
> > > through the Tegra tree and then ARM SoC?
> > 
> > Sorry, I missed this somehow. I've got some perf patches pending already, so
> > it would be easiest for me to take this one directly (and then I can apply
> > Robin's stuff on top). Is that ok?
> 
> Sure, works for me. Do you still want me to address Mark's comment
> regarding the sorting order (chronological vs. alphabetical)? It wasn't
> clear to me if Mark still wanted that after my explanation.

No need -- Robin's picked this into his series:

https://lore.kernel.org/r/5f0f69d47acca78a9e479501aa4d8b429e23cf11.1639490264.git.robin.murphy@arm.com

so now I just need to pick that lot up.

Thanks!

Will

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