* [Intel-gfx] [PATCH v3 01/11] drm/i915: Use parameterized GPR register definitions everywhere
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
@ 2022-01-11 5:15 ` Matt Roper
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 02/11] drm/i915: Parameterize PWRCTX_MAXCNT Matt Roper
` (14 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2022-01-11 5:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Since we have an engine-parameterized macro GEN8_RING_CS_GPR, let's use
that in place of the HSW_CS_GPR and BCS_GPR register definitions.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 68 ++++++++++++++------------
drivers/gpu/drm/i915/i915_reg.h | 8 ---
2 files changed, 36 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 9c90740520a9..a804373bcd17 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -592,6 +592,10 @@ struct drm_i915_reg_descriptor {
{ .addr = _reg(idx) }, \
{ .addr = _reg ## _UDW(idx) }
+#define REG64_BASE_IDX(_reg, base, idx) \
+ { .addr = _reg(base, idx) }, \
+ { .addr = _reg ## _UDW(base, idx) }
+
static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
REG64(GPGPU_THREADS_DISPATCHED),
REG64(HS_INVOCATION_COUNT),
@@ -637,22 +641,22 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
};
static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
- REG64_IDX(HSW_CS_GPR, 0),
- REG64_IDX(HSW_CS_GPR, 1),
- REG64_IDX(HSW_CS_GPR, 2),
- REG64_IDX(HSW_CS_GPR, 3),
- REG64_IDX(HSW_CS_GPR, 4),
- REG64_IDX(HSW_CS_GPR, 5),
- REG64_IDX(HSW_CS_GPR, 6),
- REG64_IDX(HSW_CS_GPR, 7),
- REG64_IDX(HSW_CS_GPR, 8),
- REG64_IDX(HSW_CS_GPR, 9),
- REG64_IDX(HSW_CS_GPR, 10),
- REG64_IDX(HSW_CS_GPR, 11),
- REG64_IDX(HSW_CS_GPR, 12),
- REG64_IDX(HSW_CS_GPR, 13),
- REG64_IDX(HSW_CS_GPR, 14),
- REG64_IDX(HSW_CS_GPR, 15),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 9),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 10),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 11),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 12),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 13),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 14),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 15),
REG32(HSW_SCRATCH1,
.mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
.value = 0),
@@ -675,22 +679,22 @@ static const struct drm_i915_reg_descriptor gen9_blt_regs[] = {
REG32(BCS_SWCTRL),
REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),
- REG64_IDX(BCS_GPR, 0),
- REG64_IDX(BCS_GPR, 1),
- REG64_IDX(BCS_GPR, 2),
- REG64_IDX(BCS_GPR, 3),
- REG64_IDX(BCS_GPR, 4),
- REG64_IDX(BCS_GPR, 5),
- REG64_IDX(BCS_GPR, 6),
- REG64_IDX(BCS_GPR, 7),
- REG64_IDX(BCS_GPR, 8),
- REG64_IDX(BCS_GPR, 9),
- REG64_IDX(BCS_GPR, 10),
- REG64_IDX(BCS_GPR, 11),
- REG64_IDX(BCS_GPR, 12),
- REG64_IDX(BCS_GPR, 13),
- REG64_IDX(BCS_GPR, 14),
- REG64_IDX(BCS_GPR, 15),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 5),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 6),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 7),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 8),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 9),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 10),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 11),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 12),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 13),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 14),
+ REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 15),
};
#undef REG64
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 61ade07068c8..149cf4d25569 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -521,10 +521,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define BCS_SRC_Y REG_BIT(0)
#define BCS_DST_Y REG_BIT(1)
-/* There are 16 GPR registers */
-#define BCS_GPR(n) _MMIO(0x22600 + (n) * 8)
-#define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4)
-
#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
#define HS_INVOCATION_COUNT _MMIO(0x2300)
@@ -568,10 +564,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
-/* There are the 16 64-bit CS General Purpose Registers */
-#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
-#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
-
#define GEN7_OACONTROL _MMIO(0x2360)
#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 02/11] drm/i915: Parameterize PWRCTX_MAXCNT
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 01/11] drm/i915: Use parameterized GPR register definitions everywhere Matt Roper
@ 2022-01-11 5:15 ` Matt Roper
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 03/11] drm/i915: Parameterize ECOSKPD Matt Roper
` (13 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2022-01-11 5:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Rather than having separate definitions for each engine, create a single
parameterized macro that takes the engine base offset. This will also
ensure we get to the proper offset if we ever need to use these
registers on newer platforms (where the media engine offsets have
changed).
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 8 ++++----
drivers/gpu/drm/i915/i915_reg.h | 6 +-----
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index c3155ee58689..45891e6f0b98 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -449,10 +449,10 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
enable_rc6 = false;
}
- if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
+ if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
drm_dbg(&i915->drm,
"Engine Idle wait time not set properly.\n");
enable_rc6 = false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 149cf4d25569..3ef332833c4c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9048,11 +9048,7 @@ enum {
#define RC6_CTX_IN_DRAM (1 << 0)
#define RC6_CTX_BASE _MMIO(0xD48)
#define RC6_CTX_BASE_MASK 0xFFFFFFF0
-#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
-#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
-#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
-#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
-#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
+#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
#define IDLE_TIME_MASK 0xFFFFF
#define FORCEWAKE _MMIO(0xA18C)
#define FORCEWAKE_VLV _MMIO(0x1300b0)
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 03/11] drm/i915: Parameterize ECOSKPD
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 01/11] drm/i915: Use parameterized GPR register definitions everywhere Matt Roper
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 02/11] drm/i915: Parameterize PWRCTX_MAXCNT Matt Roper
@ 2022-01-11 5:15 ` Matt Roper
2022-01-12 15:09 ` Ville Syrjälä
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 04/11] drm/i915: Use RING_PSMI_CTL rather than per-engine macros Matt Roper
` (12 subsequent siblings)
15 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2022-01-11 5:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Combine the separate render and blitter register definitions into a
single definition. We already know we have some workarounds on an
upcoming platform that will need to update the ECOSKPD register for
other engines too, so this helps pave the way for that.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 14 ++++++--------
drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
4 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ab3277a3d593..2d87dc81cd63 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2536,7 +2536,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* they are already accustomed to from before contexts were
* enabled.
*/
- wa_add(wal, ECOSKPD,
+ wa_add(wal, ECOSKPD(RENDER_RING_BASE),
0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
0 /* XXX bit doesn't stick on Broadwater */,
true);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 3938df0db188..329d30a36f4f 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2877,9 +2877,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_D(_MMIO(0x3c), D_ALL);
MMIO_D(_MMIO(0x860), D_ALL);
- MMIO_D(ECOSKPD, D_ALL);
+ MMIO_D(ECOSKPD(RENDER_RING_BASE), D_ALL);
MMIO_D(_MMIO(0x121d0), D_ALL);
- MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
+ MMIO_D(ECOSKPD(BLT_RING_BASE), D_ALL);
MMIO_D(_MMIO(0x41d0), D_ALL);
MMIO_D(GAC_ECO_BITS, D_ALL);
MMIO_D(_MMIO(0x6200), D_ALL);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ef332833c4c..a4c9d2005c46 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2858,10 +2858,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
#define GFX_FLSH_CNTL_EN (1 << 0)
-#define ECOSKPD _MMIO(0x21d0)
-#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
-#define ECO_GATING_CX_ONLY (1 << 3)
-#define ECO_FLIP_DONE (1 << 0)
+#define ECOSKPD(base) _MMIO((base) + 0x1d0)
+#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
+#define ECO_GATING_CX_ONLY REG_BIT(3)
+#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
+#define ECO_FLIP_DONE REG_BIT(0)
+#define GEN6_BLITTER_LOCK_SHIFT 16
#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
#define RC_OP_FLUSH_ENABLE (1 << 0)
@@ -2871,10 +2873,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
-#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
-#define GEN6_BLITTER_LOCK_SHIFT 16
-#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
-
#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8b357ec35a4a..2d0955d13776 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7868,10 +7868,12 @@ static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
if (IS_PINEVIEW(dev_priv))
- intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
+ intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
+ _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
/* IIR "flip pending" means done if this bit is set */
- intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
+ intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
+ _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
/* interrupts should cause a wake up from C3 */
intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Intel-gfx] [PATCH v3 03/11] drm/i915: Parameterize ECOSKPD
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 03/11] drm/i915: Parameterize ECOSKPD Matt Roper
@ 2022-01-12 15:09 ` Ville Syrjälä
2022-01-13 4:14 ` Matt Roper
0 siblings, 1 reply; 29+ messages in thread
From: Ville Syrjälä @ 2022-01-12 15:09 UTC (permalink / raw)
To: Matt Roper; +Cc: Jani Nikula, intel-gfx
On Mon, Jan 10, 2022 at 09:15:52PM -0800, Matt Roper wrote:
> Combine the separate render and blitter register definitions into a
> single definition. We already know we have some workarounds on an
> upcoming platform that will need to update the ECOSKPD register for
> other engines too, so this helps pave the way for that.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 14 ++++++--------
> drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
> 4 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index ab3277a3d593..2d87dc81cd63 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2536,7 +2536,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> * they are already accustomed to from before contexts were
> * enabled.
> */
> - wa_add(wal, ECOSKPD,
> + wa_add(wal, ECOSKPD(RENDER_RING_BASE),
> 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
> 0 /* XXX bit doesn't stick on Broadwater */,
> true);
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 3938df0db188..329d30a36f4f 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2877,9 +2877,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>
> MMIO_D(_MMIO(0x3c), D_ALL);
> MMIO_D(_MMIO(0x860), D_ALL);
> - MMIO_D(ECOSKPD, D_ALL);
> + MMIO_D(ECOSKPD(RENDER_RING_BASE), D_ALL);
> MMIO_D(_MMIO(0x121d0), D_ALL);
> - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
> + MMIO_D(ECOSKPD(BLT_RING_BASE), D_ALL);
> MMIO_D(_MMIO(0x41d0), D_ALL);
> MMIO_D(GAC_ECO_BITS, D_ALL);
> MMIO_D(_MMIO(0x6200), D_ALL);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3ef332833c4c..a4c9d2005c46 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2858,10 +2858,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
> #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
> #define GFX_FLSH_CNTL_EN (1 << 0)
> -#define ECOSKPD _MMIO(0x21d0)
> -#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
> -#define ECO_GATING_CX_ONLY (1 << 3)
> -#define ECO_FLIP_DONE (1 << 0)
> +#define ECOSKPD(base) _MMIO((base) + 0x1d0)
> +#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
> +#define ECO_GATING_CX_ONLY REG_BIT(3)
> +#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
> +#define ECO_FLIP_DONE REG_BIT(0)
> +#define GEN6_BLITTER_LOCK_SHIFT 16
This looks messy. The register contents are (mostly?) unique for
each engine, so this is making it rather hard to see which register
takes which bits. I think we should at least group the bits clearly
based on which engine they belong to.
>
> #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
> #define RC_OP_FLUSH_ENABLE (1 << 0)
> @@ -2871,10 +2873,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
> #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
>
> -#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
> -#define GEN6_BLITTER_LOCK_SHIFT 16
> -#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
> -
> #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
> #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
> #define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8b357ec35a4a..2d0955d13776 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7868,10 +7868,12 @@ static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
> intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
>
> if (IS_PINEVIEW(dev_priv))
> - intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
> + intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
> + _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
>
> /* IIR "flip pending" means done if this bit is set */
> - intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
> + intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
> + _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
>
> /* interrupts should cause a wake up from C3 */
> intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
> --
> 2.34.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Intel-gfx] [PATCH v3 03/11] drm/i915: Parameterize ECOSKPD
2022-01-12 15:09 ` Ville Syrjälä
@ 2022-01-13 4:14 ` Matt Roper
2022-01-13 9:06 ` Jani Nikula
0 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2022-01-13 4:14 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Jani Nikula, intel-gfx
On Wed, Jan 12, 2022 at 05:09:55PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 10, 2022 at 09:15:52PM -0800, Matt Roper wrote:
> > Combine the separate render and blitter register definitions into a
> > single definition. We already know we have some workarounds on an
> > upcoming platform that will need to update the ECOSKPD register for
> > other engines too, so this helps pave the way for that.
> >
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> > drivers/gpu/drm/i915/gvt/handlers.c | 4 ++--
> > drivers/gpu/drm/i915/i915_reg.h | 14 ++++++--------
> > drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
> > 4 files changed, 13 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index ab3277a3d593..2d87dc81cd63 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -2536,7 +2536,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > * they are already accustomed to from before contexts were
> > * enabled.
> > */
> > - wa_add(wal, ECOSKPD,
> > + wa_add(wal, ECOSKPD(RENDER_RING_BASE),
> > 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
> > 0 /* XXX bit doesn't stick on Broadwater */,
> > true);
> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> > index 3938df0db188..329d30a36f4f 100644
> > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> > @@ -2877,9 +2877,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> >
> > MMIO_D(_MMIO(0x3c), D_ALL);
> > MMIO_D(_MMIO(0x860), D_ALL);
> > - MMIO_D(ECOSKPD, D_ALL);
> > + MMIO_D(ECOSKPD(RENDER_RING_BASE), D_ALL);
> > MMIO_D(_MMIO(0x121d0), D_ALL);
> > - MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
> > + MMIO_D(ECOSKPD(BLT_RING_BASE), D_ALL);
> > MMIO_D(_MMIO(0x41d0), D_ALL);
> > MMIO_D(GAC_ECO_BITS, D_ALL);
> > MMIO_D(_MMIO(0x6200), D_ALL);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3ef332833c4c..a4c9d2005c46 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2858,10 +2858,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> > #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
> > #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
> > #define GFX_FLSH_CNTL_EN (1 << 0)
> > -#define ECOSKPD _MMIO(0x21d0)
> > -#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
> > -#define ECO_GATING_CX_ONLY (1 << 3)
> > -#define ECO_FLIP_DONE (1 << 0)
> > +#define ECOSKPD(base) _MMIO((base) + 0x1d0)
> > +#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
> > +#define ECO_GATING_CX_ONLY REG_BIT(3)
> > +#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
> > +#define ECO_FLIP_DONE REG_BIT(0)
> > +#define GEN6_BLITTER_LOCK_SHIFT 16
>
> This looks messy. The register contents are (mostly?) unique for
> each engine, so this is making it rather hard to see which register
> takes which bits. I think we should at least group the bits clearly
> based on which engine they belong to.
Makes sense. I'll send a follow-up patch tomorrow that reorganizes this
a bit.
Matt
>
> >
> > #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
> > #define RC_OP_FLUSH_ENABLE (1 << 0)
> > @@ -2871,10 +2873,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> > #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
> > #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
> >
> > -#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
> > -#define GEN6_BLITTER_LOCK_SHIFT 16
> > -#define GEN6_BLITTER_FBC_NOTIFY (1 << 3)
> > -
> > #define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
> > #define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
> > #define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 8b357ec35a4a..2d0955d13776 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -7868,10 +7868,12 @@ static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
> > intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
> >
> > if (IS_PINEVIEW(dev_priv))
> > - intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
> > + intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
> > + _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
> >
> > /* IIR "flip pending" means done if this bit is set */
> > - intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
> > + intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
> > + _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
> >
> > /* interrupts should cause a wake up from C3 */
> > intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
> > --
> > 2.34.1
>
> --
> Ville Syrjälä
> Intel
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Intel-gfx] [PATCH v3 03/11] drm/i915: Parameterize ECOSKPD
2022-01-13 4:14 ` Matt Roper
@ 2022-01-13 9:06 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2022-01-13 9:06 UTC (permalink / raw)
To: Matt Roper, Ville Syrjälä; +Cc: intel-gfx
On Wed, 12 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Wed, Jan 12, 2022 at 05:09:55PM +0200, Ville Syrjälä wrote:
>> On Mon, Jan 10, 2022 at 09:15:52PM -0800, Matt Roper wrote:
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index 3ef332833c4c..a4c9d2005c46 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -2858,10 +2858,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>> > #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
>> > #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
>> > #define GFX_FLSH_CNTL_EN (1 << 0)
>> > -#define ECOSKPD _MMIO(0x21d0)
>> > -#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
>> > -#define ECO_GATING_CX_ONLY (1 << 3)
>> > -#define ECO_FLIP_DONE (1 << 0)
>> > +#define ECOSKPD(base) _MMIO((base) + 0x1d0)
>> > +#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
>> > +#define ECO_GATING_CX_ONLY REG_BIT(3)
>> > +#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
>> > +#define ECO_FLIP_DONE REG_BIT(0)
>> > +#define GEN6_BLITTER_LOCK_SHIFT 16
>>
>> This looks messy. The register contents are (mostly?) unique for
>> each engine, so this is making it rather hard to see which register
>> takes which bits. I think we should at least group the bits clearly
>> based on which engine they belong to.
>
> Makes sense. I'll send a follow-up patch tomorrow that reorganizes this
> a bit.
For things that you're rearranging in the series, sure, please clean it
up. But for stuff already in i915_reg.h, let's not let those block this
work. Split up the file, and IMO the cleanup will be easier in the
smaller files with follow-up patches.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH v3 04/11] drm/i915: Use RING_PSMI_CTL rather than per-engine macros
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (2 preceding siblings ...)
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 03/11] drm/i915: Parameterize ECOSKPD Matt Roper
@ 2022-01-11 5:15 ` Matt Roper
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 05/11] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7 Matt Roper
` (11 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2022-01-11 5:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
We have a parameterized macro for RING_PSMI_CTL; let's use that instead
of the per-engine definitions where possible.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 10 +++++-----
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 19 +++++++------------
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
4 files changed, 15 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 3e6fac0340ef..56c009ecfdf2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1002,15 +1002,15 @@ static void gen6_bsd_submit_request(struct i915_request *request)
/* Disable notification that the ring is IDLE. The GT
* will then assume that it is busy and bring it out of rc6.
*/
- intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
- _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
+ intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
+ _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
/* Clear the context id. Here be magic! */
intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);
/* Wait for the ring not to be idle, i.e. for it to wake up. */
if (__intel_wait_for_register_fw(uncore,
- GEN6_BSD_SLEEP_PSMI_CONTROL,
+ RING_PSMI_CTL(GEN6_BSD_RING_BASE),
GEN6_BSD_SLEEP_INDICATOR,
0,
1000, 0, NULL))
@@ -1023,8 +1023,8 @@ static void gen6_bsd_submit_request(struct i915_request *request)
/* Let the ring send IDLE messages to the GT again,
* and so let it sleep to conserve power when idle.
*/
- intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
- _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
+ intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),
+ _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2d87dc81cd63..977619ea839a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2208,7 +2208,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* For DG1 this only applies to A0.
*/
wa_masked_en(wal,
- GEN6_RC_SLEEP_PSMI_CONTROL,
+ RING_PSMI_CTL(RENDER_RING_BASE),
GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
GEN8_RC_SEMA_IDLE_MSG_DISABLE);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a4c9d2005c46..0be2397fc61e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2314,6 +2314,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
#define GEN6_NOSYNC INVALID_MMIO_REG
#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
+#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
+#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
+#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
+#define GEN6_BSD_GO_INDICATOR REG_BIT(4)
+#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
+#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
+#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
#define RING_ID(base) _MMIO((base) + 0x8c)
@@ -2873,12 +2880,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6)
#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1)
-#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
-#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
-#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
-#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
-#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10)
-
#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
@@ -2964,12 +2965,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define XEHP_EU_ENABLE _MMIO(0x9134)
#define XEHP_EU_ENA_MASK 0xFF
-#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
-#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
-#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
-#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
-#define GEN6_BSD_GO_INDICATOR (1 << 4)
-
/* On modern GEN architectures interrupt control consists of two sets
* of registers. The first set pertains to the ring generating the
* interrupt. The second control is for the functional block generating the
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2d0955d13776..710dee28a014 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7654,7 +7654,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
- intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
+ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
/* WaDisableSDEUnitClockGating:bdw */
@@ -7795,7 +7795,7 @@ static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
/* WaDisableSemaphoreAndSyncFlipWait:chv */
- intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
+ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
/* WaDisableCSUnitClockGating:chv */
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 05/11] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (3 preceding siblings ...)
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 04/11] drm/i915: Use RING_PSMI_CTL rather than per-engine macros Matt Roper
@ 2022-01-11 5:15 ` Matt Roper
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 06/11] drm/i915: Introduce i915_reg_defs.h Matt Roper
` (10 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2022-01-11 5:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
It's preferable to use parameterized register macros where possible.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 -
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 977619ea839a..895939a941d6 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2423,7 +2423,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (GRAPHICS_VER(i915) == 7) {
/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
wa_masked_en(wal,
- GFX_MODE_GEN7,
+ RING_MODE_GEN7(RENDER_RING_BASE),
GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
/* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index f776c470914d..abc81cdc9e5d 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -44,7 +44,7 @@
/* Raw offset is appened to each line for convenience. */
static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
- {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
+ {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
@@ -76,7 +76,7 @@ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
};
static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
- {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
+ {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0be2397fc61e..25f6bde36add 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2669,7 +2669,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
#define GFX_MODE _MMIO(0x2520)
-#define GFX_MODE_GEN7 _MMIO(0x229c)
#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
#define GFX_RUN_LIST_ENABLE (1 << 15)
#define GFX_INTERRUPT_STEERING (1 << 14)
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 06/11] drm/i915: Introduce i915_reg_defs.h
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (4 preceding siblings ...)
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 05/11] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7 Matt Roper
@ 2022-01-11 5:15 ` Matt Roper
2022-01-11 8:42 ` Jani Nikula
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 07/11] drm/i915/gt: Move engine registers to their own header Matt Roper
` (9 subsequent siblings)
15 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2022-01-11 5:15 UTC (permalink / raw)
To: intel-gfx
We'd like to start splitting i915_reg.h into various domain-specific
register files and cleaning them up. Let's move the basic macros and
type definitions to their own header file that can be including in each
of the new split headers.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 88 +------------------------
drivers/gpu/drm/i915/i915_reg_defs.h | 98 ++++++++++++++++++++++++++++
2 files changed, 99 insertions(+), 87 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_reg_defs.h
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 25f6bde36add..b7e03b6e886d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,8 +25,7 @@
#ifndef _I915_REG_H_
#define _I915_REG_H_
-#include <linux/bitfield.h>
-#include <linux/bits.h>
+#include "i915_reg_defs.h"
/**
* DOC: The i915 register macro definition style guide
@@ -116,91 +115,6 @@
* #define GEN8_BAR _MMIO(0xb888)
*/
-/**
- * REG_BIT() - Prepare a u32 bit value
- * @__n: 0-based bit number
- *
- * Local wrapper for BIT() to force u32, with compile time checks.
- *
- * @return: Value with bit @__n set.
- */
-#define REG_BIT(__n) \
- ((u32)(BIT(__n) + \
- BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
- ((__n) < 0 || (__n) > 31))))
-
-/**
- * REG_GENMASK() - Prepare a continuous u32 bitmask
- * @__high: 0-based high bit
- * @__low: 0-based low bit
- *
- * Local wrapper for GENMASK() to force u32, with compile time checks.
- *
- * @return: Continuous bitmask from @__high to @__low, inclusive.
- */
-#define REG_GENMASK(__high, __low) \
- ((u32)(GENMASK(__high, __low) + \
- BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
- __is_constexpr(__low) && \
- ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-
-/*
- * Local integer constant expression version of is_power_of_2().
- */
-#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
-
-/**
- * REG_FIELD_PREP() - Prepare a u32 bitfield value
- * @__mask: shifted mask defining the field's length and position
- * @__val: value to put in the field
- *
- * Local copy of FIELD_PREP() to generate an integer constant expression, force
- * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
- *
- * @return: @__val masked and shifted into the field defined by @__mask.
- */
-#define REG_FIELD_PREP(__mask, __val) \
- ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
- BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
- BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
- BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
- BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-
-/**
- * REG_FIELD_GET() - Extract a u32 bitfield value
- * @__mask: shifted mask defining the field's length and position
- * @__val: value to extract the bitfield value from
- *
- * Local wrapper for FIELD_GET() to force u32 and for consistency with
- * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
- *
- * @return: Masked and shifted value of the field defined by @__mask in @__val.
- */
-#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
-
-typedef struct {
- u32 reg;
-} i915_reg_t;
-
-#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
-
-#define INVALID_MMIO_REG _MMIO(0)
-
-static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
-{
- return reg.reg;
-}
-
-static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
-{
- return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
-}
-
-static inline bool i915_mmio_reg_valid(i915_reg_t reg)
-{
- return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
-}
-
#define VLV_DISPLAY_BASE 0x180000
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
#define BXT_MIPI_BASE 0x60000
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
new file mode 100644
index 000000000000..5f64aa086ace
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __I915_REG_DEFS__
+#define __I915_REG_DEFS__
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+
+/**
+ * REG_BIT() - Prepare a u32 bit value
+ * @__n: 0-based bit number
+ *
+ * Local wrapper for BIT() to force u32, with compile time checks.
+ *
+ * @return: Value with bit @__n set.
+ */
+#define REG_BIT(__n) \
+ ((u32)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 31))))
+
+/**
+ * REG_GENMASK() - Prepare a continuous u32 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u32, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
+
+/*
+ * Local integer constant expression version of is_power_of_2().
+ */
+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
+
+/**
+ * REG_FIELD_PREP() - Prepare a u32 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to put in the field
+ *
+ * Local copy of FIELD_PREP() to generate an integer constant expression, force
+ * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: @__val masked and shifted into the field defined by @__mask.
+ */
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
+
+/**
+ * REG_FIELD_GET() - Extract a u32 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to extract the bitfield value from
+ *
+ * Local wrapper for FIELD_GET() to force u32 and for consistency with
+ * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
+ */
+#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
+
+typedef struct {
+ u32 reg;
+} i915_reg_t;
+
+#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
+
+#define INVALID_MMIO_REG _MMIO(0)
+
+static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
+{
+ return reg.reg;
+}
+
+static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
+{
+ return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
+}
+
+static inline bool i915_mmio_reg_valid(i915_reg_t reg)
+{
+ return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
+}
+
+
+#endif /* __I915_REG_DEFS__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Intel-gfx] [PATCH v3 06/11] drm/i915: Introduce i915_reg_defs.h
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 06/11] drm/i915: Introduce i915_reg_defs.h Matt Roper
@ 2022-01-11 8:42 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2022-01-11 8:42 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Mon, 10 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> We'd like to start splitting i915_reg.h into various domain-specific
> register files and cleaning them up. Let's move the basic macros and
> type definitions to their own header file that can be including in each
> of the new split headers.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
One nitpick near the end, can be fixed while applying, otherwise,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 88 +------------------------
> drivers/gpu/drm/i915/i915_reg_defs.h | 98 ++++++++++++++++++++++++++++
> 2 files changed, 99 insertions(+), 87 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/i915_reg_defs.h
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 25f6bde36add..b7e03b6e886d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -25,8 +25,7 @@
> #ifndef _I915_REG_H_
> #define _I915_REG_H_
>
> -#include <linux/bitfield.h>
> -#include <linux/bits.h>
> +#include "i915_reg_defs.h"
>
> /**
> * DOC: The i915 register macro definition style guide
> @@ -116,91 +115,6 @@
> * #define GEN8_BAR _MMIO(0xb888)
> */
>
> -/**
> - * REG_BIT() - Prepare a u32 bit value
> - * @__n: 0-based bit number
> - *
> - * Local wrapper for BIT() to force u32, with compile time checks.
> - *
> - * @return: Value with bit @__n set.
> - */
> -#define REG_BIT(__n) \
> - ((u32)(BIT(__n) + \
> - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
> - ((__n) < 0 || (__n) > 31))))
> -
> -/**
> - * REG_GENMASK() - Prepare a continuous u32 bitmask
> - * @__high: 0-based high bit
> - * @__low: 0-based low bit
> - *
> - * Local wrapper for GENMASK() to force u32, with compile time checks.
> - *
> - * @return: Continuous bitmask from @__high to @__low, inclusive.
> - */
> -#define REG_GENMASK(__high, __low) \
> - ((u32)(GENMASK(__high, __low) + \
> - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
> - __is_constexpr(__low) && \
> - ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
> -
> -/*
> - * Local integer constant expression version of is_power_of_2().
> - */
> -#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
> -
> -/**
> - * REG_FIELD_PREP() - Prepare a u32 bitfield value
> - * @__mask: shifted mask defining the field's length and position
> - * @__val: value to put in the field
> - *
> - * Local copy of FIELD_PREP() to generate an integer constant expression, force
> - * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
> - *
> - * @return: @__val masked and shifted into the field defined by @__mask.
> - */
> -#define REG_FIELD_PREP(__mask, __val) \
> - ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
> - BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
> - BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
> - BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
> - BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
> -
> -/**
> - * REG_FIELD_GET() - Extract a u32 bitfield value
> - * @__mask: shifted mask defining the field's length and position
> - * @__val: value to extract the bitfield value from
> - *
> - * Local wrapper for FIELD_GET() to force u32 and for consistency with
> - * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
> - *
> - * @return: Masked and shifted value of the field defined by @__mask in @__val.
> - */
> -#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
> -
> -typedef struct {
> - u32 reg;
> -} i915_reg_t;
> -
> -#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
> -
> -#define INVALID_MMIO_REG _MMIO(0)
> -
> -static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
> -{
> - return reg.reg;
> -}
> -
> -static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
> -{
> - return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
> -}
> -
> -static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> -{
> - return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
> -}
> -
> #define VLV_DISPLAY_BASE 0x180000
> #define VLV_MIPI_BASE VLV_DISPLAY_BASE
> #define BXT_MIPI_BASE 0x60000
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
> new file mode 100644
> index 000000000000..5f64aa086ace
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -0,0 +1,98 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __I915_REG_DEFS__
> +#define __I915_REG_DEFS__
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +
> +/**
> + * REG_BIT() - Prepare a u32 bit value
> + * @__n: 0-based bit number
> + *
> + * Local wrapper for BIT() to force u32, with compile time checks.
> + *
> + * @return: Value with bit @__n set.
> + */
> +#define REG_BIT(__n) \
> + ((u32)(BIT(__n) + \
> + BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
> + ((__n) < 0 || (__n) > 31))))
> +
> +/**
> + * REG_GENMASK() - Prepare a continuous u32 bitmask
> + * @__high: 0-based high bit
> + * @__low: 0-based low bit
> + *
> + * Local wrapper for GENMASK() to force u32, with compile time checks.
> + *
> + * @return: Continuous bitmask from @__high to @__low, inclusive.
> + */
> +#define REG_GENMASK(__high, __low) \
> + ((u32)(GENMASK(__high, __low) + \
> + BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
> + __is_constexpr(__low) && \
> + ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
> +
> +/*
> + * Local integer constant expression version of is_power_of_2().
> + */
> +#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
> +
> +/**
> + * REG_FIELD_PREP() - Prepare a u32 bitfield value
> + * @__mask: shifted mask defining the field's length and position
> + * @__val: value to put in the field
> + *
> + * Local copy of FIELD_PREP() to generate an integer constant expression, force
> + * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
> + *
> + * @return: @__val masked and shifted into the field defined by @__mask.
> + */
> +#define REG_FIELD_PREP(__mask, __val) \
> + ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
> + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
> + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
> + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
> + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
> +
> +/**
> + * REG_FIELD_GET() - Extract a u32 bitfield value
> + * @__mask: shifted mask defining the field's length and position
> + * @__val: value to extract the bitfield value from
> + *
> + * Local wrapper for FIELD_GET() to force u32 and for consistency with
> + * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
> + *
> + * @return: Masked and shifted value of the field defined by @__mask in @__val.
> + */
> +#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
> +
> +typedef struct {
> + u32 reg;
> +} i915_reg_t;
> +
> +#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
> +
> +#define INVALID_MMIO_REG _MMIO(0)
> +
> +static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
> +{
> + return reg.reg;
> +}
> +
> +static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
> +{
> + return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
> +}
> +
> +static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> +{
> + return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
> +}
> +
> +
The double newline is going to give a checkpatch complaint.
> +#endif /* __I915_REG_DEFS__ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH v3 07/11] drm/i915/gt: Move engine registers to their own header
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (5 preceding siblings ...)
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 06/11] drm/i915: Introduce i915_reg_defs.h Matt Roper
@ 2022-01-11 5:15 ` Matt Roper
2022-01-11 16:29 ` Lucas De Marchi
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 08/11] drm/i915: Move SNPS PHY " Matt Roper
` (8 subsequent siblings)
15 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2022-01-11 5:15 UTC (permalink / raw)
To: intel-gfx
Let's start breaking up and cleaning up the massive i915_reg.h file.
We'll start by moving all registers that are defined in relation to an
engine base to their own header.
There are probably a bunch of other "engine registers" that we haven't
moved yet (especially those that belong to the render engine in the
0x2??? range), but this is a relatively straightforward first step.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 197 ++++++++++++++++++
.../drm/i915/gt/intel_execlists_submission.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 15 --
drivers/gpu/drm/i915/gt/intel_rc6.c | 1 +
drivers/gpu/drm/i915/gt/intel_reset.c | 1 +
drivers/gpu/drm/i915/gt/intel_ring.c | 1 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 1 +
drivers/gpu/drm/i915/gt/selftest_timeline.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/mmio_context.c | 1 +
drivers/gpu/drm/i915/gvt/mmio_context.h | 1 +
drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
drivers/gpu/drm/i915/i915_perf.c | 1 +
drivers/gpu/drm/i915/i915_pmu.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 179 +---------------
drivers/gpu/drm/i915/i915_request.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
31 files changed, 228 insertions(+), 194 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_regs.h
diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
index 61383830505e..e0e8d228b31f 100644
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
@@ -6,6 +6,7 @@
#include "gen2_engine_cs.h"
#include "i915_drv.h"
#include "intel_engine.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
index b388ceeeb1c9..5e65550b4dfb 100644
--- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
@@ -5,6 +5,7 @@
#include "gen6_engine_cs.h"
#include "intel_engine.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 6e9292918bfc..56999186830b 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -9,6 +9,7 @@
#include "i915_scatterlist.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
/* Write pde (index) from the page directory @pd to the page table @pt */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 548d599c09dc..30c199bb6ce5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -13,6 +13,7 @@
#include "intel_context.h"
#include "intel_engine.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_engine_user.h"
#include "intel_execlists_submission.h"
#include "intel_gt.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
new file mode 100644
index 000000000000..60511f310767
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_ENGINE_REGS__
+#define __INTEL_ENGINE_REGS__
+
+#include "i915_reg_defs.h"
+
+#define RING_TAIL(base) _MMIO((base) + 0x30)
+#define TAIL_ADDR 0x001FFFF8
+#define RING_HEAD(base) _MMIO((base) + 0x34)
+#define HEAD_WRAP_COUNT 0xFFE00000
+#define HEAD_WRAP_ONE 0x00200000
+#define HEAD_ADDR 0x001FFFFC
+#define RING_START(base) _MMIO((base) + 0x38)
+#define RING_CTL(base) _MMIO((base) + 0x3c)
+#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
+#define RING_NR_PAGES 0x001FF000
+#define RING_REPORT_MASK 0x00000006
+#define RING_REPORT_64K 0x00000002
+#define RING_REPORT_128K 0x00000004
+#define RING_NO_REPORT 0x00000000
+#define RING_VALID_MASK 0x00000001
+#define RING_VALID 0x00000001
+#define RING_INVALID 0x00000000
+#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
+#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
+#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
+#define RING_SYNC_0(base) _MMIO((base) + 0x40)
+#define RING_SYNC_1(base) _MMIO((base) + 0x44)
+#define RING_SYNC_2(base) _MMIO((base) + 0x48)
+#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
+#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
+#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
+#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
+#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
+#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
+#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
+#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
+#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
+#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
+#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
+#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
+#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
+#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
+#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
+#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
+#define GEN6_BSD_GO_INDICATOR REG_BIT(4)
+#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
+#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
+#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
+#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
+#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
+#define IDLE_TIME_MASK 0xFFFFF
+#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
+#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
+#define RING_IPEIR(base) _MMIO((base) + 0x64)
+#define RING_IPEHR(base) _MMIO((base) + 0x68)
+#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
+#define RING_INSTPS(base) _MMIO((base) + 0x70)
+#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
+#define RING_ACTHD(base) _MMIO((base) + 0x74)
+#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
+#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
+#define IPEIR(base) _MMIO((base) + 0x88)
+#define IPEHR(base) _MMIO((base) + 0x8c)
+#define RING_ID(base) _MMIO((base) + 0x8c)
+#define RING_NOPID(base) _MMIO((base) + 0x94)
+#define RING_HWSTAM(base) _MMIO((base) + 0x98)
+#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
+#define RING_IMR(base) _MMIO((base) + 0xa8)
+#define RING_EIR(base) _MMIO((base) + 0xb0)
+#define RING_EMR(base) _MMIO((base) + 0xb4)
+#define RING_ESR(base) _MMIO((base) + 0xb8)
+#define RING_INSTPM(base) _MMIO((base) + 0xc0)
+#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
+#define ACTHD(base) _MMIO((base) + 0xc8)
+#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
+#define RESET_CTL_CAT_ERROR REG_BIT(2)
+#define RESET_CTL_READY_TO_RESET REG_BIT(1)
+#define RESET_CTL_REQUEST_RESET REG_BIT(0)
+#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
+#define RING_BBSTATE(base) _MMIO((base) + 0x110)
+#define RING_BB_PPGTT (1 << 5)
+#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
+#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
+#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
+#define RING_BBADDR(base) _MMIO((base) + 0x140)
+#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
+#define CCID(base) _MMIO((base) + 0x180)
+#define CCID_EN BIT(0)
+#define CCID_EXTENDED_STATE_RESTORE BIT(2)
+#define CCID_EXTENDED_STATE_SAVE BIT(3)
+#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
+#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
+#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
+#define ECOSKPD(base) _MMIO((base) + 0x1d0)
+#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
+#define ECO_GATING_CX_ONLY REG_BIT(3)
+#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
+#define ECO_FLIP_DONE REG_BIT(0)
+#define GEN6_BLITTER_LOCK_SHIFT 16
+
+#define BLIT_CCTL(base) _MMIO((base) + 0x204)
+#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
+#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
+#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
+ BLIT_CCTL_SRC_MOCS_MASK)
+#define BLIT_CCTL_MOCS(dst, src) \
+ (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
+ REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
+
+/*
+ * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
+ * The lsb of each can be considered a separate enabling bit for encryption.
+ * 6:0 == default MOCS value for reads => 6:1 == table index for reads.
+ * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
+ * 15:14 == Reserved => 31:30 are set to 0.
+ */
+#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
+#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
+#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
+ CMD_CCTL_READ_OVERRIDE_MASK)
+#define CMD_CCTL_MOCS_OVERRIDE(write, read) \
+ (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
+ REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
+
+#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
+#define PP_DIR_DCLV_2G 0xffffffff
+#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
+#define RING_ELSP(base) _MMIO((base) + 0x230)
+#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
+#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
+#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
+#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
+#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
+#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)
+#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
+#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
+#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
+#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
+#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
+#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
+#define GFX_RUN_LIST_ENABLE (1 << 15)
+#define GFX_INTERRUPT_STEERING (1 << 14)
+#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
+#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
+#define GFX_REPLAY_MODE (1 << 11)
+#define GFX_PSMI_GRANULARITY (1 << 10)
+#define GFX_PPGTT_ENABLE (1 << 9)
+#define GEN8_GFX_PPGTT_48B (1 << 7)
+#define GFX_FORWARD_VBLANK_MASK (3 << 5)
+#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
+#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
+#define GFX_FORWARD_VBLANK_COND (2 << 5)
+#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
+#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
+#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
+#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
+#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
+#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
+#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
+#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
+#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
+#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
+#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
+#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
+#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
+#define RING_FORCE_TO_NONPRIV_MASK_VALID \
+ (RING_FORCE_TO_NONPRIV_RANGE_MASK | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
+#define RING_MAX_NONPRIV_SLOTS 12
+
+#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
+#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
+#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
+#define EL_CTRL_LOAD REG_BIT(0)
+
+/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
+#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
+#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
+
+#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
+
+#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
+#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
+
+#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
+#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
+
+
+#endif /* __INTEL_ENGINE_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index be56d0b41892..960a9aaf4f3a 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -116,6 +116,7 @@
#include "intel_context.h"
#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_engine_stats.h"
#include "intel_execlists_submission.h"
#include "intel_gt.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 298ff32c8d0c..622cdfed8a8b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -11,6 +11,7 @@
#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "intel_context.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_buffer_pool.h"
#include "intel_gt_clock_utils.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 84456ffeb4cd..89a95a125fc8 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -9,6 +9,7 @@
#include "i915_drv.h"
#include "i915_perf.h"
#include "intel_engine.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_lrc.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
index f785d0ed238f..304000c7e345 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
@@ -53,21 +53,6 @@
#define GEN8_EXECLISTS_STATUS_BUF 0x370
#define GEN11_EXECLISTS_STATUS_BUF2 0x3c0
-/* Execlists regs */
-#define RING_ELSP(base) _MMIO((base) + 0x230)
-#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
-#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
-#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
-#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0)
-#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1)
-#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2)
-#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3)
-#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8)
-#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
-#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
-#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
-#define EL_CTRL_LOAD REG_BIT(0)
-
/*
* The docs specify that the write pointer wraps around after 5h, "After status
* is written out to the last available status QW at offset 5h, this pointer
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 45891e6f0b98..31ebe3f1765d 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -7,6 +7,7 @@
#include "i915_drv.h"
#include "i915_vgpu.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_pcode.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index a75ef7bf36c3..6f2821cca409 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -16,6 +16,7 @@
#include "i915_irq.h"
#include "intel_breadcrumbs.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_gt_requests.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c
index 2fdd52b62092..723055340c9b 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -9,6 +9,7 @@
#include "i915_drv.h"
#include "i915_vma.h"
#include "intel_engine.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_ring.h"
#include "intel_timeline.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 56c009ecfdf2..a2b7be1d4f5c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -11,6 +11,7 @@
#include "i915_mitigations.h"
#include "intel_breadcrumbs.h"
#include "intel_context.h"
+#include "intel_engine_regs.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
#include "intel_reset.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 895939a941d6..6a4372c3a3c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "intel_context.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_ring.h"
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
index 8af261831470..0dcb3ed44a73 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
@@ -6,6 +6,7 @@
#include <linux/sort.h>
#include "i915_selftest.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt_clock_utils.h"
#include "selftest_engine.h"
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index 8bf62a5826cc..be94f863bdef 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -5,6 +5,7 @@
#include <linux/sort.h>
+#include "intel_engine_regs.h"
#include "intel_gt_clock_utils.h"
#include "selftest_llc.h"
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 7ee2513e15f9..bd170ba1cf00 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -8,6 +8,7 @@
#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt_clock_utils.h"
#include "intel_gt_pm.h"
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index e2eb686a9763..0410c402f2a3 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -8,6 +8,7 @@
#include "intel_context.h"
#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
+#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_gt_requests.h"
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 1a1edae67e4e..93a975597b4d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -5,6 +5,7 @@
#include <linux/bsearch.h>
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gt.h"
#include "gt/intel_lrc.h"
#include "gt/shmem_utils.h"
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9989d121127d..c4f9f051a695 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -9,8 +9,9 @@
#include "gt/gen8_engine_cs.h"
#include "gt/intel_breadcrumbs.h"
#include "gt/intel_context.h"
-#include "gt/intel_engine_pm.h"
#include "gt/intel_engine_heartbeat.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_clock_utils.h"
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index c4118b808268..733e68ea210a 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -37,6 +37,7 @@
#include <linux/slab.h>
#include "i915_drv.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_lrc.h"
#include "gt/intel_ring.h"
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index abc81cdc9e5d..99d3534d2bd8 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -35,6 +35,7 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
#include "gvt.h"
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.h b/drivers/gpu/drm/i915/gvt/mmio_context.h
index b6b69777af49..128fd7f4d509 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.h
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.h
@@ -38,6 +38,7 @@
#include <linux/types.h>
+#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_types.h"
#include "gt/intel_lrc_reg.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index a804373bcd17..96c398051084 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -26,6 +26,7 @@
*/
#include "gt/intel_engine.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "i915_cmd_parser.h"
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5ae812d60abe..edcc2ae6d66c 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -41,6 +41,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_lmem.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 298857b69180..14bf1b67aa43 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -197,6 +197,7 @@
#include "gem/i915_gem_context.h"
#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_execlists_submission.h"
#include "gt/intel_gpu_commands.h"
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index ea655161793e..bf93f9720e0a 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -8,6 +8,7 @@
#include "gt/intel_engine.h"
#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b7e03b6e886d..b504d67c2752 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -272,14 +272,6 @@
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
#define GEN12_SFC_DONE_MAX 4
-#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
-#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
-#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
-#define PP_DIR_DCLV_2G 0xffffffff
-
-#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
-#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
-
#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
#define GEN8_RPCS_ENABLE (1 << 31)
#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
@@ -2206,71 +2198,8 @@
#define XEHP_VEBOX3_RING_BASE 0x1e8000
#define XEHP_VEBOX4_RING_BASE 0x1f8000
#define BLT_RING_BASE 0x22000
-#define RING_TAIL(base) _MMIO((base) + 0x30)
-#define RING_HEAD(base) _MMIO((base) + 0x34)
-#define RING_START(base) _MMIO((base) + 0x38)
-#define RING_CTL(base) _MMIO((base) + 0x3c)
-#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
-#define RING_SYNC_0(base) _MMIO((base) + 0x40)
-#define RING_SYNC_1(base) _MMIO((base) + 0x44)
-#define RING_SYNC_2(base) _MMIO((base) + 0x48)
-#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
-#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
-#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
-#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
-#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
-#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
-#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
-#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
-#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
-#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
-#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
-#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
-#define GEN6_NOSYNC INVALID_MMIO_REG
-#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
-#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
-#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
-#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
-#define GEN6_BSD_GO_INDICATOR REG_BIT(4)
-#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
-#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
-#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
-#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
-#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
-#define RING_ID(base) _MMIO((base) + 0x8c)
-#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
-
-#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
-/*
- * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
- * The lsb of each can be considered a separate enabling bit for encryption.
- * 6:0 == default MOCS value for reads => 6:1 == table index for reads.
- * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
- * 15:14 == Reserved => 31:30 are set to 0.
- */
-#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
-#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
-#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \
- CMD_CCTL_READ_OVERRIDE_MASK)
-#define CMD_CCTL_MOCS_OVERRIDE(write, read) \
- (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
- REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
-
-#define BLIT_CCTL(base) _MMIO((base) + 0x204)
-#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
-#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
-#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \
- BLIT_CCTL_SRC_MOCS_MASK)
-#define BLIT_CCTL_MOCS(dst, src) \
- (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
- REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
-
-#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
-#define RESET_CTL_CAT_ERROR REG_BIT(2)
-#define RESET_CTL_READY_TO_RESET REG_BIT(1)
-#define RESET_CTL_REQUEST_RESET REG_BIT(0)
-
-#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
+
+
#define HSW_GTT_CACHE_EN _MMIO(0x4024)
#define GTT_CACHE_EN_ALL 0xF0007FFF
@@ -2325,52 +2254,9 @@
#define AUX_INV REG_BIT(0)
#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
-#define RING_ACTHD(base) _MMIO((base) + 0x74)
-#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c)
-#define RING_NOPID(base) _MMIO((base) + 0x94)
-#define RING_IMR(base) _MMIO((base) + 0xa8)
-#define RING_HWSTAM(base) _MMIO((base) + 0x98)
-#define RING_TIMESTAMP(base) _MMIO((base) + 0x358)
-#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4)
-#define TAIL_ADDR 0x001FFFF8
-#define HEAD_WRAP_COUNT 0xFFE00000
-#define HEAD_WRAP_ONE 0x00200000
-#define HEAD_ADDR 0x001FFFFC
-#define RING_NR_PAGES 0x001FF000
-#define RING_REPORT_MASK 0x00000006
-#define RING_REPORT_64K 0x00000002
-#define RING_REPORT_128K 0x00000004
-#define RING_NO_REPORT 0x00000000
-#define RING_VALID_MASK 0x00000001
-#define RING_VALID 0x00000001
-#define RING_INVALID 0x00000000
-#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */
-#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */
-#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */
#define GUCPMTIMESTAMP _MMIO(0xC3E8)
-/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
-#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8)
-#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4)
-
-#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
-#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
-#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */
-#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28)
-#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28)
-#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */
-#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0)
-#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0)
-#define RING_FORCE_TO_NONPRIV_MASK_VALID \
- (RING_FORCE_TO_NONPRIV_RANGE_MASK \
- | RING_FORCE_TO_NONPRIV_ACCESS_MASK)
-#define RING_MAX_NONPRIV_SLOTS 12
-
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
@@ -2414,23 +2300,11 @@
#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
-#define RING_IPEIR(base) _MMIO((base) + 0x64)
-#define RING_IPEHR(base) _MMIO((base) + 0x68)
-#define RING_EIR(base) _MMIO((base) + 0xb0)
-#define RING_EMR(base) _MMIO((base) + 0xb4)
-#define RING_ESR(base) _MMIO((base) + 0xb8)
/*
* On GEN4, only the render ring INSTDONE exists and has a different
* layout than the GEN7+ version.
* The GEN2 counterpart of this register is GEN2_INSTDONE.
*/
-#define RING_INSTDONE(base) _MMIO((base) + 0x6c)
-#define RING_INSTPS(base) _MMIO((base) + 0x70)
-#define RING_DMA_FADD(base) _MMIO((base) + 0x78)
-#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
-#define RING_INSTPM(base) _MMIO((base) + 0xc0)
-#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
-#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
#define INSTPS _MMIO(0x2070) /* 965+ only */
#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
#define ACTHD_I965 _MMIO(0x2074)
@@ -2439,29 +2313,9 @@
#define HWS_START_ADDRESS_SHIFT 4
#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
#define PWRCTX_EN (1 << 0)
-#define IPEIR(base) _MMIO((base) + 0x88)
-#define IPEHR(base) _MMIO((base) + 0x8c)
#define GEN2_INSTDONE _MMIO(0x2090)
#define NOPID _MMIO(0x2094)
#define HWSTAM _MMIO(0x2098)
-#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
-#define RING_BBSTATE(base) _MMIO((base) + 0x110)
-#define RING_BB_PPGTT (1 << 5)
-#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
-#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */
-#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */
-#define RING_BBADDR(base) _MMIO((base) + 0x140)
-#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */
-#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */
-#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */
-#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */
-#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */
-
-#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10)
-#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
-
-#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18)
-#define ALNUNIT_CLKGATE_DIS REG_BIT(13)
#define ERROR_GEN6 _MMIO(0x40a0)
#define GEN7_ERR_INT _MMIO(0x44040)
@@ -2583,22 +2437,6 @@
GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
#define GFX_MODE _MMIO(0x2520)
-#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
-#define GFX_RUN_LIST_ENABLE (1 << 15)
-#define GFX_INTERRUPT_STEERING (1 << 14)
-#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)
-#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
-#define GFX_REPLAY_MODE (1 << 11)
-#define GFX_PSMI_GRANULARITY (1 << 10)
-#define GFX_PPGTT_ENABLE (1 << 9)
-#define GEN8_GFX_PPGTT_48B (1 << 7)
-
-#define GFX_FORWARD_VBLANK_MASK (3 << 5)
-#define GFX_FORWARD_VBLANK_NEVER (0 << 5)
-#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5)
-#define GFX_FORWARD_VBLANK_COND (2 << 5)
-
-#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3)
#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
@@ -2639,7 +2477,6 @@
#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
#define INSTPM_TLB_INVALIDATE (1 << 9)
#define INSTPM_SYNC_FLUSH (1 << 5)
-#define ACTHD(base) _MMIO((base) + 0xc8)
#define MEM_MODE _MMIO(0x20cc)
#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
@@ -2778,12 +2615,6 @@
#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
#define GFX_FLSH_CNTL_EN (1 << 0)
-#define ECOSKPD(base) _MMIO((base) + 0x1d0)
-#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
-#define ECO_GATING_CX_ONLY REG_BIT(3)
-#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3)
-#define ECO_FLIP_DONE REG_BIT(0)
-#define GEN6_BLITTER_LOCK_SHIFT 16
#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
#define RC_OP_FLUSH_ENABLE (1 << 0)
@@ -3846,10 +3677,6 @@
/*
* Logical Context regs
*/
-#define CCID(base) _MMIO((base) + 0x180)
-#define CCID_EN BIT(0)
-#define CCID_EXTENDED_STATE_RESTORE BIT(2)
-#define CCID_EXTENDED_STATE_SAVE BIT(3)
/*
* Notes on SNB/IVB/VLV context size:
* - Power context is saved elsewhere (LLC or stolen)
@@ -8954,8 +8781,6 @@ enum {
#define RC6_CTX_IN_DRAM (1 << 0)
#define RC6_CTX_BASE _MMIO(0xD48)
#define RC6_CTX_BASE_MASK 0xFFFFFFF0
-#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
-#define IDLE_TIME_MASK 0xFFFFF
#define FORCEWAKE _MMIO(0xA18C)
#define FORCEWAKE_VLV _MMIO(0x1300b0)
#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 76cf5ac91e94..5d94f86940f7 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -36,6 +36,7 @@
#include "gt/intel_context.h"
#include "gt/intel_engine.h"
#include "gt/intel_engine_heartbeat.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_reset.h"
#include "gt/intel_ring.h"
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 710dee28a014..4ecd995c5cc7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,6 +43,7 @@
#include "display/intel_sprite.h"
#include "display/skl_universal_plane.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_llc.h"
#include "i915_drv.h"
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index fc25ebf1a593..41d082213e81 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -23,7 +23,7 @@
#include <linux/pm_runtime.h>
-#include "gt/intel_lrc_reg.h" /* for shadow reg list */
+#include "gt/intel_engine_regs.h"
#include "i915_drv.h"
#include "i915_iosf_mbi.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Intel-gfx] [PATCH v3 07/11] drm/i915/gt: Move engine registers to their own header
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 07/11] drm/i915/gt: Move engine registers to their own header Matt Roper
@ 2022-01-11 16:29 ` Lucas De Marchi
0 siblings, 0 replies; 29+ messages in thread
From: Lucas De Marchi @ 2022-01-11 16:29 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Mon, Jan 10, 2022 at 09:15:56PM -0800, Matt Roper wrote:
>Let's start breaking up and cleaning up the massive i915_reg.h file.
>We'll start by moving all registers that are defined in relation to an
>engine base to their own header.
maybe reword this a little bit since now this isn't the start of
this series anymore?
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index b7e03b6e886d..b504d67c2752 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -272,14 +272,6 @@
> #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
> #define GEN12_SFC_DONE_MAX 4
>
>-#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
>-#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
>-#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
>-#define PP_DIR_DCLV_2G 0xffffffff
>-
>-#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
>-#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
>-
> #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
> #define GEN8_RPCS_ENABLE (1 << 31)
> #define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
>@@ -2206,71 +2198,8 @@
> #define XEHP_VEBOX3_RING_BASE 0x1e8000
> #define XEHP_VEBOX4_RING_BASE 0x1f8000
> #define BLT_RING_BASE 0x22000
I know from the commit message this is not all, but since we are moving
the RING_TAIL() and friends that take the base as parameter, I don't
understand why we woul leave the bases behind in the old header.
Up to you if squashing the additional move here or following up with
more patches
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>-#define RING_TAIL(base) _MMIO((base) + 0x30)
>-#define RING_HEAD(base) _MMIO((base) + 0x34)
>-#define RING_START(base) _MMIO((base) + 0x38)
>-#define RING_CTL(base) _MMIO((base) + 0x3c)
>-#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
>-#define RING_SYNC_0(base) _MMIO((base) + 0x40)
>-#define RING_SYNC_1(base) _MMIO((base) + 0x44)
>-#define RING_SYNC_2(base) _MMIO((base) + 0x48)
>-#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
>-#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
>-#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
>-#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
>-#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
>-#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
>-#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
>-#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
>-#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
>-#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
>-#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
>-#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
>-#define GEN6_NOSYNC INVALID_MMIO_REG
>-#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
>-#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
>-#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10)
>-#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
>-#define GEN6_BSD_GO_INDICATOR REG_BIT(4)
>-#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
>-#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2)
>-#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0)
>-#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
>-#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
>-#define RING_ID(base) _MMIO((base) + 0x8c)
>-#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH v3 08/11] drm/i915: Move SNPS PHY registers to their own header
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (6 preceding siblings ...)
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 07/11] drm/i915/gt: Move engine registers to their own header Matt Roper
@ 2022-01-11 5:15 ` Matt Roper
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 09/11] drm/i915: Move combo " Matt Roper
` (7 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2022-01-11 5:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
These registers are only needed in a couple files and on specific
platforms; let's keep them separate from the general register pool.
v2:
- Don't forget to include i915_reg_defs.h (Jani)
- Ensure include guard matches header name (Jani)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 1 +
.../drm/i915/display/intel_snps_phy_regs.h | 75 +++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 67 -----------------
3 files changed, 76 insertions(+), 67 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 09f405e4d363..718bfdbae9c8 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -10,6 +10,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_snps_phy.h"
+#include "intel_snps_phy_regs.h"
/**
* DOC: Synopsis PHY support
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h b/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
new file mode 100644
index 000000000000..0543465aaf14
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_SNPS_PHY_REGS__
+#define __INTEL_SNPS_PHY_REGS__
+
+#include "i915_reg_defs.h"
+
+#define _SNPS_PHY_A_BASE 0x168000
+#define _SNPS_PHY_B_BASE 0x169000
+#define _SNPS_PHY(phy) _PHY(phy, \
+ _SNPS_PHY_A_BASE, \
+ _SNPS_PHY_B_BASE)
+#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
+ _SNPS_PHY_A_BASE + (reg))
+#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
+#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
+ (reg) + (ln) * 0x10))
+
+#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
+#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
+#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
+#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
+#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
+
+#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
+#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
+#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
+#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
+#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
+#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
+#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
+#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
+#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
+#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
+#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
+#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
+
+#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
+#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
+#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
+#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
+
+#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
+#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
+#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
+
+#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
+#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
+#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
+#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
+
+#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
+#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
+
+#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
+#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
+#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
+#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
+#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
+
+#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
+#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
+
+#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
+#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
+
+#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
+#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
+#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
+#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
+
+#endif /* __INTEL_SNPS_PHY_REGS__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b504d67c2752..71fefd04d71b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1883,73 +1883,6 @@
#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
-/*
- * DG2 SNPS PHY registers (TC1 = PHY_E)
- */
-#define _SNPS_PHY_A_BASE 0x168000
-#define _SNPS_PHY_B_BASE 0x169000
-#define _SNPS_PHY(phy) _PHY(phy, \
- _SNPS_PHY_A_BASE, \
- _SNPS_PHY_B_BASE)
-#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
- _SNPS_PHY_A_BASE + (reg))
-#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
-#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
- (reg) + (ln) * 0x10))
-
-#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
-#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
-#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
-#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
-#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
-
-#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
-#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
-#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
-#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
-#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
-#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
-#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
-#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
-#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
-#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
-#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
-#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
-
-#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
-#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
-#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
-#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
-
-#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
-#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
-#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
-
-#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
-#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
-#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
-#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
-
-#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
-#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
-
-#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
-#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
-#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
-#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
-#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
-
-#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
-#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
-
-#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
-#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
-
-#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
-#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
-#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
-#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
-
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 09/11] drm/i915: Move combo PHY registers to their own header
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (7 preceding siblings ...)
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 08/11] drm/i915: Move SNPS PHY " Matt Roper
@ 2022-01-11 5:15 ` Matt Roper
2022-01-11 13:44 ` Jani Nikula
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 10/11] drm/i915: Move TC " Matt Roper
` (6 subsequent siblings)
15 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2022-01-11 5:15 UTC (permalink / raw)
To: intel-gfx
These registers are only needed in a couple files and on specific
platforms; let's keep them separate from the general register pool.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
.../gpu/drm/i915/display/intel_combo_phy.c | 1 +
.../drm/i915/display/intel_combo_phy_regs.h | 162 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
.../drm/i915/display/intel_display_power.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 154 -----------------
7 files changed, 167 insertions(+), 154 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5781e9fac8b4..95f49535fa6e 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -32,6 +32,7 @@
#include "intel_atomic.h"
#include "intel_backlight.h"
#include "intel_combo_phy.h"
+#include "intel_combo_phy_regs.h"
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index f628e0542933..4dfe77351b8b 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -4,6 +4,7 @@
*/
#include "intel_combo_phy.h"
+#include "intel_combo_phy_regs.h"
#include "intel_de.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
new file mode 100644
index 000000000000..2ed65193ca19
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_COMBO_PHY_REGS__
+#define __INTEL_COMBO_PHY_REGS__
+
+#include "i915_reg_defs.h"
+
+#define _ICL_COMBOPHY_A 0x162000
+#define _ICL_COMBOPHY_B 0x6C000
+#define _EHL_COMBOPHY_C 0x160000
+#define _RKL_COMBOPHY_D 0x161000
+#define _ADL_COMBOPHY_E 0x16B000
+
+#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
+ _ICL_COMBOPHY_B, \
+ _EHL_COMBOPHY_C, \
+ _RKL_COMBOPHY_D, \
+ _ADL_COMBOPHY_E)
+
+/* ICL Port CL_DW registers */
+#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
+ 4 * (dw))
+
+#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
+#define CL_POWER_DOWN_ENABLE (1 << 4)
+#define SUS_CLOCK_CONFIG (3 << 0)
+
+#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
+#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
+#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
+#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
+#define PWR_UP_ALL_LANES (0x0 << 4)
+#define PWR_DOWN_LN_3_2_1 (0xe << 4)
+#define PWR_DOWN_LN_3_2 (0xc << 4)
+#define PWR_DOWN_LN_3 (0x8 << 4)
+#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
+#define PWR_DOWN_LN_1_0 (0x3 << 4)
+#define PWR_DOWN_LN_3_1 (0xa << 4)
+#define PWR_DOWN_LN_3_1_0 (0xb << 4)
+#define PWR_DOWN_LN_MASK (0xf << 4)
+#define PWR_DOWN_LN_SHIFT 4
+#define EDP4K2K_MODE_OVRD_EN (1 << 3)
+#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
+
+#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
+#define ICL_LANE_ENABLE_AUX (1 << 0)
+
+/* ICL Port COMP_DW registers */
+#define _ICL_PORT_COMP 0x100
+#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_COMP + 4 * (dw))
+
+#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
+#define COMP_INIT (1 << 31)
+
+#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
+
+#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
+#define PROCESS_INFO_DOT_0 (0 << 26)
+#define PROCESS_INFO_DOT_1 (1 << 26)
+#define PROCESS_INFO_DOT_4 (2 << 26)
+#define PROCESS_INFO_MASK (7 << 26)
+#define PROCESS_INFO_SHIFT 26
+#define VOLTAGE_INFO_0_85V (0 << 24)
+#define VOLTAGE_INFO_0_95V (1 << 24)
+#define VOLTAGE_INFO_1_05V (2 << 24)
+#define VOLTAGE_INFO_MASK (3 << 24)
+#define VOLTAGE_INFO_SHIFT 24
+
+#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
+#define IREFGEN (1 << 24)
+
+#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
+
+#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
+
+/* ICL Port PCS registers */
+#define _ICL_PORT_PCS_AUX 0x300
+#define _ICL_PORT_PCS_GRP 0x600
+#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
+#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_PCS_AUX + 4 * (dw))
+#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_PCS_GRP + 4 * (dw))
+#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_PCS_LN(ln) + 4 * (dw))
+#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
+#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
+#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
+#define DCC_MODE_SELECT_MASK (0x3 << 20)
+#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
+#define COMMON_KEEPER_EN (1 << 26)
+#define LATENCY_OPTIM_MASK (0x3 << 2)
+#define LATENCY_OPTIM_VAL(x) ((x) << 2)
+
+/* ICL Port TX registers */
+#define _ICL_PORT_TX_AUX 0x380
+#define _ICL_PORT_TX_GRP 0x680
+#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
+
+#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_TX_AUX + 4 * (dw))
+#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_TX_GRP + 4 * (dw))
+#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
+ _ICL_PORT_TX_LN(ln) + 4 * (dw))
+
+#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
+#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
+#define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
+#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
+#define SWING_SEL_UPPER_MASK (1 << 15)
+#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
+#define SWING_SEL_LOWER_MASK (0x7 << 11)
+#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
+#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
+#define RCOMP_SCALAR(x) ((x) << 0)
+#define RCOMP_SCALAR_MASK (0xFF << 0)
+
+#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
+#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
+#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
+#define LOADGEN_SELECT (1 << 31)
+#define POST_CURSOR_1(x) ((x) << 12)
+#define POST_CURSOR_1_MASK (0x3F << 12)
+#define POST_CURSOR_2(x) ((x) << 6)
+#define POST_CURSOR_2_MASK (0x3F << 6)
+#define CURSOR_COEFF(x) ((x) << 0)
+#define CURSOR_COEFF_MASK (0x3F << 0)
+
+#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
+#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
+#define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
+#define TX_TRAINING_EN (1 << 31)
+#define TAP2_DISABLE (1 << 30)
+#define TAP3_DISABLE (1 << 29)
+#define SCALING_MODE_SEL(x) ((x) << 18)
+#define SCALING_MODE_SEL_MASK (0x7 << 18)
+#define RTERM_SELECT(x) ((x) << 3)
+#define RTERM_SELECT_MASK (0x7 << 3)
+
+#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
+#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
+#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
+#define N_SCALAR(x) ((x) << 24)
+#define N_SCALAR_MASK (0x7F << 24)
+
+#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
+#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
+#define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
+#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
+#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
+#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
+
+#define _ICL_DPHY_CHKN_REG 0x194
+#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
+#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
+
+#endif /* __INTEL_COMBO_PHY_REGS__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9c9d574f0b8c..766a8dbe095d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -32,6 +32,7 @@
#include "intel_audio.h"
#include "intel_backlight.h"
#include "intel_combo_phy.h"
+#include "intel_combo_phy_regs.h"
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 05babdcf5f2e..fba35fb6d2df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -7,6 +7,7 @@
#include "i915_irq.h"
#include "intel_cdclk.h"
#include "intel_combo_phy.h"
+#include "intel_combo_phy_regs.h"
#include "intel_crt.h"
#include "intel_de.h"
#include "intel_display_power.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d6d8c9922feb..942a755a0c48 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -46,6 +46,7 @@
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_backlight.h"
+#include "intel_combo_phy_regs.h"
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 71fefd04d71b..7646982be30b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1554,160 +1554,6 @@
#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
-/*
- * ICL Port/COMBO-PHY Registers
- */
-#define _ICL_COMBOPHY_A 0x162000
-#define _ICL_COMBOPHY_B 0x6C000
-#define _EHL_COMBOPHY_C 0x160000
-#define _RKL_COMBOPHY_D 0x161000
-#define _ADL_COMBOPHY_E 0x16B000
-
-#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
- _ICL_COMBOPHY_B, \
- _EHL_COMBOPHY_C, \
- _RKL_COMBOPHY_D, \
- _ADL_COMBOPHY_E)
-
-/* ICL Port CL_DW registers */
-#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
- 4 * (dw))
-
-#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
-#define CL_POWER_DOWN_ENABLE (1 << 4)
-#define SUS_CLOCK_CONFIG (3 << 0)
-
-#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
-#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
-#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
-#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
-#define PWR_UP_ALL_LANES (0x0 << 4)
-#define PWR_DOWN_LN_3_2_1 (0xe << 4)
-#define PWR_DOWN_LN_3_2 (0xc << 4)
-#define PWR_DOWN_LN_3 (0x8 << 4)
-#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
-#define PWR_DOWN_LN_1_0 (0x3 << 4)
-#define PWR_DOWN_LN_3_1 (0xa << 4)
-#define PWR_DOWN_LN_3_1_0 (0xb << 4)
-#define PWR_DOWN_LN_MASK (0xf << 4)
-#define PWR_DOWN_LN_SHIFT 4
-#define EDP4K2K_MODE_OVRD_EN (1 << 3)
-#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
-
-#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
-#define ICL_LANE_ENABLE_AUX (1 << 0)
-
-/* ICL Port COMP_DW registers */
-#define _ICL_PORT_COMP 0x100
-#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_COMP + 4 * (dw))
-
-#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
-#define COMP_INIT (1 << 31)
-
-#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
-
-#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
-#define PROCESS_INFO_DOT_0 (0 << 26)
-#define PROCESS_INFO_DOT_1 (1 << 26)
-#define PROCESS_INFO_DOT_4 (2 << 26)
-#define PROCESS_INFO_MASK (7 << 26)
-#define PROCESS_INFO_SHIFT 26
-#define VOLTAGE_INFO_0_85V (0 << 24)
-#define VOLTAGE_INFO_0_95V (1 << 24)
-#define VOLTAGE_INFO_1_05V (2 << 24)
-#define VOLTAGE_INFO_MASK (3 << 24)
-#define VOLTAGE_INFO_SHIFT 24
-
-#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
-#define IREFGEN (1 << 24)
-
-#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
-
-#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
-
-/* ICL Port PCS registers */
-#define _ICL_PORT_PCS_AUX 0x300
-#define _ICL_PORT_PCS_GRP 0x600
-#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
-#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_PCS_AUX + 4 * (dw))
-#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_PCS_GRP + 4 * (dw))
-#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_PCS_LN(ln) + 4 * (dw))
-#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
-#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
-#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
-#define DCC_MODE_SELECT_MASK (0x3 << 20)
-#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
-#define COMMON_KEEPER_EN (1 << 26)
-#define LATENCY_OPTIM_MASK (0x3 << 2)
-#define LATENCY_OPTIM_VAL(x) ((x) << 2)
-
-/* ICL Port TX registers */
-#define _ICL_PORT_TX_AUX 0x380
-#define _ICL_PORT_TX_GRP 0x680
-#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
-
-#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_TX_AUX + 4 * (dw))
-#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_TX_GRP + 4 * (dw))
-#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
- _ICL_PORT_TX_LN(ln) + 4 * (dw))
-
-#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
-#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
-#define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
-#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
-#define SWING_SEL_UPPER_MASK (1 << 15)
-#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
-#define SWING_SEL_LOWER_MASK (0x7 << 11)
-#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
-#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
-#define RCOMP_SCALAR(x) ((x) << 0)
-#define RCOMP_SCALAR_MASK (0xFF << 0)
-
-#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
-#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
-#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
-#define LOADGEN_SELECT (1 << 31)
-#define POST_CURSOR_1(x) ((x) << 12)
-#define POST_CURSOR_1_MASK (0x3F << 12)
-#define POST_CURSOR_2(x) ((x) << 6)
-#define POST_CURSOR_2_MASK (0x3F << 6)
-#define CURSOR_COEFF(x) ((x) << 0)
-#define CURSOR_COEFF_MASK (0x3F << 0)
-
-#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
-#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
-#define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
-#define TX_TRAINING_EN (1 << 31)
-#define TAP2_DISABLE (1 << 30)
-#define TAP3_DISABLE (1 << 29)
-#define SCALING_MODE_SEL(x) ((x) << 18)
-#define SCALING_MODE_SEL_MASK (0x7 << 18)
-#define RTERM_SELECT(x) ((x) << 3)
-#define RTERM_SELECT_MASK (0x7 << 3)
-
-#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
-#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
-#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
-#define N_SCALAR(x) ((x) << 24)
-#define N_SCALAR_MASK (0x7F << 24)
-
-#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
-#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
-#define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
-#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
-#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
-#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
-
-#define _ICL_DPHY_CHKN_REG 0x194
-#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
-#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
-
#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
_MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Intel-gfx] [PATCH v3 09/11] drm/i915: Move combo PHY registers to their own header
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 09/11] drm/i915: Move combo " Matt Roper
@ 2022-01-11 13:44 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2022-01-11 13:44 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Mon, 10 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> These registers are only needed in a couple files and on specific
> platforms; let's keep them separate from the general register pool.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
> .../gpu/drm/i915/display/intel_combo_phy.c | 1 +
> .../drm/i915/display/intel_combo_phy_regs.h | 162 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> .../drm/i915/display/intel_display_power.c | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 154 -----------------
> 7 files changed, 167 insertions(+), 154 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 5781e9fac8b4..95f49535fa6e 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -32,6 +32,7 @@
> #include "intel_atomic.h"
> #include "intel_backlight.h"
> #include "intel_combo_phy.h"
> +#include "intel_combo_phy_regs.h"
> #include "intel_connector.h"
> #include "intel_crtc.h"
> #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index f628e0542933..4dfe77351b8b 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -4,6 +4,7 @@
> */
>
> #include "intel_combo_phy.h"
> +#include "intel_combo_phy_regs.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
>
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
> new file mode 100644
> index 000000000000..2ed65193ca19
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
> @@ -0,0 +1,162 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_COMBO_PHY_REGS__
> +#define __INTEL_COMBO_PHY_REGS__
> +
> +#include "i915_reg_defs.h"
> +
> +#define _ICL_COMBOPHY_A 0x162000
> +#define _ICL_COMBOPHY_B 0x6C000
> +#define _EHL_COMBOPHY_C 0x160000
> +#define _RKL_COMBOPHY_D 0x161000
> +#define _ADL_COMBOPHY_E 0x16B000
> +
> +#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
> + _ICL_COMBOPHY_B, \
> + _EHL_COMBOPHY_C, \
> + _RKL_COMBOPHY_D, \
> + _ADL_COMBOPHY_E)
> +
> +/* ICL Port CL_DW registers */
> +#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> + 4 * (dw))
> +
> +#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
> +#define CL_POWER_DOWN_ENABLE (1 << 4)
> +#define SUS_CLOCK_CONFIG (3 << 0)
> +
> +#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
> +#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
> +#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
> +#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
> +#define PWR_UP_ALL_LANES (0x0 << 4)
> +#define PWR_DOWN_LN_3_2_1 (0xe << 4)
> +#define PWR_DOWN_LN_3_2 (0xc << 4)
> +#define PWR_DOWN_LN_3 (0x8 << 4)
> +#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
> +#define PWR_DOWN_LN_1_0 (0x3 << 4)
> +#define PWR_DOWN_LN_3_1 (0xa << 4)
> +#define PWR_DOWN_LN_3_1_0 (0xb << 4)
> +#define PWR_DOWN_LN_MASK (0xf << 4)
> +#define PWR_DOWN_LN_SHIFT 4
> +#define EDP4K2K_MODE_OVRD_EN (1 << 3)
> +#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
> +
> +#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
> +#define ICL_LANE_ENABLE_AUX (1 << 0)
> +
> +/* ICL Port COMP_DW registers */
> +#define _ICL_PORT_COMP 0x100
> +#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> + _ICL_PORT_COMP + 4 * (dw))
> +
> +#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
> +#define COMP_INIT (1 << 31)
> +
> +#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
> +
> +#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
> +#define PROCESS_INFO_DOT_0 (0 << 26)
> +#define PROCESS_INFO_DOT_1 (1 << 26)
> +#define PROCESS_INFO_DOT_4 (2 << 26)
> +#define PROCESS_INFO_MASK (7 << 26)
> +#define PROCESS_INFO_SHIFT 26
> +#define VOLTAGE_INFO_0_85V (0 << 24)
> +#define VOLTAGE_INFO_0_95V (1 << 24)
> +#define VOLTAGE_INFO_1_05V (2 << 24)
> +#define VOLTAGE_INFO_MASK (3 << 24)
> +#define VOLTAGE_INFO_SHIFT 24
> +
> +#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
> +#define IREFGEN (1 << 24)
> +
> +#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
> +
> +#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
> +
> +/* ICL Port PCS registers */
> +#define _ICL_PORT_PCS_AUX 0x300
> +#define _ICL_PORT_PCS_GRP 0x600
> +#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
> +#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
> + _ICL_PORT_PCS_AUX + 4 * (dw))
> +#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
> + _ICL_PORT_PCS_GRP + 4 * (dw))
> +#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
> + _ICL_PORT_PCS_LN(ln) + 4 * (dw))
> +#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
> +#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
> +#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
> +#define DCC_MODE_SELECT_MASK (0x3 << 20)
> +#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
> +#define COMMON_KEEPER_EN (1 << 26)
> +#define LATENCY_OPTIM_MASK (0x3 << 2)
> +#define LATENCY_OPTIM_VAL(x) ((x) << 2)
> +
> +/* ICL Port TX registers */
> +#define _ICL_PORT_TX_AUX 0x380
> +#define _ICL_PORT_TX_GRP 0x680
> +#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
> +
> +#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
> + _ICL_PORT_TX_AUX + 4 * (dw))
> +#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
> + _ICL_PORT_TX_GRP + 4 * (dw))
> +#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
> + _ICL_PORT_TX_LN(ln) + 4 * (dw))
> +
> +#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
> +#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
> +#define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
> +#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
> +#define SWING_SEL_UPPER_MASK (1 << 15)
> +#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
> +#define SWING_SEL_LOWER_MASK (0x7 << 11)
> +#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
> +#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
> +#define RCOMP_SCALAR(x) ((x) << 0)
> +#define RCOMP_SCALAR_MASK (0xFF << 0)
> +
> +#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
> +#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
> +#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
> +#define LOADGEN_SELECT (1 << 31)
> +#define POST_CURSOR_1(x) ((x) << 12)
> +#define POST_CURSOR_1_MASK (0x3F << 12)
> +#define POST_CURSOR_2(x) ((x) << 6)
> +#define POST_CURSOR_2_MASK (0x3F << 6)
> +#define CURSOR_COEFF(x) ((x) << 0)
> +#define CURSOR_COEFF_MASK (0x3F << 0)
> +
> +#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
> +#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
> +#define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
> +#define TX_TRAINING_EN (1 << 31)
> +#define TAP2_DISABLE (1 << 30)
> +#define TAP3_DISABLE (1 << 29)
> +#define SCALING_MODE_SEL(x) ((x) << 18)
> +#define SCALING_MODE_SEL_MASK (0x7 << 18)
> +#define RTERM_SELECT(x) ((x) << 3)
> +#define RTERM_SELECT_MASK (0x7 << 3)
> +
> +#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
> +#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
> +#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
> +#define N_SCALAR(x) ((x) << 24)
> +#define N_SCALAR_MASK (0x7F << 24)
> +
> +#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
> +#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
> +#define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
> +#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
> +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
> +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
> +
> +#define _ICL_DPHY_CHKN_REG 0x194
> +#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
> +#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
> +
> +#endif /* __INTEL_COMBO_PHY_REGS__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9c9d574f0b8c..766a8dbe095d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -32,6 +32,7 @@
> #include "intel_audio.h"
> #include "intel_backlight.h"
> #include "intel_combo_phy.h"
> +#include "intel_combo_phy_regs.h"
> #include "intel_connector.h"
> #include "intel_crtc.h"
> #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 05babdcf5f2e..fba35fb6d2df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -7,6 +7,7 @@
> #include "i915_irq.h"
> #include "intel_cdclk.h"
> #include "intel_combo_phy.h"
> +#include "intel_combo_phy_regs.h"
> #include "intel_crt.h"
> #include "intel_de.h"
> #include "intel_display_power.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index d6d8c9922feb..942a755a0c48 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -46,6 +46,7 @@
> #include "intel_atomic.h"
> #include "intel_audio.h"
> #include "intel_backlight.h"
> +#include "intel_combo_phy_regs.h"
> #include "intel_connector.h"
> #include "intel_crtc.h"
> #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 71fefd04d71b..7646982be30b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1554,160 +1554,6 @@
> #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
> #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
>
> -/*
> - * ICL Port/COMBO-PHY Registers
> - */
> -#define _ICL_COMBOPHY_A 0x162000
> -#define _ICL_COMBOPHY_B 0x6C000
> -#define _EHL_COMBOPHY_C 0x160000
> -#define _RKL_COMBOPHY_D 0x161000
> -#define _ADL_COMBOPHY_E 0x16B000
> -
> -#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
> - _ICL_COMBOPHY_B, \
> - _EHL_COMBOPHY_C, \
> - _RKL_COMBOPHY_D, \
> - _ADL_COMBOPHY_E)
> -
> -/* ICL Port CL_DW registers */
> -#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> - 4 * (dw))
> -
> -#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
> -#define CL_POWER_DOWN_ENABLE (1 << 4)
> -#define SUS_CLOCK_CONFIG (3 << 0)
> -
> -#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
> -#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
> -#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
> -#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
> -#define PWR_UP_ALL_LANES (0x0 << 4)
> -#define PWR_DOWN_LN_3_2_1 (0xe << 4)
> -#define PWR_DOWN_LN_3_2 (0xc << 4)
> -#define PWR_DOWN_LN_3 (0x8 << 4)
> -#define PWR_DOWN_LN_2_1_0 (0x7 << 4)
> -#define PWR_DOWN_LN_1_0 (0x3 << 4)
> -#define PWR_DOWN_LN_3_1 (0xa << 4)
> -#define PWR_DOWN_LN_3_1_0 (0xb << 4)
> -#define PWR_DOWN_LN_MASK (0xf << 4)
> -#define PWR_DOWN_LN_SHIFT 4
> -#define EDP4K2K_MODE_OVRD_EN (1 << 3)
> -#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2)
> -
> -#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
> -#define ICL_LANE_ENABLE_AUX (1 << 0)
> -
> -/* ICL Port COMP_DW registers */
> -#define _ICL_PORT_COMP 0x100
> -#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> - _ICL_PORT_COMP + 4 * (dw))
> -
> -#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
> -#define COMP_INIT (1 << 31)
> -
> -#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
> -
> -#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
> -#define PROCESS_INFO_DOT_0 (0 << 26)
> -#define PROCESS_INFO_DOT_1 (1 << 26)
> -#define PROCESS_INFO_DOT_4 (2 << 26)
> -#define PROCESS_INFO_MASK (7 << 26)
> -#define PROCESS_INFO_SHIFT 26
> -#define VOLTAGE_INFO_0_85V (0 << 24)
> -#define VOLTAGE_INFO_0_95V (1 << 24)
> -#define VOLTAGE_INFO_1_05V (2 << 24)
> -#define VOLTAGE_INFO_MASK (3 << 24)
> -#define VOLTAGE_INFO_SHIFT 24
> -
> -#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
> -#define IREFGEN (1 << 24)
> -
> -#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
> -
> -#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
> -
> -/* ICL Port PCS registers */
> -#define _ICL_PORT_PCS_AUX 0x300
> -#define _ICL_PORT_PCS_GRP 0x600
> -#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
> -#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
> - _ICL_PORT_PCS_AUX + 4 * (dw))
> -#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
> - _ICL_PORT_PCS_GRP + 4 * (dw))
> -#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
> - _ICL_PORT_PCS_LN(ln) + 4 * (dw))
> -#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
> -#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
> -#define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
> -#define DCC_MODE_SELECT_MASK (0x3 << 20)
> -#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
> -#define COMMON_KEEPER_EN (1 << 26)
> -#define LATENCY_OPTIM_MASK (0x3 << 2)
> -#define LATENCY_OPTIM_VAL(x) ((x) << 2)
> -
> -/* ICL Port TX registers */
> -#define _ICL_PORT_TX_AUX 0x380
> -#define _ICL_PORT_TX_GRP 0x680
> -#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
> -
> -#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
> - _ICL_PORT_TX_AUX + 4 * (dw))
> -#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
> - _ICL_PORT_TX_GRP + 4 * (dw))
> -#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
> - _ICL_PORT_TX_LN(ln) + 4 * (dw))
> -
> -#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
> -#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
> -#define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
> -#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
> -#define SWING_SEL_UPPER_MASK (1 << 15)
> -#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
> -#define SWING_SEL_LOWER_MASK (0x7 << 11)
> -#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
> -#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
> -#define RCOMP_SCALAR(x) ((x) << 0)
> -#define RCOMP_SCALAR_MASK (0xFF << 0)
> -
> -#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
> -#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
> -#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
> -#define LOADGEN_SELECT (1 << 31)
> -#define POST_CURSOR_1(x) ((x) << 12)
> -#define POST_CURSOR_1_MASK (0x3F << 12)
> -#define POST_CURSOR_2(x) ((x) << 6)
> -#define POST_CURSOR_2_MASK (0x3F << 6)
> -#define CURSOR_COEFF(x) ((x) << 0)
> -#define CURSOR_COEFF_MASK (0x3F << 0)
> -
> -#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
> -#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
> -#define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
> -#define TX_TRAINING_EN (1 << 31)
> -#define TAP2_DISABLE (1 << 30)
> -#define TAP3_DISABLE (1 << 29)
> -#define SCALING_MODE_SEL(x) ((x) << 18)
> -#define SCALING_MODE_SEL_MASK (0x7 << 18)
> -#define RTERM_SELECT(x) ((x) << 3)
> -#define RTERM_SELECT_MASK (0x7 << 3)
> -
> -#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
> -#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
> -#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
> -#define N_SCALAR(x) ((x) << 24)
> -#define N_SCALAR_MASK (0x7F << 24)
> -
> -#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
> -#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
> -#define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
> -#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
> -#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
> -#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
> -
> -#define _ICL_DPHY_CHKN_REG 0x194
> -#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
> -#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
> -
> #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
> _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH v3 10/11] drm/i915: Move TC PHY registers to their own header
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (8 preceding siblings ...)
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 09/11] drm/i915: Move combo " Matt Roper
@ 2022-01-11 5:15 ` Matt Roper
2022-01-11 13:49 ` Jani Nikula
2022-01-11 5:16 ` [Intel-gfx] [PATCH v3 11/11] drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets Matt Roper
` (5 subsequent siblings)
15 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2022-01-11 5:15 UTC (permalink / raw)
To: intel-gfx
Registers representing the MG/DKL TC PHYs (including the TC DPLLs which
exist inside the PHY) are only needed in a couple files and on specific
platforms; let's keep them separate from the general register pool.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
drivers/gpu/drm/i915/display/intel_tc.c | 1 +
.../gpu/drm/i915/display/intel_tc_phy_regs.h | 344 ++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 333 -----------------
5 files changed, 347 insertions(+), 333 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 766a8dbe095d..6ee0f77b7927 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -57,6 +57,7 @@
#include "intel_snps_phy.h"
#include "intel_sprite.h"
#include "intel_tc.h"
+#include "intel_tc_phy_regs.h"
#include "intel_vdsc.h"
#include "intel_vrr.h"
#include "skl_scaler.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index fc8fda77483a..3f7357123a6d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -28,6 +28,7 @@
#include "intel_dpll_mgr.h"
#include "intel_pch_refclk.h"
#include "intel_tc.h"
+#include "intel_tc_phy_regs.h"
/**
* DOC: Display PLLs
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 40faa18947c9..4eefe7b0bb26 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -8,6 +8,7 @@
#include "intel_display_types.h"
#include "intel_dp_mst.h"
#include "intel_tc.h"
+#include "intel_tc_phy_regs.h"
static const char *tc_port_mode_name(enum tc_port_mode mode)
{
diff --git a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h b/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
new file mode 100644
index 000000000000..87b74c3c35a7
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
@@ -0,0 +1,344 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_TC_PHY_REGS__
+#define __INTEL_TC_PHY_REGS__
+
+#include "i915_reg_defs.h"
+
+#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
+ _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
+
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
+#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
+#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
+#define MG_TX1_LINK_PARAMS(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
+ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
+ MG_TX_LINK_PARAMS_TX1LN1_PORT1)
+
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
+#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
+#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
+#define MG_TX2_LINK_PARAMS(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
+ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
+ MG_TX_LINK_PARAMS_TX2LN1_PORT1)
+#define CRI_USE_FS32 (1 << 5)
+
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
+#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
+#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
+#define MG_TX1_PISO_READLOAD(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
+ MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
+ MG_TX_PISO_READLOAD_TX1LN1_PORT1)
+
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
+#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
+#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
+#define MG_TX2_PISO_READLOAD(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
+ MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
+ MG_TX_PISO_READLOAD_TX2LN1_PORT1)
+#define CRI_CALCINIT (1 << 1)
+
+#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
+#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
+#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
+#define MG_TX1_SWINGCTRL(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
+ MG_TX_SWINGCTRL_TX1LN0_PORT2, \
+ MG_TX_SWINGCTRL_TX1LN1_PORT1)
+
+#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
+#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
+#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
+#define MG_TX2_SWINGCTRL(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
+ MG_TX_SWINGCTRL_TX2LN0_PORT2, \
+ MG_TX_SWINGCTRL_TX2LN1_PORT1)
+#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
+#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
+
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
+#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
+#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
+#define MG_TX1_DRVCTRL(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
+ MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
+ MG_TX_DRVCTRL_TX1LN1_TXPORT1)
+
+#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
+#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
+#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
+#define MG_TX2_DRVCTRL(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
+ MG_TX_DRVCTRL_TX2LN0_PORT2, \
+ MG_TX_DRVCTRL_TX2LN1_PORT1)
+#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
+#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
+#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
+#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
+#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
+#define CRI_LOADGEN_SEL(x) ((x) << 12)
+#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
+
+#define MG_CLKHUB_LN0_PORT1 0x16839C
+#define MG_CLKHUB_LN1_PORT1 0x16879C
+#define MG_CLKHUB_LN0_PORT2 0x16939C
+#define MG_CLKHUB_LN1_PORT2 0x16979C
+#define MG_CLKHUB_LN0_PORT3 0x16A39C
+#define MG_CLKHUB_LN1_PORT3 0x16A79C
+#define MG_CLKHUB_LN0_PORT4 0x16B39C
+#define MG_CLKHUB_LN1_PORT4 0x16B79C
+#define MG_CLKHUB(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
+ MG_CLKHUB_LN0_PORT2, \
+ MG_CLKHUB_LN1_PORT1)
+#define CFG_LOW_RATE_LKREN_EN (1 << 11)
+
+#define MG_TX_DCC_TX1LN0_PORT1 0x168110
+#define MG_TX_DCC_TX1LN1_PORT1 0x168510
+#define MG_TX_DCC_TX1LN0_PORT2 0x169110
+#define MG_TX_DCC_TX1LN1_PORT2 0x169510
+#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
+#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
+#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
+#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
+#define MG_TX1_DCC(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
+ MG_TX_DCC_TX1LN0_PORT2, \
+ MG_TX_DCC_TX1LN1_PORT1)
+#define MG_TX_DCC_TX2LN0_PORT1 0x168090
+#define MG_TX_DCC_TX2LN1_PORT1 0x168490
+#define MG_TX_DCC_TX2LN0_PORT2 0x169090
+#define MG_TX_DCC_TX2LN1_PORT2 0x169490
+#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
+#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
+#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
+#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
+#define MG_TX2_DCC(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
+ MG_TX_DCC_TX2LN0_PORT2, \
+ MG_TX_DCC_TX2LN1_PORT1)
+#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
+#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
+#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
+
+#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
+#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
+#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
+#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
+#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
+#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
+#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
+#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
+#define MG_DP_MODE(ln, tc_port) \
+ MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
+ MG_DP_MODE_LN0_ACU_PORT2, \
+ MG_DP_MODE_LN1_ACU_PORT1)
+#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
+#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
+
+#define FIA1_BASE 0x163000
+#define FIA2_BASE 0x16E000
+#define FIA3_BASE 0x16F000
+#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
+#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
+
+/* ICL PHY DFLEX registers */
+#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
+#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
+#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
+
+#define _MG_REFCLKIN_CTL_PORT1 0x16892C
+#define _MG_REFCLKIN_CTL_PORT2 0x16992C
+#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
+#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
+#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
+#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
+#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
+ _MG_REFCLKIN_CTL_PORT1, \
+ _MG_REFCLKIN_CTL_PORT2)
+
+#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
+#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
+#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
+#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
+#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
+#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
+#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
+#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
+#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
+ _MG_CLKTOP2_CORECLKCTL1_PORT1, \
+ _MG_CLKTOP2_CORECLKCTL1_PORT2)
+
+#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
+#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
+#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
+#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
+#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
+#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
+#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
+#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
+#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
+#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
+#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
+#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
+ _MG_CLKTOP2_HSCLKCTL_PORT1, \
+ _MG_CLKTOP2_HSCLKCTL_PORT2)
+
+#define _MG_PLL_DIV0_PORT1 0x168A00
+#define _MG_PLL_DIV0_PORT2 0x169A00
+#define _MG_PLL_DIV0_PORT3 0x16AA00
+#define _MG_PLL_DIV0_PORT4 0x16BA00
+#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
+#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
+#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
+#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
+#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
+#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
+#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
+ _MG_PLL_DIV0_PORT2)
+
+#define _MG_PLL_DIV1_PORT1 0x168A04
+#define _MG_PLL_DIV1_PORT2 0x169A04
+#define _MG_PLL_DIV1_PORT3 0x16AA04
+#define _MG_PLL_DIV1_PORT4 0x16BA04
+#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
+#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
+#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
+#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
+#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
+#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
+#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
+#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
+#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
+ _MG_PLL_DIV1_PORT2)
+
+#define _MG_PLL_LF_PORT1 0x168A08
+#define _MG_PLL_LF_PORT2 0x169A08
+#define _MG_PLL_LF_PORT3 0x16AA08
+#define _MG_PLL_LF_PORT4 0x16BA08
+#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
+#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
+#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
+#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
+#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
+#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
+#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
+ _MG_PLL_LF_PORT2)
+
+#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
+#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
+#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
+#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
+#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
+#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
+#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
+#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
+#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
+#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
+#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
+ _MG_PLL_FRAC_LOCK_PORT1, \
+ _MG_PLL_FRAC_LOCK_PORT2)
+
+#define _MG_PLL_SSC_PORT1 0x168A10
+#define _MG_PLL_SSC_PORT2 0x169A10
+#define _MG_PLL_SSC_PORT3 0x16AA10
+#define _MG_PLL_SSC_PORT4 0x16BA10
+#define MG_PLL_SSC_EN (1 << 28)
+#define MG_PLL_SSC_TYPE(x) ((x) << 26)
+#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
+#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
+#define MG_PLL_SSC_FLLEN (1 << 9)
+#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
+#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
+ _MG_PLL_SSC_PORT2)
+
+#define _MG_PLL_BIAS_PORT1 0x168A14
+#define _MG_PLL_BIAS_PORT2 0x169A14
+#define _MG_PLL_BIAS_PORT3 0x16AA14
+#define _MG_PLL_BIAS_PORT4 0x16BA14
+#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
+#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
+#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
+#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
+#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
+#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
+#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
+#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
+#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
+#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
+#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
+#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
+#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
+#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
+ _MG_PLL_BIAS_PORT2)
+
+#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
+#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
+#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
+#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
+#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
+#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
+#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
+#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
+#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
+#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
+ _MG_PLL_TDC_COLDST_BIAS_PORT1, \
+ _MG_PLL_TDC_COLDST_BIAS_PORT2)
+
+#endif /* __INTEL_TC_PHY_REGS__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7646982be30b..2f28888cc651 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1554,181 +1554,6 @@
#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
-#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
- _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
-
-#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
-#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
-#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
-#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
-#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
-#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
-#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
-#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
-#define MG_TX1_LINK_PARAMS(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
- MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
- MG_TX_LINK_PARAMS_TX1LN1_PORT1)
-
-#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
-#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
-#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
-#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
-#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
-#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
-#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
-#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
-#define MG_TX2_LINK_PARAMS(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
- MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
- MG_TX_LINK_PARAMS_TX2LN1_PORT1)
-#define CRI_USE_FS32 (1 << 5)
-
-#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
-#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
-#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
-#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
-#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
-#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
-#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
-#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
-#define MG_TX1_PISO_READLOAD(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
- MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
- MG_TX_PISO_READLOAD_TX1LN1_PORT1)
-
-#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
-#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
-#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
-#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
-#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
-#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
-#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
-#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
-#define MG_TX2_PISO_READLOAD(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
- MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
- MG_TX_PISO_READLOAD_TX2LN1_PORT1)
-#define CRI_CALCINIT (1 << 1)
-
-#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
-#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
-#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
-#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
-#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
-#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
-#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
-#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
-#define MG_TX1_SWINGCTRL(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
- MG_TX_SWINGCTRL_TX1LN0_PORT2, \
- MG_TX_SWINGCTRL_TX1LN1_PORT1)
-
-#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
-#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
-#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
-#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
-#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
-#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
-#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
-#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
-#define MG_TX2_SWINGCTRL(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
- MG_TX_SWINGCTRL_TX2LN0_PORT2, \
- MG_TX_SWINGCTRL_TX2LN1_PORT1)
-#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
-#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
-
-#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
-#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
-#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
-#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
-#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
-#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
-#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
-#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
-#define MG_TX1_DRVCTRL(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
- MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
- MG_TX_DRVCTRL_TX1LN1_TXPORT1)
-
-#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
-#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
-#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
-#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
-#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
-#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
-#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
-#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
-#define MG_TX2_DRVCTRL(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
- MG_TX_DRVCTRL_TX2LN0_PORT2, \
- MG_TX_DRVCTRL_TX2LN1_PORT1)
-#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
-#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
-#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
-#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
-#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
-#define CRI_LOADGEN_SEL(x) ((x) << 12)
-#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
-
-#define MG_CLKHUB_LN0_PORT1 0x16839C
-#define MG_CLKHUB_LN1_PORT1 0x16879C
-#define MG_CLKHUB_LN0_PORT2 0x16939C
-#define MG_CLKHUB_LN1_PORT2 0x16979C
-#define MG_CLKHUB_LN0_PORT3 0x16A39C
-#define MG_CLKHUB_LN1_PORT3 0x16A79C
-#define MG_CLKHUB_LN0_PORT4 0x16B39C
-#define MG_CLKHUB_LN1_PORT4 0x16B79C
-#define MG_CLKHUB(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
- MG_CLKHUB_LN0_PORT2, \
- MG_CLKHUB_LN1_PORT1)
-#define CFG_LOW_RATE_LKREN_EN (1 << 11)
-
-#define MG_TX_DCC_TX1LN0_PORT1 0x168110
-#define MG_TX_DCC_TX1LN1_PORT1 0x168510
-#define MG_TX_DCC_TX1LN0_PORT2 0x169110
-#define MG_TX_DCC_TX1LN1_PORT2 0x169510
-#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
-#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
-#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
-#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
-#define MG_TX1_DCC(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
- MG_TX_DCC_TX1LN0_PORT2, \
- MG_TX_DCC_TX1LN1_PORT1)
-#define MG_TX_DCC_TX2LN0_PORT1 0x168090
-#define MG_TX_DCC_TX2LN1_PORT1 0x168490
-#define MG_TX_DCC_TX2LN0_PORT2 0x169090
-#define MG_TX_DCC_TX2LN1_PORT2 0x169490
-#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
-#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
-#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
-#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
-#define MG_TX2_DCC(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
- MG_TX_DCC_TX2LN0_PORT2, \
- MG_TX_DCC_TX2LN1_PORT1)
-#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
-#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
-#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
-
-#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
-#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
-#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
-#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
-#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
-#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
-#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
-#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
-#define MG_DP_MODE(ln, tc_port) \
- MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
- MG_DP_MODE_LN0_ACU_PORT2, \
- MG_DP_MODE_LN1_ACU_PORT1)
-#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
-#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
-
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
*/
@@ -1737,21 +1562,6 @@
#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
-#define FIA1_BASE 0x163000
-#define FIA2_BASE 0x16E000
-#define FIA3_BASE 0x16F000
-#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
-#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
-
-/* ICL PHY DFLEX registers */
-#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
-#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
-#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
-#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
-#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
-#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
-#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
-
/* BXT PHY Ref registers */
#define _PORT_REF_DW3_A 0x16218C
#define _PORT_REF_DW3_BC 0x6C18C
@@ -10076,149 +9886,6 @@ enum skl_power_gate {
PORTTC1_PLL_ENABLE, \
PORTTC2_PLL_ENABLE)
-#define _MG_REFCLKIN_CTL_PORT1 0x16892C
-#define _MG_REFCLKIN_CTL_PORT2 0x16992C
-#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
-#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
-#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
-#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
-#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
- _MG_REFCLKIN_CTL_PORT1, \
- _MG_REFCLKIN_CTL_PORT2)
-
-#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
-#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
-#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
-#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
-#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
-#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
-#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
-#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
-#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
- _MG_CLKTOP2_CORECLKCTL1_PORT1, \
- _MG_CLKTOP2_CORECLKCTL1_PORT2)
-
-#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
-#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
-#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
-#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
-#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
-#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
-#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
-#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
-#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
-#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
-#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
-#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
-#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
-#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
-#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
-#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
-#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
- _MG_CLKTOP2_HSCLKCTL_PORT1, \
- _MG_CLKTOP2_HSCLKCTL_PORT2)
-
-#define _MG_PLL_DIV0_PORT1 0x168A00
-#define _MG_PLL_DIV0_PORT2 0x169A00
-#define _MG_PLL_DIV0_PORT3 0x16AA00
-#define _MG_PLL_DIV0_PORT4 0x16BA00
-#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
-#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
-#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
-#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
-#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
-#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
-#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
- _MG_PLL_DIV0_PORT2)
-
-#define _MG_PLL_DIV1_PORT1 0x168A04
-#define _MG_PLL_DIV1_PORT2 0x169A04
-#define _MG_PLL_DIV1_PORT3 0x16AA04
-#define _MG_PLL_DIV1_PORT4 0x16BA04
-#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
-#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
-#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
-#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
-#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
-#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
-#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
-#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
-#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
- _MG_PLL_DIV1_PORT2)
-
-#define _MG_PLL_LF_PORT1 0x168A08
-#define _MG_PLL_LF_PORT2 0x169A08
-#define _MG_PLL_LF_PORT3 0x16AA08
-#define _MG_PLL_LF_PORT4 0x16BA08
-#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
-#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
-#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
-#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
-#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
-#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
-#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
- _MG_PLL_LF_PORT2)
-
-#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
-#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
-#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
-#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
-#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
-#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
-#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
-#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
-#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
-#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
-#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
- _MG_PLL_FRAC_LOCK_PORT1, \
- _MG_PLL_FRAC_LOCK_PORT2)
-
-#define _MG_PLL_SSC_PORT1 0x168A10
-#define _MG_PLL_SSC_PORT2 0x169A10
-#define _MG_PLL_SSC_PORT3 0x16AA10
-#define _MG_PLL_SSC_PORT4 0x16BA10
-#define MG_PLL_SSC_EN (1 << 28)
-#define MG_PLL_SSC_TYPE(x) ((x) << 26)
-#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
-#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
-#define MG_PLL_SSC_FLLEN (1 << 9)
-#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
-#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
- _MG_PLL_SSC_PORT2)
-
-#define _MG_PLL_BIAS_PORT1 0x168A14
-#define _MG_PLL_BIAS_PORT2 0x169A14
-#define _MG_PLL_BIAS_PORT3 0x16AA14
-#define _MG_PLL_BIAS_PORT4 0x16BA14
-#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
-#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
-#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
-#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
-#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
-#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
-#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
-#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
-#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
-#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
-#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
-#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
-#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
-#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
- _MG_PLL_BIAS_PORT2)
-
-#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
-#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
-#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
-#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
-#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
-#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
-#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
-#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
-#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
-#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
- _MG_PLL_TDC_COLDST_BIAS_PORT1, \
- _MG_PLL_TDC_COLDST_BIAS_PORT2)
-
#define _ICL_DPLL0_CFGCR0 0x164000
#define _ICL_DPLL1_CFGCR0 0x164080
#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Intel-gfx] [PATCH v3 10/11] drm/i915: Move TC PHY registers to their own header
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 10/11] drm/i915: Move TC " Matt Roper
@ 2022-01-11 13:49 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2022-01-11 13:49 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Mon, 10 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> Registers representing the MG/DKL TC PHYs (including the TC DPLLs which
> exist inside the PHY) are only needed in a couple files and on specific
> platforms; let's keep them separate from the general register pool.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
> drivers/gpu/drm/i915/display/intel_tc.c | 1 +
> .../gpu/drm/i915/display/intel_tc_phy_regs.h | 344 ++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 333 -----------------
> 5 files changed, 347 insertions(+), 333 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 766a8dbe095d..6ee0f77b7927 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -57,6 +57,7 @@
> #include "intel_snps_phy.h"
> #include "intel_sprite.h"
> #include "intel_tc.h"
> +#include "intel_tc_phy_regs.h"
> #include "intel_vdsc.h"
> #include "intel_vrr.h"
> #include "skl_scaler.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index fc8fda77483a..3f7357123a6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -28,6 +28,7 @@
> #include "intel_dpll_mgr.h"
> #include "intel_pch_refclk.h"
> #include "intel_tc.h"
> +#include "intel_tc_phy_regs.h"
>
> /**
> * DOC: Display PLLs
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 40faa18947c9..4eefe7b0bb26 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -8,6 +8,7 @@
> #include "intel_display_types.h"
> #include "intel_dp_mst.h"
> #include "intel_tc.h"
> +#include "intel_tc_phy_regs.h"
>
> static const char *tc_port_mode_name(enum tc_port_mode mode)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h b/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
> new file mode 100644
> index 000000000000..87b74c3c35a7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
> @@ -0,0 +1,344 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_TC_PHY_REGS__
> +#define __INTEL_TC_PHY_REGS__
> +
> +#include "i915_reg_defs.h"
> +
> +#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
> + _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
> +
> +#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
> +#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
> +#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
> +#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
> +#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
> +#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
> +#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
> +#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
> +#define MG_TX1_LINK_PARAMS(ln, tc_port) \
> + MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
> + MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
> + MG_TX_LINK_PARAMS_TX1LN1_PORT1)
> +
> +#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
> +#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
> +#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
> +#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
> +#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
> +#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
> +#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
> +#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
> +#define MG_TX2_LINK_PARAMS(ln, tc_port) \
> + MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
> + MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
> + MG_TX_LINK_PARAMS_TX2LN1_PORT1)
> +#define CRI_USE_FS32 (1 << 5)
> +
> +#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
> +#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
> +#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
> +#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
> +#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
> +#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
> +#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
> +#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
> +#define MG_TX1_PISO_READLOAD(ln, tc_port) \
> + MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
> + MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
> + MG_TX_PISO_READLOAD_TX1LN1_PORT1)
> +
> +#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
> +#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
> +#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
> +#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
> +#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
> +#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
> +#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
> +#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
> +#define MG_TX2_PISO_READLOAD(ln, tc_port) \
> + MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
> + MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
> + MG_TX_PISO_READLOAD_TX2LN1_PORT1)
> +#define CRI_CALCINIT (1 << 1)
> +
> +#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
> +#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
> +#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
> +#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
> +#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
> +#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
> +#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
> +#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
> +#define MG_TX1_SWINGCTRL(ln, tc_port) \
> + MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
> + MG_TX_SWINGCTRL_TX1LN0_PORT2, \
> + MG_TX_SWINGCTRL_TX1LN1_PORT1)
> +
> +#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
> +#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
> +#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
> +#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
> +#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
> +#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
> +#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
> +#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
> +#define MG_TX2_SWINGCTRL(ln, tc_port) \
> + MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
> + MG_TX_SWINGCTRL_TX2LN0_PORT2, \
> + MG_TX_SWINGCTRL_TX2LN1_PORT1)
> +#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
> +#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
> +
> +#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
> +#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
> +#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
> +#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
> +#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
> +#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
> +#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
> +#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
> +#define MG_TX1_DRVCTRL(ln, tc_port) \
> + MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
> + MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
> + MG_TX_DRVCTRL_TX1LN1_TXPORT1)
> +
> +#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
> +#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
> +#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
> +#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
> +#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
> +#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
> +#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
> +#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
> +#define MG_TX2_DRVCTRL(ln, tc_port) \
> + MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
> + MG_TX_DRVCTRL_TX2LN0_PORT2, \
> + MG_TX_DRVCTRL_TX2LN1_PORT1)
> +#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
> +#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
> +#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
> +#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
> +#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
> +#define CRI_LOADGEN_SEL(x) ((x) << 12)
> +#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
> +
> +#define MG_CLKHUB_LN0_PORT1 0x16839C
> +#define MG_CLKHUB_LN1_PORT1 0x16879C
> +#define MG_CLKHUB_LN0_PORT2 0x16939C
> +#define MG_CLKHUB_LN1_PORT2 0x16979C
> +#define MG_CLKHUB_LN0_PORT3 0x16A39C
> +#define MG_CLKHUB_LN1_PORT3 0x16A79C
> +#define MG_CLKHUB_LN0_PORT4 0x16B39C
> +#define MG_CLKHUB_LN1_PORT4 0x16B79C
> +#define MG_CLKHUB(ln, tc_port) \
> + MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
> + MG_CLKHUB_LN0_PORT2, \
> + MG_CLKHUB_LN1_PORT1)
> +#define CFG_LOW_RATE_LKREN_EN (1 << 11)
> +
> +#define MG_TX_DCC_TX1LN0_PORT1 0x168110
> +#define MG_TX_DCC_TX1LN1_PORT1 0x168510
> +#define MG_TX_DCC_TX1LN0_PORT2 0x169110
> +#define MG_TX_DCC_TX1LN1_PORT2 0x169510
> +#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
> +#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
> +#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
> +#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
> +#define MG_TX1_DCC(ln, tc_port) \
> + MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
> + MG_TX_DCC_TX1LN0_PORT2, \
> + MG_TX_DCC_TX1LN1_PORT1)
> +#define MG_TX_DCC_TX2LN0_PORT1 0x168090
> +#define MG_TX_DCC_TX2LN1_PORT1 0x168490
> +#define MG_TX_DCC_TX2LN0_PORT2 0x169090
> +#define MG_TX_DCC_TX2LN1_PORT2 0x169490
> +#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
> +#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
> +#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
> +#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
> +#define MG_TX2_DCC(ln, tc_port) \
> + MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
> + MG_TX_DCC_TX2LN0_PORT2, \
> + MG_TX_DCC_TX2LN1_PORT1)
> +#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
> +#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
> +#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
> +
> +#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
> +#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
> +#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
> +#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
> +#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
> +#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
> +#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
> +#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
> +#define MG_DP_MODE(ln, tc_port) \
> + MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
> + MG_DP_MODE_LN0_ACU_PORT2, \
> + MG_DP_MODE_LN1_ACU_PORT1)
> +#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
> +#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
> +
> +#define FIA1_BASE 0x163000
> +#define FIA2_BASE 0x16E000
> +#define FIA3_BASE 0x16F000
> +#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
> +#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
> +
> +/* ICL PHY DFLEX registers */
> +#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
> +#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
> +#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
> +#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
> +#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
> +#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
> +#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
> +
> +#define _MG_REFCLKIN_CTL_PORT1 0x16892C
> +#define _MG_REFCLKIN_CTL_PORT2 0x16992C
> +#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
> +#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
> +#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
> +#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
> +#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
> + _MG_REFCLKIN_CTL_PORT1, \
> + _MG_REFCLKIN_CTL_PORT2)
> +
> +#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
> +#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
> +#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
> +#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
> +#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
> +#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
> +#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
> +#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
> +#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
> + _MG_CLKTOP2_CORECLKCTL1_PORT1, \
> + _MG_CLKTOP2_CORECLKCTL1_PORT2)
> +
> +#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
> +#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
> +#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
> +#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
> +#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
> +#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
> +#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
> +#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
> +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
> +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
> +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
> +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
> +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
> +#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
> +#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
> +#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
> +#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
> + _MG_CLKTOP2_HSCLKCTL_PORT1, \
> + _MG_CLKTOP2_HSCLKCTL_PORT2)
> +
> +#define _MG_PLL_DIV0_PORT1 0x168A00
> +#define _MG_PLL_DIV0_PORT2 0x169A00
> +#define _MG_PLL_DIV0_PORT3 0x16AA00
> +#define _MG_PLL_DIV0_PORT4 0x16BA00
> +#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
> +#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
> +#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
> +#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
> +#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
> +#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
> +#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
> + _MG_PLL_DIV0_PORT2)
> +
> +#define _MG_PLL_DIV1_PORT1 0x168A04
> +#define _MG_PLL_DIV1_PORT2 0x169A04
> +#define _MG_PLL_DIV1_PORT3 0x16AA04
> +#define _MG_PLL_DIV1_PORT4 0x16BA04
> +#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
> +#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
> +#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
> +#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
> +#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
> +#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
> +#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
> +#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
> +#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
> + _MG_PLL_DIV1_PORT2)
> +
> +#define _MG_PLL_LF_PORT1 0x168A08
> +#define _MG_PLL_LF_PORT2 0x169A08
> +#define _MG_PLL_LF_PORT3 0x16AA08
> +#define _MG_PLL_LF_PORT4 0x16BA08
> +#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
> +#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
> +#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
> +#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
> +#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
> +#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
> +#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
> + _MG_PLL_LF_PORT2)
> +
> +#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
> +#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
> +#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
> +#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
> +#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
> +#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
> +#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
> +#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
> +#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
> +#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
> +#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
> + _MG_PLL_FRAC_LOCK_PORT1, \
> + _MG_PLL_FRAC_LOCK_PORT2)
> +
> +#define _MG_PLL_SSC_PORT1 0x168A10
> +#define _MG_PLL_SSC_PORT2 0x169A10
> +#define _MG_PLL_SSC_PORT3 0x16AA10
> +#define _MG_PLL_SSC_PORT4 0x16BA10
> +#define MG_PLL_SSC_EN (1 << 28)
> +#define MG_PLL_SSC_TYPE(x) ((x) << 26)
> +#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
> +#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
> +#define MG_PLL_SSC_FLLEN (1 << 9)
> +#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
> +#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
> + _MG_PLL_SSC_PORT2)
> +
> +#define _MG_PLL_BIAS_PORT1 0x168A14
> +#define _MG_PLL_BIAS_PORT2 0x169A14
> +#define _MG_PLL_BIAS_PORT3 0x16AA14
> +#define _MG_PLL_BIAS_PORT4 0x16BA14
> +#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
> +#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
> +#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
> +#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
> +#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
> +#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
> +#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
> +#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
> +#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
> +#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
> +#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
> +#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
> +#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
> +#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
> + _MG_PLL_BIAS_PORT2)
> +
> +#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
> +#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
> +#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
> +#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
> +#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
> +#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
> +#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
> +#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
> +#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
> +#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
> + _MG_PLL_TDC_COLDST_BIAS_PORT1, \
> + _MG_PLL_TDC_COLDST_BIAS_PORT2)
> +
> +#endif /* __INTEL_TC_PHY_REGS__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7646982be30b..2f28888cc651 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1554,181 +1554,6 @@
> #define OCL2_LDOFUSE_PWR_DIS (1 << 6)
> #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
>
> -#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
> - _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
> -
> -#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
> -#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
> -#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
> -#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
> -#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
> -#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
> -#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
> -#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
> -#define MG_TX1_LINK_PARAMS(ln, tc_port) \
> - MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
> - MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
> - MG_TX_LINK_PARAMS_TX1LN1_PORT1)
> -
> -#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
> -#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
> -#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
> -#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
> -#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
> -#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
> -#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
> -#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
> -#define MG_TX2_LINK_PARAMS(ln, tc_port) \
> - MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
> - MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
> - MG_TX_LINK_PARAMS_TX2LN1_PORT1)
> -#define CRI_USE_FS32 (1 << 5)
> -
> -#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
> -#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
> -#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
> -#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
> -#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
> -#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
> -#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
> -#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
> -#define MG_TX1_PISO_READLOAD(ln, tc_port) \
> - MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
> - MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
> - MG_TX_PISO_READLOAD_TX1LN1_PORT1)
> -
> -#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
> -#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
> -#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
> -#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
> -#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
> -#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
> -#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
> -#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
> -#define MG_TX2_PISO_READLOAD(ln, tc_port) \
> - MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
> - MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
> - MG_TX_PISO_READLOAD_TX2LN1_PORT1)
> -#define CRI_CALCINIT (1 << 1)
> -
> -#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
> -#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
> -#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
> -#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
> -#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
> -#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
> -#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
> -#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
> -#define MG_TX1_SWINGCTRL(ln, tc_port) \
> - MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
> - MG_TX_SWINGCTRL_TX1LN0_PORT2, \
> - MG_TX_SWINGCTRL_TX1LN1_PORT1)
> -
> -#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
> -#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
> -#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
> -#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
> -#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
> -#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
> -#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
> -#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
> -#define MG_TX2_SWINGCTRL(ln, tc_port) \
> - MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
> - MG_TX_SWINGCTRL_TX2LN0_PORT2, \
> - MG_TX_SWINGCTRL_TX2LN1_PORT1)
> -#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
> -#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
> -
> -#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
> -#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
> -#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
> -#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
> -#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
> -#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
> -#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
> -#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
> -#define MG_TX1_DRVCTRL(ln, tc_port) \
> - MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
> - MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
> - MG_TX_DRVCTRL_TX1LN1_TXPORT1)
> -
> -#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
> -#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
> -#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
> -#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
> -#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
> -#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
> -#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
> -#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
> -#define MG_TX2_DRVCTRL(ln, tc_port) \
> - MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
> - MG_TX_DRVCTRL_TX2LN0_PORT2, \
> - MG_TX_DRVCTRL_TX2LN1_PORT1)
> -#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
> -#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
> -#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
> -#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
> -#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
> -#define CRI_LOADGEN_SEL(x) ((x) << 12)
> -#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
> -
> -#define MG_CLKHUB_LN0_PORT1 0x16839C
> -#define MG_CLKHUB_LN1_PORT1 0x16879C
> -#define MG_CLKHUB_LN0_PORT2 0x16939C
> -#define MG_CLKHUB_LN1_PORT2 0x16979C
> -#define MG_CLKHUB_LN0_PORT3 0x16A39C
> -#define MG_CLKHUB_LN1_PORT3 0x16A79C
> -#define MG_CLKHUB_LN0_PORT4 0x16B39C
> -#define MG_CLKHUB_LN1_PORT4 0x16B79C
> -#define MG_CLKHUB(ln, tc_port) \
> - MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
> - MG_CLKHUB_LN0_PORT2, \
> - MG_CLKHUB_LN1_PORT1)
> -#define CFG_LOW_RATE_LKREN_EN (1 << 11)
> -
> -#define MG_TX_DCC_TX1LN0_PORT1 0x168110
> -#define MG_TX_DCC_TX1LN1_PORT1 0x168510
> -#define MG_TX_DCC_TX1LN0_PORT2 0x169110
> -#define MG_TX_DCC_TX1LN1_PORT2 0x169510
> -#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
> -#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
> -#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
> -#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
> -#define MG_TX1_DCC(ln, tc_port) \
> - MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
> - MG_TX_DCC_TX1LN0_PORT2, \
> - MG_TX_DCC_TX1LN1_PORT1)
> -#define MG_TX_DCC_TX2LN0_PORT1 0x168090
> -#define MG_TX_DCC_TX2LN1_PORT1 0x168490
> -#define MG_TX_DCC_TX2LN0_PORT2 0x169090
> -#define MG_TX_DCC_TX2LN1_PORT2 0x169490
> -#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
> -#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
> -#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
> -#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
> -#define MG_TX2_DCC(ln, tc_port) \
> - MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
> - MG_TX_DCC_TX2LN0_PORT2, \
> - MG_TX_DCC_TX2LN1_PORT1)
> -#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
> -#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
> -#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
> -
> -#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
> -#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
> -#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
> -#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
> -#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
> -#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
> -#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
> -#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
> -#define MG_DP_MODE(ln, tc_port) \
> - MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
> - MG_DP_MODE_LN0_ACU_PORT2, \
> - MG_DP_MODE_LN1_ACU_PORT1)
> -#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
> -#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
> -
> /* The spec defines this only for BXT PHY0, but lets assume that this
> * would exist for PHY1 too if it had a second channel.
> */
> @@ -1737,21 +1562,6 @@
> #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>
> -#define FIA1_BASE 0x163000
> -#define FIA2_BASE 0x16E000
> -#define FIA3_BASE 0x16F000
> -#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
> -#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
> -
> -/* ICL PHY DFLEX registers */
> -#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
> -#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
> -#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
> -#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
> -#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
> -#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
> -#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
> -
> /* BXT PHY Ref registers */
> #define _PORT_REF_DW3_A 0x16218C
> #define _PORT_REF_DW3_BC 0x6C18C
> @@ -10076,149 +9886,6 @@ enum skl_power_gate {
> PORTTC1_PLL_ENABLE, \
> PORTTC2_PLL_ENABLE)
>
> -#define _MG_REFCLKIN_CTL_PORT1 0x16892C
> -#define _MG_REFCLKIN_CTL_PORT2 0x16992C
> -#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
> -#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
> -#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
> -#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
> -#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
> - _MG_REFCLKIN_CTL_PORT1, \
> - _MG_REFCLKIN_CTL_PORT2)
> -
> -#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
> -#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
> -#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
> -#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
> -#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
> -#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
> -#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
> -#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
> -#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
> - _MG_CLKTOP2_CORECLKCTL1_PORT1, \
> - _MG_CLKTOP2_CORECLKCTL1_PORT2)
> -
> -#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
> -#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
> -#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
> -#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
> -#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
> -#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
> -#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
> -#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
> -#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
> -#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
> -#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
> -#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
> -#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
> -#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
> -#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
> -#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
> -#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
> - _MG_CLKTOP2_HSCLKCTL_PORT1, \
> - _MG_CLKTOP2_HSCLKCTL_PORT2)
> -
> -#define _MG_PLL_DIV0_PORT1 0x168A00
> -#define _MG_PLL_DIV0_PORT2 0x169A00
> -#define _MG_PLL_DIV0_PORT3 0x16AA00
> -#define _MG_PLL_DIV0_PORT4 0x16BA00
> -#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
> -#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
> -#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
> -#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
> -#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
> -#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
> -#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
> - _MG_PLL_DIV0_PORT2)
> -
> -#define _MG_PLL_DIV1_PORT1 0x168A04
> -#define _MG_PLL_DIV1_PORT2 0x169A04
> -#define _MG_PLL_DIV1_PORT3 0x16AA04
> -#define _MG_PLL_DIV1_PORT4 0x16BA04
> -#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
> -#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
> -#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
> -#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
> -#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
> -#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
> -#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
> -#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
> -#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
> - _MG_PLL_DIV1_PORT2)
> -
> -#define _MG_PLL_LF_PORT1 0x168A08
> -#define _MG_PLL_LF_PORT2 0x169A08
> -#define _MG_PLL_LF_PORT3 0x16AA08
> -#define _MG_PLL_LF_PORT4 0x16BA08
> -#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
> -#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
> -#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
> -#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
> -#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
> -#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
> -#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
> - _MG_PLL_LF_PORT2)
> -
> -#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
> -#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
> -#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
> -#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
> -#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
> -#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
> -#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
> -#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
> -#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
> -#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
> -#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
> - _MG_PLL_FRAC_LOCK_PORT1, \
> - _MG_PLL_FRAC_LOCK_PORT2)
> -
> -#define _MG_PLL_SSC_PORT1 0x168A10
> -#define _MG_PLL_SSC_PORT2 0x169A10
> -#define _MG_PLL_SSC_PORT3 0x16AA10
> -#define _MG_PLL_SSC_PORT4 0x16BA10
> -#define MG_PLL_SSC_EN (1 << 28)
> -#define MG_PLL_SSC_TYPE(x) ((x) << 26)
> -#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
> -#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
> -#define MG_PLL_SSC_FLLEN (1 << 9)
> -#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
> -#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
> - _MG_PLL_SSC_PORT2)
> -
> -#define _MG_PLL_BIAS_PORT1 0x168A14
> -#define _MG_PLL_BIAS_PORT2 0x169A14
> -#define _MG_PLL_BIAS_PORT3 0x16AA14
> -#define _MG_PLL_BIAS_PORT4 0x16BA14
> -#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
> -#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
> -#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
> -#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
> -#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
> -#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
> -#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
> -#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
> -#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
> -#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
> -#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
> -#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
> -#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
> -#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
> - _MG_PLL_BIAS_PORT2)
> -
> -#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
> -#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
> -#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
> -#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
> -#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
> -#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
> -#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
> -#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
> -#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
> -#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
> - _MG_PLL_TDC_COLDST_BIAS_PORT1, \
> - _MG_PLL_TDC_COLDST_BIAS_PORT2)
> -
> #define _ICL_DPLL0_CFGCR0 0x164000
> #define _ICL_DPLL1_CFGCR0 0x164080
> #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH v3 11/11] drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (9 preceding siblings ...)
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 10/11] drm/i915: Move TC " Matt Roper
@ 2022-01-11 5:16 ` Matt Roper
2022-01-11 13:50 ` Jani Nikula
2022-01-11 5:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Start cleaning up register definitions (rev3) Patchwork
` (4 subsequent siblings)
15 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2022-01-11 5:16 UTC (permalink / raw)
To: intel-gfx
All MG/DKL PHY register regions are evenly spaced offset-wise (0x168000,
0x169000, 0x16A000, 0x16B000) so the _MMIO_PORT() macro we use to access
their registers only needs the first two offsets. We can drop the
_PORT3 and _PORT4 offsets which are never directly referenced.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../gpu/drm/i915/display/intel_tc_phy_regs.h | 64 -------------------
1 file changed, 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h b/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
index 87b74c3c35a7..5a545086f959 100644
--- a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
@@ -15,10 +15,6 @@
#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
-#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
-#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
-#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
-#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
#define MG_TX1_LINK_PARAMS(ln, tc_port) \
MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
@@ -28,10 +24,6 @@
#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
-#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
-#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
-#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
-#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
#define MG_TX2_LINK_PARAMS(ln, tc_port) \
MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
@@ -42,10 +34,6 @@
#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
-#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
-#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
-#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
-#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
#define MG_TX1_PISO_READLOAD(ln, tc_port) \
MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
@@ -55,10 +43,6 @@
#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
-#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
-#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
-#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
-#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
#define MG_TX2_PISO_READLOAD(ln, tc_port) \
MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
@@ -69,10 +53,6 @@
#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
-#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
-#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
-#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
-#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
#define MG_TX1_SWINGCTRL(ln, tc_port) \
MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
MG_TX_SWINGCTRL_TX1LN0_PORT2, \
@@ -82,10 +62,6 @@
#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
-#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
-#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
-#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
-#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
#define MG_TX2_SWINGCTRL(ln, tc_port) \
MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
MG_TX_SWINGCTRL_TX2LN0_PORT2, \
@@ -110,10 +86,6 @@
#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
-#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
-#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
-#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
-#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
#define MG_TX2_DRVCTRL(ln, tc_port) \
MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
MG_TX_DRVCTRL_TX2LN0_PORT2, \
@@ -130,10 +102,6 @@
#define MG_CLKHUB_LN1_PORT1 0x16879C
#define MG_CLKHUB_LN0_PORT2 0x16939C
#define MG_CLKHUB_LN1_PORT2 0x16979C
-#define MG_CLKHUB_LN0_PORT3 0x16A39C
-#define MG_CLKHUB_LN1_PORT3 0x16A79C
-#define MG_CLKHUB_LN0_PORT4 0x16B39C
-#define MG_CLKHUB_LN1_PORT4 0x16B79C
#define MG_CLKHUB(ln, tc_port) \
MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
MG_CLKHUB_LN0_PORT2, \
@@ -144,10 +112,6 @@
#define MG_TX_DCC_TX1LN1_PORT1 0x168510
#define MG_TX_DCC_TX1LN0_PORT2 0x169110
#define MG_TX_DCC_TX1LN1_PORT2 0x169510
-#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
-#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
-#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
-#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
#define MG_TX1_DCC(ln, tc_port) \
MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
MG_TX_DCC_TX1LN0_PORT2, \
@@ -156,10 +120,6 @@
#define MG_TX_DCC_TX2LN1_PORT1 0x168490
#define MG_TX_DCC_TX2LN0_PORT2 0x169090
#define MG_TX_DCC_TX2LN1_PORT2 0x169490
-#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
-#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
-#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
-#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
#define MG_TX2_DCC(ln, tc_port) \
MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
MG_TX_DCC_TX2LN0_PORT2, \
@@ -172,10 +132,6 @@
#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
-#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
-#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
-#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
-#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
#define MG_DP_MODE(ln, tc_port) \
MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
MG_DP_MODE_LN0_ACU_PORT2, \
@@ -200,8 +156,6 @@
#define _MG_REFCLKIN_CTL_PORT1 0x16892C
#define _MG_REFCLKIN_CTL_PORT2 0x16992C
-#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
-#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
@@ -210,8 +164,6 @@
#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
-#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
-#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
@@ -222,8 +174,6 @@
#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
-#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
-#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
@@ -242,8 +192,6 @@
#define _MG_PLL_DIV0_PORT1 0x168A00
#define _MG_PLL_DIV0_PORT2 0x169A00
-#define _MG_PLL_DIV0_PORT3 0x16AA00
-#define _MG_PLL_DIV0_PORT4 0x16BA00
#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
@@ -255,8 +203,6 @@
#define _MG_PLL_DIV1_PORT1 0x168A04
#define _MG_PLL_DIV1_PORT2 0x169A04
-#define _MG_PLL_DIV1_PORT3 0x16AA04
-#define _MG_PLL_DIV1_PORT4 0x16BA04
#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
@@ -270,8 +216,6 @@
#define _MG_PLL_LF_PORT1 0x168A08
#define _MG_PLL_LF_PORT2 0x169A08
-#define _MG_PLL_LF_PORT3 0x16AA08
-#define _MG_PLL_LF_PORT4 0x16BA08
#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
@@ -283,8 +227,6 @@
#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
-#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
-#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
@@ -297,8 +239,6 @@
#define _MG_PLL_SSC_PORT1 0x168A10
#define _MG_PLL_SSC_PORT2 0x169A10
-#define _MG_PLL_SSC_PORT3 0x16AA10
-#define _MG_PLL_SSC_PORT4 0x16BA10
#define MG_PLL_SSC_EN (1 << 28)
#define MG_PLL_SSC_TYPE(x) ((x) << 26)
#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
@@ -310,8 +250,6 @@
#define _MG_PLL_BIAS_PORT1 0x168A14
#define _MG_PLL_BIAS_PORT2 0x169A14
-#define _MG_PLL_BIAS_PORT3 0x16AA14
-#define _MG_PLL_BIAS_PORT4 0x16BA14
#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
@@ -330,8 +268,6 @@
#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
-#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
-#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Intel-gfx] [PATCH v3 11/11] drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets
2022-01-11 5:16 ` [Intel-gfx] [PATCH v3 11/11] drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets Matt Roper
@ 2022-01-11 13:50 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2022-01-11 13:50 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On Mon, 10 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> All MG/DKL PHY register regions are evenly spaced offset-wise (0x168000,
> 0x169000, 0x16A000, 0x16B000) so the _MMIO_PORT() macro we use to access
> their registers only needs the first two offsets. We can drop the
> _PORT3 and _PORT4 offsets which are never directly referenced.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_tc_phy_regs.h | 64 -------------------
> 1 file changed, 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h b/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
> index 87b74c3c35a7..5a545086f959 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
> @@ -15,10 +15,6 @@
> #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
> #define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
> #define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
> -#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C
> -#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C
> -#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C
> -#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C
> #define MG_TX1_LINK_PARAMS(ln, tc_port) \
> MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
> MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
> @@ -28,10 +24,6 @@
> #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
> #define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
> #define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
> -#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC
> -#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC
> -#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC
> -#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC
> #define MG_TX2_LINK_PARAMS(ln, tc_port) \
> MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
> MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
> @@ -42,10 +34,6 @@
> #define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
> #define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
> #define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
> -#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C
> -#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C
> -#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C
> -#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C
> #define MG_TX1_PISO_READLOAD(ln, tc_port) \
> MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
> MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
> @@ -55,10 +43,6 @@
> #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
> #define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
> #define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
> -#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC
> -#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC
> -#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC
> -#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC
> #define MG_TX2_PISO_READLOAD(ln, tc_port) \
> MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
> MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
> @@ -69,10 +53,6 @@
> #define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
> #define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
> #define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
> -#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148
> -#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548
> -#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148
> -#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548
> #define MG_TX1_SWINGCTRL(ln, tc_port) \
> MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
> MG_TX_SWINGCTRL_TX1LN0_PORT2, \
> @@ -82,10 +62,6 @@
> #define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
> #define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
> #define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
> -#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8
> -#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8
> -#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8
> -#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8
> #define MG_TX2_SWINGCTRL(ln, tc_port) \
> MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
> MG_TX_SWINGCTRL_TX2LN0_PORT2, \
> @@ -110,10 +86,6 @@
> #define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
> #define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
> #define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
> -#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4
> -#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4
> -#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4
> -#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4
> #define MG_TX2_DRVCTRL(ln, tc_port) \
> MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
> MG_TX_DRVCTRL_TX2LN0_PORT2, \
> @@ -130,10 +102,6 @@
> #define MG_CLKHUB_LN1_PORT1 0x16879C
> #define MG_CLKHUB_LN0_PORT2 0x16939C
> #define MG_CLKHUB_LN1_PORT2 0x16979C
> -#define MG_CLKHUB_LN0_PORT3 0x16A39C
> -#define MG_CLKHUB_LN1_PORT3 0x16A79C
> -#define MG_CLKHUB_LN0_PORT4 0x16B39C
> -#define MG_CLKHUB_LN1_PORT4 0x16B79C
> #define MG_CLKHUB(ln, tc_port) \
> MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
> MG_CLKHUB_LN0_PORT2, \
> @@ -144,10 +112,6 @@
> #define MG_TX_DCC_TX1LN1_PORT1 0x168510
> #define MG_TX_DCC_TX1LN0_PORT2 0x169110
> #define MG_TX_DCC_TX1LN1_PORT2 0x169510
> -#define MG_TX_DCC_TX1LN0_PORT3 0x16A110
> -#define MG_TX_DCC_TX1LN1_PORT3 0x16A510
> -#define MG_TX_DCC_TX1LN0_PORT4 0x16B110
> -#define MG_TX_DCC_TX1LN1_PORT4 0x16B510
> #define MG_TX1_DCC(ln, tc_port) \
> MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
> MG_TX_DCC_TX1LN0_PORT2, \
> @@ -156,10 +120,6 @@
> #define MG_TX_DCC_TX2LN1_PORT1 0x168490
> #define MG_TX_DCC_TX2LN0_PORT2 0x169090
> #define MG_TX_DCC_TX2LN1_PORT2 0x169490
> -#define MG_TX_DCC_TX2LN0_PORT3 0x16A090
> -#define MG_TX_DCC_TX2LN1_PORT3 0x16A490
> -#define MG_TX_DCC_TX2LN0_PORT4 0x16B090
> -#define MG_TX_DCC_TX2LN1_PORT4 0x16B490
> #define MG_TX2_DCC(ln, tc_port) \
> MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
> MG_TX_DCC_TX2LN0_PORT2, \
> @@ -172,10 +132,6 @@
> #define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
> #define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
> #define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
> -#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
> -#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
> -#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
> -#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
> #define MG_DP_MODE(ln, tc_port) \
> MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
> MG_DP_MODE_LN0_ACU_PORT2, \
> @@ -200,8 +156,6 @@
>
> #define _MG_REFCLKIN_CTL_PORT1 0x16892C
> #define _MG_REFCLKIN_CTL_PORT2 0x16992C
> -#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
> -#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
> #define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
> #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
> #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
> @@ -210,8 +164,6 @@
>
> #define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
> #define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
> -#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
> -#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
> #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
> #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
> #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
> @@ -222,8 +174,6 @@
>
> #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
> #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
> -#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
> -#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
> #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
> #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
> #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
> @@ -242,8 +192,6 @@
>
> #define _MG_PLL_DIV0_PORT1 0x168A00
> #define _MG_PLL_DIV0_PORT2 0x169A00
> -#define _MG_PLL_DIV0_PORT3 0x16AA00
> -#define _MG_PLL_DIV0_PORT4 0x16BA00
> #define MG_PLL_DIV0_FRACNEN_H (1 << 30)
> #define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
> #define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
> @@ -255,8 +203,6 @@
>
> #define _MG_PLL_DIV1_PORT1 0x168A04
> #define _MG_PLL_DIV1_PORT2 0x169A04
> -#define _MG_PLL_DIV1_PORT3 0x16AA04
> -#define _MG_PLL_DIV1_PORT4 0x16BA04
> #define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
> #define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
> #define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
> @@ -270,8 +216,6 @@
>
> #define _MG_PLL_LF_PORT1 0x168A08
> #define _MG_PLL_LF_PORT2 0x169A08
> -#define _MG_PLL_LF_PORT3 0x16AA08
> -#define _MG_PLL_LF_PORT4 0x16BA08
> #define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
> #define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
> #define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
> @@ -283,8 +227,6 @@
>
> #define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
> #define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
> -#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C
> -#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C
> #define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
> #define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
> #define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
> @@ -297,8 +239,6 @@
>
> #define _MG_PLL_SSC_PORT1 0x168A10
> #define _MG_PLL_SSC_PORT2 0x169A10
> -#define _MG_PLL_SSC_PORT3 0x16AA10
> -#define _MG_PLL_SSC_PORT4 0x16BA10
> #define MG_PLL_SSC_EN (1 << 28)
> #define MG_PLL_SSC_TYPE(x) ((x) << 26)
> #define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
> @@ -310,8 +250,6 @@
>
> #define _MG_PLL_BIAS_PORT1 0x168A14
> #define _MG_PLL_BIAS_PORT2 0x169A14
> -#define _MG_PLL_BIAS_PORT3 0x16AA14
> -#define _MG_PLL_BIAS_PORT4 0x16BA14
> #define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
> #define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
> #define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
> @@ -330,8 +268,6 @@
>
> #define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
> #define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
> -#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18
> -#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18
> #define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
> #define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
> #define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Start cleaning up register definitions (rev3)
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (10 preceding siblings ...)
2022-01-11 5:16 ` [Intel-gfx] [PATCH v3 11/11] drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets Matt Roper
@ 2022-01-11 5:45 ` Patchwork
2022-01-11 5:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2022-01-11 5:45 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: Start cleaning up register definitions (rev3)
URL : https://patchwork.freedesktop.org/series/98575/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e41d2f04b72a drm/i915: Use parameterized GPR register definitions everywhere
-:22: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#22: FILE: drivers/gpu/drm/i915/i915_cmd_parser.c:595:
+#define REG64_BASE_IDX(_reg, base, idx) \
+ { .addr = _reg(base, idx) }, \
+ { .addr = _reg ## _UDW(base, idx) }
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/i915_cmd_parser.c:595:
+#define REG64_BASE_IDX(_reg, base, idx) \
+ { .addr = _reg(base, idx) }, \
+ { .addr = _reg ## _UDW(base, idx) }
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'idx' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/i915_cmd_parser.c:595:
+#define REG64_BASE_IDX(_reg, base, idx) \
+ { .addr = _reg(base, idx) }, \
+ { .addr = _reg ## _UDW(base, idx) }
total: 1 errors, 0 warnings, 2 checks, 106 lines checked
e327ba8e8c11 drm/i915: Parameterize PWRCTX_MAXCNT
015378528220 drm/i915: Parameterize ECOSKPD
b7b8ca9b04ef drm/i915: Use RING_PSMI_CTL rather than per-engine macros
-:114: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#114: FILE: drivers/gpu/drm/i915/intel_pm.c:7658:
+ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
-:123: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#123: FILE: drivers/gpu/drm/i915/intel_pm.c:7799:
+ intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
total: 0 errors, 0 warnings, 2 checks, 89 lines checked
b3f3b6cd9677 drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7
00c2a2d5bca6 drm/i915: Introduce i915_reg_defs.h
-:121: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#121:
new file mode 100644
-:145: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__n' - possible side-effects?
#145: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:20:
+#define REG_BIT(__n) \
+ ((u32)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 31))))
-:159: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__high' - possible side-effects?
#159: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:34:
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-:159: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__low' - possible side-effects?
#159: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:34:
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-:168: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__x' - possible side-effects?
#168: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:43:
+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
-:180: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__mask' - possible side-effects?
#180: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:55:
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:180: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__val' - possible side-effects?
#180: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:55:
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:185: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#185: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:60:
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:199: WARNING:NEW_TYPEDEFS: do not add new typedefs
#199: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:74:
+typedef struct {
-:222: CHECK:LINE_SPACING: Please don't use multiple blank lines
#222: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:97:
+
+
total: 0 errors, 3 warnings, 7 checks, 198 lines checked
c6d204da3552 drm/i915/gt: Move engine registers to their own header
-:66: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#66:
new file mode 100644
-:266: CHECK:LINE_SPACING: Please don't use multiple blank lines
#266: FILE: drivers/gpu/drm/i915/gt/intel_engine_regs.h:196:
+
+
-:638: CHECK:LINE_SPACING: Please don't use multiple blank lines
#638: FILE: drivers/gpu/drm/i915/i915_reg.h:2202:
+
+
total: 0 errors, 1 warnings, 2 checks, 668 lines checked
f9b30303c8f3 drm/i915: Move SNPS PHY registers to their own header
-:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#30:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 155 lines checked
a1b5e1b0786f drm/i915: Move combo PHY registers to their own header
-:37: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#37:
new file mode 100644
-:149: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#149: FILE: drivers/gpu/drm/i915/display/intel_combo_phy_regs.h:108:
+#define _ICL_PORT_TX_DW_LN(dw, ln, phy) ^I(_ICL_COMBOPHY(phy) + \$
-:197: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#197: FILE: drivers/gpu/drm/i915/display/intel_combo_phy_regs.h:156:
+#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
total: 0 errors, 3 warnings, 0 checks, 357 lines checked
00b848b9a979 drm/i915: Move TC PHY registers to their own header
-:50: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#50:
new file mode 100644
-:65: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0p1' - possible side-effects?
#65: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:11:
+#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
+ _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
total: 0 errors, 1 warnings, 1 checks, 716 lines checked
024d6cafab40 drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets
^ permalink raw reply [flat|nested] 29+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Start cleaning up register definitions (rev3)
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (11 preceding siblings ...)
2022-01-11 5:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Start cleaning up register definitions (rev3) Patchwork
@ 2022-01-11 5:47 ` Patchwork
2022-01-11 6:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2022-01-11 5:47 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: Start cleaning up register definitions (rev3)
URL : https://patchwork.freedesktop.org/series/98575/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 29+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Start cleaning up register definitions (rev3)
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (12 preceding siblings ...)
2022-01-11 5:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-01-11 6:02 ` Patchwork
2022-01-11 10:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-01-12 21:41 ` [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Rodrigo Vivi
15 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2022-01-11 6:02 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6480 bytes --]
== Series Details ==
Series: Start cleaning up register definitions (rev3)
URL : https://patchwork.freedesktop.org/series/98575/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11061 -> Patchwork_21961
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/index.html
Participating hosts (46 -> 38)
------------------------------
Additional (2): fi-icl-u2 fi-pnv-d510
Missing (10): fi-bdw-samus bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 bat-rpls-1 bat-rpls-2 bat-jsl-2 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_21961 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770: NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-hsw-4770/igt@amdgpu/amd_basic@cs-gfx.html
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][4] -> [INCOMPLETE][5] ([i915#4547])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][6] ([i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#109278]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][11] ([fdo#109271]) +57 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][12] ([i915#3301])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][13] ([i915#2426] / [i915#4312])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][14] ([i915#2940]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][16] ([i915#4785]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
Build changes
-------------
* Linux: CI_DRM_11061 -> Patchwork_21961
CI-20190529: 20190529
CI_DRM_11061: 0ee2fe64a0021c173a686de95f9961c35c82cb99 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6326: ec75f64fcbcf4aac58fbf1bf629e8f59b19db4ce @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21961: 024d6cafab40d3aad4c9d37d6233c116d52aec8b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
024d6cafab40 drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets
00b848b9a979 drm/i915: Move TC PHY registers to their own header
a1b5e1b0786f drm/i915: Move combo PHY registers to their own header
f9b30303c8f3 drm/i915: Move SNPS PHY registers to their own header
c6d204da3552 drm/i915/gt: Move engine registers to their own header
00c2a2d5bca6 drm/i915: Introduce i915_reg_defs.h
b3f3b6cd9677 drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7
b7b8ca9b04ef drm/i915: Use RING_PSMI_CTL rather than per-engine macros
015378528220 drm/i915: Parameterize ECOSKPD
e327ba8e8c11 drm/i915: Parameterize PWRCTX_MAXCNT
e41d2f04b72a drm/i915: Use parameterized GPR register definitions everywhere
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/index.html
[-- Attachment #2: Type: text/html, Size: 7688 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Start cleaning up register definitions (rev3)
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (13 preceding siblings ...)
2022-01-11 6:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-01-11 10:45 ` Patchwork
2022-01-11 22:17 ` Matt Roper
2022-01-12 21:41 ` [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Rodrigo Vivi
15 siblings, 1 reply; 29+ messages in thread
From: Patchwork @ 2022-01-11 10:45 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30268 bytes --]
== Series Details ==
Series: Start cleaning up register definitions (rev3)
URL : https://patchwork.freedesktop.org/series/98575/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11061_full -> Patchwork_21961_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21961_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21961_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21961_full:
### IGT changes ###
#### Possible regressions ####
* igt@drm_mm@all@insert:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl10/igt@drm_mm@all@insert.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@drm_mm@all@insert.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb5/igt@i915_pm_rpm@modeset-lpsp-stress.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb7/igt@i915_pm_rpm@modeset-lpsp-stress.html
Known issues
------------
Here are the changes found in Patchwork_21961_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@q-in-order:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271]) +35 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-snb5/igt@gem_ctx_shared@q-in-order.html
* igt@gem_eio@unwedge-stress:
- shard-skl: [PASS][6] -> [TIMEOUT][7] ([i915#3063])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl6/igt@gem_eio@unwedge-stress.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl4/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb4/igt@gem_exec_balancer@parallel-keep-submit-fence.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb3/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: [PASS][10] -> [INCOMPLETE][11] ([i915#4547])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl10/igt@gem_exec_capture@pi@bcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_capture@userptr:
- shard-skl: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl2/igt@gem_exec_capture@userptr.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl5/igt@gem_exec_capture@userptr.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][14] -> [FAIL][15] ([i915#2842]) +4 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][18] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_lmem_swapping@basic:
- shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-skl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@smem-oom:
- shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_pwrite@basic-exhaustion:
- shard-kbl: NOTRUN -> [WARN][22] ([i915#2658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@gem_pwrite@basic-exhaustion.html
- shard-apl: NOTRUN -> [WARN][23] ([i915#2658])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl8/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-tglb: NOTRUN -> [SKIP][24] ([i915#4270])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-tglb: NOTRUN -> [SKIP][25] ([i915#3323])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb5/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][26] ([i915#3002])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl1/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-tglb: NOTRUN -> [FAIL][27] ([i915#3318])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#2527] / [i915#2856]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@gen9_exec_parse@bb-start-cmd.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-tglb: NOTRUN -> [SKIP][29] ([fdo#111644] / [i915#1397] / [i915#2411])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][30] -> [FAIL][31] ([i915#2521])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_async_flips@crc:
- shard-skl: NOTRUN -> [FAIL][32] ([i915#4272])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_async_flips@crc.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-glk: [PASS][33] -> [DMESG-WARN][34] ([i915#118])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk7/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][36] ([i915#3743])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3777])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][38] ([fdo#111614])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][39] ([i915#3763])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][40] ([fdo#111615]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][41] ([i915#3689]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3886]) +7 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#111615] / [i915#3689]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3886]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl8/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-crc-fast:
- shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +8 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl8/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl7/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-snb: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +2 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-snb5/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-tglb: NOTRUN -> [SKIP][49] ([fdo#109284] / [fdo#111827]) +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb5/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
- shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +6 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl10/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding:
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#3359]) +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen:
- shard-tglb: NOTRUN -> [SKIP][52] ([i915#3319]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-sliding:
- shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109279] / [i915#3359]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-512x170-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-iclb: [PASS][54] -> [FAIL][55] ([i915#2346])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb8/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][56] -> [INCOMPLETE][57] ([i915#636])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-tglb: NOTRUN -> [SKIP][58] ([fdo#109274] / [fdo#111825]) +3 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][59] -> [DMESG-WARN][60] ([i915#180]) +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
- shard-iclb: [PASS][61] -> [SKIP][62] ([i915#3701])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
- shard-tglb: NOTRUN -> [SKIP][63] ([fdo#109280] / [fdo#111825]) +12 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][64] ([i915#180])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl8/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][65] ([fdo#109271]) +113 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-tglb: [PASS][66] -> [DMESG-WARN][67] ([i915#2411] / [i915#2867])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-tglb2/igt@kms_frontbuffer_tracking@psr-suspend.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb2/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][68] -> [FAIL][69] ([i915#1188])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl2/igt@kms_hdr@bpc-switch.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl1/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#533])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#533])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][72] ([fdo#108145] / [i915#265]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][73] -> [FAIL][74] ([fdo#108145] / [i915#265])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][76] ([i915#265])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][77] ([fdo#108145] / [i915#265])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
- shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271]) +50 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl4/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2733])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-tglb: NOTRUN -> [SKIP][80] ([i915#1911])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][81] -> [SKIP][82] ([fdo#109441]) +4 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb2/igt@kms_psr@psr2_suspend.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb6/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][83] -> [FAIL][84] ([i915#31])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl4/igt@kms_setmode@basic.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl1/igt@kms_setmode@basic.html
- shard-glk: [PASS][85] -> [FAIL][86] ([i915#31])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk7/igt@kms_setmode@basic.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk4/igt@kms_setmode@basic.html
* igt@kms_sysfs_edid_timing:
- shard-kbl: NOTRUN -> [FAIL][87] ([IGT#2])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl7/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-a-accuracy-idle:
- shard-skl: NOTRUN -> [FAIL][88] ([i915#43])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@kms_vblank@pipe-a-accuracy-idle.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2437]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@kms_writeback@writeback-check-output.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271]) +109 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl3/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@perf@polling-parameterized:
- shard-skl: NOTRUN -> [FAIL][91] ([i915#1542])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@perf@polling-parameterized.html
* igt@prime_nv_api@i915_nv_import_vs_close:
- shard-tglb: NOTRUN -> [SKIP][92] ([fdo#109291]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@prime_nv_api@i915_nv_import_vs_close.html
* igt@sysfs_clients@fair-0:
- shard-kbl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#2994])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@split-25:
- shard-skl: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#2994]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@sysfs_clients@split-25.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][95] ([i915#658]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb7/igt@feature_discovery@psr2.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][97] ([i915#2846]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk5/igt@gem_exec_fair@basic-deadline.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk5/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [FAIL][99] ([i915#2842]) -> [PASS][100] +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk2/igt@gem_exec_fair@basic-none@vcs0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_parallel@engines@basic:
- shard-glk: [DMESG-WARN][101] ([i915#118]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk7/igt@gem_exec_parallel@engines@basic.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk7/igt@gem_exec_parallel@engines@basic.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][103] ([i915#2190]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb3/igt@gem_huc_copy@huc-copy.html
* igt@gem_workarounds@reset-context:
- shard-snb: [TIMEOUT][105] -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-snb2/igt@gem_workarounds@reset-context.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-snb2/igt@gem_workarounds@reset-context.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][107] ([i915#3921]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-snb7/igt@i915_selftest@live@hangcheck.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-snb5/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][109] ([i915#180]) -> [PASS][110] +4 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-skl: [FAIL][111] ([i915#2346]) -> [PASS][112] +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][113] ([i915#2122]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [FAIL][115] ([i915#79]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][117] ([i915#1188]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-apl: [DMESG-WARN][119] ([i915#180]) -> [PASS][120] +3 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][121] ([fdo#108145] / [i915#265]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][123] ([fdo#109441]) -> [PASS][124] +2 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@perf@polling-small-buf:
- shard-skl: [FAIL][125] ([i915#1722]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl4/igt@perf@polling-small-buf.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl8/igt@perf@polling-small-buf.html
#### Warnings ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][127] ([i915#2852]) -> [FAIL][128] ([i915#2842])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][129] ([i915#2684]) -> [WARN][130] ([i915#1804] / [i915#2684])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][131] ([i915#1804] / [i915#2684]) -> [FAIL][132] ([i915#2680])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#4312]) -> ([FAIL][139], [FAIL][140]) ([i915#3002] / [i915#4312])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl6/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl1/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl1/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl4/igt@runner@aborted.html
- shard-apl: ([FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#4312]) -> ([FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl6/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl3/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/index.html
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^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Start cleaning up register definitions (rev3)
2022-01-11 10:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-01-11 22:17 ` Matt Roper
2022-01-11 22:19 ` Matt Roper
0 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2022-01-11 22:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Vudum, Lakshminarayana
On Tue, Jan 11, 2022 at 10:45:38AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: Start cleaning up register definitions (rev3)
> URL : https://patchwork.freedesktop.org/series/98575/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11061_full -> Patchwork_21961_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_21961_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_21961_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (10 -> 10)
> ------------------------------
>
> No changes in participating hosts
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_21961_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@drm_mm@all@insert:
> - shard-skl: [PASS][1] -> [INCOMPLETE][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl10/igt@drm_mm@all@insert.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@drm_mm@all@insert.html
Timeout:
[IGT] Per-test timeout exceeded. Killing the current test with SIGQUIT.
Seems that https://gitlab.freedesktop.org/drm/intel/-/issues/2485 is
still an issue.
>
> * igt@i915_pm_rpm@modeset-lpsp-stress:
> - shard-iclb: [PASS][3] -> [INCOMPLETE][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb5/igt@i915_pm_rpm@modeset-lpsp-stress.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb7/igt@i915_pm_rpm@modeset-lpsp-stress.html
Seems like an ext4 filesystem panic after some disk I/O errors:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb7/pstore4-1641881385_Panic_1.txt
Failing hard drive?
Neither issue is caused by the register cleanup here. Patches applied
to drm-intel-next; thanks for the reviews.
Matt
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_21961_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_ctx_shared@q-in-order:
> - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271]) +35 similar issues
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-snb5/igt@gem_ctx_shared@q-in-order.html
>
> * igt@gem_eio@unwedge-stress:
> - shard-skl: [PASS][6] -> [TIMEOUT][7] ([i915#3063])
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl6/igt@gem_eio@unwedge-stress.html
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl4/igt@gem_eio@unwedge-stress.html
>
> * igt@gem_exec_balancer@parallel-keep-submit-fence:
> - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525])
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb4/igt@gem_exec_balancer@parallel-keep-submit-fence.html
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb3/igt@gem_exec_balancer@parallel-keep-submit-fence.html
>
> * igt@gem_exec_capture@pi@bcs0:
> - shard-skl: [PASS][10] -> [INCOMPLETE][11] ([i915#4547])
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl10/igt@gem_exec_capture@pi@bcs0.html
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@gem_exec_capture@pi@bcs0.html
>
> * igt@gem_exec_capture@userptr:
> - shard-skl: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) +1 similar issue
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl2/igt@gem_exec_capture@userptr.html
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl5/igt@gem_exec_capture@userptr.html
>
> * igt@gem_exec_fair@basic-none@vcs0:
> - shard-kbl: [PASS][14] -> [FAIL][15] ([i915#2842]) +4 similar issues
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
>
> * igt@gem_exec_fair@basic-pace@vcs0:
> - shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2842])
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs0.html
>
> * igt@gem_exec_fair@basic-pace@vcs1:
> - shard-iclb: NOTRUN -> [FAIL][18] ([i915#2842])
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
>
> * igt@gem_lmem_swapping@basic:
> - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@gem_lmem_swapping@basic.html
>
> * igt@gem_lmem_swapping@heavy-verify-random:
> - shard-skl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@gem_lmem_swapping@heavy-verify-random.html
>
> * igt@gem_lmem_swapping@smem-oom:
> - shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +1 similar issue
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@gem_lmem_swapping@smem-oom.html
>
> * igt@gem_pwrite@basic-exhaustion:
> - shard-kbl: NOTRUN -> [WARN][22] ([i915#2658])
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@gem_pwrite@basic-exhaustion.html
> - shard-apl: NOTRUN -> [WARN][23] ([i915#2658])
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl8/igt@gem_pwrite@basic-exhaustion.html
>
> * igt@gem_pxp@regular-baseline-src-copy-readible:
> - shard-tglb: NOTRUN -> [SKIP][24] ([i915#4270])
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@gem_pxp@regular-baseline-src-copy-readible.html
>
> * igt@gem_userptr_blits@dmabuf-sync:
> - shard-tglb: NOTRUN -> [SKIP][25] ([i915#3323])
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb5/igt@gem_userptr_blits@dmabuf-sync.html
>
> * igt@gem_userptr_blits@input-checking:
> - shard-apl: NOTRUN -> [DMESG-WARN][26] ([i915#3002])
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl1/igt@gem_userptr_blits@input-checking.html
>
> * igt@gem_userptr_blits@vma-merge:
> - shard-tglb: NOTRUN -> [FAIL][27] ([i915#3318])
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@gem_userptr_blits@vma-merge.html
>
> * igt@gen9_exec_parse@bb-start-cmd:
> - shard-tglb: NOTRUN -> [SKIP][28] ([i915#2527] / [i915#2856]) +1 similar issue
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@gen9_exec_parse@bb-start-cmd.html
>
> * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
> - shard-tglb: NOTRUN -> [SKIP][29] ([fdo#111644] / [i915#1397] / [i915#2411])
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
>
> * igt@kms_async_flips@alternate-sync-async-flip:
> - shard-skl: [PASS][30] -> [FAIL][31] ([i915#2521])
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip.html
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
>
> * igt@kms_async_flips@crc:
> - shard-skl: NOTRUN -> [FAIL][32] ([i915#4272])
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_async_flips@crc.html
>
> * igt@kms_big_fb@linear-32bpp-rotate-0:
> - shard-glk: [PASS][33] -> [DMESG-WARN][34] ([i915#118])
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-0.html
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk7/igt@kms_big_fb@linear-32bpp-rotate-0.html
>
> * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
> - shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777])
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
>
> * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
> - shard-skl: NOTRUN -> [FAIL][36] ([i915#3743])
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
>
> * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
> - shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3777])
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
>
> * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
> - shard-tglb: NOTRUN -> [SKIP][38] ([fdo#111614])
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
>
> * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
> - shard-skl: NOTRUN -> [FAIL][39] ([i915#3763])
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
>
> * igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
> - shard-tglb: NOTRUN -> [SKIP][40] ([fdo#111615]) +1 similar issue
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
>
> * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs:
> - shard-tglb: NOTRUN -> [SKIP][41] ([i915#3689]) +2 similar issues
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs.html
>
> * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
> - shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3886]) +7 similar issues
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
>
> * igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs:
> - shard-tglb: NOTRUN -> [SKIP][43] ([fdo#111615] / [i915#3689]) +2 similar issues
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs.html
>
> * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
> - shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3886]) +2 similar issues
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
>
> * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
> - shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +3 similar issues
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl8/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
>
> * igt@kms_chamelium@hdmi-crc-fast:
> - shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +8 similar issues
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl8/igt@kms_chamelium@hdmi-crc-fast.html
>
> * igt@kms_chamelium@hdmi-hpd-storm:
> - shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +5 similar issues
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl7/igt@kms_chamelium@hdmi-hpd-storm.html
>
> * igt@kms_chamelium@hdmi-mode-timings:
> - shard-snb: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +2 similar issues
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-snb5/igt@kms_chamelium@hdmi-mode-timings.html
>
> * igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
> - shard-tglb: NOTRUN -> [SKIP][49] ([fdo#109284] / [fdo#111827]) +3 similar issues
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb5/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
> - shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +6 similar issues
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl10/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
>
> * igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding:
> - shard-tglb: NOTRUN -> [SKIP][51] ([i915#3359]) +4 similar issues
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen:
> - shard-tglb: NOTRUN -> [SKIP][52] ([i915#3319]) +1 similar issue
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen.html
>
> * igt@kms_cursor_crc@pipe-d-cursor-512x170-sliding:
> - shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109279] / [i915#3359]) +1 similar issue
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-512x170-sliding.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
> - shard-iclb: [PASS][54] -> [FAIL][55] ([i915#2346])
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb8/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
>
> * igt@kms_fbcon_fbt@fbc-suspend:
> - shard-kbl: [PASS][56] -> [INCOMPLETE][57] ([i915#636])
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
>
> * igt@kms_flip@2x-dpms-vs-vblank-race:
> - shard-tglb: NOTRUN -> [SKIP][58] ([fdo#109274] / [fdo#111825]) +3 similar issues
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_flip@2x-dpms-vs-vblank-race.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
> - shard-apl: [PASS][59] -> [DMESG-WARN][60] ([i915#180]) +3 similar issues
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
>
> * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
> - shard-iclb: [PASS][61] -> [SKIP][62] ([i915#3701])
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
>
> * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
> - shard-tglb: NOTRUN -> [SKIP][63] ([fdo#109280] / [fdo#111825]) +12 similar issues
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html
>
> * igt@kms_frontbuffer_tracking@fbc-suspend:
> - shard-apl: NOTRUN -> [DMESG-WARN][64] ([i915#180])
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl8/igt@kms_frontbuffer_tracking@fbc-suspend.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
> - shard-skl: NOTRUN -> [SKIP][65] ([fdo#109271]) +113 similar issues
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
>
> * igt@kms_frontbuffer_tracking@psr-suspend:
> - shard-tglb: [PASS][66] -> [DMESG-WARN][67] ([i915#2411] / [i915#2867])
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-tglb2/igt@kms_frontbuffer_tracking@psr-suspend.html
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb2/igt@kms_frontbuffer_tracking@psr-suspend.html
>
> * igt@kms_hdr@bpc-switch:
> - shard-skl: [PASS][68] -> [FAIL][69] ([i915#1188])
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl2/igt@kms_hdr@bpc-switch.html
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl1/igt@kms_hdr@bpc-switch.html
>
> * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
> - shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#533])
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
>
> * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
> - shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#533])
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
>
> * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
> - shard-apl: NOTRUN -> [FAIL][72] ([fdo#108145] / [i915#265]) +1 similar issue
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
>
> * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
> - shard-skl: [PASS][73] -> [FAIL][74] ([fdo#108145] / [i915#265])
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
>
> * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
> - shard-kbl: NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265]) +2 similar issues
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
>
> * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
> - shard-apl: NOTRUN -> [FAIL][76] ([i915#265])
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
>
> * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
> - shard-skl: NOTRUN -> [FAIL][77] ([fdo#108145] / [i915#265])
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
>
> * igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
> - shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271]) +50 similar issues
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl4/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html
>
> * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
> - shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2733])
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
>
> * igt@kms_psr2_su@frontbuffer-xrgb8888:
> - shard-tglb: NOTRUN -> [SKIP][80] ([i915#1911])
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
>
> * igt@kms_psr@psr2_suspend:
> - shard-iclb: [PASS][81] -> [SKIP][82] ([fdo#109441]) +4 similar issues
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb2/igt@kms_psr@psr2_suspend.html
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb6/igt@kms_psr@psr2_suspend.html
>
> * igt@kms_setmode@basic:
> - shard-apl: [PASS][83] -> [FAIL][84] ([i915#31])
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl4/igt@kms_setmode@basic.html
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl1/igt@kms_setmode@basic.html
> - shard-glk: [PASS][85] -> [FAIL][86] ([i915#31])
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk7/igt@kms_setmode@basic.html
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk4/igt@kms_setmode@basic.html
>
> * igt@kms_sysfs_edid_timing:
> - shard-kbl: NOTRUN -> [FAIL][87] ([IGT#2])
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl7/igt@kms_sysfs_edid_timing.html
>
> * igt@kms_vblank@pipe-a-accuracy-idle:
> - shard-skl: NOTRUN -> [FAIL][88] ([i915#43])
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@kms_vblank@pipe-a-accuracy-idle.html
>
> * igt@kms_writeback@writeback-check-output:
> - shard-apl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2437]) +1 similar issue
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@kms_writeback@writeback-check-output.html
>
> * igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
> - shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271]) +109 similar issues
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl3/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
>
> * igt@perf@polling-parameterized:
> - shard-skl: NOTRUN -> [FAIL][91] ([i915#1542])
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@perf@polling-parameterized.html
>
> * igt@prime_nv_api@i915_nv_import_vs_close:
> - shard-tglb: NOTRUN -> [SKIP][92] ([fdo#109291]) +1 similar issue
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@prime_nv_api@i915_nv_import_vs_close.html
>
> * igt@sysfs_clients@fair-0:
> - shard-kbl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#2994])
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@sysfs_clients@fair-0.html
>
> * igt@sysfs_clients@split-25:
> - shard-skl: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#2994]) +1 similar issue
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@sysfs_clients@split-25.html
>
>
> #### Possible fixes ####
>
> * igt@feature_discovery@psr2:
> - shard-iclb: [SKIP][95] ([i915#658]) -> [PASS][96]
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb7/igt@feature_discovery@psr2.html
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb2/igt@feature_discovery@psr2.html
>
> * igt@gem_exec_fair@basic-deadline:
> - shard-glk: [FAIL][97] ([i915#2846]) -> [PASS][98]
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk5/igt@gem_exec_fair@basic-deadline.html
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk5/igt@gem_exec_fair@basic-deadline.html
>
> * igt@gem_exec_fair@basic-none@vcs0:
> - shard-glk: [FAIL][99] ([i915#2842]) -> [PASS][100] +1 similar issue
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk2/igt@gem_exec_fair@basic-none@vcs0.html
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk4/igt@gem_exec_fair@basic-none@vcs0.html
>
> * igt@gem_exec_parallel@engines@basic:
> - shard-glk: [DMESG-WARN][101] ([i915#118]) -> [PASS][102] +1 similar issue
> [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk7/igt@gem_exec_parallel@engines@basic.html
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk7/igt@gem_exec_parallel@engines@basic.html
>
> * igt@gem_huc_copy@huc-copy:
> - shard-tglb: [SKIP][103] ([i915#2190]) -> [PASS][104]
> [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-tglb7/igt@gem_huc_copy@huc-copy.html
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb3/igt@gem_huc_copy@huc-copy.html
>
> * igt@gem_workarounds@reset-context:
> - shard-snb: [TIMEOUT][105] -> [PASS][106]
> [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-snb2/igt@gem_workarounds@reset-context.html
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-snb2/igt@gem_workarounds@reset-context.html
>
> * igt@i915_selftest@live@hangcheck:
> - shard-snb: [INCOMPLETE][107] ([i915#3921]) -> [PASS][108]
> [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-snb7/igt@i915_selftest@live@hangcheck.html
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-snb5/igt@i915_selftest@live@hangcheck.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-suspend:
> - shard-kbl: [DMESG-WARN][109] ([i915#180]) -> [PASS][110] +4 similar issues
> [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
> - shard-skl: [FAIL][111] ([i915#2346]) -> [PASS][112] +1 similar issue
> [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
> - shard-skl: [FAIL][113] ([i915#2122]) -> [PASS][114]
> [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
> - shard-skl: [FAIL][115] ([i915#79]) -> [PASS][116]
> [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
> [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
>
> * igt@kms_hdr@bpc-switch-dpms:
> - shard-skl: [FAIL][117] ([i915#1188]) -> [PASS][118]
> [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
> [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
> - shard-apl: [DMESG-WARN][119] ([i915#180]) -> [PASS][120] +3 similar issues
> [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
> [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
>
> * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
> - shard-skl: [FAIL][121] ([fdo#108145] / [i915#265]) -> [PASS][122]
> [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
> [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
>
> * igt@kms_psr@psr2_cursor_blt:
> - shard-iclb: [SKIP][123] ([fdo#109441]) -> [PASS][124] +2 similar issues
> [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html
> [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
>
> * igt@perf@polling-small-buf:
> - shard-skl: [FAIL][125] ([i915#1722]) -> [PASS][126]
> [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl4/igt@perf@polling-small-buf.html
> [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl8/igt@perf@polling-small-buf.html
>
>
> #### Warnings ####
>
> * igt@gem_exec_fair@basic-none-rrul@rcs0:
> - shard-iclb: [FAIL][127] ([i915#2852]) -> [FAIL][128] ([i915#2842])
> [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
> [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>
> * igt@i915_pm_rc6_residency@rc6-fence:
> - shard-iclb: [WARN][129] ([i915#2684]) -> [WARN][130] ([i915#1804] / [i915#2684])
> [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html
> [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
>
> * igt@i915_pm_rc6_residency@rc6-idle:
> - shard-iclb: [WARN][131] ([i915#1804] / [i915#2684]) -> [FAIL][132] ([i915#2680])
> [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
> [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
>
> * igt@runner@aborted:
> - shard-kbl: ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#4312]) -> ([FAIL][139], [FAIL][140]) ([i915#3002] / [i915#4312])
> [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl6/igt@runner@aborted.html
> [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@runner@aborted.html
> [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@runner@aborted.html
> [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl1/igt@runner@aborted.html
> [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@runner@aborted.html
> [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@runner@aborted.html
> [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl1/igt@runner@aborted.html
> [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl4/igt@runner@aborted.html
> - shard-apl: ([FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#4312]) -> ([FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312])
> [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl6/igt@runner@aborted.html
> [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl3/igt@runner@aborted.html
> [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Start cleaning up register definitions (rev3)
2022-01-11 22:17 ` Matt Roper
@ 2022-01-11 22:19 ` Matt Roper
0 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2022-01-11 22:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Vudum, Lakshminarayana, tejasreex.illipilli
+Cc Tejasree since Lakshmi is out at the moment.
Matt
On Tue, Jan 11, 2022 at 02:17:45PM -0800, Matt Roper wrote:
> On Tue, Jan 11, 2022 at 10:45:38AM +0000, Patchwork wrote:
> > == Series Details ==
> >
> > Series: Start cleaning up register definitions (rev3)
> > URL : https://patchwork.freedesktop.org/series/98575/
> > State : failure
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_11061_full -> Patchwork_21961_full
> > ====================================================
> >
> > Summary
> > -------
> >
> > **FAILURE**
> >
> > Serious unknown changes coming with Patchwork_21961_full absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_21961_full, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in CI.
> >
> >
> >
> > Participating hosts (10 -> 10)
> > ------------------------------
> >
> > No changes in participating hosts
> >
> > Possible new issues
> > -------------------
> >
> > Here are the unknown changes that may have been introduced in Patchwork_21961_full:
> >
> > ### IGT changes ###
> >
> > #### Possible regressions ####
> >
> > * igt@drm_mm@all@insert:
> > - shard-skl: [PASS][1] -> [INCOMPLETE][2]
> > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl10/igt@drm_mm@all@insert.html
> > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@drm_mm@all@insert.html
>
> Timeout:
> [IGT] Per-test timeout exceeded. Killing the current test with SIGQUIT.
>
> Seems that https://gitlab.freedesktop.org/drm/intel/-/issues/2485 is
> still an issue.
>
> >
> > * igt@i915_pm_rpm@modeset-lpsp-stress:
> > - shard-iclb: [PASS][3] -> [INCOMPLETE][4]
> > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb5/igt@i915_pm_rpm@modeset-lpsp-stress.html
> > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb7/igt@i915_pm_rpm@modeset-lpsp-stress.html
>
> Seems like an ext4 filesystem panic after some disk I/O errors:
>
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb7/pstore4-1641881385_Panic_1.txt
>
> Failing hard drive?
>
>
> Neither issue is caused by the register cleanup here. Patches applied
> to drm-intel-next; thanks for the reviews.
>
>
> Matt
>
> >
> >
> > Known issues
> > ------------
> >
> > Here are the changes found in Patchwork_21961_full that come from known issues:
> >
> > ### IGT changes ###
> >
> > #### Issues hit ####
> >
> > * igt@gem_ctx_shared@q-in-order:
> > - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271]) +35 similar issues
> > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-snb5/igt@gem_ctx_shared@q-in-order.html
> >
> > * igt@gem_eio@unwedge-stress:
> > - shard-skl: [PASS][6] -> [TIMEOUT][7] ([i915#3063])
> > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl6/igt@gem_eio@unwedge-stress.html
> > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl4/igt@gem_eio@unwedge-stress.html
> >
> > * igt@gem_exec_balancer@parallel-keep-submit-fence:
> > - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525])
> > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb4/igt@gem_exec_balancer@parallel-keep-submit-fence.html
> > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb3/igt@gem_exec_balancer@parallel-keep-submit-fence.html
> >
> > * igt@gem_exec_capture@pi@bcs0:
> > - shard-skl: [PASS][10] -> [INCOMPLETE][11] ([i915#4547])
> > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl10/igt@gem_exec_capture@pi@bcs0.html
> > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@gem_exec_capture@pi@bcs0.html
> >
> > * igt@gem_exec_capture@userptr:
> > - shard-skl: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) +1 similar issue
> > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl2/igt@gem_exec_capture@userptr.html
> > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl5/igt@gem_exec_capture@userptr.html
> >
> > * igt@gem_exec_fair@basic-none@vcs0:
> > - shard-kbl: [PASS][14] -> [FAIL][15] ([i915#2842]) +4 similar issues
> > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
> > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
> >
> > * igt@gem_exec_fair@basic-pace@vcs0:
> > - shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2842])
> > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
> > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs0.html
> >
> > * igt@gem_exec_fair@basic-pace@vcs1:
> > - shard-iclb: NOTRUN -> [FAIL][18] ([i915#2842])
> > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
> >
> > * igt@gem_lmem_swapping@basic:
> > - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
> > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@gem_lmem_swapping@basic.html
> >
> > * igt@gem_lmem_swapping@heavy-verify-random:
> > - shard-skl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
> > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@gem_lmem_swapping@heavy-verify-random.html
> >
> > * igt@gem_lmem_swapping@smem-oom:
> > - shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +1 similar issue
> > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@gem_lmem_swapping@smem-oom.html
> >
> > * igt@gem_pwrite@basic-exhaustion:
> > - shard-kbl: NOTRUN -> [WARN][22] ([i915#2658])
> > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@gem_pwrite@basic-exhaustion.html
> > - shard-apl: NOTRUN -> [WARN][23] ([i915#2658])
> > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl8/igt@gem_pwrite@basic-exhaustion.html
> >
> > * igt@gem_pxp@regular-baseline-src-copy-readible:
> > - shard-tglb: NOTRUN -> [SKIP][24] ([i915#4270])
> > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@gem_pxp@regular-baseline-src-copy-readible.html
> >
> > * igt@gem_userptr_blits@dmabuf-sync:
> > - shard-tglb: NOTRUN -> [SKIP][25] ([i915#3323])
> > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb5/igt@gem_userptr_blits@dmabuf-sync.html
> >
> > * igt@gem_userptr_blits@input-checking:
> > - shard-apl: NOTRUN -> [DMESG-WARN][26] ([i915#3002])
> > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl1/igt@gem_userptr_blits@input-checking.html
> >
> > * igt@gem_userptr_blits@vma-merge:
> > - shard-tglb: NOTRUN -> [FAIL][27] ([i915#3318])
> > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@gem_userptr_blits@vma-merge.html
> >
> > * igt@gen9_exec_parse@bb-start-cmd:
> > - shard-tglb: NOTRUN -> [SKIP][28] ([i915#2527] / [i915#2856]) +1 similar issue
> > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@gen9_exec_parse@bb-start-cmd.html
> >
> > * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
> > - shard-tglb: NOTRUN -> [SKIP][29] ([fdo#111644] / [i915#1397] / [i915#2411])
> > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
> >
> > * igt@kms_async_flips@alternate-sync-async-flip:
> > - shard-skl: [PASS][30] -> [FAIL][31] ([i915#2521])
> > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip.html
> > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
> >
> > * igt@kms_async_flips@crc:
> > - shard-skl: NOTRUN -> [FAIL][32] ([i915#4272])
> > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_async_flips@crc.html
> >
> > * igt@kms_big_fb@linear-32bpp-rotate-0:
> > - shard-glk: [PASS][33] -> [DMESG-WARN][34] ([i915#118])
> > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-0.html
> > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk7/igt@kms_big_fb@linear-32bpp-rotate-0.html
> >
> > * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
> > - shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777])
> > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
> >
> > * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
> > - shard-skl: NOTRUN -> [FAIL][36] ([i915#3743])
> > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
> >
> > * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
> > - shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3777])
> > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
> >
> > * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
> > - shard-tglb: NOTRUN -> [SKIP][38] ([fdo#111614])
> > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
> >
> > * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
> > - shard-skl: NOTRUN -> [FAIL][39] ([i915#3763])
> > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
> >
> > * igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
> > - shard-tglb: NOTRUN -> [SKIP][40] ([fdo#111615]) +1 similar issue
> > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
> >
> > * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs:
> > - shard-tglb: NOTRUN -> [SKIP][41] ([i915#3689]) +2 similar issues
> > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs.html
> >
> > * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
> > - shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3886]) +7 similar issues
> > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
> >
> > * igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs:
> > - shard-tglb: NOTRUN -> [SKIP][43] ([fdo#111615] / [i915#3689]) +2 similar issues
> > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs.html
> >
> > * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
> > - shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3886]) +2 similar issues
> > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
> >
> > * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
> > - shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +3 similar issues
> > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl8/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
> >
> > * igt@kms_chamelium@hdmi-crc-fast:
> > - shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +8 similar issues
> > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl8/igt@kms_chamelium@hdmi-crc-fast.html
> >
> > * igt@kms_chamelium@hdmi-hpd-storm:
> > - shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +5 similar issues
> > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl7/igt@kms_chamelium@hdmi-hpd-storm.html
> >
> > * igt@kms_chamelium@hdmi-mode-timings:
> > - shard-snb: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +2 similar issues
> > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-snb5/igt@kms_chamelium@hdmi-mode-timings.html
> >
> > * igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
> > - shard-tglb: NOTRUN -> [SKIP][49] ([fdo#109284] / [fdo#111827]) +3 similar issues
> > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb5/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
> > - shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +6 similar issues
> > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl10/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
> >
> > * igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding:
> > - shard-tglb: NOTRUN -> [SKIP][51] ([i915#3359]) +4 similar issues
> > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
> >
> > * igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen:
> > - shard-tglb: NOTRUN -> [SKIP][52] ([i915#3319]) +1 similar issue
> > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-32x32-onscreen.html
> >
> > * igt@kms_cursor_crc@pipe-d-cursor-512x170-sliding:
> > - shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109279] / [i915#3359]) +1 similar issue
> > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-512x170-sliding.html
> >
> > * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
> > - shard-iclb: [PASS][54] -> [FAIL][55] ([i915#2346])
> > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb8/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
> > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
> >
> > * igt@kms_fbcon_fbt@fbc-suspend:
> > - shard-kbl: [PASS][56] -> [INCOMPLETE][57] ([i915#636])
> > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
> > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
> >
> > * igt@kms_flip@2x-dpms-vs-vblank-race:
> > - shard-tglb: NOTRUN -> [SKIP][58] ([fdo#109274] / [fdo#111825]) +3 similar issues
> > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_flip@2x-dpms-vs-vblank-race.html
> >
> > * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
> > - shard-apl: [PASS][59] -> [DMESG-WARN][60] ([i915#180]) +3 similar issues
> > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
> > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
> >
> > * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
> > - shard-iclb: [PASS][61] -> [SKIP][62] ([i915#3701])
> > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
> > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
> >
> > * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
> > - shard-tglb: NOTRUN -> [SKIP][63] ([fdo#109280] / [fdo#111825]) +12 similar issues
> > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html
> >
> > * igt@kms_frontbuffer_tracking@fbc-suspend:
> > - shard-apl: NOTRUN -> [DMESG-WARN][64] ([i915#180])
> > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl8/igt@kms_frontbuffer_tracking@fbc-suspend.html
> >
> > * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
> > - shard-skl: NOTRUN -> [SKIP][65] ([fdo#109271]) +113 similar issues
> > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
> >
> > * igt@kms_frontbuffer_tracking@psr-suspend:
> > - shard-tglb: [PASS][66] -> [DMESG-WARN][67] ([i915#2411] / [i915#2867])
> > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-tglb2/igt@kms_frontbuffer_tracking@psr-suspend.html
> > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb2/igt@kms_frontbuffer_tracking@psr-suspend.html
> >
> > * igt@kms_hdr@bpc-switch:
> > - shard-skl: [PASS][68] -> [FAIL][69] ([i915#1188])
> > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl2/igt@kms_hdr@bpc-switch.html
> > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl1/igt@kms_hdr@bpc-switch.html
> >
> > * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
> > - shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#533])
> > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
> >
> > * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
> > - shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#533])
> > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
> >
> > * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
> > - shard-apl: NOTRUN -> [FAIL][72] ([fdo#108145] / [i915#265]) +1 similar issue
> > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
> >
> > * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
> > - shard-skl: [PASS][73] -> [FAIL][74] ([fdo#108145] / [i915#265])
> > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
> > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
> >
> > * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
> > - shard-kbl: NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265]) +2 similar issues
> > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
> >
> > * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
> > - shard-apl: NOTRUN -> [FAIL][76] ([i915#265])
> > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
> >
> > * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
> > - shard-skl: NOTRUN -> [FAIL][77] ([fdo#108145] / [i915#265])
> > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
> >
> > * igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
> > - shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271]) +50 similar issues
> > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl4/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html
> >
> > * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
> > - shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2733])
> > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
> >
> > * igt@kms_psr2_su@frontbuffer-xrgb8888:
> > - shard-tglb: NOTRUN -> [SKIP][80] ([i915#1911])
> > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
> >
> > * igt@kms_psr@psr2_suspend:
> > - shard-iclb: [PASS][81] -> [SKIP][82] ([fdo#109441]) +4 similar issues
> > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb2/igt@kms_psr@psr2_suspend.html
> > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb6/igt@kms_psr@psr2_suspend.html
> >
> > * igt@kms_setmode@basic:
> > - shard-apl: [PASS][83] -> [FAIL][84] ([i915#31])
> > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl4/igt@kms_setmode@basic.html
> > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl1/igt@kms_setmode@basic.html
> > - shard-glk: [PASS][85] -> [FAIL][86] ([i915#31])
> > [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk7/igt@kms_setmode@basic.html
> > [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk4/igt@kms_setmode@basic.html
> >
> > * igt@kms_sysfs_edid_timing:
> > - shard-kbl: NOTRUN -> [FAIL][87] ([IGT#2])
> > [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl7/igt@kms_sysfs_edid_timing.html
> >
> > * igt@kms_vblank@pipe-a-accuracy-idle:
> > - shard-skl: NOTRUN -> [FAIL][88] ([i915#43])
> > [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@kms_vblank@pipe-a-accuracy-idle.html
> >
> > * igt@kms_writeback@writeback-check-output:
> > - shard-apl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2437]) +1 similar issue
> > [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl2/igt@kms_writeback@writeback-check-output.html
> >
> > * igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
> > - shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271]) +109 similar issues
> > [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl3/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
> >
> > * igt@perf@polling-parameterized:
> > - shard-skl: NOTRUN -> [FAIL][91] ([i915#1542])
> > [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl7/igt@perf@polling-parameterized.html
> >
> > * igt@prime_nv_api@i915_nv_import_vs_close:
> > - shard-tglb: NOTRUN -> [SKIP][92] ([fdo#109291]) +1 similar issue
> > [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb8/igt@prime_nv_api@i915_nv_import_vs_close.html
> >
> > * igt@sysfs_clients@fair-0:
> > - shard-kbl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#2994])
> > [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl6/igt@sysfs_clients@fair-0.html
> >
> > * igt@sysfs_clients@split-25:
> > - shard-skl: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#2994]) +1 similar issue
> > [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl3/igt@sysfs_clients@split-25.html
> >
> >
> > #### Possible fixes ####
> >
> > * igt@feature_discovery@psr2:
> > - shard-iclb: [SKIP][95] ([i915#658]) -> [PASS][96]
> > [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb7/igt@feature_discovery@psr2.html
> > [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb2/igt@feature_discovery@psr2.html
> >
> > * igt@gem_exec_fair@basic-deadline:
> > - shard-glk: [FAIL][97] ([i915#2846]) -> [PASS][98]
> > [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk5/igt@gem_exec_fair@basic-deadline.html
> > [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk5/igt@gem_exec_fair@basic-deadline.html
> >
> > * igt@gem_exec_fair@basic-none@vcs0:
> > - shard-glk: [FAIL][99] ([i915#2842]) -> [PASS][100] +1 similar issue
> > [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk2/igt@gem_exec_fair@basic-none@vcs0.html
> > [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk4/igt@gem_exec_fair@basic-none@vcs0.html
> >
> > * igt@gem_exec_parallel@engines@basic:
> > - shard-glk: [DMESG-WARN][101] ([i915#118]) -> [PASS][102] +1 similar issue
> > [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-glk7/igt@gem_exec_parallel@engines@basic.html
> > [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-glk7/igt@gem_exec_parallel@engines@basic.html
> >
> > * igt@gem_huc_copy@huc-copy:
> > - shard-tglb: [SKIP][103] ([i915#2190]) -> [PASS][104]
> > [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-tglb7/igt@gem_huc_copy@huc-copy.html
> > [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-tglb3/igt@gem_huc_copy@huc-copy.html
> >
> > * igt@gem_workarounds@reset-context:
> > - shard-snb: [TIMEOUT][105] -> [PASS][106]
> > [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-snb2/igt@gem_workarounds@reset-context.html
> > [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-snb2/igt@gem_workarounds@reset-context.html
> >
> > * igt@i915_selftest@live@hangcheck:
> > - shard-snb: [INCOMPLETE][107] ([i915#3921]) -> [PASS][108]
> > [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-snb7/igt@i915_selftest@live@hangcheck.html
> > [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-snb5/igt@i915_selftest@live@hangcheck.html
> >
> > * igt@kms_cursor_crc@pipe-a-cursor-suspend:
> > - shard-kbl: [DMESG-WARN][109] ([i915#180]) -> [PASS][110] +4 similar issues
> > [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> > [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> >
> > * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
> > - shard-skl: [FAIL][111] ([i915#2346]) -> [PASS][112] +1 similar issue
> > [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
> > [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
> >
> > * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
> > - shard-skl: [FAIL][113] ([i915#2122]) -> [PASS][114]
> > [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
> > [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
> >
> > * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
> > - shard-skl: [FAIL][115] ([i915#79]) -> [PASS][116]
> > [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
> > [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
> >
> > * igt@kms_hdr@bpc-switch-dpms:
> > - shard-skl: [FAIL][117] ([i915#1188]) -> [PASS][118]
> > [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
> > [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
> >
> > * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
> > - shard-apl: [DMESG-WARN][119] ([i915#180]) -> [PASS][120] +3 similar issues
> > [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
> > [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
> >
> > * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
> > - shard-skl: [FAIL][121] ([fdo#108145] / [i915#265]) -> [PASS][122]
> > [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
> > [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
> >
> > * igt@kms_psr@psr2_cursor_blt:
> > - shard-iclb: [SKIP][123] ([fdo#109441]) -> [PASS][124] +2 similar issues
> > [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html
> > [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
> >
> > * igt@perf@polling-small-buf:
> > - shard-skl: [FAIL][125] ([i915#1722]) -> [PASS][126]
> > [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-skl4/igt@perf@polling-small-buf.html
> > [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-skl8/igt@perf@polling-small-buf.html
> >
> >
> > #### Warnings ####
> >
> > * igt@gem_exec_fair@basic-none-rrul@rcs0:
> > - shard-iclb: [FAIL][127] ([i915#2852]) -> [FAIL][128] ([i915#2842])
> > [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
> > [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
> >
> > * igt@i915_pm_rc6_residency@rc6-fence:
> > - shard-iclb: [WARN][129] ([i915#2684]) -> [WARN][130] ([i915#1804] / [i915#2684])
> > [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html
> > [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
> >
> > * igt@i915_pm_rc6_residency@rc6-idle:
> > - shard-iclb: [WARN][131] ([i915#1804] / [i915#2684]) -> [FAIL][132] ([i915#2680])
> > [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
> > [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
> >
> > * igt@runner@aborted:
> > - shard-kbl: ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#4312]) -> ([FAIL][139], [FAIL][140]) ([i915#3002] / [i915#4312])
> > [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl6/igt@runner@aborted.html
> > [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@runner@aborted.html
> > [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@runner@aborted.html
> > [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl1/igt@runner@aborted.html
> > [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@runner@aborted.html
> > [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-kbl7/igt@runner@aborted.html
> > [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl1/igt@runner@aborted.html
> > [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/shard-kbl4/igt@runner@aborted.html
> > - shard-apl: ([FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#4312]) -> ([FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312])
> > [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl6/igt@runner@aborted.html
> > [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11061/shard-apl3/igt@runner@aborted.html
> > [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_
> >
> > == Logs ==
> >
> > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21961/index.html
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
` (14 preceding siblings ...)
2022-01-11 10:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-01-12 21:41 ` Rodrigo Vivi
2022-01-13 16:58 ` Jani Nikula
15 siblings, 1 reply; 29+ messages in thread
From: Rodrigo Vivi @ 2022-01-12 21:41 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, Lucas De Marchi
On Mon, Jan 10, 2022 at 09:15:49PM -0800, Matt Roper wrote:
> Let's start splitting up and cleaning up parts of i915_reg.h. Rather
> than starting with dead code removal as we did in v1, this time we'll
> switch a few macros to parameterized style, and then move a few types of
> registers (engine registers, SNPS PHY registers) off to their own header
> files.
>
> v3:
> - Split out i915_reg_defs.h in its own patch
> - Also split out combo PHY and MG/DKL PHY sets of registers
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Matt Roper (11):
> drm/i915: Use parameterized GPR register definitions everywhere
> drm/i915: Parameterize PWRCTX_MAXCNT
> drm/i915: Parameterize ECOSKPD
> drm/i915: Use RING_PSMI_CTL rather than per-engine macros
> drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7
> drm/i915: Introduce i915_reg_defs.h
> drm/i915/gt: Move engine registers to their own header
> drm/i915: Move SNPS PHY registers to their own header
> drm/i915: Move combo PHY registers to their own header
> drm/i915: Move TC PHY registers to their own header
> drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets
>
> drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
> .../gpu/drm/i915/display/intel_combo_phy.c | 1 +
> .../drm/i915/display/intel_combo_phy_regs.h | 162 ++++
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
> .../drm/i915/display/intel_display_power.c | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 1 +
> .../drm/i915/display/intel_snps_phy_regs.h | 75 ++
> drivers/gpu/drm/i915/display/intel_tc.c | 1 +
> .../gpu/drm/i915/display/intel_tc_phy_regs.h | 280 ++++++
> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 1 +
> drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 1 +
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 +
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
> drivers/gpu/drm/i915/gt/intel_engine_regs.h | 197 ++++
> .../drm/i915/gt/intel_execlists_submission.c | 1 +
> drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 15 -
> drivers/gpu/drm/i915/gt/intel_rc6.c | 9 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 1 +
> drivers/gpu/drm/i915/gt/intel_ring.c | 1 +
> .../gpu/drm/i915/gt/intel_ring_submission.c | 11 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +-
> drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 1 +
> drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
> drivers/gpu/drm/i915/gt/selftest_rps.c | 1 +
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 1 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +-
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
> drivers/gpu/drm/i915/gvt/handlers.c | 4 +-
> drivers/gpu/drm/i915/gvt/mmio_context.c | 5 +-
> drivers/gpu/drm/i915/gvt/mmio_context.h | 1 +
> drivers/gpu/drm/i915/i915_cmd_parser.c | 69 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
> drivers/gpu/drm/i915/i915_perf.c | 1 +
> drivers/gpu/drm/i915/i915_pmu.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 841 +-----------------
> drivers/gpu/drm/i915/i915_reg_defs.h | 98 ++
> drivers/gpu/drm/i915/i915_request.c | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 11 +-
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 44 files changed, 911 insertions(+), 907 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
> create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
> create mode 100644 drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
> create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_regs.h
> create mode 100644 drivers/gpu/drm/i915/i915_reg_defs.h
I understand that I'm late to the fun here, but I got myself wondering if
we couldn't separated the registers in a "regs" directory
and find some way to organize them in IP blocks matching the hw...
mainly thinking about 2 cases:
1. searching for registers usages...
2. the idea of having some sort of auto generation from spec...
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions
2022-01-12 21:41 ` [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Rodrigo Vivi
@ 2022-01-13 16:58 ` Jani Nikula
2022-01-13 20:23 ` Rodrigo Vivi
0 siblings, 1 reply; 29+ messages in thread
From: Jani Nikula @ 2022-01-13 16:58 UTC (permalink / raw)
To: Rodrigo Vivi, Matt Roper; +Cc: intel-gfx, Lucas De Marchi
On Wed, 12 Jan 2022, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> I understand that I'm late to the fun here, but I got myself wondering if
> we couldn't separated the registers in a "regs" directory
> and find some way to organize them in IP blocks matching the hw...
>
> mainly thinking about 2 cases:
>
> 1. searching for registers usages...
> 2. the idea of having some sort of auto generation from spec...
At least to me it's more important to split these between display and
gt, and I'd prefer not to have them in the same directory.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions
2022-01-13 16:58 ` Jani Nikula
@ 2022-01-13 20:23 ` Rodrigo Vivi
0 siblings, 0 replies; 29+ messages in thread
From: Rodrigo Vivi @ 2022-01-13 20:23 UTC (permalink / raw)
To: Jani Nikula; +Cc: Lucas De Marchi, intel-gfx
On Thu, Jan 13, 2022 at 06:58:47PM +0200, Jani Nikula wrote:
> On Wed, 12 Jan 2022, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > I understand that I'm late to the fun here, but I got myself wondering if
> > we couldn't separated the registers in a "regs" directory
> > and find some way to organize them in IP blocks matching the hw...
> >
> > mainly thinking about 2 cases:
> >
> > 1. searching for registers usages...
> > 2. the idea of having some sort of auto generation from spec...
>
> At least to me it's more important to split these between display and
> gt, and I'd prefer not to have them in the same directory.
yeap, it makes sense...
>
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 29+ messages in thread