Re: net: phy: marvell: network working with generic PHY and not with marvell PHY

From: Andrew Lunn <andrew@lunn.ch>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: Corentin Labbe <clabbe.montjoie@gmail.com>,
	linus.walleij@linaro.org, ulli.kroll@googlemail.com,
	kuba@kernel.org, davem@davemloft.net, hkallweit1@gmail.com,
	linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: net: phy: marvell: network working with generic PHY and not with marvell PHY
Date: Tue, 4 Jan 2022 16:02:45 +0100	[thread overview]
Message-ID: <YdRhlUR4ukwS5WMH@lunn.ch> (raw)
In-Reply-To: <YdRgXbpK6CFB/eCU@shell.armlinux.org.uk>

> > #define MII_88E1121_PHY_MSCR_RX_DELAY	BIT(5)
> > #define MII_88E1121_PHY_MSCR_TX_DELAY	BIT(4)
> > #define MII_88E1121_PHY_MSCR_DELAY_MASK	(BIT(5) | BIT(4))
> > 
> > Bits 6 is the MSB of the default MAC speed.
> > Bit 13 is the LSB of the default MAC speed. These two should default to 10b = 1000Mbps
> > Bit 12 is reserved, and should be written 1.
> 
> Hmm, seems odd that these speed bits match BMCR, and I'm not sure why
> the default MAC speed would have any bearing on whether gigabit mode
> is enabled. If they default to 10b, then the write should have no effect
> unless boot firmware has changed them.

There is a bit more, which is did not copy:

    Also, used for setting speed of MAC interface during MAC side
    loop-back. Requires that customer set both these bits and force
    speed using register 0 to the same speed.  MAC Interface Speed
    during Link down.

So i don't think they matter during normal operation.

   Andrew