* [PATCH V3 2/2] rtc: zynqmp: Add calibration set and get support
@ 2021-11-30 5:55 ` Srinivas Neeli
0 siblings, 0 replies; 12+ messages in thread
From: Srinivas Neeli @ 2021-11-30 5:55 UTC (permalink / raw)
To: a.zummo, alexandre.belloni, michal.simek, sgoud, shubhraj, radheys
Cc: linux-rtc, linux-arm-kernel, linux-kernel, git, Srinivas Neeli
Zynqmp RTC controller has a calibration feature to compensate
time deviation due to input clock inaccuracy.
Set and get calibration API's are used for setting and getting
calibration value from the controller calibration register.
Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com>
---
Changes in V3:
-Calculated tick_mult using crystal frequency.
-Calibration register updating based on crystal frequency in probe.
-Supressed MIN an MAX calibration values,Will send separate patch in future.
Changes in V2:
-Removed unused macro.
-Updated code with review comments.
---
drivers/rtc/rtc-zynqmp.c | 104 +++++++++++++++++++++++++++++++--------
1 file changed, 84 insertions(+), 20 deletions(-)
diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c
index f440bb52be92..eb6ee55ca725 100644
--- a/drivers/rtc/rtc-zynqmp.c
+++ b/drivers/rtc/rtc-zynqmp.c
@@ -6,6 +6,7 @@
*
*/
+#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
@@ -36,17 +37,21 @@
#define RTC_OSC_EN BIT(24)
#define RTC_BATT_EN BIT(31)
-#define RTC_CALIB_DEF 0x198233
+#define RTC_CALIB_DEF 0x8000
#define RTC_CALIB_MASK 0x1FFFFF
#define RTC_ALRM_MASK BIT(1)
#define RTC_MSEC 1000
+#define RTC_FR_MASK 0xF0000
+#define RTC_FR_MAX_TICKS 16
+#define RTC_PPB 1000000000LL
struct xlnx_rtc_dev {
struct rtc_device *rtc;
void __iomem *reg_base;
int alarm_irq;
int sec_irq;
- unsigned int calibval;
+ struct clk *rtc_clk;
+ unsigned int freq;
};
static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
@@ -61,13 +66,6 @@ static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
*/
new_time = rtc_tm_to_time64(tm) + 1;
- /*
- * Writing into calibration register will clear the Tick Counter and
- * force the next second to be signaled exactly in 1 second period
- */
- xrtcdev->calibval &= RTC_CALIB_MASK;
- writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
-
writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
/*
@@ -173,15 +171,71 @@ static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
rtc_ctrl |= RTC_BATT_EN;
writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
+}
- /*
- * Based on crystal freq of 33.330 KHz
- * set the seconds counter and enable, set fractions counter
- * to default value suggested as per design spec
- * to correct RTC delay in frequency over period of time.
+static int xlnx_rtc_read_offset(struct device *dev, long *offset)
+{
+ struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
+ long offset_val = 0;
+ unsigned int tick_mult = RTC_PPB / xrtcdev->freq;
+ unsigned int calibval;
+
+ calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD);
+ /* Offset with seconds ticks */
+ offset_val = calibval & RTC_TICK_MASK;
+ offset_val = offset_val - RTC_CALIB_DEF;
+ offset_val = offset_val * tick_mult;
+
+ /* Offset with fractional ticks */
+ if (calibval & RTC_FR_EN)
+ offset_val += ((calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT)
+ * (tick_mult / RTC_FR_MAX_TICKS);
+ *offset = offset_val;
+
+ return 0;
+}
+
+static int xlnx_rtc_set_offset(struct device *dev, long offset)
+{
+ struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
+ short int max_tick;
+ unsigned char fract_tick = 0;
+ unsigned int calibval;
+ int fract_offset;
+ unsigned int tick_mult = RTC_PPB / xrtcdev->freq;
+
+ /* Number ticks for given offset */
+ max_tick = div_s64_rem(offset, tick_mult, &fract_offset);
+
+ /* Number fractional ticks for given offset */
+ if (fract_offset) {
+ if (fract_offset < 0) {
+ fract_offset = fract_offset + tick_mult;
+ max_tick--;
+ }
+ if (fract_offset > (tick_mult / RTC_FR_MAX_TICKS)) {
+ for (fract_tick = 1; fract_tick < 16; fract_tick++) {
+ if (fract_offset <=
+ (fract_tick *
+ (tick_mult / RTC_FR_MAX_TICKS)))
+ break;
+ }
+ }
+ }
+
+ /* Zynqmp RTC uses second and fractional tick
+ * counters for compensation
*/
- xrtcdev->calibval &= RTC_CALIB_MASK;
- writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
+ calibval = max_tick + RTC_CALIB_DEF;
+
+ if (fract_tick)
+ calibval |= RTC_FR_EN;
+
+ calibval |= (fract_tick << RTC_FR_DATSHIFT);
+
+ writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
+
+ return 0;
}
static const struct rtc_class_ops xlnx_rtc_ops = {
@@ -190,6 +244,8 @@ static const struct rtc_class_ops xlnx_rtc_ops = {
.read_alarm = xlnx_rtc_read_alarm,
.set_alarm = xlnx_rtc_set_alarm,
.alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
+ .read_offset = xlnx_rtc_read_offset,
+ .set_offset = xlnx_rtc_set_offset,
};
static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
@@ -255,10 +311,18 @@ static int xlnx_rtc_probe(struct platform_device *pdev)
return ret;
}
- ret = of_property_read_u32(pdev->dev.of_node, "calibration",
- &xrtcdev->calibval);
- if (ret)
- xrtcdev->calibval = RTC_CALIB_DEF;
+ /* Getting the rtc_clk info */
+ xrtcdev->rtc_clk = devm_clk_get_optional(&pdev->dev, "rtc_clk");
+ if (IS_ERR(xrtcdev->rtc_clk)) {
+ if (PTR_ERR(xrtcdev->rtc_clk) != -EPROBE_DEFER)
+ dev_warn(&pdev->dev, "Device clock not found.\n");
+ }
+ xrtcdev->freq = clk_get_rate(xrtcdev->rtc_clk);
+ if (!xrtcdev->freq)
+ xrtcdev->freq = RTC_CALIB_DEF;
+ ret = readl(xrtcdev->reg_base + RTC_CALIB_RD);
+ if (!ret)
+ writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR));
xlnx_init_rtc(xrtcdev);
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH V3 2/2] rtc: zynqmp: Add calibration set and get support
2021-11-30 5:55 ` Srinivas Neeli
(?)
@ 2021-11-30 9:15 ` kernel test robot
-1 siblings, 0 replies; 12+ messages in thread
From: kernel test robot @ 2021-11-30 9:15 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2652 bytes --]
Hi Srinivas,
I love your patch! Yet something to improve:
[auto build test ERROR on abelloni/rtc-next]
[also build test ERROR on v5.16-rc3 next-20211129]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Srinivas-Neeli/dt-bindings-rtc-zynqmp-Add-clock-information/20211130-135800
base: https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git rtc-next
config: i386-randconfig-a005-20211130 (https://download.01.org/0day-ci/archive/20211130/202111301703.oeV6PbAf-lkp(a)intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/41ffd7c6e4799c865a4b74130d1bf5db3cfb85f7
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Srinivas-Neeli/dt-bindings-rtc-zynqmp-Add-clock-information/20211130-135800
git checkout 41ffd7c6e4799c865a4b74130d1bf5db3cfb85f7
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
ld: drivers/rtc/rtc-zynqmp.o: in function `xlnx_rtc_read_offset':
>> drivers/rtc/rtc-zynqmp.c:180: undefined reference to `__divdi3'
ld: drivers/rtc/rtc-zynqmp.o: in function `xlnx_rtc_set_offset':
drivers/rtc/rtc-zynqmp.c:205: undefined reference to `__divdi3'
vim +180 drivers/rtc/rtc-zynqmp.c
175
176 static int xlnx_rtc_read_offset(struct device *dev, long *offset)
177 {
178 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
179 long offset_val = 0;
> 180 unsigned int tick_mult = RTC_PPB / xrtcdev->freq;
181 unsigned int calibval;
182
183 calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD);
184 /* Offset with seconds ticks */
185 offset_val = calibval & RTC_TICK_MASK;
186 offset_val = offset_val - RTC_CALIB_DEF;
187 offset_val = offset_val * tick_mult;
188
189 /* Offset with fractional ticks */
190 if (calibval & RTC_FR_EN)
191 offset_val += ((calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT)
192 * (tick_mult / RTC_FR_MAX_TICKS);
193 *offset = offset_val;
194
195 return 0;
196 }
197
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH V3 2/2] rtc: zynqmp: Add calibration set and get support
2021-11-30 5:55 ` Srinivas Neeli
(?)
(?)
@ 2021-11-30 14:52 ` kernel test robot
-1 siblings, 0 replies; 12+ messages in thread
From: kernel test robot @ 2021-11-30 14:52 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 1985 bytes --]
Hi Srinivas,
I love your patch! Yet something to improve:
[auto build test ERROR on abelloni/rtc-next]
[also build test ERROR on v5.16-rc3]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Srinivas-Neeli/dt-bindings-rtc-zynqmp-Add-clock-information/20211130-135800
base: https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git rtc-next
config: m68k-allyesconfig (https://download.01.org/0day-ci/archive/20211130/202111302250.aj9yAATQ-lkp(a)intel.com/config)
compiler: m68k-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/41ffd7c6e4799c865a4b74130d1bf5db3cfb85f7
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Srinivas-Neeli/dt-bindings-rtc-zynqmp-Add-clock-information/20211130-135800
git checkout 41ffd7c6e4799c865a4b74130d1bf5db3cfb85f7
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=m68k SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
m68k-linux-ld: drivers/rtc/rtc-zynqmp.o: in function `xlnx_rtc_read_offset':
>> rtc-zynqmp.c:(.text+0x24): undefined reference to `__divdi3'
m68k-linux-ld: drivers/rtc/rtc-zynqmp.o: in function `xlnx_rtc_set_offset':
rtc-zynqmp.c:(.text+0x224): undefined reference to `__divdi3'
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH V3 2/2] rtc: zynqmp: Add calibration set and get support
2021-11-30 5:55 ` Srinivas Neeli
@ 2022-01-04 23:48 ` Alexandre Belloni
-1 siblings, 0 replies; 12+ messages in thread
From: Alexandre Belloni @ 2022-01-04 23:48 UTC (permalink / raw)
To: Srinivas Neeli
Cc: a.zummo, michal.simek, sgoud, shubhraj, radheys, linux-rtc,
linux-arm-kernel, linux-kernel, git
On 30/11/2021 11:25:41+0530, Srinivas Neeli wrote:
> Zynqmp RTC controller has a calibration feature to compensate
> time deviation due to input clock inaccuracy.
> Set and get calibration API's are used for setting and getting
> calibration value from the controller calibration register.
>
> Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com>
> ---
> Changes in V3:
> -Calculated tick_mult using crystal frequency.
> -Calibration register updating based on crystal frequency in probe.
> -Supressed MIN an MAX calibration values,Will send separate patch in future.
I believe this should go in with this patch and it shouldn't be too
complicated to know whether the calculated value overflows the register.
> Changes in V2:
> -Removed unused macro.
> -Updated code with review comments.
> ---
> drivers/rtc/rtc-zynqmp.c | 104 +++++++++++++++++++++++++++++++--------
> 1 file changed, 84 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c
> index f440bb52be92..eb6ee55ca725 100644
> --- a/drivers/rtc/rtc-zynqmp.c
> +++ b/drivers/rtc/rtc-zynqmp.c
> @@ -6,6 +6,7 @@
> *
> */
>
> +#include <linux/clk.h>
> #include <linux/delay.h>
> #include <linux/init.h>
> #include <linux/io.h>
> @@ -36,17 +37,21 @@
> #define RTC_OSC_EN BIT(24)
> #define RTC_BATT_EN BIT(31)
>
> -#define RTC_CALIB_DEF 0x198233
> +#define RTC_CALIB_DEF 0x8000
> #define RTC_CALIB_MASK 0x1FFFFF
> #define RTC_ALRM_MASK BIT(1)
> #define RTC_MSEC 1000
> +#define RTC_FR_MASK 0xF0000
> +#define RTC_FR_MAX_TICKS 16
> +#define RTC_PPB 1000000000LL
>
> struct xlnx_rtc_dev {
> struct rtc_device *rtc;
> void __iomem *reg_base;
> int alarm_irq;
> int sec_irq;
> - unsigned int calibval;
> + struct clk *rtc_clk;
> + unsigned int freq;
> };
>
> static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
> @@ -61,13 +66,6 @@ static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
> */
> new_time = rtc_tm_to_time64(tm) + 1;
>
> - /*
> - * Writing into calibration register will clear the Tick Counter and
> - * force the next second to be signaled exactly in 1 second period
> - */
> - xrtcdev->calibval &= RTC_CALIB_MASK;
> - writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
> -
> writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
>
> /*
> @@ -173,15 +171,71 @@ static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
> rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
> rtc_ctrl |= RTC_BATT_EN;
> writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
> +}
>
> - /*
> - * Based on crystal freq of 33.330 KHz
> - * set the seconds counter and enable, set fractions counter
> - * to default value suggested as per design spec
> - * to correct RTC delay in frequency over period of time.
> +static int xlnx_rtc_read_offset(struct device *dev, long *offset)
> +{
> + struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
> + long offset_val = 0;
> + unsigned int tick_mult = RTC_PPB / xrtcdev->freq;
> + unsigned int calibval;
> +
> + calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD);
> + /* Offset with seconds ticks */
> + offset_val = calibval & RTC_TICK_MASK;
> + offset_val = offset_val - RTC_CALIB_DEF;
> + offset_val = offset_val * tick_mult;
> +
> + /* Offset with fractional ticks */
> + if (calibval & RTC_FR_EN)
> + offset_val += ((calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT)
> + * (tick_mult / RTC_FR_MAX_TICKS);
> + *offset = offset_val;
> +
> + return 0;
> +}
> +
> +static int xlnx_rtc_set_offset(struct device *dev, long offset)
> +{
> + struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
> + short int max_tick;
> + unsigned char fract_tick = 0;
> + unsigned int calibval;
> + int fract_offset;
> + unsigned int tick_mult = RTC_PPB / xrtcdev->freq;
> +
> + /* Number ticks for given offset */
> + max_tick = div_s64_rem(offset, tick_mult, &fract_offset);
> +
> + /* Number fractional ticks for given offset */
> + if (fract_offset) {
> + if (fract_offset < 0) {
> + fract_offset = fract_offset + tick_mult;
> + max_tick--;
> + }
> + if (fract_offset > (tick_mult / RTC_FR_MAX_TICKS)) {
> + for (fract_tick = 1; fract_tick < 16; fract_tick++) {
> + if (fract_offset <=
> + (fract_tick *
> + (tick_mult / RTC_FR_MAX_TICKS)))
> + break;
> + }
> + }
> + }
> +
> + /* Zynqmp RTC uses second and fractional tick
> + * counters for compensation
> */
> - xrtcdev->calibval &= RTC_CALIB_MASK;
> - writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
> + calibval = max_tick + RTC_CALIB_DEF;
> +
> + if (fract_tick)
> + calibval |= RTC_FR_EN;
> +
> + calibval |= (fract_tick << RTC_FR_DATSHIFT);
> +
> + writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
> +
> + return 0;
> }
>
> static const struct rtc_class_ops xlnx_rtc_ops = {
> @@ -190,6 +244,8 @@ static const struct rtc_class_ops xlnx_rtc_ops = {
> .read_alarm = xlnx_rtc_read_alarm,
> .set_alarm = xlnx_rtc_set_alarm,
> .alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
> + .read_offset = xlnx_rtc_read_offset,
> + .set_offset = xlnx_rtc_set_offset,
> };
>
> static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
> @@ -255,10 +311,18 @@ static int xlnx_rtc_probe(struct platform_device *pdev)
> return ret;
> }
>
> - ret = of_property_read_u32(pdev->dev.of_node, "calibration",
> - &xrtcdev->calibval);
> - if (ret)
> - xrtcdev->calibval = RTC_CALIB_DEF;
> + /* Getting the rtc_clk info */
> + xrtcdev->rtc_clk = devm_clk_get_optional(&pdev->dev, "rtc_clk");
> + if (IS_ERR(xrtcdev->rtc_clk)) {
> + if (PTR_ERR(xrtcdev->rtc_clk) != -EPROBE_DEFER)
> + dev_warn(&pdev->dev, "Device clock not found.\n");
> + }
> + xrtcdev->freq = clk_get_rate(xrtcdev->rtc_clk);
> + if (!xrtcdev->freq)
> + xrtcdev->freq = RTC_CALIB_DEF;
Because you changed the value of RTC_CALIB_DEF, I think this breaks
existing DTs.
> + ret = readl(xrtcdev->reg_base + RTC_CALIB_RD);
> + if (!ret)
> + writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR));
>
> xlnx_init_rtc(xrtcdev);
>
> --
> 2.17.1
>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH V3 2/2] rtc: zynqmp: Add calibration set and get support
@ 2022-01-04 23:48 ` Alexandre Belloni
0 siblings, 0 replies; 12+ messages in thread
From: Alexandre Belloni @ 2022-01-04 23:48 UTC (permalink / raw)
To: Srinivas Neeli
Cc: a.zummo, michal.simek, sgoud, shubhraj, radheys, linux-rtc,
linux-arm-kernel, linux-kernel, git
On 30/11/2021 11:25:41+0530, Srinivas Neeli wrote:
> Zynqmp RTC controller has a calibration feature to compensate
> time deviation due to input clock inaccuracy.
> Set and get calibration API's are used for setting and getting
> calibration value from the controller calibration register.
>
> Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com>
> ---
> Changes in V3:
> -Calculated tick_mult using crystal frequency.
> -Calibration register updating based on crystal frequency in probe.
> -Supressed MIN an MAX calibration values,Will send separate patch in future.
I believe this should go in with this patch and it shouldn't be too
complicated to know whether the calculated value overflows the register.
> Changes in V2:
> -Removed unused macro.
> -Updated code with review comments.
> ---
> drivers/rtc/rtc-zynqmp.c | 104 +++++++++++++++++++++++++++++++--------
> 1 file changed, 84 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/rtc/rtc-zynqmp.c b/drivers/rtc/rtc-zynqmp.c
> index f440bb52be92..eb6ee55ca725 100644
> --- a/drivers/rtc/rtc-zynqmp.c
> +++ b/drivers/rtc/rtc-zynqmp.c
> @@ -6,6 +6,7 @@
> *
> */
>
> +#include <linux/clk.h>
> #include <linux/delay.h>
> #include <linux/init.h>
> #include <linux/io.h>
> @@ -36,17 +37,21 @@
> #define RTC_OSC_EN BIT(24)
> #define RTC_BATT_EN BIT(31)
>
> -#define RTC_CALIB_DEF 0x198233
> +#define RTC_CALIB_DEF 0x8000
> #define RTC_CALIB_MASK 0x1FFFFF
> #define RTC_ALRM_MASK BIT(1)
> #define RTC_MSEC 1000
> +#define RTC_FR_MASK 0xF0000
> +#define RTC_FR_MAX_TICKS 16
> +#define RTC_PPB 1000000000LL
>
> struct xlnx_rtc_dev {
> struct rtc_device *rtc;
> void __iomem *reg_base;
> int alarm_irq;
> int sec_irq;
> - unsigned int calibval;
> + struct clk *rtc_clk;
> + unsigned int freq;
> };
>
> static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
> @@ -61,13 +66,6 @@ static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
> */
> new_time = rtc_tm_to_time64(tm) + 1;
>
> - /*
> - * Writing into calibration register will clear the Tick Counter and
> - * force the next second to be signaled exactly in 1 second period
> - */
> - xrtcdev->calibval &= RTC_CALIB_MASK;
> - writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
> -
> writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
>
> /*
> @@ -173,15 +171,71 @@ static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
> rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
> rtc_ctrl |= RTC_BATT_EN;
> writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
> +}
>
> - /*
> - * Based on crystal freq of 33.330 KHz
> - * set the seconds counter and enable, set fractions counter
> - * to default value suggested as per design spec
> - * to correct RTC delay in frequency over period of time.
> +static int xlnx_rtc_read_offset(struct device *dev, long *offset)
> +{
> + struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
> + long offset_val = 0;
> + unsigned int tick_mult = RTC_PPB / xrtcdev->freq;
> + unsigned int calibval;
> +
> + calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD);
> + /* Offset with seconds ticks */
> + offset_val = calibval & RTC_TICK_MASK;
> + offset_val = offset_val - RTC_CALIB_DEF;
> + offset_val = offset_val * tick_mult;
> +
> + /* Offset with fractional ticks */
> + if (calibval & RTC_FR_EN)
> + offset_val += ((calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT)
> + * (tick_mult / RTC_FR_MAX_TICKS);
> + *offset = offset_val;
> +
> + return 0;
> +}
> +
> +static int xlnx_rtc_set_offset(struct device *dev, long offset)
> +{
> + struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
> + short int max_tick;
> + unsigned char fract_tick = 0;
> + unsigned int calibval;
> + int fract_offset;
> + unsigned int tick_mult = RTC_PPB / xrtcdev->freq;
> +
> + /* Number ticks for given offset */
> + max_tick = div_s64_rem(offset, tick_mult, &fract_offset);
> +
> + /* Number fractional ticks for given offset */
> + if (fract_offset) {
> + if (fract_offset < 0) {
> + fract_offset = fract_offset + tick_mult;
> + max_tick--;
> + }
> + if (fract_offset > (tick_mult / RTC_FR_MAX_TICKS)) {
> + for (fract_tick = 1; fract_tick < 16; fract_tick++) {
> + if (fract_offset <=
> + (fract_tick *
> + (tick_mult / RTC_FR_MAX_TICKS)))
> + break;
> + }
> + }
> + }
> +
> + /* Zynqmp RTC uses second and fractional tick
> + * counters for compensation
> */
> - xrtcdev->calibval &= RTC_CALIB_MASK;
> - writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
> + calibval = max_tick + RTC_CALIB_DEF;
> +
> + if (fract_tick)
> + calibval |= RTC_FR_EN;
> +
> + calibval |= (fract_tick << RTC_FR_DATSHIFT);
> +
> + writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
> +
> + return 0;
> }
>
> static const struct rtc_class_ops xlnx_rtc_ops = {
> @@ -190,6 +244,8 @@ static const struct rtc_class_ops xlnx_rtc_ops = {
> .read_alarm = xlnx_rtc_read_alarm,
> .set_alarm = xlnx_rtc_set_alarm,
> .alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
> + .read_offset = xlnx_rtc_read_offset,
> + .set_offset = xlnx_rtc_set_offset,
> };
>
> static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
> @@ -255,10 +311,18 @@ static int xlnx_rtc_probe(struct platform_device *pdev)
> return ret;
> }
>
> - ret = of_property_read_u32(pdev->dev.of_node, "calibration",
> - &xrtcdev->calibval);
> - if (ret)
> - xrtcdev->calibval = RTC_CALIB_DEF;
> + /* Getting the rtc_clk info */
> + xrtcdev->rtc_clk = devm_clk_get_optional(&pdev->dev, "rtc_clk");
> + if (IS_ERR(xrtcdev->rtc_clk)) {
> + if (PTR_ERR(xrtcdev->rtc_clk) != -EPROBE_DEFER)
> + dev_warn(&pdev->dev, "Device clock not found.\n");
> + }
> + xrtcdev->freq = clk_get_rate(xrtcdev->rtc_clk);
> + if (!xrtcdev->freq)
> + xrtcdev->freq = RTC_CALIB_DEF;
Because you changed the value of RTC_CALIB_DEF, I think this breaks
existing DTs.
> + ret = readl(xrtcdev->reg_base + RTC_CALIB_RD);
> + if (!ret)
> + writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR));
>
> xlnx_init_rtc(xrtcdev);
>
> --
> 2.17.1
>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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