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* [PATCH] crypto: octeontx2: CN10K CPT to RNM workaround
@ 2022-01-25 18:26 Shijith Thotton
  2022-01-25 18:26 ` [PATCH] crypto: octeontx2: disable DMA black hole on an DMA fault Shijith Thotton
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Shijith Thotton @ 2022-01-25 18:26 UTC (permalink / raw)
  To: Arnaud Ebalard, Herbert Xu, Boris Brezillon
  Cc: Srujana Challa, linux-crypto, jerinj, sgoutham, Shijith Thotton,
	David S. Miller, Dan Carpenter, Jiapeng Chong, open list

From: Srujana Challa <schalla@marvell.com>

When software sets CPT_AF_CTL[RNM_REQ_EN]=1 and RNM in not producing
entropy(i.e., RNM_ENTROPY_STATUS[NORMAL_CNT] < 0x40), the first cycle of
the response may be lost due to a conditional clocking issue. Due to
this, the subsequent random number stream will be corrupted. So, this
patch adds support to ensure RNM_ENTROPY_STATUS[NORMAL_CNT] = 0x40
before writing CPT_AF_CTL[RNM_REQ_EN] = 1, as a workaround.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
---
 .../marvell/octeontx2/otx2_cptpf_ucode.c      | 43 ++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
index 4c8ebdf671ca..addc760501a9 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
@@ -1076,6 +1076,39 @@ static void delete_engine_grps(struct pci_dev *pdev,
 		delete_engine_group(&pdev->dev, &eng_grps->grp[i]);
 }
 
+#define PCI_DEVID_CN10K_RNM 0xA098
+#define RNM_ENTROPY_STATUS  0x8
+
+static void rnm_to_cpt_errata_fixup(struct device *dev)
+{
+	struct pci_dev *pdev;
+	void __iomem *base;
+	int timeout = 5000;
+
+	pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RNM, NULL);
+	if (!pdev)
+		return;
+
+	base = pci_ioremap_bar(pdev, 0);
+	if (!base)
+		goto put_pdev;
+
+	while ((readq(base + RNM_ENTROPY_STATUS) & 0x7F) != 0x40) {
+		cpu_relax();
+		udelay(1);
+		timeout--;
+		if (!timeout) {
+			dev_warn(dev, "RNM is not producing entropy\n");
+			break;
+		}
+	}
+
+	iounmap(base);
+
+put_pdev:
+	pci_dev_put(pdev);
+}
+
 int otx2_cpt_get_eng_grp(struct otx2_cpt_eng_grps *eng_grps, int eng_type)
 {
 
@@ -1189,9 +1222,17 @@ int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf,
 
 	if (is_dev_otx2(pdev))
 		goto unlock;
+
+	/*
+	 * Ensure RNM_ENTROPY_STATUS[NORMAL_CNT] = 0x40 before writing
+	 * CPT_AF_CTL[RNM_REQ_EN] = 1 as a workaround for HW errata.
+	 */
+	rnm_to_cpt_errata_fixup(&pdev->dev);
+
 	/*
 	 * Configure engine group mask to allow context prefetching
-	 * for the groups.
+	 * for the groups and enable random number request, to enable
+	 * CPT to request random numbers from RNM.
 	 */
 	otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL,
 			      OTX2_CPT_ALL_ENG_GRPS_MASK << 3 | BIT_ULL(16),
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH] crypto: octeontx2: disable DMA black hole on an DMA fault
  2022-01-25 18:26 [PATCH] crypto: octeontx2: CN10K CPT to RNM workaround Shijith Thotton
@ 2022-01-25 18:26 ` Shijith Thotton
  2022-02-05  4:30   ` Herbert Xu
  2022-01-25 18:26 ` [PATCH] crypto: octeontx2: increase CPT HW instruction queue length Shijith Thotton
  2022-02-05  4:30 ` [PATCH] crypto: octeontx2: CN10K CPT to RNM workaround Herbert Xu
  2 siblings, 1 reply; 6+ messages in thread
From: Shijith Thotton @ 2022-01-25 18:26 UTC (permalink / raw)
  To: Arnaud Ebalard, Herbert Xu, Boris Brezillon
  Cc: Srujana Challa, linux-crypto, jerinj, sgoutham, Shijith Thotton,
	David S. Miller, Linu Cherian, Geetha sowjanya, hariprasad,
	Subbaraya Sundeep, Jakub Kicinski, Dan Carpenter, Jiapeng Chong,
	open list, open list:MARVELL OCTEONTX2 RVU ADMIN FUNCTION DRIVER

From: Srujana Challa <schalla@marvell.com>

When CPT_AF_DIAG[FLT_DIS] = 0 and a CPT engine access to
LLC/DRAM encounters a fault/poison, a rare case may result
in unpredictable data being delivered to a CPT engine.
So, this patch adds code to set FLT_DIS as a workaround.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
---
 drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c | 13 +++++++++++++
 drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c |  1 +
 2 files changed, 14 insertions(+)

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
index 4c8ebdf671ca..e0b29cf504b9 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
@@ -1111,6 +1111,7 @@ int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf,
 	struct otx2_cpt_engines engs[OTX2_CPT_MAX_ETYPES_PER_GRP] = { {0} };
 	struct pci_dev *pdev = cptpf->pdev;
 	struct fw_info_t fw_info;
+	u64 reg_val;
 	int ret = 0;
 
 	mutex_lock(&eng_grps->lock);
@@ -1203,6 +1204,18 @@ int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf,
 	 */
 	otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTX_FLUSH_TIMER,
 			      CTX_FLUSH_TIMER_CNT, BLKADDR_CPT0);
+
+	/*
+	 * Set CPT_AF_DIAG[FLT_DIS], as a workaround for HW errata, when
+	 * CPT_AF_DIAG[FLT_DIS] = 0 and a CPT engine access to LLC/DRAM
+	 * encounters a fault/poison, a rare case may result in
+	 * unpredictable data being delivered to a CPT engine.
+	 */
+	otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_DIAG, &reg_val,
+			     BLKADDR_CPT0);
+	otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_DIAG,
+			      reg_val | BIT_ULL(24), BLKADDR_CPT0);
+
 	mutex_unlock(&eng_grps->lock);
 	return 0;
 
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
index 45357deecabb..1f7c971e6757 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
@@ -606,6 +606,7 @@ static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req)
 	} else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) {
 		/* Registers that can be accessed from PF */
 		switch (offset) {
+		case CPT_AF_DIAG:
 		case CPT_AF_CTL:
 		case CPT_AF_PF_FUNC:
 		case CPT_AF_BLK_RST:
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH] crypto: octeontx2: increase CPT HW instruction queue length
  2022-01-25 18:26 [PATCH] crypto: octeontx2: CN10K CPT to RNM workaround Shijith Thotton
  2022-01-25 18:26 ` [PATCH] crypto: octeontx2: disable DMA black hole on an DMA fault Shijith Thotton
@ 2022-01-25 18:26 ` Shijith Thotton
  2022-02-05  4:30   ` Herbert Xu
  2022-02-05  4:30 ` [PATCH] crypto: octeontx2: CN10K CPT to RNM workaround Herbert Xu
  2 siblings, 1 reply; 6+ messages in thread
From: Shijith Thotton @ 2022-01-25 18:26 UTC (permalink / raw)
  To: Arnaud Ebalard, Herbert Xu, Boris Brezillon
  Cc: Srujana Challa, linux-crypto, jerinj, sgoutham, Shijith Thotton,
	David S. Miller, open list

From: Srujana Challa <schalla@marvell.com>

LDWB is getting incorrectly used in HW when
CPT_AF_LF()_PTR_CTL[IQB_LDWB]=1 and CPT instruction queue has less than
320 free entries. So, increase HW instruction queue size by 320 and give
320 entries less for SW/NIX RX as a SW workaround.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
---
 drivers/crypto/marvell/octeontx2/otx2_cptlf.h | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h b/drivers/crypto/marvell/octeontx2/otx2_cptlf.h
index b691b6c1d5c4..4fcaf61a70e3 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptlf.h
@@ -26,12 +26,22 @@
  */
 #define OTX2_CPT_INST_QLEN_MSGS	((OTX2_CPT_SIZE_DIV40 - 1) * 40)
 
+/*
+ * LDWB is getting incorrectly used when IQB_LDWB = 1 and CPT instruction
+ * queue has less than 320 free entries. So, increase HW instruction queue
+ * size by 320 and give 320 entries less for SW/NIX RX as a workaround.
+ */
+#define OTX2_CPT_INST_QLEN_EXTRA_BYTES  (320 * OTX2_CPT_INST_SIZE)
+#define OTX2_CPT_EXTRA_SIZE_DIV40       (320/40)
+
 /* CPT instruction queue length in bytes */
-#define OTX2_CPT_INST_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 40 * \
-				  OTX2_CPT_INST_SIZE)
+#define OTX2_CPT_INST_QLEN_BYTES                                               \
+		((OTX2_CPT_SIZE_DIV40 * 40 * OTX2_CPT_INST_SIZE) +             \
+		OTX2_CPT_INST_QLEN_EXTRA_BYTES)
 
 /* CPT instruction group queue length in bytes */
-#define OTX2_CPT_INST_GRP_QLEN_BYTES (OTX2_CPT_SIZE_DIV40 * 16)
+#define OTX2_CPT_INST_GRP_QLEN_BYTES                                           \
+		((OTX2_CPT_SIZE_DIV40 + OTX2_CPT_EXTRA_SIZE_DIV40) * 16)
 
 /* CPT FC length in bytes */
 #define OTX2_CPT_Q_FC_LEN 128
@@ -179,7 +189,8 @@ static inline void otx2_cptlf_do_set_iqueue_size(struct otx2_cptlf_info *lf)
 {
 	union otx2_cptx_lf_q_size lf_q_size = { .u = 0x0 };
 
-	lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40;
+	lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40 +
+				 OTX2_CPT_EXTRA_SIZE_DIV40;
 	otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
 			 OTX2_CPT_LF_Q_SIZE, lf_q_size.u);
 }
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH] crypto: octeontx2: CN10K CPT to RNM workaround
  2022-01-25 18:26 [PATCH] crypto: octeontx2: CN10K CPT to RNM workaround Shijith Thotton
  2022-01-25 18:26 ` [PATCH] crypto: octeontx2: disable DMA black hole on an DMA fault Shijith Thotton
  2022-01-25 18:26 ` [PATCH] crypto: octeontx2: increase CPT HW instruction queue length Shijith Thotton
@ 2022-02-05  4:30 ` Herbert Xu
  2 siblings, 0 replies; 6+ messages in thread
From: Herbert Xu @ 2022-02-05  4:30 UTC (permalink / raw)
  To: Shijith Thotton
  Cc: Arnaud Ebalard, Boris Brezillon, Srujana Challa, linux-crypto,
	jerinj, sgoutham, David S. Miller, Dan Carpenter, Jiapeng Chong,
	open list

On Tue, Jan 25, 2022 at 11:56:22PM +0530, Shijith Thotton wrote:
> From: Srujana Challa <schalla@marvell.com>
> 
> When software sets CPT_AF_CTL[RNM_REQ_EN]=1 and RNM in not producing
> entropy(i.e., RNM_ENTROPY_STATUS[NORMAL_CNT] < 0x40), the first cycle of
> the response may be lost due to a conditional clocking issue. Due to
> this, the subsequent random number stream will be corrupted. So, this
> patch adds support to ensure RNM_ENTROPY_STATUS[NORMAL_CNT] = 0x40
> before writing CPT_AF_CTL[RNM_REQ_EN] = 1, as a workaround.
> 
> Signed-off-by: Srujana Challa <schalla@marvell.com>
> Signed-off-by: Shijith Thotton <sthotton@marvell.com>
> ---
>  .../marvell/octeontx2/otx2_cptpf_ucode.c      | 43 ++++++++++++++++++-
>  1 file changed, 42 insertions(+), 1 deletion(-)

Patch applied.  Thanks.
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] crypto: octeontx2: disable DMA black hole on an DMA fault
  2022-01-25 18:26 ` [PATCH] crypto: octeontx2: disable DMA black hole on an DMA fault Shijith Thotton
@ 2022-02-05  4:30   ` Herbert Xu
  0 siblings, 0 replies; 6+ messages in thread
From: Herbert Xu @ 2022-02-05  4:30 UTC (permalink / raw)
  To: Shijith Thotton
  Cc: Arnaud Ebalard, Boris Brezillon, Srujana Challa, linux-crypto,
	jerinj, sgoutham, David S. Miller, Linu Cherian, Geetha sowjanya,
	hariprasad, Subbaraya Sundeep, Jakub Kicinski, Dan Carpenter,
	Jiapeng Chong, open list,
	open list:MARVELL OCTEONTX2 RVU ADMIN FUNCTION DRIVER

On Tue, Jan 25, 2022 at 11:56:23PM +0530, Shijith Thotton wrote:
> From: Srujana Challa <schalla@marvell.com>
> 
> When CPT_AF_DIAG[FLT_DIS] = 0 and a CPT engine access to
> LLC/DRAM encounters a fault/poison, a rare case may result
> in unpredictable data being delivered to a CPT engine.
> So, this patch adds code to set FLT_DIS as a workaround.
> 
> Signed-off-by: Srujana Challa <schalla@marvell.com>
> Signed-off-by: Shijith Thotton <sthotton@marvell.com>
> ---
>  drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c | 13 +++++++++++++
>  drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c |  1 +
>  2 files changed, 14 insertions(+)

Patch applied.  Thanks.
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] crypto: octeontx2: increase CPT HW instruction queue length
  2022-01-25 18:26 ` [PATCH] crypto: octeontx2: increase CPT HW instruction queue length Shijith Thotton
@ 2022-02-05  4:30   ` Herbert Xu
  0 siblings, 0 replies; 6+ messages in thread
From: Herbert Xu @ 2022-02-05  4:30 UTC (permalink / raw)
  To: Shijith Thotton
  Cc: Arnaud Ebalard, Boris Brezillon, Srujana Challa, linux-crypto,
	jerinj, sgoutham, David S. Miller, open list

On Tue, Jan 25, 2022 at 11:56:24PM +0530, Shijith Thotton wrote:
> From: Srujana Challa <schalla@marvell.com>
> 
> LDWB is getting incorrectly used in HW when
> CPT_AF_LF()_PTR_CTL[IQB_LDWB]=1 and CPT instruction queue has less than
> 320 free entries. So, increase HW instruction queue size by 320 and give
> 320 entries less for SW/NIX RX as a SW workaround.
> 
> Signed-off-by: Srujana Challa <schalla@marvell.com>
> Signed-off-by: Shijith Thotton <sthotton@marvell.com>
> ---
>  drivers/crypto/marvell/octeontx2/otx2_cptlf.h | 19 +++++++++++++++----
>  1 file changed, 15 insertions(+), 4 deletions(-)

Patch applied.  Thanks.
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2022-02-05  4:30 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-25 18:26 [PATCH] crypto: octeontx2: CN10K CPT to RNM workaround Shijith Thotton
2022-01-25 18:26 ` [PATCH] crypto: octeontx2: disable DMA black hole on an DMA fault Shijith Thotton
2022-02-05  4:30   ` Herbert Xu
2022-01-25 18:26 ` [PATCH] crypto: octeontx2: increase CPT HW instruction queue length Shijith Thotton
2022-02-05  4:30   ` Herbert Xu
2022-02-05  4:30 ` [PATCH] crypto: octeontx2: CN10K CPT to RNM workaround Herbert Xu

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