* [PATCH v2 0/4] irqchip/meson-gpio: Add support for Meson-S4 SoC
@ 2022-01-19 7:08 ` Qianggui Song
0 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic, devicetree, Rob Herring
This patchset add support for GPIO interrupt controller of Meson-S4 SoC
Which has something different with current other meson chips. To
support the new chips, current gpio irqchip driver need to rework as
below:
1. support more than 8 gpio irq lines.
2. add a set trigger type callback function.
With above work, add support for S4 gpio irqchip
Changes since v1 at [0]:
- fix leaking issue
- fix some typos
- change implementation of new feature.
[0] https://lore.kernel.org/linux-amlogic/20220108084218.31877-1-qianggui.song@amlogic.com/
Qianggui Song (4):
dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs
irqchip/meson-gpio: support more than 8 channels gpio irq line
irqchip/meson-gpio: add select trigger type callback
irqchip/meson-gpio: Add support for meson s4 SoCs
.../amlogic,meson-gpio-intc.txt | 1 +
drivers/irqchip/irq-meson-gpio.c | 105 ++++++++++++++++--
2 files changed, 97 insertions(+), 9 deletions(-)
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 0/4] irqchip/meson-gpio: Add support for Meson-S4 SoC
@ 2022-01-19 7:08 ` Qianggui Song
0 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic, devicetree, Rob Herring
This patchset add support for GPIO interrupt controller of Meson-S4 SoC
Which has something different with current other meson chips. To
support the new chips, current gpio irqchip driver need to rework as
below:
1. support more than 8 gpio irq lines.
2. add a set trigger type callback function.
With above work, add support for S4 gpio irqchip
Changes since v1 at [0]:
- fix leaking issue
- fix some typos
- change implementation of new feature.
[0] https://lore.kernel.org/linux-amlogic/20220108084218.31877-1-qianggui.song@amlogic.com/
Qianggui Song (4):
dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs
irqchip/meson-gpio: support more than 8 channels gpio irq line
irqchip/meson-gpio: add select trigger type callback
irqchip/meson-gpio: Add support for meson s4 SoCs
.../amlogic,meson-gpio-intc.txt | 1 +
drivers/irqchip/irq-meson-gpio.c | 105 ++++++++++++++++--
2 files changed, 97 insertions(+), 9 deletions(-)
--
2.34.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 1/4] dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs
2022-01-19 7:08 ` Qianggui Song
(?)
@ 2022-01-19 7:08 ` Qianggui Song
-1 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic, devicetree, Rob Herring
Update dt-binding document for GPIO interrupt controller of Meson-S4 SoCs
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
---
.../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index 23b18b92c558..bde63f8f090e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -18,6 +18,7 @@ Required properties:
"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
"amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
"amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
+ "amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 1/4] dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs
@ 2022-01-19 7:08 ` Qianggui Song
0 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic, devicetree, Rob Herring
Update dt-binding document for GPIO interrupt controller of Meson-S4 SoCs
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
---
.../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index 23b18b92c558..bde63f8f090e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -18,6 +18,7 @@ Required properties:
"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
"amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
"amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
+ "amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 1/4] dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs
@ 2022-01-19 7:08 ` Qianggui Song
0 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic, devicetree, Rob Herring
Update dt-binding document for GPIO interrupt controller of Meson-S4 SoCs
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
---
.../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index 23b18b92c558..bde63f8f090e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -18,6 +18,7 @@ Required properties:
"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
"amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
"amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
+ "amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
--
2.34.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 1/4] dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs
2022-01-19 7:08 ` Qianggui Song
(?)
@ 2022-02-07 22:15 ` Rob Herring
-1 siblings, 0 replies; 27+ messages in thread
From: Rob Herring @ 2022-02-07 22:15 UTC (permalink / raw)
To: Qianggui Song
Cc: Marc Zyngier, Kevin Hilman, Martin Blumenstingl, Thomas Gleixner,
Neil Armstrong, Jerome Brunet, Rob Herring, devicetree,
linux-arm-kernel, linux-amlogic, linux-kernel
On Wed, 19 Jan 2022 15:08:06 +0800, Qianggui Song wrote:
> Update dt-binding document for GPIO interrupt controller of Meson-S4 SoCs
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs
@ 2022-02-07 22:15 ` Rob Herring
0 siblings, 0 replies; 27+ messages in thread
From: Rob Herring @ 2022-02-07 22:15 UTC (permalink / raw)
To: Qianggui Song
Cc: Marc Zyngier, Kevin Hilman, Martin Blumenstingl, Thomas Gleixner,
Neil Armstrong, Jerome Brunet, Rob Herring, devicetree,
linux-arm-kernel, linux-amlogic, linux-kernel
On Wed, 19 Jan 2022 15:08:06 +0800, Qianggui Song wrote:
> Update dt-binding document for GPIO interrupt controller of Meson-S4 SoCs
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs
@ 2022-02-07 22:15 ` Rob Herring
0 siblings, 0 replies; 27+ messages in thread
From: Rob Herring @ 2022-02-07 22:15 UTC (permalink / raw)
To: Qianggui Song
Cc: Marc Zyngier, Kevin Hilman, Martin Blumenstingl, Thomas Gleixner,
Neil Armstrong, Jerome Brunet, Rob Herring, devicetree,
linux-arm-kernel, linux-amlogic, linux-kernel
On Wed, 19 Jan 2022 15:08:06 +0800, Qianggui Song wrote:
> Update dt-binding document for GPIO interrupt controller of Meson-S4 SoCs
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line
2022-01-19 7:08 ` Qianggui Song
(?)
@ 2022-01-19 7:08 ` Qianggui Song
-1 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic
Current meson gpio irqchip driver only support 8 channels for gpio irq
line, later chips may have more then 8 channels, so need to modify code
to support more.
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index d90ff0b92480..eefe15e1b3a6 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -16,7 +16,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
-#define NUM_CHANNEL 8
#define MAX_INPUT_MUX 256
#define REG_EDGE_POL 0x00
@@ -60,6 +59,7 @@ struct irq_ctl_ops {
struct meson_gpio_irq_params {
unsigned int nr_hwirq;
+ unsigned int nr_channels;
bool support_edge_both;
unsigned int edge_both_offset;
unsigned int edge_single_offset;
@@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
.edge_single_offset = 0, \
.pol_low_offset = 16, \
.pin_sel_mask = 0xff, \
+ .nr_channels = 8, \
#define INIT_MESON_A1_COMMON_DATA(irqs) \
INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
@@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
.edge_single_offset = 8, \
.pol_low_offset = 0, \
.pin_sel_mask = 0x7f, \
+ .nr_channels = 8, \
static const struct meson_gpio_irq_params meson8_params = {
INIT_MESON8_COMMON_DATA(134)
@@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
struct meson_gpio_irq_controller {
const struct meson_gpio_irq_params *params;
void __iomem *base;
- u32 channel_irqs[NUM_CHANNEL];
- DECLARE_BITMAP(channel_map, NUM_CHANNEL);
+ u32 *channel_irqs;
+ unsigned long *channel_map;
spinlock_t lock;
};
@@ -207,8 +209,8 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
spin_lock_irqsave(&ctl->lock, flags);
/* Find a free channel */
- idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
- if (idx >= NUM_CHANNEL) {
+ idx = find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels);
+ if (idx >= ctl->params->nr_channels) {
spin_unlock_irqrestore(&ctl->lock, flags);
pr_err("No channel available\n");
return -ENOSPC;
@@ -447,13 +449,26 @@ static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_i
ctl->params = match->data;
+ ctl->channel_irqs = kcalloc(ctl->params->nr_channels, sizeof(*ctl->channel_irqs),
+ GFP_KERNEL);
+ if (!ctl->channel_irqs)
+ return -ENOMEM;
+
+ ctl->channel_map = bitmap_zalloc(ctl->params->nr_channels, GFP_KERNEL);
+ if (!ctl->channel_map) {
+ kfree(ctl->channel_irqs);
+ return -ENOMEM;
+ }
+
ret = of_property_read_variable_u32_array(node,
"amlogic,channel-interrupts",
ctl->channel_irqs,
- NUM_CHANNEL,
- NUM_CHANNEL);
+ ctl->params->nr_channels,
+ ctl->params->nr_channels);
if (ret < 0) {
- pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
+ pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels);
+ kfree(ctl->channel_map);
+ kfree(ctl->channel_irqs);
return ret;
}
@@ -507,7 +522,7 @@ static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *
}
pr_info("%d to %d gpio interrupt mux initialized\n",
- ctl->params->nr_hwirq, NUM_CHANNEL);
+ ctl->params->nr_hwirq, ctl->params->nr_channels);
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line
@ 2022-01-19 7:08 ` Qianggui Song
0 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic
Current meson gpio irqchip driver only support 8 channels for gpio irq
line, later chips may have more then 8 channels, so need to modify code
to support more.
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index d90ff0b92480..eefe15e1b3a6 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -16,7 +16,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
-#define NUM_CHANNEL 8
#define MAX_INPUT_MUX 256
#define REG_EDGE_POL 0x00
@@ -60,6 +59,7 @@ struct irq_ctl_ops {
struct meson_gpio_irq_params {
unsigned int nr_hwirq;
+ unsigned int nr_channels;
bool support_edge_both;
unsigned int edge_both_offset;
unsigned int edge_single_offset;
@@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
.edge_single_offset = 0, \
.pol_low_offset = 16, \
.pin_sel_mask = 0xff, \
+ .nr_channels = 8, \
#define INIT_MESON_A1_COMMON_DATA(irqs) \
INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
@@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
.edge_single_offset = 8, \
.pol_low_offset = 0, \
.pin_sel_mask = 0x7f, \
+ .nr_channels = 8, \
static const struct meson_gpio_irq_params meson8_params = {
INIT_MESON8_COMMON_DATA(134)
@@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
struct meson_gpio_irq_controller {
const struct meson_gpio_irq_params *params;
void __iomem *base;
- u32 channel_irqs[NUM_CHANNEL];
- DECLARE_BITMAP(channel_map, NUM_CHANNEL);
+ u32 *channel_irqs;
+ unsigned long *channel_map;
spinlock_t lock;
};
@@ -207,8 +209,8 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
spin_lock_irqsave(&ctl->lock, flags);
/* Find a free channel */
- idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
- if (idx >= NUM_CHANNEL) {
+ idx = find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels);
+ if (idx >= ctl->params->nr_channels) {
spin_unlock_irqrestore(&ctl->lock, flags);
pr_err("No channel available\n");
return -ENOSPC;
@@ -447,13 +449,26 @@ static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_i
ctl->params = match->data;
+ ctl->channel_irqs = kcalloc(ctl->params->nr_channels, sizeof(*ctl->channel_irqs),
+ GFP_KERNEL);
+ if (!ctl->channel_irqs)
+ return -ENOMEM;
+
+ ctl->channel_map = bitmap_zalloc(ctl->params->nr_channels, GFP_KERNEL);
+ if (!ctl->channel_map) {
+ kfree(ctl->channel_irqs);
+ return -ENOMEM;
+ }
+
ret = of_property_read_variable_u32_array(node,
"amlogic,channel-interrupts",
ctl->channel_irqs,
- NUM_CHANNEL,
- NUM_CHANNEL);
+ ctl->params->nr_channels,
+ ctl->params->nr_channels);
if (ret < 0) {
- pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
+ pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels);
+ kfree(ctl->channel_map);
+ kfree(ctl->channel_irqs);
return ret;
}
@@ -507,7 +522,7 @@ static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *
}
pr_info("%d to %d gpio interrupt mux initialized\n",
- ctl->params->nr_hwirq, NUM_CHANNEL);
+ ctl->params->nr_hwirq, ctl->params->nr_channels);
return 0;
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line
@ 2022-01-19 7:08 ` Qianggui Song
0 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic
Current meson gpio irqchip driver only support 8 channels for gpio irq
line, later chips may have more then 8 channels, so need to modify code
to support more.
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index d90ff0b92480..eefe15e1b3a6 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -16,7 +16,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
-#define NUM_CHANNEL 8
#define MAX_INPUT_MUX 256
#define REG_EDGE_POL 0x00
@@ -60,6 +59,7 @@ struct irq_ctl_ops {
struct meson_gpio_irq_params {
unsigned int nr_hwirq;
+ unsigned int nr_channels;
bool support_edge_both;
unsigned int edge_both_offset;
unsigned int edge_single_offset;
@@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
.edge_single_offset = 0, \
.pol_low_offset = 16, \
.pin_sel_mask = 0xff, \
+ .nr_channels = 8, \
#define INIT_MESON_A1_COMMON_DATA(irqs) \
INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
@@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
.edge_single_offset = 8, \
.pol_low_offset = 0, \
.pin_sel_mask = 0x7f, \
+ .nr_channels = 8, \
static const struct meson_gpio_irq_params meson8_params = {
INIT_MESON8_COMMON_DATA(134)
@@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
struct meson_gpio_irq_controller {
const struct meson_gpio_irq_params *params;
void __iomem *base;
- u32 channel_irqs[NUM_CHANNEL];
- DECLARE_BITMAP(channel_map, NUM_CHANNEL);
+ u32 *channel_irqs;
+ unsigned long *channel_map;
spinlock_t lock;
};
@@ -207,8 +209,8 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
spin_lock_irqsave(&ctl->lock, flags);
/* Find a free channel */
- idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
- if (idx >= NUM_CHANNEL) {
+ idx = find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels);
+ if (idx >= ctl->params->nr_channels) {
spin_unlock_irqrestore(&ctl->lock, flags);
pr_err("No channel available\n");
return -ENOSPC;
@@ -447,13 +449,26 @@ static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_i
ctl->params = match->data;
+ ctl->channel_irqs = kcalloc(ctl->params->nr_channels, sizeof(*ctl->channel_irqs),
+ GFP_KERNEL);
+ if (!ctl->channel_irqs)
+ return -ENOMEM;
+
+ ctl->channel_map = bitmap_zalloc(ctl->params->nr_channels, GFP_KERNEL);
+ if (!ctl->channel_map) {
+ kfree(ctl->channel_irqs);
+ return -ENOMEM;
+ }
+
ret = of_property_read_variable_u32_array(node,
"amlogic,channel-interrupts",
ctl->channel_irqs,
- NUM_CHANNEL,
- NUM_CHANNEL);
+ ctl->params->nr_channels,
+ ctl->params->nr_channels);
if (ret < 0) {
- pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
+ pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels);
+ kfree(ctl->channel_map);
+ kfree(ctl->channel_irqs);
return ret;
}
@@ -507,7 +522,7 @@ static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *
}
pr_info("%d to %d gpio interrupt mux initialized\n",
- ctl->params->nr_hwirq, NUM_CHANNEL);
+ ctl->params->nr_hwirq, ctl->params->nr_channels);
return 0;
--
2.34.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line
2022-01-19 7:08 ` Qianggui Song
(?)
@ 2022-01-19 8:53 ` Neil Armstrong
-1 siblings, 0 replies; 27+ messages in thread
From: Neil Armstrong @ 2022-01-19 8:53 UTC (permalink / raw)
To: Qianggui Song, Thomas Gleixner, Marc Zyngier
Cc: Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-kernel,
linux-arm-kernel, linux-amlogic
On 19/01/2022 08:08, Qianggui Song wrote:
> Current meson gpio irqchip driver only support 8 channels for gpio irq
> line, later chips may have more then 8 channels, so need to modify code
> to support more.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
> 1 file changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index d90ff0b92480..eefe15e1b3a6 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -16,7 +16,6 @@
> #include <linux/of.h>
> #include <linux/of_address.h>
>
> -#define NUM_CHANNEL 8
> #define MAX_INPUT_MUX 256
>
> #define REG_EDGE_POL 0x00
> @@ -60,6 +59,7 @@ struct irq_ctl_ops {
>
> struct meson_gpio_irq_params {
> unsigned int nr_hwirq;
> + unsigned int nr_channels;
> bool support_edge_both;
> unsigned int edge_both_offset;
> unsigned int edge_single_offset;
> @@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 0, \
> .pol_low_offset = 16, \
> .pin_sel_mask = 0xff, \
> + .nr_channels = 8, \
>
> #define INIT_MESON_A1_COMMON_DATA(irqs) \
> INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
> @@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 8, \
> .pol_low_offset = 0, \
> .pin_sel_mask = 0x7f, \
> + .nr_channels = 8, \
>
> static const struct meson_gpio_irq_params meson8_params = {
> INIT_MESON8_COMMON_DATA(134)
> @@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
> struct meson_gpio_irq_controller {
> const struct meson_gpio_irq_params *params;
> void __iomem *base;
> - u32 channel_irqs[NUM_CHANNEL];
> - DECLARE_BITMAP(channel_map, NUM_CHANNEL);
> + u32 *channel_irqs;
> + unsigned long *channel_map;
> spinlock_t lock;
> };
>
> @@ -207,8 +209,8 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
> spin_lock_irqsave(&ctl->lock, flags);
>
> /* Find a free channel */
> - idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
> - if (idx >= NUM_CHANNEL) {
> + idx = find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels);
> + if (idx >= ctl->params->nr_channels) {
> spin_unlock_irqrestore(&ctl->lock, flags);
> pr_err("No channel available\n");
> return -ENOSPC;
> @@ -447,13 +449,26 @@ static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_i
>
> ctl->params = match->data;
>
> + ctl->channel_irqs = kcalloc(ctl->params->nr_channels, sizeof(*ctl->channel_irqs),
> + GFP_KERNEL);
> + if (!ctl->channel_irqs)
> + return -ENOMEM;
> +
> + ctl->channel_map = bitmap_zalloc(ctl->params->nr_channels, GFP_KERNEL);
> + if (!ctl->channel_map) {
> + kfree(ctl->channel_irqs);
> + return -ENOMEM;
> + }
> +
> ret = of_property_read_variable_u32_array(node,
> "amlogic,channel-interrupts",
> ctl->channel_irqs,
> - NUM_CHANNEL,
> - NUM_CHANNEL);
> + ctl->params->nr_channels,
> + ctl->params->nr_channels);
> if (ret < 0) {
> - pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
> + pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels);
> + kfree(ctl->channel_map);
> + kfree(ctl->channel_irqs);
> return ret;
> }
>
> @@ -507,7 +522,7 @@ static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *
> }
>
> pr_info("%d to %d gpio interrupt mux initialized\n",
> - ctl->params->nr_hwirq, NUM_CHANNEL);
> + ctl->params->nr_hwirq, ctl->params->nr_channels);
>
> return 0;
>
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line
@ 2022-01-19 8:53 ` Neil Armstrong
0 siblings, 0 replies; 27+ messages in thread
From: Neil Armstrong @ 2022-01-19 8:53 UTC (permalink / raw)
To: Qianggui Song, Thomas Gleixner, Marc Zyngier
Cc: Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-kernel,
linux-arm-kernel, linux-amlogic
On 19/01/2022 08:08, Qianggui Song wrote:
> Current meson gpio irqchip driver only support 8 channels for gpio irq
> line, later chips may have more then 8 channels, so need to modify code
> to support more.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
> 1 file changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index d90ff0b92480..eefe15e1b3a6 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -16,7 +16,6 @@
> #include <linux/of.h>
> #include <linux/of_address.h>
>
> -#define NUM_CHANNEL 8
> #define MAX_INPUT_MUX 256
>
> #define REG_EDGE_POL 0x00
> @@ -60,6 +59,7 @@ struct irq_ctl_ops {
>
> struct meson_gpio_irq_params {
> unsigned int nr_hwirq;
> + unsigned int nr_channels;
> bool support_edge_both;
> unsigned int edge_both_offset;
> unsigned int edge_single_offset;
> @@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 0, \
> .pol_low_offset = 16, \
> .pin_sel_mask = 0xff, \
> + .nr_channels = 8, \
>
> #define INIT_MESON_A1_COMMON_DATA(irqs) \
> INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
> @@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 8, \
> .pol_low_offset = 0, \
> .pin_sel_mask = 0x7f, \
> + .nr_channels = 8, \
>
> static const struct meson_gpio_irq_params meson8_params = {
> INIT_MESON8_COMMON_DATA(134)
> @@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
> struct meson_gpio_irq_controller {
> const struct meson_gpio_irq_params *params;
> void __iomem *base;
> - u32 channel_irqs[NUM_CHANNEL];
> - DECLARE_BITMAP(channel_map, NUM_CHANNEL);
> + u32 *channel_irqs;
> + unsigned long *channel_map;
> spinlock_t lock;
> };
>
> @@ -207,8 +209,8 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
> spin_lock_irqsave(&ctl->lock, flags);
>
> /* Find a free channel */
> - idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
> - if (idx >= NUM_CHANNEL) {
> + idx = find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels);
> + if (idx >= ctl->params->nr_channels) {
> spin_unlock_irqrestore(&ctl->lock, flags);
> pr_err("No channel available\n");
> return -ENOSPC;
> @@ -447,13 +449,26 @@ static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_i
>
> ctl->params = match->data;
>
> + ctl->channel_irqs = kcalloc(ctl->params->nr_channels, sizeof(*ctl->channel_irqs),
> + GFP_KERNEL);
> + if (!ctl->channel_irqs)
> + return -ENOMEM;
> +
> + ctl->channel_map = bitmap_zalloc(ctl->params->nr_channels, GFP_KERNEL);
> + if (!ctl->channel_map) {
> + kfree(ctl->channel_irqs);
> + return -ENOMEM;
> + }
> +
> ret = of_property_read_variable_u32_array(node,
> "amlogic,channel-interrupts",
> ctl->channel_irqs,
> - NUM_CHANNEL,
> - NUM_CHANNEL);
> + ctl->params->nr_channels,
> + ctl->params->nr_channels);
> if (ret < 0) {
> - pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
> + pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels);
> + kfree(ctl->channel_map);
> + kfree(ctl->channel_irqs);
> return ret;
> }
>
> @@ -507,7 +522,7 @@ static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *
> }
>
> pr_info("%d to %d gpio interrupt mux initialized\n",
> - ctl->params->nr_hwirq, NUM_CHANNEL);
> + ctl->params->nr_hwirq, ctl->params->nr_channels);
>
> return 0;
>
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line
@ 2022-01-19 8:53 ` Neil Armstrong
0 siblings, 0 replies; 27+ messages in thread
From: Neil Armstrong @ 2022-01-19 8:53 UTC (permalink / raw)
To: Qianggui Song, Thomas Gleixner, Marc Zyngier
Cc: Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-kernel,
linux-arm-kernel, linux-amlogic
On 19/01/2022 08:08, Qianggui Song wrote:
> Current meson gpio irqchip driver only support 8 channels for gpio irq
> line, later chips may have more then 8 channels, so need to modify code
> to support more.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
> 1 file changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index d90ff0b92480..eefe15e1b3a6 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -16,7 +16,6 @@
> #include <linux/of.h>
> #include <linux/of_address.h>
>
> -#define NUM_CHANNEL 8
> #define MAX_INPUT_MUX 256
>
> #define REG_EDGE_POL 0x00
> @@ -60,6 +59,7 @@ struct irq_ctl_ops {
>
> struct meson_gpio_irq_params {
> unsigned int nr_hwirq;
> + unsigned int nr_channels;
> bool support_edge_both;
> unsigned int edge_both_offset;
> unsigned int edge_single_offset;
> @@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 0, \
> .pol_low_offset = 16, \
> .pin_sel_mask = 0xff, \
> + .nr_channels = 8, \
>
> #define INIT_MESON_A1_COMMON_DATA(irqs) \
> INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
> @@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 8, \
> .pol_low_offset = 0, \
> .pin_sel_mask = 0x7f, \
> + .nr_channels = 8, \
>
> static const struct meson_gpio_irq_params meson8_params = {
> INIT_MESON8_COMMON_DATA(134)
> @@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
> struct meson_gpio_irq_controller {
> const struct meson_gpio_irq_params *params;
> void __iomem *base;
> - u32 channel_irqs[NUM_CHANNEL];
> - DECLARE_BITMAP(channel_map, NUM_CHANNEL);
> + u32 *channel_irqs;
> + unsigned long *channel_map;
> spinlock_t lock;
> };
>
> @@ -207,8 +209,8 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
> spin_lock_irqsave(&ctl->lock, flags);
>
> /* Find a free channel */
> - idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
> - if (idx >= NUM_CHANNEL) {
> + idx = find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels);
> + if (idx >= ctl->params->nr_channels) {
> spin_unlock_irqrestore(&ctl->lock, flags);
> pr_err("No channel available\n");
> return -ENOSPC;
> @@ -447,13 +449,26 @@ static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_i
>
> ctl->params = match->data;
>
> + ctl->channel_irqs = kcalloc(ctl->params->nr_channels, sizeof(*ctl->channel_irqs),
> + GFP_KERNEL);
> + if (!ctl->channel_irqs)
> + return -ENOMEM;
> +
> + ctl->channel_map = bitmap_zalloc(ctl->params->nr_channels, GFP_KERNEL);
> + if (!ctl->channel_map) {
> + kfree(ctl->channel_irqs);
> + return -ENOMEM;
> + }
> +
> ret = of_property_read_variable_u32_array(node,
> "amlogic,channel-interrupts",
> ctl->channel_irqs,
> - NUM_CHANNEL,
> - NUM_CHANNEL);
> + ctl->params->nr_channels,
> + ctl->params->nr_channels);
> if (ret < 0) {
> - pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
> + pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels);
> + kfree(ctl->channel_map);
> + kfree(ctl->channel_irqs);
> return ret;
> }
>
> @@ -507,7 +522,7 @@ static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *
> }
>
> pr_info("%d to %d gpio interrupt mux initialized\n",
> - ctl->params->nr_hwirq, NUM_CHANNEL);
> + ctl->params->nr_hwirq, ctl->params->nr_channels);
>
> return 0;
>
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line
2022-01-19 7:08 ` Qianggui Song
(?)
@ 2022-01-19 13:31 ` Marc Zyngier
-1 siblings, 0 replies; 27+ messages in thread
From: Marc Zyngier @ 2022-01-19 13:31 UTC (permalink / raw)
To: Qianggui Song
Cc: Thomas Gleixner, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic
On Wed, 19 Jan 2022 07:08:07 +0000,
Qianggui Song <qianggui.song@amlogic.com> wrote:
>
> Current meson gpio irqchip driver only support 8 channels for gpio irq
> line, later chips may have more then 8 channels, so need to modify code
> to support more.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
> 1 file changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index d90ff0b92480..eefe15e1b3a6 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -16,7 +16,6 @@
> #include <linux/of.h>
> #include <linux/of_address.h>
>
> -#define NUM_CHANNEL 8
> #define MAX_INPUT_MUX 256
>
> #define REG_EDGE_POL 0x00
> @@ -60,6 +59,7 @@ struct irq_ctl_ops {
>
> struct meson_gpio_irq_params {
> unsigned int nr_hwirq;
> + unsigned int nr_channels;
> bool support_edge_both;
> unsigned int edge_both_offset;
> unsigned int edge_single_offset;
> @@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 0, \
> .pol_low_offset = 16, \
> .pin_sel_mask = 0xff, \
> + .nr_channels = 8, \
>
> #define INIT_MESON_A1_COMMON_DATA(irqs) \
> INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
> @@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 8, \
> .pol_low_offset = 0, \
> .pin_sel_mask = 0x7f, \
> + .nr_channels = 8, \
>
> static const struct meson_gpio_irq_params meson8_params = {
> INIT_MESON8_COMMON_DATA(134)
> @@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
> struct meson_gpio_irq_controller {
> const struct meson_gpio_irq_params *params;
> void __iomem *base;
> - u32 channel_irqs[NUM_CHANNEL];
> - DECLARE_BITMAP(channel_map, NUM_CHANNEL);
> + u32 *channel_irqs;
> + unsigned long *channel_map;
This really is over-engineering at its best.
With your new fancy HW, you have at most 12 bits being used in this
bitmap. So why not have a single unsigned long, no dynamic allocation,
and simply an assertion somewhere that checks that nr_channel is never
bigger than BITS_PER_LONG? Less code, less memory wasted, less problems.
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line
@ 2022-01-19 13:31 ` Marc Zyngier
0 siblings, 0 replies; 27+ messages in thread
From: Marc Zyngier @ 2022-01-19 13:31 UTC (permalink / raw)
To: Qianggui Song
Cc: Thomas Gleixner, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic
On Wed, 19 Jan 2022 07:08:07 +0000,
Qianggui Song <qianggui.song@amlogic.com> wrote:
>
> Current meson gpio irqchip driver only support 8 channels for gpio irq
> line, later chips may have more then 8 channels, so need to modify code
> to support more.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
> 1 file changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index d90ff0b92480..eefe15e1b3a6 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -16,7 +16,6 @@
> #include <linux/of.h>
> #include <linux/of_address.h>
>
> -#define NUM_CHANNEL 8
> #define MAX_INPUT_MUX 256
>
> #define REG_EDGE_POL 0x00
> @@ -60,6 +59,7 @@ struct irq_ctl_ops {
>
> struct meson_gpio_irq_params {
> unsigned int nr_hwirq;
> + unsigned int nr_channels;
> bool support_edge_both;
> unsigned int edge_both_offset;
> unsigned int edge_single_offset;
> @@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 0, \
> .pol_low_offset = 16, \
> .pin_sel_mask = 0xff, \
> + .nr_channels = 8, \
>
> #define INIT_MESON_A1_COMMON_DATA(irqs) \
> INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
> @@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 8, \
> .pol_low_offset = 0, \
> .pin_sel_mask = 0x7f, \
> + .nr_channels = 8, \
>
> static const struct meson_gpio_irq_params meson8_params = {
> INIT_MESON8_COMMON_DATA(134)
> @@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
> struct meson_gpio_irq_controller {
> const struct meson_gpio_irq_params *params;
> void __iomem *base;
> - u32 channel_irqs[NUM_CHANNEL];
> - DECLARE_BITMAP(channel_map, NUM_CHANNEL);
> + u32 *channel_irqs;
> + unsigned long *channel_map;
This really is over-engineering at its best.
With your new fancy HW, you have at most 12 bits being used in this
bitmap. So why not have a single unsigned long, no dynamic allocation,
and simply an assertion somewhere that checks that nr_channel is never
bigger than BITS_PER_LONG? Less code, less memory wasted, less problems.
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 2/4] irqchip/meson-gpio: support more than 8 channels gpio irq line
@ 2022-01-19 13:31 ` Marc Zyngier
0 siblings, 0 replies; 27+ messages in thread
From: Marc Zyngier @ 2022-01-19 13:31 UTC (permalink / raw)
To: Qianggui Song
Cc: Thomas Gleixner, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic
On Wed, 19 Jan 2022 07:08:07 +0000,
Qianggui Song <qianggui.song@amlogic.com> wrote:
>
> Current meson gpio irqchip driver only support 8 channels for gpio irq
> line, later chips may have more then 8 channels, so need to modify code
> to support more.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
> 1 file changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index d90ff0b92480..eefe15e1b3a6 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -16,7 +16,6 @@
> #include <linux/of.h>
> #include <linux/of_address.h>
>
> -#define NUM_CHANNEL 8
> #define MAX_INPUT_MUX 256
>
> #define REG_EDGE_POL 0x00
> @@ -60,6 +59,7 @@ struct irq_ctl_ops {
>
> struct meson_gpio_irq_params {
> unsigned int nr_hwirq;
> + unsigned int nr_channels;
> bool support_edge_both;
> unsigned int edge_both_offset;
> unsigned int edge_single_offset;
> @@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 0, \
> .pol_low_offset = 16, \
> .pin_sel_mask = 0xff, \
> + .nr_channels = 8, \
>
> #define INIT_MESON_A1_COMMON_DATA(irqs) \
> INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
> @@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 8, \
> .pol_low_offset = 0, \
> .pin_sel_mask = 0x7f, \
> + .nr_channels = 8, \
>
> static const struct meson_gpio_irq_params meson8_params = {
> INIT_MESON8_COMMON_DATA(134)
> @@ -136,8 +138,8 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
> struct meson_gpio_irq_controller {
> const struct meson_gpio_irq_params *params;
> void __iomem *base;
> - u32 channel_irqs[NUM_CHANNEL];
> - DECLARE_BITMAP(channel_map, NUM_CHANNEL);
> + u32 *channel_irqs;
> + unsigned long *channel_map;
This really is over-engineering at its best.
With your new fancy HW, you have at most 12 bits being used in this
bitmap. So why not have a single unsigned long, no dynamic allocation,
and simply an assertion somewhere that checks that nr_channel is never
bigger than BITS_PER_LONG? Less code, less memory wasted, less problems.
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 3/4] irqchip/meson-gpio: add select trigger type callback
2022-01-19 7:08 ` Qianggui Song
(?)
@ 2022-01-19 7:08 ` Qianggui Song
-1 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic
Due to some chips may use different registers and offset, provide
a set trigger type call back.
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index eefe15e1b3a6..b511f9532adc 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -55,6 +55,8 @@ struct irq_ctl_ops {
void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
unsigned int channel, unsigned long hwirq);
void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
+ void (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl,
+ unsigned int idx, u32 val);
};
struct meson_gpio_irq_params {
@@ -278,6 +280,12 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
*/
type &= IRQ_TYPE_SENSE_MASK;
+ /* Some controllers may have different calculation method*/
+ if (params->ops.gpio_irq_sel_type) {
+ params->ops.gpio_irq_sel_type(ctl, idx, type);
+ return 0;
+ }
+
/*
* New controller support EDGE_BOTH trigger. This setting takes
* precedence over the other edge/polarity settings
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 3/4] irqchip/meson-gpio: add select trigger type callback
@ 2022-01-19 7:08 ` Qianggui Song
0 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic
Due to some chips may use different registers and offset, provide
a set trigger type call back.
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index eefe15e1b3a6..b511f9532adc 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -55,6 +55,8 @@ struct irq_ctl_ops {
void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
unsigned int channel, unsigned long hwirq);
void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
+ void (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl,
+ unsigned int idx, u32 val);
};
struct meson_gpio_irq_params {
@@ -278,6 +280,12 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
*/
type &= IRQ_TYPE_SENSE_MASK;
+ /* Some controllers may have different calculation method*/
+ if (params->ops.gpio_irq_sel_type) {
+ params->ops.gpio_irq_sel_type(ctl, idx, type);
+ return 0;
+ }
+
/*
* New controller support EDGE_BOTH trigger. This setting takes
* precedence over the other edge/polarity settings
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 3/4] irqchip/meson-gpio: add select trigger type callback
@ 2022-01-19 7:08 ` Qianggui Song
0 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic
Due to some chips may use different registers and offset, provide
a set trigger type call back.
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index eefe15e1b3a6..b511f9532adc 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -55,6 +55,8 @@ struct irq_ctl_ops {
void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
unsigned int channel, unsigned long hwirq);
void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
+ void (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl,
+ unsigned int idx, u32 val);
};
struct meson_gpio_irq_params {
@@ -278,6 +280,12 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
*/
type &= IRQ_TYPE_SENSE_MASK;
+ /* Some controllers may have different calculation method*/
+ if (params->ops.gpio_irq_sel_type) {
+ params->ops.gpio_irq_sel_type(ctl, idx, type);
+ return 0;
+ }
+
/*
* New controller support EDGE_BOTH trigger. This setting takes
* precedence over the other edge/polarity settings
--
2.34.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 3/4] irqchip/meson-gpio: add select trigger type callback
2022-01-19 7:08 ` Qianggui Song
(?)
@ 2022-01-19 8:52 ` Neil Armstrong
-1 siblings, 0 replies; 27+ messages in thread
From: Neil Armstrong @ 2022-01-19 8:52 UTC (permalink / raw)
To: Qianggui Song, Thomas Gleixner, Marc Zyngier
Cc: Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-kernel,
linux-arm-kernel, linux-amlogic
Hi,
On 19/01/2022 08:08, Qianggui Song wrote:
> Due to some chips may use different registers and offset, provide
> a set trigger type call back.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> drivers/irqchip/irq-meson-gpio.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index eefe15e1b3a6..b511f9532adc 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -55,6 +55,8 @@ struct irq_ctl_ops {
> void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
> unsigned int channel, unsigned long hwirq);
> void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
> + void (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl,
> + unsigned int idx, u32 val);
> };
>
> struct meson_gpio_irq_params {
> @@ -278,6 +280,12 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
> */
> type &= IRQ_TYPE_SENSE_MASK;
>
> + /* Some controllers may have different calculation method*/
> + if (params->ops.gpio_irq_sel_type) {
> + params->ops.gpio_irq_sel_type(ctl, idx, type);
> + return 0;
> + }
> +
> /*
> * New controller support EDGE_BOTH trigger. This setting takes
> * precedence over the other edge/polarity settings
>
The comment on v1 hasn't been addresses here, it was asked to move the old controllers
sel_type to a callback and introduce an S4 callback instead of doing this.
Neil
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 3/4] irqchip/meson-gpio: add select trigger type callback
@ 2022-01-19 8:52 ` Neil Armstrong
0 siblings, 0 replies; 27+ messages in thread
From: Neil Armstrong @ 2022-01-19 8:52 UTC (permalink / raw)
To: Qianggui Song, Thomas Gleixner, Marc Zyngier
Cc: Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-kernel,
linux-arm-kernel, linux-amlogic
Hi,
On 19/01/2022 08:08, Qianggui Song wrote:
> Due to some chips may use different registers and offset, provide
> a set trigger type call back.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> drivers/irqchip/irq-meson-gpio.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index eefe15e1b3a6..b511f9532adc 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -55,6 +55,8 @@ struct irq_ctl_ops {
> void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
> unsigned int channel, unsigned long hwirq);
> void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
> + void (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl,
> + unsigned int idx, u32 val);
> };
>
> struct meson_gpio_irq_params {
> @@ -278,6 +280,12 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
> */
> type &= IRQ_TYPE_SENSE_MASK;
>
> + /* Some controllers may have different calculation method*/
> + if (params->ops.gpio_irq_sel_type) {
> + params->ops.gpio_irq_sel_type(ctl, idx, type);
> + return 0;
> + }
> +
> /*
> * New controller support EDGE_BOTH trigger. This setting takes
> * precedence over the other edge/polarity settings
>
The comment on v1 hasn't been addresses here, it was asked to move the old controllers
sel_type to a callback and introduce an S4 callback instead of doing this.
Neil
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v2 3/4] irqchip/meson-gpio: add select trigger type callback
@ 2022-01-19 8:52 ` Neil Armstrong
0 siblings, 0 replies; 27+ messages in thread
From: Neil Armstrong @ 2022-01-19 8:52 UTC (permalink / raw)
To: Qianggui Song, Thomas Gleixner, Marc Zyngier
Cc: Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-kernel,
linux-arm-kernel, linux-amlogic
Hi,
On 19/01/2022 08:08, Qianggui Song wrote:
> Due to some chips may use different registers and offset, provide
> a set trigger type call back.
>
> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
> ---
> drivers/irqchip/irq-meson-gpio.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index eefe15e1b3a6..b511f9532adc 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -55,6 +55,8 @@ struct irq_ctl_ops {
> void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
> unsigned int channel, unsigned long hwirq);
> void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
> + void (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl,
> + unsigned int idx, u32 val);
> };
>
> struct meson_gpio_irq_params {
> @@ -278,6 +280,12 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
> */
> type &= IRQ_TYPE_SENSE_MASK;
>
> + /* Some controllers may have different calculation method*/
> + if (params->ops.gpio_irq_sel_type) {
> + params->ops.gpio_irq_sel_type(ctl, idx, type);
> + return 0;
> + }
> +
> /*
> * New controller support EDGE_BOTH trigger. This setting takes
> * precedence over the other edge/polarity settings
>
The comment on v1 hasn't been addresses here, it was asked to move the old controllers
sel_type to a callback and introduce an S4 callback instead of doing this.
Neil
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 4/4] irqchip/meson-gpio: Add support for meson s4 SoCs
2022-01-19 7:08 ` Qianggui Song
(?)
@ 2022-01-19 7:08 ` Qianggui Song
-1 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic
The meson s4 SoCs support 12 gpio irq lines compared with previous
serial chips and have something different, details are as below.
IRQ Number:
- 80:68 13 pins on bank Z
- 67:48 20 pins on bank X
- 47:36 12 pins on bank H
- 35:24 12 pins on bank D
- 23:22 2 pins on bank E
- 21:14 8 pins on bank C
- 13:0 13 pins on bank B
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 64 ++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index b511f9532adc..896201d2f01f 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -42,6 +42,9 @@
#define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
#define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
+/* Used for s4 chips */
+#define REG_EDGE_POL_S4 0x1c
+
struct meson_gpio_irq_controller;
static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
unsigned int channel, unsigned long hwirq);
@@ -50,6 +53,8 @@ static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
unsigned int channel,
unsigned long hwirq);
static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
+static void meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int idx, u32 val);
struct irq_ctl_ops {
void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
@@ -95,6 +100,20 @@ struct meson_gpio_irq_params {
.pin_sel_mask = 0x7f, \
.nr_channels = 8, \
+#define INIT_MESON_S4_COMMON_DATA(irqs) \
+ .nr_hwirq = irqs, \
+ .ops = { \
+ .gpio_irq_init = meson_a1_gpio_irq_init, \
+ .gpio_irq_sel_pin = meson_a1_gpio_irq_sel_pin, \
+ .gpio_irq_sel_type = meson_s4_gpio_irq_sel_type,\
+ }, \
+ .support_edge_both = true, \
+ .edge_both_offset = 0, \
+ .edge_single_offset = 12, \
+ .pol_low_offset = 0, \
+ .pin_sel_mask = 0xff, \
+ .nr_channels = 12, \
+
static const struct meson_gpio_irq_params meson8_params = {
INIT_MESON8_COMMON_DATA(134)
};
@@ -125,6 +144,10 @@ static const struct meson_gpio_irq_params a1_params = {
INIT_MESON_A1_COMMON_DATA(62)
};
+static const struct meson_gpio_irq_params s4_params = {
+ INIT_MESON_S4_COMMON_DATA(82)
+};
+
static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
@@ -134,6 +157,7 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
+ { .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
{ }
};
@@ -200,6 +224,46 @@ static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl)
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31));
}
+/*
+ * gpio irq relative registers for s4
+ * -PADCTRL_GPIO_IRQ_CTRL0
+ * bit[31]: enable/disable all the irq lines
+ * bit[12-23]: single edge trigger
+ * bit[0-11]: polarity trigger
+ *
+ * -PADCTRL_GPIO_IRQ_CTRL[X]
+ * bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2
+ * bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1
+ * where X = 1-6
+ *
+ * -PADCTRL_GPIO_IRQ_CTRL[7]
+ * bit[0-11]: both edge trigger
+ */
+static void
+meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int idx, unsigned int type)
+{
+ unsigned int val = 0;
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(idx), 0);
+
+ if (type == IRQ_TYPE_EDGE_BOTH) {
+ val |= BIT(ctl->params->edge_both_offset + idx);
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4,
+ BIT(ctl->params->edge_both_offset + idx), val);
+ return;
+ }
+
+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->pol_low_offset + idx);
+
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->edge_single_offset + idx);
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
+ BIT(idx) | BIT(12 + idx), val);
+};
+
static int
meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
unsigned long hwirq,
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 4/4] irqchip/meson-gpio: Add support for meson s4 SoCs
@ 2022-01-19 7:08 ` Qianggui Song
0 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic
The meson s4 SoCs support 12 gpio irq lines compared with previous
serial chips and have something different, details are as below.
IRQ Number:
- 80:68 13 pins on bank Z
- 67:48 20 pins on bank X
- 47:36 12 pins on bank H
- 35:24 12 pins on bank D
- 23:22 2 pins on bank E
- 21:14 8 pins on bank C
- 13:0 13 pins on bank B
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 64 ++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index b511f9532adc..896201d2f01f 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -42,6 +42,9 @@
#define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
#define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
+/* Used for s4 chips */
+#define REG_EDGE_POL_S4 0x1c
+
struct meson_gpio_irq_controller;
static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
unsigned int channel, unsigned long hwirq);
@@ -50,6 +53,8 @@ static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
unsigned int channel,
unsigned long hwirq);
static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
+static void meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int idx, u32 val);
struct irq_ctl_ops {
void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
@@ -95,6 +100,20 @@ struct meson_gpio_irq_params {
.pin_sel_mask = 0x7f, \
.nr_channels = 8, \
+#define INIT_MESON_S4_COMMON_DATA(irqs) \
+ .nr_hwirq = irqs, \
+ .ops = { \
+ .gpio_irq_init = meson_a1_gpio_irq_init, \
+ .gpio_irq_sel_pin = meson_a1_gpio_irq_sel_pin, \
+ .gpio_irq_sel_type = meson_s4_gpio_irq_sel_type,\
+ }, \
+ .support_edge_both = true, \
+ .edge_both_offset = 0, \
+ .edge_single_offset = 12, \
+ .pol_low_offset = 0, \
+ .pin_sel_mask = 0xff, \
+ .nr_channels = 12, \
+
static const struct meson_gpio_irq_params meson8_params = {
INIT_MESON8_COMMON_DATA(134)
};
@@ -125,6 +144,10 @@ static const struct meson_gpio_irq_params a1_params = {
INIT_MESON_A1_COMMON_DATA(62)
};
+static const struct meson_gpio_irq_params s4_params = {
+ INIT_MESON_S4_COMMON_DATA(82)
+};
+
static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
@@ -134,6 +157,7 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
+ { .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
{ }
};
@@ -200,6 +224,46 @@ static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl)
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31));
}
+/*
+ * gpio irq relative registers for s4
+ * -PADCTRL_GPIO_IRQ_CTRL0
+ * bit[31]: enable/disable all the irq lines
+ * bit[12-23]: single edge trigger
+ * bit[0-11]: polarity trigger
+ *
+ * -PADCTRL_GPIO_IRQ_CTRL[X]
+ * bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2
+ * bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1
+ * where X = 1-6
+ *
+ * -PADCTRL_GPIO_IRQ_CTRL[7]
+ * bit[0-11]: both edge trigger
+ */
+static void
+meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int idx, unsigned int type)
+{
+ unsigned int val = 0;
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(idx), 0);
+
+ if (type == IRQ_TYPE_EDGE_BOTH) {
+ val |= BIT(ctl->params->edge_both_offset + idx);
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4,
+ BIT(ctl->params->edge_both_offset + idx), val);
+ return;
+ }
+
+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->pol_low_offset + idx);
+
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->edge_single_offset + idx);
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
+ BIT(idx) | BIT(12 + idx), val);
+};
+
static int
meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
unsigned long hwirq,
--
2.34.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 4/4] irqchip/meson-gpio: Add support for meson s4 SoCs
@ 2022-01-19 7:08 ` Qianggui Song
0 siblings, 0 replies; 27+ messages in thread
From: Qianggui Song @ 2022-01-19 7:08 UTC (permalink / raw)
To: Thomas Gleixner, Marc Zyngier
Cc: Qianggui Song, Kevin Hilman, Neil Armstrong, Jerome Brunet,
Martin Blumenstingl, linux-kernel, linux-arm-kernel,
linux-amlogic
The meson s4 SoCs support 12 gpio irq lines compared with previous
serial chips and have something different, details are as below.
IRQ Number:
- 80:68 13 pins on bank Z
- 67:48 20 pins on bank X
- 47:36 12 pins on bank H
- 35:24 12 pins on bank D
- 23:22 2 pins on bank E
- 21:14 8 pins on bank C
- 13:0 13 pins on bank B
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
---
drivers/irqchip/irq-meson-gpio.c | 64 ++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index b511f9532adc..896201d2f01f 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -42,6 +42,9 @@
#define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
#define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
+/* Used for s4 chips */
+#define REG_EDGE_POL_S4 0x1c
+
struct meson_gpio_irq_controller;
static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
unsigned int channel, unsigned long hwirq);
@@ -50,6 +53,8 @@ static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
unsigned int channel,
unsigned long hwirq);
static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
+static void meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int idx, u32 val);
struct irq_ctl_ops {
void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
@@ -95,6 +100,20 @@ struct meson_gpio_irq_params {
.pin_sel_mask = 0x7f, \
.nr_channels = 8, \
+#define INIT_MESON_S4_COMMON_DATA(irqs) \
+ .nr_hwirq = irqs, \
+ .ops = { \
+ .gpio_irq_init = meson_a1_gpio_irq_init, \
+ .gpio_irq_sel_pin = meson_a1_gpio_irq_sel_pin, \
+ .gpio_irq_sel_type = meson_s4_gpio_irq_sel_type,\
+ }, \
+ .support_edge_both = true, \
+ .edge_both_offset = 0, \
+ .edge_single_offset = 12, \
+ .pol_low_offset = 0, \
+ .pin_sel_mask = 0xff, \
+ .nr_channels = 12, \
+
static const struct meson_gpio_irq_params meson8_params = {
INIT_MESON8_COMMON_DATA(134)
};
@@ -125,6 +144,10 @@ static const struct meson_gpio_irq_params a1_params = {
INIT_MESON_A1_COMMON_DATA(62)
};
+static const struct meson_gpio_irq_params s4_params = {
+ INIT_MESON_S4_COMMON_DATA(82)
+};
+
static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
@@ -134,6 +157,7 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
+ { .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
{ }
};
@@ -200,6 +224,46 @@ static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl)
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31));
}
+/*
+ * gpio irq relative registers for s4
+ * -PADCTRL_GPIO_IRQ_CTRL0
+ * bit[31]: enable/disable all the irq lines
+ * bit[12-23]: single edge trigger
+ * bit[0-11]: polarity trigger
+ *
+ * -PADCTRL_GPIO_IRQ_CTRL[X]
+ * bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2
+ * bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1
+ * where X = 1-6
+ *
+ * -PADCTRL_GPIO_IRQ_CTRL[7]
+ * bit[0-11]: both edge trigger
+ */
+static void
+meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int idx, unsigned int type)
+{
+ unsigned int val = 0;
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(idx), 0);
+
+ if (type == IRQ_TYPE_EDGE_BOTH) {
+ val |= BIT(ctl->params->edge_both_offset + idx);
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4,
+ BIT(ctl->params->edge_both_offset + idx), val);
+ return;
+ }
+
+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->pol_low_offset + idx);
+
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->edge_single_offset + idx);
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
+ BIT(idx) | BIT(12 + idx), val);
+};
+
static int
meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
unsigned long hwirq,
--
2.34.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread