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From: Qian Cai <quic_qiancai@quicinc.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Shuah Khan <skhan@linuxfoundation.org>,
	"Shuah Khan" <shuah@kernel.org>,
	Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
	Luis Machado <luis.machado@arm.com>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kselftest@vger.kernel.org>,
	Alan Hayward <alan.hayward@arm.com>,
	<kvmarm@lists.cs.columbia.edu>,
	"Salil Akerkar" <Salil.Akerkar@arm.com>
Subject: Re: [PATCH v11 03/40] arm64: cpufeature: Always specify and use a field width for capabilities
Date: Tue, 1 Mar 2022 17:56:41 -0500	[thread overview]
Message-ID: <Yh6kqaR9FQXg8Q4w@qian> (raw)
In-Reply-To: <20220207152109.197566-4-broonie@kernel.org>

On Mon, Feb 07, 2022 at 03:20:32PM +0000, Mark Brown wrote:
> Since all the fields in the main ID registers are 4 bits wide we have up
> until now not bothered specifying the width in the code. Since we now
> wish to use this mechanism to enumerate features from the floating point
> feature registers which do not follow this pattern add a width to the
> table.  This means updating all the existing table entries but makes it
> less likely that we run into issues in future due to implicitly assuming
> a 4 bit width.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>

Do we leave this one alone on purpose?

                .desc = "GIC system register CPU interface",
                .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
                .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
                .matches = has_useable_gicv3_cpuif,
                .sys_reg = SYS_ID_AA64PFR0_EL1,
                .field_pos = ID_AA64PFR0_GIC_SHIFT,
                .sign = FTR_UNSIGNED,
                .min_field_value = 1,

Since width == 0, it will generate an undefined behavior.

UBSAN: shift-out-of-bounds in ./arch/arm64/include/asm/cpufeature.h:535:49
 shift exponent 64 is too large for 64-bit type 'long long unsigned int'
 CPU: 0 PID: 0 Comm: swapper Not tainted 5.17.0-rc6-next-20220301 #1
 Call trace:
  dump_backtrace
  show_stack
  dump_stack_lvl
  dump_stack
  ubsan_epilogue
  __ubsan_handle_shift_out_of_bounds
  has_cpuid_feature
  cpuid_feature_extract_unsigned_field_width at arch/arm64/include/asm/cpufeature.h:535
  (inlined by) cpuid_feature_extract_field_width at arch/arm64/include/asm/cpufeature.h:582
  (inlined by) cpuid_feature_extract_field_width at arch/arm64/include/asm/cpufeature.h:578
  (inlined by) feature_matches at arch/arm64/kernel/cpufeature.c:1317
  (inlined by) has_cpuid_feature at arch/arm64/kernel/cpufeature.c:1335
  has_useable_gicv3_cpuif
  has_useable_gicv3_cpuif at arch/arm64/kernel/cpufeature.c:1389
  update_cpu_capabilities
  init_cpu_features
  cpuinfo_store_boot_cpu
  smp_prepare_boot_cpu
  start_kernel
  __primary_switched

WARNING: multiple messages have this Message-ID (diff)
From: Qian Cai <quic_qiancai@quicinc.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,  Marc Zyngier <maz@kernel.org>,
	Shuah Khan <skhan@linuxfoundation.org>,
	"Shuah Khan" <shuah@kernel.org>,
	Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
	 Luis Machado <luis.machado@arm.com>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kselftest@vger.kernel.org>,
	Alan Hayward <alan.hayward@arm.com>,
	<kvmarm@lists.cs.columbia.edu>,
	"Salil Akerkar" <Salil.Akerkar@arm.com>
Subject: Re: [PATCH v11 03/40] arm64: cpufeature: Always specify and use a field width for capabilities
Date: Tue, 1 Mar 2022 17:56:41 -0500	[thread overview]
Message-ID: <Yh6kqaR9FQXg8Q4w@qian> (raw)
In-Reply-To: <20220207152109.197566-4-broonie@kernel.org>

On Mon, Feb 07, 2022 at 03:20:32PM +0000, Mark Brown wrote:
> Since all the fields in the main ID registers are 4 bits wide we have up
> until now not bothered specifying the width in the code. Since we now
> wish to use this mechanism to enumerate features from the floating point
> feature registers which do not follow this pattern add a width to the
> table.  This means updating all the existing table entries but makes it
> less likely that we run into issues in future due to implicitly assuming
> a 4 bit width.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>

Do we leave this one alone on purpose?

                .desc = "GIC system register CPU interface",
                .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
                .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
                .matches = has_useable_gicv3_cpuif,
                .sys_reg = SYS_ID_AA64PFR0_EL1,
                .field_pos = ID_AA64PFR0_GIC_SHIFT,
                .sign = FTR_UNSIGNED,
                .min_field_value = 1,

Since width == 0, it will generate an undefined behavior.

UBSAN: shift-out-of-bounds in ./arch/arm64/include/asm/cpufeature.h:535:49
 shift exponent 64 is too large for 64-bit type 'long long unsigned int'
 CPU: 0 PID: 0 Comm: swapper Not tainted 5.17.0-rc6-next-20220301 #1
 Call trace:
  dump_backtrace
  show_stack
  dump_stack_lvl
  dump_stack
  ubsan_epilogue
  __ubsan_handle_shift_out_of_bounds
  has_cpuid_feature
  cpuid_feature_extract_unsigned_field_width at arch/arm64/include/asm/cpufeature.h:535
  (inlined by) cpuid_feature_extract_field_width at arch/arm64/include/asm/cpufeature.h:582
  (inlined by) cpuid_feature_extract_field_width at arch/arm64/include/asm/cpufeature.h:578
  (inlined by) feature_matches at arch/arm64/kernel/cpufeature.c:1317
  (inlined by) has_cpuid_feature at arch/arm64/kernel/cpufeature.c:1335
  has_useable_gicv3_cpuif
  has_useable_gicv3_cpuif at arch/arm64/kernel/cpufeature.c:1389
  update_cpu_capabilities
  init_cpu_features
  cpuinfo_store_boot_cpu
  smp_prepare_boot_cpu
  start_kernel
  __primary_switched

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Qian Cai <quic_qiancai@quicinc.com>
To: Mark Brown <broonie@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>,
	Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
	Will Deacon <will@kernel.org>,
	Luis Machado <luis.machado@arm.com>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Alan Hayward <alan.hayward@arm.com>,
	Salil Akerkar <Salil.Akerkar@arm.com>,
	linux-kselftest@vger.kernel.org,
	Shuah Khan <skhan@linuxfoundation.org>,
	Shuah Khan <shuah@kernel.org>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v11 03/40] arm64: cpufeature: Always specify and use a field width for capabilities
Date: Tue, 1 Mar 2022 17:56:41 -0500	[thread overview]
Message-ID: <Yh6kqaR9FQXg8Q4w@qian> (raw)
In-Reply-To: <20220207152109.197566-4-broonie@kernel.org>

On Mon, Feb 07, 2022 at 03:20:32PM +0000, Mark Brown wrote:
> Since all the fields in the main ID registers are 4 bits wide we have up
> until now not bothered specifying the width in the code. Since we now
> wish to use this mechanism to enumerate features from the floating point
> feature registers which do not follow this pattern add a width to the
> table.  This means updating all the existing table entries but makes it
> less likely that we run into issues in future due to implicitly assuming
> a 4 bit width.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>

Do we leave this one alone on purpose?

                .desc = "GIC system register CPU interface",
                .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
                .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
                .matches = has_useable_gicv3_cpuif,
                .sys_reg = SYS_ID_AA64PFR0_EL1,
                .field_pos = ID_AA64PFR0_GIC_SHIFT,
                .sign = FTR_UNSIGNED,
                .min_field_value = 1,

Since width == 0, it will generate an undefined behavior.

UBSAN: shift-out-of-bounds in ./arch/arm64/include/asm/cpufeature.h:535:49
 shift exponent 64 is too large for 64-bit type 'long long unsigned int'
 CPU: 0 PID: 0 Comm: swapper Not tainted 5.17.0-rc6-next-20220301 #1
 Call trace:
  dump_backtrace
  show_stack
  dump_stack_lvl
  dump_stack
  ubsan_epilogue
  __ubsan_handle_shift_out_of_bounds
  has_cpuid_feature
  cpuid_feature_extract_unsigned_field_width at arch/arm64/include/asm/cpufeature.h:535
  (inlined by) cpuid_feature_extract_field_width at arch/arm64/include/asm/cpufeature.h:582
  (inlined by) cpuid_feature_extract_field_width at arch/arm64/include/asm/cpufeature.h:578
  (inlined by) feature_matches at arch/arm64/kernel/cpufeature.c:1317
  (inlined by) has_cpuid_feature at arch/arm64/kernel/cpufeature.c:1335
  has_useable_gicv3_cpuif
  has_useable_gicv3_cpuif at arch/arm64/kernel/cpufeature.c:1389
  update_cpu_capabilities
  init_cpu_features
  cpuinfo_store_boot_cpu
  smp_prepare_boot_cpu
  start_kernel
  __primary_switched
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

  parent reply	other threads:[~2022-03-01 22:56 UTC|newest]

Thread overview: 399+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-07 15:20 [PATCH v11 00/40] arm64/sme: Initial support for the Scalable Matrix Extension Mark Brown
2022-02-07 15:20 ` Mark Brown
2022-02-07 15:20 ` Mark Brown
2022-02-07 15:20 ` [PATCH v11 01/40] arm64: Define CPACR_EL1_FPEN similarly to other floating point controls Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-10 11:34   ` Catalin Marinas
2022-02-10 11:34     ` Catalin Marinas
2022-02-10 11:34     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 02/40] arm64: Always use individual bits in CPACR floating point enables Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-10 11:36   ` Catalin Marinas
2022-02-10 11:36     ` Catalin Marinas
2022-02-10 11:36     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 03/40] arm64: cpufeature: Always specify and use a field width for capabilities Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-10 11:39   ` Catalin Marinas
2022-02-10 11:39     ` Catalin Marinas
2022-02-10 11:39     ` Catalin Marinas
2022-02-10 11:55   ` Suzuki K Poulose
2022-02-10 11:55     ` Suzuki K Poulose
2022-02-10 11:55     ` Suzuki K Poulose
2022-03-01 22:56   ` Qian Cai [this message]
2022-03-01 22:56     ` Qian Cai
2022-03-01 22:56     ` Qian Cai
2022-03-02 10:12     ` Marc Zyngier
2022-03-02 10:12       ` Marc Zyngier
2022-03-02 11:52       ` Catalin Marinas
2022-03-02 11:52         ` Catalin Marinas
2022-03-02 11:52         ` Catalin Marinas
2022-03-02 13:02         ` Mark Brown
2022-03-02 13:02           ` Mark Brown
2022-03-02 13:02           ` Mark Brown
2022-03-02 12:58     ` Mark Brown
2022-03-02 12:58       ` Mark Brown
2022-03-02 12:58       ` Mark Brown
2022-02-07 15:20 ` [PATCH v11 04/40] kselftest/arm64: Remove local ARRAY_SIZE() definitions Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 23:45   ` Shuah Khan
2022-02-07 23:45     ` Shuah Khan
2022-02-07 23:45     ` Shuah Khan
2022-02-10 15:03   ` Catalin Marinas
2022-02-10 15:03     ` Catalin Marinas
2022-02-10 15:03     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 05/40] kselftest/arm64: signal: Allow tests to be incompatible with features Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 23:54   ` Shuah Khan
2022-02-07 23:54     ` Shuah Khan
2022-02-07 23:54     ` Shuah Khan
2022-02-08 15:32     ` Mark Brown
2022-02-08 15:32       ` Mark Brown
2022-02-08 15:32       ` Mark Brown
2022-02-10 15:08   ` Catalin Marinas
2022-02-10 15:08     ` Catalin Marinas
2022-02-10 15:08     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 06/40] arm64/sme: Provide ABI documentation for SME Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-08  0:10   ` Shuah Khan
2022-02-08  0:10     ` Shuah Khan
2022-02-08  0:10     ` Shuah Khan
2022-02-08 15:46     ` Mark Brown
2022-02-08 15:46       ` Mark Brown
2022-02-08 15:46       ` Mark Brown
2022-02-08 18:38       ` Mark Brown
2022-02-08 18:38         ` Mark Brown
2022-02-08 18:38         ` Mark Brown
2022-02-08 18:48         ` Shuah Khan
2022-02-08 18:48           ` Shuah Khan
2022-02-08 18:48           ` Shuah Khan
2022-02-08 19:00           ` Mark Brown
2022-02-08 19:00             ` Mark Brown
2022-02-08 19:00             ` Mark Brown
2022-02-10 15:12             ` Shuah Khan
2022-02-10 15:12               ` Shuah Khan
2022-02-10 15:12               ` Shuah Khan
2022-02-10 16:18               ` Mark Brown
2022-02-10 16:18                 ` Mark Brown
2022-02-10 16:18                 ` Mark Brown
2022-02-10 16:46                 ` Shuah Khan
2022-02-10 16:46                   ` Shuah Khan
2022-02-10 16:46                   ` Shuah Khan
2022-02-10 18:32   ` Catalin Marinas
2022-02-10 18:32     ` Catalin Marinas
2022-02-10 18:32     ` Catalin Marinas
2022-02-10 19:45     ` Mark Brown
2022-02-10 19:45       ` Mark Brown
2022-02-10 19:45       ` Mark Brown
2022-02-11 17:02       ` Catalin Marinas
2022-02-11 17:02         ` Catalin Marinas
2022-02-11 17:02         ` Catalin Marinas
2022-02-11 18:13         ` Mark Brown
2022-02-11 18:13           ` Mark Brown
2022-02-11 18:13           ` Mark Brown
2022-02-14 18:19           ` Catalin Marinas
2022-02-14 18:19             ` Catalin Marinas
2022-02-14 18:19             ` Catalin Marinas
2022-02-14 19:40             ` Mark Brown
2022-02-14 19:40               ` Mark Brown
2022-02-14 19:40               ` Mark Brown
2022-02-07 15:20 ` [PATCH v11 07/40] arm64/sme: System register and exception syndrome definitions Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-10 18:35   ` Catalin Marinas
2022-02-10 18:35     ` Catalin Marinas
2022-02-10 18:35     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 08/40] arm64/sme: Manually encode SME instructions Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-10 18:57   ` Catalin Marinas
2022-02-10 18:57     ` Catalin Marinas
2022-02-10 18:57     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 09/40] arm64/sme: Early CPU setup for SME Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-21 11:54   ` Catalin Marinas
2022-02-21 11:54     ` Catalin Marinas
2022-02-21 11:54     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 10/40] arm64/sme: Basic enumeration support Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-21 14:32   ` Catalin Marinas
2022-02-21 14:32     ` Catalin Marinas
2022-02-21 14:32     ` Catalin Marinas
2022-02-21 15:01     ` Mark Brown
2022-02-21 15:01       ` Mark Brown
2022-02-21 15:01       ` Mark Brown
2022-02-21 19:24       ` Catalin Marinas
2022-02-21 19:24         ` Catalin Marinas
2022-02-21 19:24         ` Catalin Marinas
2022-02-21 23:10         ` Mark Brown
2022-02-21 23:10           ` Mark Brown
2022-02-21 23:10           ` Mark Brown
2022-02-22 12:09           ` Catalin Marinas
2022-02-22 12:09             ` Catalin Marinas
2022-02-22 12:09             ` Catalin Marinas
2022-02-21 16:07     ` Szabolcs Nagy
2022-02-21 16:07       ` Szabolcs Nagy
2022-02-21 16:07       ` Szabolcs Nagy
2022-02-21 19:04       ` Catalin Marinas
2022-02-21 19:04         ` Catalin Marinas
2022-02-21 19:04         ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 11/40] arm64/sme: Identify supported SME vector lengths at boot Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-21 15:57   ` Catalin Marinas
2022-02-21 15:57     ` Catalin Marinas
2022-02-21 15:57     ` Catalin Marinas
2022-02-21 23:39     ` Mark Brown
2022-02-21 23:39       ` Mark Brown
2022-02-21 23:39       ` Mark Brown
2022-02-07 15:20 ` [PATCH v11 12/40] arm64/sme: Implement sysctl to set the default vector length Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-21 16:48   ` Catalin Marinas
2022-02-21 16:48     ` Catalin Marinas
2022-02-21 16:48     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 13/40] arm64/sme: Implement vector length configuration prctl()s Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-21 16:48   ` Catalin Marinas
2022-02-21 16:48     ` Catalin Marinas
2022-02-21 16:48     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 14/40] arm64/sme: Implement support for TPIDR2 Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-21 16:58   ` Catalin Marinas
2022-02-21 16:58     ` Catalin Marinas
2022-02-21 16:58     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 15/40] arm64/sme: Implement SVCR context switching Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-21 18:12   ` Catalin Marinas
2022-02-21 18:12     ` Catalin Marinas
2022-02-21 18:12     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 16/40] arm64/sme: Implement streaming SVE " Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-22 12:53   ` Catalin Marinas
2022-02-22 12:53     ` Catalin Marinas
2022-02-22 12:53     ` Catalin Marinas
2022-02-22 13:42     ` Mark Brown
2022-02-22 13:42       ` Mark Brown
2022-02-22 13:42       ` Mark Brown
2022-02-07 15:20 ` [PATCH v11 17/40] arm64/sme: Implement ZA " Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-22 12:53   ` Catalin Marinas
2022-02-22 12:53     ` Catalin Marinas
2022-02-22 12:53     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 18/40] arm64/sme: Implement traps and syscall handling for SME Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-22 17:54   ` Catalin Marinas
2022-02-22 17:54     ` Catalin Marinas
2022-02-22 17:54     ` Catalin Marinas
2022-02-22 18:16     ` Mark Brown
2022-02-22 18:16       ` Mark Brown
2022-02-22 18:16       ` Mark Brown
2022-02-07 15:20 ` [PATCH v11 19/40] arm64/sme: Disable ZA and streaming mode when handling signals Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-22 18:48   ` Catalin Marinas
2022-02-22 18:48     ` Catalin Marinas
2022-02-22 18:48     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 20/40] arm64/sme: Implement streaming SVE signal handling Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-23 15:16   ` Catalin Marinas
2022-02-23 15:16     ` Catalin Marinas
2022-02-23 15:16     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 21/40] arm64/sme: Implement ZA " Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-23 15:19   ` Catalin Marinas
2022-02-23 15:19     ` Catalin Marinas
2022-02-23 15:19     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 22/40] arm64/sme: Implement ptrace support for streaming mode SVE registers Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-23 15:22   ` Catalin Marinas
2022-02-23 15:22     ` Catalin Marinas
2022-02-23 15:22     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 23/40] arm64/sme: Add ptrace support for ZA Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-23 15:27   ` Catalin Marinas
2022-02-23 15:27     ` Catalin Marinas
2022-02-23 15:27     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 24/40] arm64/sme: Disable streaming mode and ZA when flushing CPU state Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-23 15:28   ` Catalin Marinas
2022-02-23 15:28     ` Catalin Marinas
2022-02-23 15:28     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 25/40] arm64/sme: Save and restore streaming mode over EFI runtime calls Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-23 15:31   ` Catalin Marinas
2022-02-23 15:31     ` Catalin Marinas
2022-02-23 15:31     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 26/40] KVM: arm64: Hide SME system registers from guests Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-23 15:32   ` Catalin Marinas
2022-02-23 15:32     ` Catalin Marinas
2022-02-23 15:32     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 27/40] KVM: arm64: Trap SME usage in guest Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-23 15:34   ` Catalin Marinas
2022-02-23 15:34     ` Catalin Marinas
2022-02-23 15:34     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 28/40] KVM: arm64: Handle SME host state when running guests Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-23 15:40   ` Catalin Marinas
2022-02-23 15:40     ` Catalin Marinas
2022-02-23 15:40     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 29/40] arm64/sme: Provide Kconfig for SME Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 22:34   ` kernel test robot
2022-02-08 14:05     ` Mark Brown
2022-02-08 14:28   ` kernel test robot
2022-02-09  5:31   ` kernel test robot
2022-02-23 15:41   ` Catalin Marinas
2022-02-23 15:41     ` Catalin Marinas
2022-02-23 15:41     ` Catalin Marinas
2022-02-07 15:20 ` [PATCH v11 30/40] kselftest/arm64: Add manual encodings for SME instructions Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 15:20   ` Mark Brown
2022-02-07 23:57   ` Shuah Khan
2022-02-07 23:57     ` Shuah Khan
2022-02-07 23:57     ` Shuah Khan
2022-02-23 15:41   ` Catalin Marinas
2022-02-23 15:41     ` Catalin Marinas
2022-02-23 15:41     ` Catalin Marinas
2022-02-07 15:21 ` [PATCH v11 31/40] kselftest/arm64: sme: Add SME support to vlset Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-08  0:15   ` Shuah Khan
2022-02-08  0:15     ` Shuah Khan
2022-02-08  0:15     ` Shuah Khan
2022-02-08 15:51     ` Mark Brown
2022-02-08 15:51       ` Mark Brown
2022-02-08 15:51       ` Mark Brown
2022-02-23 15:42   ` Catalin Marinas
2022-02-23 15:42     ` Catalin Marinas
2022-02-23 15:42     ` Catalin Marinas
2022-02-07 15:21 ` [PATCH v11 32/40] kselftest/arm64: Add tests for TPIDR2 Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-08  0:23   ` Shuah Khan
2022-02-08  0:23     ` Shuah Khan
2022-02-08  0:23     ` Shuah Khan
2022-02-08 16:19     ` Mark Brown
2022-02-08 16:19       ` Mark Brown
2022-02-08 16:19       ` Mark Brown
2022-02-23 15:42   ` Catalin Marinas
2022-02-23 15:42     ` Catalin Marinas
2022-02-23 15:42     ` Catalin Marinas
2022-02-07 15:21 ` [PATCH v11 33/40] kselftest/arm64: Extend vector configuration API tests to cover SME Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-08  0:24   ` Shuah Khan
2022-02-08  0:24     ` Shuah Khan
2022-02-08  0:24     ` Shuah Khan
2022-02-23 15:43   ` Catalin Marinas
2022-02-23 15:43     ` Catalin Marinas
2022-02-23 15:43     ` Catalin Marinas
2022-02-07 15:21 ` [PATCH v11 34/40] kselftest/arm64: sme: Provide streaming mode SVE stress test Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-08  0:40   ` Shuah Khan
2022-02-08  0:40     ` Shuah Khan
2022-02-08  0:40     ` Shuah Khan
2022-02-08 16:23     ` Mark Brown
2022-02-08 16:23       ` Mark Brown
2022-02-08 16:23       ` Mark Brown
2022-02-23 15:45   ` Catalin Marinas
2022-02-23 15:45     ` Catalin Marinas
2022-02-23 15:45     ` Catalin Marinas
2022-02-07 15:21 ` [PATCH v11 35/40] kselftest/arm64: signal: Handle ZA signal context in core code Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-08  1:01   ` Shuah Khan
2022-02-08  1:01     ` Shuah Khan
2022-02-08  1:01     ` Shuah Khan
2022-02-08 16:29     ` Mark Brown
2022-02-08 16:29       ` Mark Brown
2022-02-08 16:29       ` Mark Brown
2022-02-23 15:46   ` Catalin Marinas
2022-02-23 15:46     ` Catalin Marinas
2022-02-23 15:46     ` Catalin Marinas
2022-02-07 15:21 ` [PATCH v11 36/40] kselftest/arm64: Add stress test for SME ZA context switching Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-23 15:47   ` Catalin Marinas
2022-02-23 15:47     ` Catalin Marinas
2022-02-23 15:47     ` Catalin Marinas
2022-02-07 15:21 ` [PATCH v11 37/40] kselftest/arm64: signal: Add SME signal handling tests Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-08  1:08   ` Shuah Khan
2022-02-08  1:08     ` Shuah Khan
2022-02-08  1:08     ` Shuah Khan
2022-02-08 17:27     ` Mark Brown
2022-02-08 17:27       ` Mark Brown
2022-02-08 17:27       ` Mark Brown
2022-02-23 15:47   ` Catalin Marinas
2022-02-23 15:47     ` Catalin Marinas
2022-02-23 15:47     ` Catalin Marinas
2022-02-07 15:21 ` [PATCH v11 38/40] kselftest/arm64: Add streaming SVE to SVE ptrace tests Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-08  1:13   ` Shuah Khan
2022-02-08  1:13     ` Shuah Khan
2022-02-08  1:13     ` Shuah Khan
2022-02-23 15:47   ` Catalin Marinas
2022-02-23 15:47     ` Catalin Marinas
2022-02-23 15:47     ` Catalin Marinas
2022-02-07 15:21 ` [PATCH v11 39/40] kselftest/arm64: Add coverage for the ZA ptrace interface Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-08  1:20   ` Shuah Khan
2022-02-08  1:20     ` Shuah Khan
2022-02-08  1:20     ` Shuah Khan
2022-02-23 15:47   ` Catalin Marinas
2022-02-23 15:47     ` Catalin Marinas
2022-02-23 15:47     ` Catalin Marinas
2022-02-07 15:21 ` [PATCH v11 40/40] kselftest/arm64: Add SME support to syscall ABI test Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-07 15:21   ` Mark Brown
2022-02-08  1:52   ` Shuah Khan
2022-02-08  1:52     ` Shuah Khan
2022-02-08  1:52     ` Shuah Khan
2022-02-08 18:15     ` Mark Brown
2022-02-08 18:15       ` Mark Brown
2022-02-08 18:15       ` Mark Brown
2022-02-08 18:50       ` Shuah Khan
2022-02-08 18:50         ` Shuah Khan
2022-02-08 18:50         ` Shuah Khan
2022-02-23 15:49   ` Catalin Marinas
2022-02-23 15:49     ` Catalin Marinas
2022-02-23 15:49     ` Catalin Marinas
2022-02-08 18:54 ` [PATCH v11 00/40] arm64/sme: Initial support for the Scalable Matrix Extension Shuah Khan
2022-02-08 18:54   ` Shuah Khan
2022-02-08 18:54   ` Shuah Khan
2022-02-25 15:50 ` Will Deacon
2022-02-25 15:50   ` Will Deacon
2022-02-25 15:50   ` Will Deacon
2022-02-25 15:52   ` Will Deacon
2022-02-25 15:52     ` Will Deacon
2022-02-25 15:52     ` Will Deacon

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